## ST7735S # 132RGB x 162dot 262K Color with Frame Memory Single-Chip TFT Controller/Driver ## Datasheet Version 1.1 2011/11 ## Sitronix Technology Corporation Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. ## LIST OF CONTENT 1 GENERAL DESCRIPTION....2 2 FEATURES 2 3 PAD ARRANGEMENT....4 3.1 Output Bump Dimension....4 3.2 Input Bump Dimension....5 3.3 Alignment Mark Dimension 6 3.4 Chip Information....7 4 PAD CENTER COORDINATES .... 8 5 BLOCK DIAGRAM....14 6 PIN DESCRIPTION....15 6.1 Power Supply Pin....15 6.2 Interface Logic Pin....15 6.3 Mode Selection Pin....17 6.4 Driver Output pins....18 6.5 Test Pins....19 7 DRIVER ELECTRICAL CHARACTERISTICS....20 7.1 Absolute Operation Range....20 7.2 DC Characteristic....21 7.3 Power Consumption....22 8 Timing chart.... 23 8.1 Parallel Interface Characteristics: 18, 16, 9 or 8-bit Bus (8080 Series MCU Interface) 23 8.2 Parallel Interface Characteristics: 18, 16, 9 or 8-bit Bus (6800 Series MCU Interface) 25 8.3 Serial Interface Characteristics (3-line Serial)....27 8.4 Serial Interface Characteristics (4-line Serial)....28 9 Function Description....29 9.1 Interface Type Selection ....29 9.2 8080-series MCU Parallel Interface (P68 = '0')....30 9.2.1 Write Cycle Sequence.... 31 9.2.2 Read Cycle Sequence 32 9.3 6800-series MCU Parallel Interface (P68 = '1')....33 9.3.1 Write Cycle Sequence.... 34 9.3.2 Read Cycle Sequence 35 9.4 Serial Interface....36 9.4.1 Command Write Mode 36 9.4.2 Read Functions....38 9.4.3 3-line Serial Protocol....38 9.4.4 4-line Serial Protocol 39 ## 9.5 Data Transfer Break and Recovery....40 ## 9.6 Data Transfer Pause....42 9.6.1 Serial Interface Pause....42 9.6.2 Parallel Interface Pause 42 ## 9.7 Data Transfer Modes ....43 9.7.1 Method 1....43 9.7.2 Method 2 43 ## 9.8 Data Color Coding ....44 9.8.1 8-bit Parallel Interface (IM2, IM1, IM0= "100").... 44 9.8.2 8-bit Data Bus for 12-bit/Pixel (RGB 4-4-4-bit Input), 4K-Colors, 3AH= "03h".... 44 9.8.3 8-bit Data Bus for 16-bit/Pixel (RGB 5-6-5-bit Input), 65K-Colors, 3AH= "05h"....45 9.8.4 8-bit Data Bus for 18-bit/Pixel (RGB 6-6-6-bit Input), 262K-Colors, 3AH= "06h"....46 9.8.5 16-Bit Parallel Interface (IM2,IM1, IM0= "101"). 47 9.8.6 16-bit Data Bus for 12-bit/Pixel (RGB 4-4-4-bit Input), 4K-Colors, 3AH= "03h"....47 9.8.7 16-bit Data Bus for 16-bit/Pixel (RGB 5-6-5-bit Input), 65K-Colors, 3AH= "05h"....48 9.8.8 16-bit Data Bus for 18-bit/Pixel (RGB 6-6-6-bit Input), 262K-Colors, 3AH= "06h"....49 9.8.9 9-Bit Parallel Interface (IM2, IM1, IM0="110").... 50 9.8.10 Write 9-bit Data for RGB 6-6-6-bit Input (262k-color) 50 9.8.11 18-Bit Parallel Interface (IM2, IM1, IM0="111"). 51 9.8.12 18-bit Data Bus for 12-bit/Pixel (RGB 4-4-4-bit Input), 4K-Colors, 3AH="03h"....51 9.8.13 18-bit Data Bus for 16-bit/Pixel (RGB 5-6-5-bit Input), 65K-Colors, 3AH="05h"....52 9.8.14 18-bit Data Bus for 18-bit/Pixel (RGB 6-6-6-bit Input), 262K-Colors, 3AH="06h"....53 9.8.15 3-line Serial Interface .... 54 9.8.16 Write Data for 12-bit/Pixel (RGB 4-4-4-bit Input), 4K-Colors, 3AH="03h"....54 9.8.17 Write Data for 16-bit/Pixel (RGB 5-6-5-bit Input), 65K-Colors, 3AH="05h"....55 9.8.18 Write Data for 18-bit/Pixel (RGB 6-6-6-bit Input), 262K-Colors, 3AH="06h"....56 9.8.19 4-line Serial Interface 57 9.8.20 Write Data for 12-bit/Pixel (RGB 4-4-4-bit Input), 4K-Colors, 3AH="03h"....57 9.8.21 Write Data for 16-bit/Pixel (RGB 5-6-5-bit Input), 65K-Colors, 3AH="05h"....58 9.8.22 Write Data for 18-bit/Pixel (RGB 6-6-6-bit Input), 262K-Colors, 3AH="06h"....58 ## 9.9 Display Data RAM....59 9.9.1 Configuration (GM[1:0] = "00").... 59 9.9.2 Memory to Display Address Mapping .... 60 9.9.3 When using 128RGB x 160 resolution (GM[1:0] = "11", SMX=SMY=SRGB= '0')....60 9.9.4 When using 132RGB x 132resolution (GM[1:0] = "01", SMX=SMY=SRGB= '0')....61 9.9.5 When using 132RGB x 162 resolution (GM[1:0] = "00", SMX=SMY=SRGB= '0')....62 9.9.6 Normal Display On or Partial Mode On....63 9.9.7 When using 128RGB x 160 resolution (GM[1:0] = "11").... 63 9.9.8 When using 128RGB x 160 resolution (GM[1:0] = "01").... 64 9.9.9 When using 132RGB x 162 resolution (GM[1:0] = "00").... 65 9.10 Address Counter....66 9.11 Memory Data Write/ Read Direction ....67 9.11.1 When 128RGBx160 (GM= "11") 67 9.11.2 When 132RGBx132 (GM= "01") 67 9.11.3 When 132RGBx162 (GM= "00") 68 9.11.4 Frame Data Write Direction According to the MADCTL Parameters (MV, MX and MY)...... 69 9.11.5 Scroll Address Circuit....70 9.11.6 Vertical Scroll Mode 70 9.11.7 Vertical Scroll Example 71 9.11.8 Case 1: TFA + VSA + BFA<162 71 9.11.9 Case 2: TFA + VSA + BFA=162 (Rolling Scrolling).... 72 9.12 Tearing Effect Output Line 73 9.12.1 Tearing Effect Line Modes 73 9.12.2 Tearing Effect Line Timings 74 9.12.3 Example 1: MPU Write is faster than panel read....75 9.12.4 Example 2: MPU Write is slower than panel read.... 76 9.13 Power ON/OFF Sequence 77 9.13.1 Uncontrolled Power Off....78 9.14 Power Level Definition ....79 9.14.1 Power Level....79 9.14.2 Power Flow Chart....80 9.15 Reset Table ....81 9.15.1 Reset Table(Default Value, GM[1:0]="11", 128RGB x 160)....81 9.15.2 Reset Table (GM[1:0]="01", 132RGB x 132)....82 9.15.3 Reset Table (GM[1:0]="00", 132RGB x 162)....83 9.16 Module Input/Output Pins ....84 9.16.1 Output or Bi-directional (I/O) Pins 84 9.17 Reset Timing....85 9.18 Color Depth Conversion Look Up Tables....86 9.18.1 65536 Color to 262,144 Color....86 9.18.2 4096 Color to 262,144 Color....90 9.19 Sleep Out-Command and Self-Diagnostic Functions of the Display Module .....92 9.19.1 Register Loading Detection....92 9.19.2 Functionality Detection....93 9.19.3 Chip Attachment Detection (Optional) 94 9.19.4 Display Glass Break Detection (Optional).... 95 ## 10 COMMAND....96 ## 10.1 System Function Command List and Description ....96 10.1.1 NOP (00h) 99 10.1.2 SWRESET (01h): Software Reset .... 100 10.1.3 RDDID (04h): Read Display ID .... 101 10.1.4 RDDST (09h): Read Display Status.... 102 10.1.5 RDDPM (0Ah): Read Display Power Mode .... 104 10.1.6 RDDMADCTL (0Bh): Read Display MADCTL 105 10.1.7 RDDCOLMOD (0Ch): Read Display Pixel Format.... 106 10.1.8 RDDIM (0Dh): Read Display Image Mode.... 107 10.1.9 RDDSM (0Eh): Read Display Signal Mode.... 108 10.1.10 RDDSDR (0Fh): Read Display Self-Diagnostic Result .... 110 10.1.11 SLPIN (10h): Sleep In 111 10.1.12 SLPOUT (11h): Sleep Out 112 10.1.13 PTLON (12h): Partial Display Mode On.... 113 10.1.14 NORON (13h): Normal Display Mode On.... 114 10.1.15 INVOFF (20h): Display Inversion Off .... 115 10.1.16 INVON (21h): Display Inversion On....116 10.1.17 GAMSET (26h): Gamma Set 117 10.1.18 DISPOFF (28h): Display Off.... 118 10.1.19 DISPON (29h): Display On 119 10.1.20 CASET (2Ah): Column Address Set 120 10.1.21 RASET (2Bh): Row Address Set 122 10.1.22 RAMWR (2Ch): Memory Write.... 124 10.1.23 RGBSET (2Dh): Color Setting for 4K, 65K and 262K.... 125 10.1.24 RAMRD (2Eh): Memory Read 126 10.1.25 PTLAR (30h): Partial Area .... 127 10.1.26 SCRLAR (33h): Scroll Area Set.... 129 10.1.27 TEOFF (34h): Tearing Effect Line OFF .... 131 10.1.28 TEON (35h): Tearing Effect Line ON 132 10.1.29 MADCTL (36h): Memory Data Access Control....134 10.1.30 VSCSAD: Vertical Scroll Start Address of RAM (37h)....137 10.1.31 IDMOFF (38h): Idle Mode Off 139 10.1.32 IDMON (39h): Idle Mode On....140 10.1.33 COLMOD (3Ah): Interface Pixel Format 142 10.1.34 RDID1 (DAh): Read ID1 Value.... 143 10.1.35 RDID2 (DBh): Read ID2 Value....144 10.1.36 RDID3 (DCh): Read ID3 Value 146 ## 10.2 Panel Function Command List and Description....147 10.2.1 FRMCTR1 (B1h): Frame Rate Control (In normal mode/ Full colors) .... 151 10.2.2 FRMCTR2 (B2h): Frame Rate Control (In Idle mode/ 8-colors).... 152 10.2.3 FRMCTR3 (B3h): Frame Rate Control (In Partial mode/ full colors) .... 153 10.2.4 INVCTR (B4h): Display Inversion Control.... 154 10.2.5 PWCTR1 (C0h): Power Control 1 155 10.2.6 PWCTR2 (C1h): Power Control 2....157 10.2.7 PWCTR3 (C2h): Power Control 3 (in Normal mode/ Full colors).... 159 10.2.8 PWCTR4 (C3h): Power Control 4 (in Idle mode/ 8-colors).... 161 10.2.9 PWCTR5 (C4h): Power Control 5 (in Partial mode/ full-colors).... 163 10.2.10 VMCTR1 (C5h): VCOM Control 1 165 10.2.11 VMOFCTR (C7h): VCOM Offset Control 167 10.2.12 WRID2 (D1h): Write ID2 Value 169 10.2.13 WRID3 (D2h): Write ID3 Value 170 10.2.14 NVFCTR1 (D9h): NVM Control Status.... 171 10.2.15 NVFCTR2 (DEh): NVM Read Command.... 172 10.2.16 NVFCTR3 (DFh): NVM Write Command 173 10.2.17 GMCTRP1 (E0h): Gamma ('+'polarity) Correction Characteristics Setting .... 174 10.2.18 GMCTRN1 (E1h): Gamma '-'polarity Correction Characteristics Setting .... 176 10.2.19 GCV(FCh): Gate Pump Clock Frequency Variable .... 178 ## 11 Power Sturcture....179 11.1 Driver IC Operating Voltage Specification....179 11.2 Power Booster Circuit .... 180 ## 12 Gamma Structure.... 181 12.1 Structure of Grayscale Amplifier ....181 12.2 Gamma Voltage Formula (Positive/ Negative Polarity)....182 ## 13 Example Connection with Panel Direction and Different Resolution 184 13.1 Application of Connection with Panel Direction....184 13.2 Application of Connection with Different Resolution....186 13.3 Microprocessor Interface Applications .... 189 13.3.1 8080-Series MCU Interface for 8-bit Data Bus (P68=0, IM2, IM1, IM0="100")..... 189 13.3.2 8080-Series MCU Interface for 16-bit Data Bus (P68=0, IM2, IM1, IM0="101")..... 189 13.3.3 8080-Series MCU Interface for 9-bit Data Bus (P68=0, IM2, IM1, IM0="110")..... 189 13.3.4 8080-Series MCU Interface for 18-bit Data Bus (P68=0, IM2, IM1, IM0="111")..... 190 13.3.5 6800-Series MCU Interface for 8-bit Data Bus (P68=1, IM2, IM1, IM0="100")..... 190 13.3.6 6800-Series MCU Interface for 16-bit Data Bus (P68=1, IM2, IM1, IM0="101")..... 190 13.3.7 6800-Series MCU Interface for 9-bit Data Bus (P68=1, IM2, IM1, IM0="110")..... 191 13.3.8 6800-Series MCU Interface for 18-bit Data Bus (P68=1, IM2, IM1, IM0="111")..... 191 13.3..9 3-Line Serial MCU Interface (IM2, IM1, IM0="000", SPI4W=0).... 191 13.3.10 4-Line Serial MCU Interface (IM2, IM1, IM0="000", SPI4W=1).... 192 ## 14 Revision History ...... 193 ## LIST OF FIGURES Figure 1 Parallel interface timing characteristics (8080 series MCU interface).... 23 Figure 2 Rising and falling timing for input and output signal....24 Figure 3 Chip selection (CSX) timing 24 Figure 4 Write-to-read and read-to-write timing....24 Figure 5 Parallel Interface Timing Characteristics (6800-Series MCU Interface) 25 Figure 6 3-line serial interface timing....27 Figure 7 4-line serial interface timing....28 Figure 8 8080-series WRX protocol .... 31 Figure 9 8080-series parallel bus protocol, write to register or display RAM 31 Figure 10 8080-series RDX protocol 32 Figure 11 8080-series parallel bus protocol, read data from register or display RAM .... 32 Figure 12 6800-Series Write Protocol 34 Figure 13 6800-series parallel bus protocol, write to register or display RAM....34 Figure 14 6800-series read protocol....35 Figure 15 6800-series parallel bus protocol, read data form register or display RAM .... 35 Figure 16 Serial interface data stream format....37 Figure 17 3-line serial interface write protocol (write to register with control bit in transmission)....37 Figure 18 4-line serial interface write protocol (write to register with control bit in transmission)....37 Figure 19 3-line serial interface read protocol 38 Figure 20 4-line serial interface read protocol 39 Figure 21 Serial bus protocol, write mode—interrupted by RESX....40 Figure 22 Serial bus protocol, write mode—interrupted by CSX .... 40 Figure 23 Write interrupts recovery (serial interface) 41 Figure 24 Write interrupts recovery (both serial and parallel Interface) 41 Figure 25 Serial interface pause protocol (pause by CSX)....42 Figure 26 Parallel bus pause protocol (paused by CSX) 42 Figure 27 Display data RAM organization....59 Figure 28 Data streaming order....67 ## LIST OF TABLES Table 1 Absolute Operation Range .... 20 Table 2 DC Characteristic....21 Table 3 Power Consumption 22 Table 4 8080 Parallel Interface Characteristics....24 Table 5 6800 Parallel Interface Characteristics....26 Table 6 3-line Serial Interface Characteristics....27 Table 7 4-line Serial Interface Characteristics....28 Table 8 Interface Type Selection....29 Table 9 Pin Connection According to Various MCU Interface....29 Table 10 The Function of 8080-series Parallel Interface....30 Table 11 The Function of 6800-series Parallel Interface.... 33 Table 12 Selection of Serial Interface....36 Table 13 AC characteristics of Tearing Effect Signal Idle Mode Off (Frame Rate = 60 Hz, Ta=25°C)..... 74 Table 14 Reset Timing....85 Table 15 System Function Command List (1)....96 Table 16 System Function Command List (2)....97 Table 17 System Function command List (3)....98 Table 18 Panel Function Command List (1)....147 Table 19 Panel Function Command List (2)....148 Table 20 Panel Function Command List (3)....149 Table 21 Panel Function Command List (4)....150 ## 1 GENERAL DESCRIPTION The ST7735S is a single-chip controller/driver for 262K-color, graphic type TFT-LCD. It consists of 396 source line and 162 gate line driving circuits. This chip is capable of connecting directly to an external microprocessor, and accepts Serial Peripheral Interface (SPI), 8-bit/9-bit/16-bit/18-bit parallel interface. Display data can be stored in the on-chip display data RAM of 132 x 162 x 18 bits. It can perform display data RAM read/write operation with no external operation clock to minimize power consumption. In addition, because of the integrated power supply circuits necessary to drive liquid crystal, it is possible to make a display system with fewer components. ## 2 FEATURES ## Single Chip TFT-LCD Controller/Driver with RAM On-chip Display Data RAM (i.e. Frame Memory) 132 (H) x RGB x 162 (V) Bits ## LCD Driver Output Circuits: Source Outputs: 132 RGB Channels Gate Outputs: 162 Channels Common Electrode Output ## Display Colors (Color Mode) Full Color: 262K, RGB=(666) Max., Idle Mode OFF Color Reduce: 8-color, RGB=(111), Idle Mode ON ## Programmable Pixel Color Format (Color Depth) for Various Display Data input Format 12-bit/pixel: RGB=(444) Using the 384k-bit Frame Memory and LUT 16-bit/pixel: RGB=(565) Using the 384k-bit Frame Memory and LUT 18-bit/pixel: RGB=(666) Using the 384k-bit Frame Memory and LUT ## Various Interfaces Parallel 8080-series MCU Interface (8-bit, 9-bit, 16-bit & 18-bit) Parallel 6800-series MCU Interface (8-bit, 9-bit, 16-bit & 18-bit) 3-line Serial Interface 4-line Serial Interface ## Display Features Support Both Normal-black & Normal-white LC Software Programmable Color Depth Mode Partial Window Moving & Data Scrolling ## Built-in Circuits DC/DC Converter Adjustable VCOM Generation Non-volatile (NV) Memory to Store Initial Register Setting Oscillator for Display Clock Generation Factory default value (module ID, module version, etc) are stored in NV memory. Timing Controller ## Built-in NV Memory for LCD Initial Register Setting 7-bits for ID2 8-bits for ID3 7-bits for VCOM Offset Adjustment ## Wide Supply Voltage Range I/O Voltage (VDDI to DGND): 1.65V\~3.7V (VDDI ≤ VDD) Analog Voltage (VDD to AGND): 2.5V\~4.8V ## On-Chip Power System Source Voltage (GVDD to AGND): 3.15V to 5V VCOM level (VCOM to AGND): -0.425V to -2.0V Gate Driver HIGH Level (VGH to AGND): +10.0V to +15V Gate Driver LOW Level (VGL to AGND): -13V to -7.5V Operating Temperature: -30°C to +85°C 3 PAD ARRANGEMENT ![](images/61f49536e16aa8267e1e9120af6d28c3aacc91f2baa5c74c3ead640c6d43f23b.jpg)
flowchart This diagram illustrates the layout and dimensions of a display panel, showing input pad, source pad, and gateway pad connections with dimensions in micrometers.
3.1 Output Bump Dimension ![](images/ad27f3978658ebe5a3f595a61694257bb642d2ad9a69ea253887bb0604b4a59d.jpg)
text_image Boundary (Include scribe Lane) C K L H J A
ItemSymbolSize
Bump PitchA16 um
Bump WidthC16 um
Bump HeightH98 um
Bump Gap1 (Vertical)J19 um
Bump Gap2 (Horizontal)K16 um
Bump AreaC x H1568 um2
Chip Boundary (Include Scribe Lane)L59 um
## 3.2 Input Bump Dimension ![](images/fe1eef8b8c2c2f483bb97d034f910b2059a369136b1e9f4df743c7aea2a94616.jpg)
text_image C2 C2 A1 A2 C1 H K K2 K1 K1 L
Boundary (Include scribe Lane)
ItemSymbolSize
Bump Pitch 1A172.5 um
Bump Pitch 2A260 um
Bump Width 1C138 um
Bump Width 2C233 um
Bump HeightH88 um
Bump GapK17 um
Bump Gap1K122 um
Bump Gap2K234.5 um
Bump Area 1C1 X H3344 um2
Bump Area 2C2 X H2904 um2
Chip Boundary(Include Scribe Lane)L60 um
## 3.3 Alignment Mark Dimension ![](images/ea1c418df6df5668871b0046487f28565bbc9d52fab17dc0b31bad6a590e3af4.jpg) ## 3.4 Chip Information Chip Size (um x um): 10080 x 670 PAD Coordinate: Pad Center Coordinate Origin: Chip Center Chip Thickness (um): 300(TYP) Bump Height (um): 12(TYP) Bump Hardness (HV): 75(TYP) ![](images/79ccc3274db8f5222be000877910f3eef8552964f77decd380ced155471addbd.jpg)
text_image No.186 No.185 ST7735S (Bump-up) S197 S200 S199 S198 X,Y (0.0) No.755 No.1
4 PAD CENTER COORDINATES
No.PAD NameXY
1Dummy-4750-231
2VDDIO-4700-231
3EXTC-4650-231
4DGNDO-4600-231
5IMO-4550-231
6VDDIO-4500-231
7IM1-4450-231
8DGNDO-4400-231
9P68-4350-231
10VDDIO-4300-231
11TEST1P-4250-231
12DGNDO-4200-231
13TEST2P-4150-231
14VDDIO-4100-231
15SRGB-4050-231
16DGNDO-4000-231
17SMX-3950-231
18VDDIO-3900-231
19SMY-3850-231
20DGNDO-3800-231
21Dummy-3750-231
22VDDIO-3700-231
23Dummy-3650-231
24DGNDO-3600-231
25Dummy-3550-231
26VDDIO-3500-231
27Dummy-3450-231
28DGNDO-3400-231
29Dummy-3350-231
30VDDIO-3300-231
31LCM-3250-231
32DGNDO-3200-231
33DUMMY-3150-231
34VDDIO-3100-231
35Dummy-3050-231
36DGNDO-3000-231
37GM1-2950-231
38VDDIO-2900-231
39GM0-2850-231
40DGNDO-2800-231
41Dummy-2750-231
42GS-2700-231
43SPI4W-2650-231
44VDDIO-2600-231
45TESTOP[8]-2550-231
46TESTOP[7]-2500-231
47TESTOP[6]-2450-231
48TESTOP[5]-2400-231
49TESTOP[4]-2350-231
50OSCP-2300-231
No.PAD NameXY
51VDD-2250-231
52VDD-2200-231
53VDD-2150-231
54VDD-2100-231
55VDD-2050-231
56VDD-2000-231
57AGND-1950-231
58AGND-1900-231
59AGND-1850-231
60AGND-1800-231
61AGND-1750-231
62AGND-1700-231
63RDX-1630-231
64D_CX-1570-231
65TESEL-1510-231
66DGNDO-1450-231
67D17-1390-231
68D16-1330-231
69D15-1270-231
70D14-1210-231
71D13-1150-231
72D12-1090-231
73D11-1030-231
74D10-970-231
75D9-910-231
76D8-850-231
77D1-790-231
78D3-730-231
79D5-670-231
80D7-610-231
81TE-550-231
82RESX-490-231
83CSX-430-231
84D6-370-231
85D4-310-231
86D2-250-231
87IM2-190-231
88D0-130-231
89WRX-70-231
90Dummy0-231
91Dummy50-231
92Dummy100-231
93Dummy150-231
94TESTOP[3]200-231
95TESTOP[2]250-231
96TESTOP[1]300-231
97DGND350-231
98DGND400-231
99DGND450-231
100DGND500-231
No.PAD NameXY
101DGND550-231
102DGND600-231
103VDDI650-231
104VDDI700-231
105VDDI750-231
106VDDI800-231
107VDDI850-231
108VDDI900-231
109VPP950-231
110VPP1000-231
111VPP1050-231
112GVDD1100-231
113GVDD1150-231
114GVDD1200-231
115VCC1250-231
116Dummy1300-231
117Dummy1350-231
118GVCL1400-231
119Dummy1450-231
120AVDD1500-231
121AVDD1550-231
122AVDD1600-231
123AVDD1650-231
124AVDD1700-231
125Dummy1750-231
126Dummy1800-231
127Dummy1850-231
128DummyR1900-231
129DummyR1950-231
130Dummy2000-231
131Dummy2050-231
132Dummy2100-231
133Dummy2150-231
134Dummy2200-231
135Dummy2250-231
136Dummy2300-231
137Dummy2350-231
138Dummy2400-231
139Dummy2450-231
140Dummy2500-231
141Dummy2550-231
142Dummy2600-231
143Dummy2650-231
144Dummy2700-231
145Dummy2750-231
146AGND2800-231
147AGND2850-231
148AGND2900-231
149AVCL2950-231
150AVCL3000-231
151AVCL3050-231
152Dummy3100-231
153Dummy3150-231
154Dummy3200-231
155Dummy3250-231
156Dummy3300-231
157Dummy3350-231
158Dummy3400-231
159Dummy3450-231
160Dummy3500-231
161Dummy3550-231
162Dummy3600-231
163Dummy3650-231
164Dummy3700-231
165Dummy3750-231
166Dummy3800-231
167Dummy3850-231
168Dummy3900-231
169Dummy3950-231
170VGL4000-231
171VGL4050-231
172VGL4100-231
173VGH4150-231
174Dummy4200-231
175Dummy4250-231
176Dummy4300-231
177Dummy4350-231
178Dummy4400-231
179VCL4450-231
180VCL4500-231
181VCL4550-231
182VCOM4600-231
183VCOM4650-231
184VCOM4700-231
185Dummy4750-231
186Dummy4772110
187Dummy4756227
188G1624740110
189G1604724227
190G1584708110
191G1564692227
192G1544676110
193G1524660227
194G1504644110
195G1484628227
196G1464612110
197G1444596227
198G1424580110
199G1404564227
200G1384548110
No.PAD NameXY
201G1364532227
202G1344516110
203G1324500227
204G1304484110
205G1284468227
206G1264452110
207G1244436227
208G1224420110
209G1204404227
210G1184388110
211G1164372227
212G1144356110
213G1124340227
214G1104324110
215G1084308227
216G1064292110
217G1044276227
218G1024260110
219G1004244227
220G984228110
221G964212227
222G944196110
223G924180227
224G904164110
225G884148227
226G864132110
227G844116227
228G824100110
229G804084227
230G784068110
231G764052227
232G744036110
233G724020227
234G704004110
235G683988227
236G663972110
237G643956227
238G623940110
239G603924227
240G583908110
241G563892227
242G543876110
243G523860227
244G503844110
245G483828227
246G463812110
247G443796227
248G423780110
249G403764227
250G383748110
No.PAD NameXY
251G363732227
252G343716110
253G323700227
254G303684110
255G283668227
256G263652110
257G243636227
258G223620110
259G203604227
260G183588110
261G163572227
262G143556110
263G123540227
264G103524110
265G83508227
266G63492110
267G43476227
268G23460110
269Dummy3444227
270Dummy3428110
271Dummy3412227
272Dummy3396110
273S3963380227
274S3953364110
275S3943348227
276S3933332110
277S3923316227
278S3913300110
279S3903284227
280S3893268110
281S3883252227
282S3873236110
283S3863220227
284S3853204110
285S3843188227
286S3833172110
287S3823156227
288S3813140110
289S3803124227
290S3793108110
291S3783092227
292S3773076110
293S3763060227
294S3753044110
295S3743028227
296S3733012110
297S3722996227
298S3712980110
299S3702964227
300S3692948110
301S3682932227
302S3672916110
303S3662900227
304S3652884110
305S3642868227
306S3632852110
307S3622836227
308S3612820110
309S3602804227
310S3592788110
311S3582772227
312S3572756110
313S3562740227
314S3552724110
315S3542708227
316S3532692110
317S3522676227
318S3512660110
319S3502644227
320S3492628110
321S3482612227
322S3472596110
323S3462580227
324S3452564110
325S3442548227
326S3432532110
327S3422516227
328S3412500110
329S3402484227
330S3392468110
331S3382452227
332S3372436110
333S3362420227
334S3352404110
335S3342388227
336S3332372110
337S3322356227
338S3312340110
339S3302324227
340S3292308110
341S3282292227
342S3272276110
343S3262260227
344S3252244110
345S3242228227
346S3232212110
347S3222196227
348S3212180110
349S3202164227
350S3192148110
No.PAD NameXY
351S3182132227
352S3172116110
353S3162100227
354S3152084110
355S3142068227
356S3132052110
357S3122036227
358S3112020110
359S3102004227
360S3091988110
361S3081972227
362S3071956110
363S3061940227
364S3051924110
365S3041908227
366S3031892110
367S3021876227
368S3011860110
369S3001844227
370S2991828110
371S2981812227
372S2971796110
373S2961780227
374S2951764110
375S2941748227
376S2931732110
377S2921716227
378S2911700110
379S2901684227
380S2891668110
381S2881652227
382S2871636110
383S2861620227
384S2851604110
385S2841588227
386S2831572110
387S2821556227
388S2811540110
389S2801524227
390S2791508110
391S2781492227
392S2771476110
393S2761460227
394S2751444110
395S2741428227
396S2731412110
397S2721396227
398S2711380110
399S2701364227
400S2691348110
No.PAD NameXY
401S2681332227
402S2671316110
403S2661300227
404S2651284110
405S2641268227
406S2631252110
407S2621236227
408S2611220110
409S2601204227
410S2591188110
411S2581172227
412S2571156110
413S2561140227
414S2551124110
415S2541108227
416S2531092110
417S2521076227
418S2511060110
419S2501044227
420S2491028110
421S2481012227
422S247996110
423S246980227
424S245964110
425S244948227
426S243932110
427S242916227
428S241900110
429S240884227
430S239868110
431S238852227
432S237836110
433S236820227
434S235804110
435S234788227
436S233772110
437S232756227
438S231740110
439S230724227
440S229708110
441S228692227
442S227676110
443S226660227
444S225644110
445S224628227
446S223612110
447S222596227
448S221580110
449S220564227
450S219548110
451S218532227
452S217516110
453S216500227
454S215484110
455S214468227
456S213452110
457S212436227
458S211420110
459S210404227
460S209388110
461S208372227
462S207356110
463S206340227
464S205324110
465S204308227
466S203292110
467S202276227
468S201260110
469S200244227
470S199228110
471S198-228110
472S197-244227
473S196-260110
474S195-276227
475S194-292110
476S193-308227
477S192-324110
478S191-340227
479S190-356110
480S189-372227
481S188-388110
482S187-404227
483S186-420110
484S185-436227
485S184-452110
486S183-468227
487S182-484110
488S181-500227
489S180-516110
490S179-532227
491S178-548110
492S177-564227
493S176-580110
494S175-596227
495S174-612110
496S173-628227
497S172-644110
498S171-660227
499S170-676110
500S169-692227
No.PAD NameXY
501S168-708110
502S167-724227
503S166-740110
504S165-756227
505S164-772110
506S163-788227
507S162-804110
508S161-820227
509S160-836110
510S159-852227
511S158-868110
512S157-884227
513S156-900110
514S155-916227
515S154-932110
516S153-948227
517S152-964110
518S151-980227
519S150-996110
520S149-1012227
521S148-1028110
522S147-1044227
523S146-1060110
524S145-1076227
525S144-1092110
526S143-1108227
527S142-1124110
528S141-1140227
529S140-1156110
530S139-1172227
531S138-1188110
532S137-1204227
533S136-1220110
534S135-1236227
535S134-1252110
536S133-1268227
537S132-1284110
538S131-1300227
539S130-1316110
540S129-1332227
541S128-1348110
542S127-1364227
543S126-1380110
544S125-1396227
545S124-1412110
546S123-1428227
547S122-1444110
548S121-1460227
549S120-1476110
550S119-1492227
No.PAD NameXY
551S118-1508110
552S117-1524227
553S116-1540110
554S115-1556227
555S114-1572110
556S113-1588227
557S112-1604110
558S111-1620227
559S110-1636110
560S109-1652227
561S108-1668110
562S107-1684227
563S106-1700110
564S105-1716227
565S104-1732110
566S103-1748227
567S102-1764110
568S101-1780227
569S100-1796110
570S99-1812227
571S98-1828110
572S97-1844227
573S96-1860110
574S95-1876227
575S94-1892110
576S93-1908227
577S92-1924110
578S91-1940227
579S90-1956110
580S89-1972227
581S88-1988110
582S87-2004227
583S86-2020110
584S85-2036227
585S84-2052110
586S83-2068227
587S82-2084110
588S81-2100227
589S80-2116110
590S79-2132227
591S78-2148110
592S77-2164227
593S76-2180110
594S75-2196227
595S74-2212110
596S73-2228227
597S72-2244110
598S71-2260227
599S70-2276110
600S69-2292227
601S68-2308110
602S67-2324227
603S66-2340110
604S65-2356227
605S64-2372110
606S63-2388227
607S62-2404110
608S61-2420227
609S60-2436110
610S59-2452227
611S58-2468110
612S57-2484227
613S56-2500110
614S55-2516227
615S54-2532110
616S53-2548227
617S52-2564110
618S51-2580227
619S50-2596110
620S49-2612227
621S48-2628110
622S47-2644227
623S46-2660110
624S45-2676227
625S44-2692110
626S43-2708227
627S42-2724110
628S41-2740227
629S40-2756110
630S39-2772227
631S38-2788110
632S37-2804227
633S36-2820110
634S35-2836227
635S34-2852110
636S33-2868227
637S32-2884110
638S31-2900227
639S30-2916110
640S29-2932227
641S28-2948110
642S27-2964227
643S26-2980110
644S25-2996227
645S24-3012110
646S23-3028227
647S22-3044110
648S21-3060227
649S20-3076110
650S19-3092227
No.PAD NameXY
651S18-3108110
652S17-3124227
653S16-3140110
654S15-3156227
655S14-3172110
656S13-3188227
657S12-3204110
658S11-3220227
659S10-3236110
660S9-3252227
661S8-3268110
662S7-3284227
663S6-3300110
664S5-3316227
665S4-3332110
666S3-3348227
667S2-3364110
668S1-3380227
669Dummy-3396110
670Dummy-3412227
671Dummy-3428110
672Dummy-3444227
673G1-3460110
674G3-3476227
675G5-3492110
676G7-3508227
677G9-3524110
678G11-3540227
679G13-3556110
680G15-3572227
681G17-3588110
682G19-3604227
683G21-3620110
684G23-3636227
685G25-3652110
686G27-3668227
687G29-3684110
688G31-3700227
689G33-3716110
690G35-3732227
691G37-3748110
692G39-3764227
693G41-3780110
694G43-3796227
695G45-3812110
696G47-3828227
697G49-3844110
698G51-3860227
699G53-3876110
700G55-3892227
No.PAD NameXY
701G57-3908110
702G59-3924227
703G61-3940110
704G63-3956227
705G65-3972110
706G67-3988227
707G69-4004110
708G71-4020227
709G73-4036110
710G75-4052227
711G77-4068110
712G79-4084227
713G81-4100110
714G83-4116227
715G85-4132110
716G87-4148227
717G89-4164110
718G91-4180227
719G93-4196110
720G95-4212227
721G97-4228110
722G99-4244227
723G101-4260110
724G103-4276227
725G105-4292110
726G107-4308227
727G109-4324110
728G111-4340227
729G113-4356110
730G115-4372227
731G117-4388110
732G119-4404227
733G121-4420110
734G123-4436227
735G125-4452110
736G127-4468227
737G129-4484110
738G131-4500227
739G133-4516110
740G135-4532227
741G137-4548110
742G139-4564227
743G141-4580110
744G143-4596227
745G145-4612110
746G147-4628227
747G149-4644110
748G151-4660227
749G153-4676110
750G155-4692227
751G157-4708110
752G159-4724227
753G161-4740110
754Dummy-4756227
755Dummy-4772110
ALIGNMENT_R4841-220
ALIGNMENT_L-4841-220
5 BLOCK DIAGRAM ![](images/38214670b3bb94eeef0fbf0d2b4747a95b6a4af98ab547fff00696afd7fd1eb8.jpg)
flowchart ```mermaid graph TD subgraph MCU_IF ["MCU IF"] direction TB MCU_IF --> ColorConversion["Color conversion LUT table"] ColorConversion --> DisplayRam["Display Ram 132x 162x18 bits"] DisplayRam --> DataLatch["Data Latch"] DataLatch --> ADC["DAC"] ADC --> LevelShifter["Level Shifter"] ADC --> VoltageReference["Voltage Reference"] VoltageReference --> GammaCircuit["Gamma Circuit"] GammaCircuit --> DisplayControl["Display control"] DisplayControl --> OSC["OSC"] OSC --> VCOM["VCOM generator"] OSC --> GateDecoder["Gate Decoder"] GateDecoder --> LevelShifter["Level Shifter"] GateDecoder --> VCOM end subgraph InstructionReg["Instruction Register"] direction TB InstructionReg --> NVM["NVM"] end subgraph VCOM["VCOM"] direction TB VCOM --> VCOM OSC --> VCOM end subgraph VCOM_Cycle["VCOM"] direction TB VCOM --> VCOM OSC --> VCOM end ```
## 6 PIN DESCRIPTION 6.1 Power Supply Pin
NameI/ODescriptionConnect Pin
VDDIPower Supply for Analog, Digital System and Booster Circuit.VDD
VDDIIPower Supply for I/O system.VDDI
AGNDISystem Ground for Analog System and Booster Circuit.GND
DGNDISystem Ground for I/O System and Digital System.GND
6.2 Interface Logic Pin
NameI/ODescriptionConnect pin
P68I-8080/6800 MCU Interface Mode Select.-P68='1', Select 6800 MCU Parallel Interface.-P68='0', Select 8080 MCU Parallel Interface.-If not used, Please Fix this Pin at DGND Level.DGND/VDDI
IM2IMCU Parallel Interface Bus and Serial Interface selectIM2='1', Parallel InterfaceIM2='0', Serial InterfaceDGND/VDDI
IM1,IM0I- MCU Parallel Interface Type Selection-If Not Used, Please Fix this Pin at VDDI or DGND Level.DGND/VDDI
IM1IM0Parallel Interface
00MCU 8-bit Parallel
01MCU 16-bit Parallel
10MCU 9-bit Parallel
11MCU 18-bit Parallel
SPI4WI- SPI4W='0', 3-line SPI Enable.- SPI4W='1', 4-line SPI Enable.-If Not Used, Please fix this Pin at DGND Level.DGND/VDDI
RESXI-This signal will reset the device and it must be applied to properly initialize the chip.-Signal is active low.MCU
CSXI-Chip Selection Pin-Low Enable.MCU
IM1IM0Parallel Interface
00MCU 8-bit Parallel
01MCU 16-bit Parallel
10MCU 9-bit Parallel
11MCU 18-bit Parallel
- SPI4W='0', 3-line SPI Enable.- SPI4W='1', 4-line SPI Enable.-If Not Used, Please fix this Pin at DGND Level.-This signal will reset the device and it must be applied to properly initialize the chip.-Signal is active low.-Chip Selection Pin-Low Enable.
D/CX(SCL)I-Display data/command Selection Pin in MCU Interface.-D/CX='1': Display Data or Parameter.-D/CX='0': Command Data.-In Serial Interface, this is used as SCL.-If not used, please fix this pin at VDDI or DGND level.MCU
RDXI-Read Enable in 8080 MCU Parallel Interface.-If not used, please fix this pin at VDDI or DGND level.MCU
WRX(D/CX)I-Write Enable in MCU Parallel Interface.-In 4-line SPI, this pin is used as D/CX (data/ command selection).-If not used, please fix this pin at VDDI or DGND level.MCU
D[17:0]I/O-D[17:0] are used as MCU parallel interface data bus.-D0 is the serial input/output signal in serial interface mode.-In serial interface, D[17:1] are not used and should be fixed at VDDI or DGND level.MCU
TEO-Tearing effect output pin to synchronies MCU to frame rate, activated by S/W command.-If not used, please open this pin.MCU
OSCO-Monitoring pin of internal oscillator clock and is turned ON/OFF by S/W command.-When this pin is inactive (function OFF), this pin is DGND level.-If not used, please open this pin.-
Note1. When in parallel mode, no use data pin must be connected to "1" or "0". Note2. When CSX="1", there is no influence to the parallel and serial interface. 6.3 Mode Selection Pin
NameI/ODescriptionConnect Pin
EXTCI-During normal operation, please connect to VDDI..VDDI/DGND
EXTCEnable/disable Modification of Extend Command
0Panel Function Commands Disable.
1Panel Function Commands Enable.
GM1, GM0I-Panel Resolution Selection Pins.VDDI/DGND
GM1GM0Selection of panel resolution
00132RGB x 162 (S1~S396 & G1~G162 output)
01132RGB x 132 (S1~S396 & G1~G132 Output)
11128RGB x 160 (S7~S390 & G2~G161 output)
SRGBI-RGB Direction Select H/W Pin for Color Filter Setting.VDDI/DGND
SRGBRGB Arrangement
0S1, S2, S3 Filter Order = 'R', 'G', 'B'
1S1, S2, S3 Filter Order = 'B', 'G', 'R'
SMXI-Module Source Output Direction H/W Selection Pin.VDDI/DGND
SMXScanning direction of source output
GM= '00'GM= '01'GM= '11'
0S1 -> S396S1 -> S396S7 -> S390
1S396 -> S1S396 -> S1S390 -> S7
SMYI-Module Gate Output Direction H/W Selection Pin.VDDI/DGND
SMYScanning direction of gate output
GM= '00'GM= '01'GM= '11'
0G1 -> G162G1 -> G132G2 -> G161
1G162 -> G1G132 -> G1G161 -> G2
LCMI-Liquid Crystal (LC) Type Selection Pins.VDDI/DGND
LCMSelection of LC Type
0Normally White LC Type
1Normally Black LC Type
GSI-Gamma Curve Selection Pin.VDDI/DGND
GSSelection of Gamma Curve
0GC0=1.0, GC1=2.5, GC2=2.2, GC3=1.8
1GC0=2.2, GC1=1.8, GC2=2.5, GC3=1.0
EXTCEnable/disable Modification of Extend Command
0Panel Function Commands Disable.
1Panel Function Commands Enable.
GM1GM0Selection of panel resolution
00132RGB x 162 (S1~S396 & G1~G162 output)
01132RGB x 132 (S1~S396 & G1~G132 Output)
11128RGB x 160 (S7~S390 & G2~G161 output)
SRGBRGB Arrangement
0S1, S2, S3 Filter Order = 'R', 'G', 'B'
1S1, S2, S3 Filter Order = 'B', 'G', 'R'
SMXScanning direction of source output
GM= '00'GM= '01'GM= '11'
0S1 -> S396S1 -> S396S7 -> S390
1S396 -> S1S396 -> S1S390 -> S7
SMYScanning direction of gate output
GM=‘00’GM=‘01’GM=‘11’
0G1 -> G162G1 -> G132G2 -> G161
1G162 -> G1G132 -> G1G161 -> G2
LCMSelection of LC Type
0Normally White LC Type
1Normally Black LC Type
GSSelection of Gamma Curve
0GC0=1.0, GC1=2.5, GC2=2.2, GC3=1.8
1GC0=2.2, GC1=1.8, GC2=2.5, GC3=1.0
VPPIWhen writing NVM, it needs external power supply voltage (7.5V).
TESELIInput pin to select horizontal line number in TE signal.This pin is internally pull low.DGND
TESELSelection of gamma curve
0TE output 162 lines
1TE output 160 lines
6.4 Driver Output pins
NameI/ODescriptionConnect Pin
S1 to S396O- Source Driver Output Pins.-
G1 to G162O- Gate Driver Output Pins.-
AVDDO- Power Pin for Analog Circuits.-
AVCLO- A power Supply Pin for Generating GVCL.-
VGHO- Power Output Pin for Gate Driver-
VGLO- Power Output (Negative) Pin for Gate Driver-
GVDDO- A power Output of Grayscale Voltage Generator.- When internal GVDD generator is not used, connect an external power supply (AVDD-0.5V) to this pin.-
GVCLO- A power Output (Negative) of Grayscale Voltage Generator.- When internal GVCL generator is not used, connect an external power supply (AVCL+0.5V) to this pin.-
VCOMO- A Power Supply for the TFT-LCD Common Electrode.Common Electrode
VCCO- Monitoring Pin of Internal Digital Reference Voltage.- Please Open These Pins.
VCLO- A power output of VCOM voltage (Negative) generator.
VDDIOO- VDDI Voltage Output Level for Monitoring.-
DGNDOO- DGND Voltage Output Level for Monitoring.-
6.5 Test Pins
NameI/ODescriptionConnect Pin
TEST2PI-These test pins for driver vender test used.DGND
TEST1P-Please connect these pins to DGND.
TESTOP[8]O-These test pins for driver vender test used.Open
TESTOP[7]-Please open these pins.
TESTOP[6]
TESTOP[5]
TESTOP[4]
TESTOP[3]
TESTOP[2]
TESTOP[1]
DummyR--These pins are dummy (have no function inside).-Pad128 DummyR internal short to pad 129 DummyR.Open
Dummy--These pins are dummy (have no function inside).-Can allow signal traces pass through these pads on TFT glass.-Please open these pins.Open
## 7 DRIVER ELECTRICAL CHARACTERISTICS ## 7.1 Absolute Operation Range
ItemSymbolRatingUnit
Supply VoltageVDD-0.3 ~ +4.8V
Supply Voltage (Logic)VDDI-0.3 ~ +4.6V
Supply Voltage (Digital)VCC-0.3 ~ +1.95V
Driver Supply VoltageVGH-VGL-0.3 ~ +30.0V
Logic Input Voltage RangeVIN-0.3 ~ VDDI + 0.3V
Logic Input Voltage RangeVO-0.3 ~ VDDI + 0.3V
Operating Temperature RangeTOPR-30 ~ +85°C
Storage Temperature RangeTSTG-40 ~ +125°C
Table 1 Absolute Operation Range Note: If one of the above items is exceeded its maximum limitation momentarily, the quality of the product may be degraded. Absolute maximum limitation, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the recommend range. 7.2 DC Characteristic
ParameterSymbolConditionSpecificationUnitRelated Pins
MinTypMax
Power & Operation Voltage
System VoltageVDDOperating Voltage2.52.754.8V
Interface Operation VoltageVDDII/O Supply Voltage1.651.83.7V
Gate Driver High VoltageVGH1116VNote 4
Gate Driver Low VoltageVGL-13-7.5V
Gate Driver Supply Voltage| VGH-VGL |18.529VNote 4
Input / Output
Logic-High Input VoltageVIH0.7VDDIVDDIVNote 1
Logic-Low Input VoltageVILVSS0.3VDDIVNote 1
Logic-High Output VoltageVOHIOH = -1.0mA0.8VDDIVDDIVNote 1
Logic-Low Output VoltageVOLIOL = +1.0mAVSS0.2VDDIVNote 1
Logic-High Input CurrentIIHVIN = VDDI1uANote 1
Logic-Low Input CurrentIILVIN = VSS-1uANote 1
Input Leakage CurrentIILIOH = -1.0mA-0.1+0.1uANote 1
VCOM Voltage
VCOM AmplitudeVCOM-2-0.425V
Source driver
Source Output RangeVsout0.1GVDDV
Gamma Reference VoltageGVDD3.154.7V
Source Output Settling TimeTrBelow with 99% precision20usNote 2
Output Offset VoltageVoffset35mVNote 3
Table 2 DC Characteristic Notes: 1. TA = -30 to 85 °C. 2. Source channel loading= 2KΩ+12pF/channel, Gate channel loading=5KΩ+40pF/channel. 3. The Max. value is between measured point of source output and gamma setting value. 4. VGH setting condition is AVDD=4.7V, the Max and Min VGH voltage depend on AVDD setting, VGH-VGL can not large than 30V. ## 7.3 Power Consumption Ta=25°C, Frame rate = 60Hz, Bare die, the registers setting are IC default setting.
Operation ModeImageCurrent Consumption
TypicalMaximum
IDDI (mA)IDD (mA)IDDI (mA)IDD (mA)
Normal ModeNote 10.010.90.022
Note 20.010.90.022
Partial + Idle Mode (40 lines)Note 10.010.80.022
Note 20.010.80.022
Sleep-In ModeN/A0.0050.0150.010.03
Table 3 Power Consumption ## Notes: 1. All pixels black. 2. All pixels white. 3. The Current Consumption is DC characteristics of ST7735S. 4. Typical: VDDI=1.8V, VDD=2.75V; Maximum: VDDI=1.65 to 3.7V, VDD=2.5 to 4.8V ## 8 Timing chart 8.1 Parallel Interface Characteristics: 18, 16, 9 or 8-bit Bus (8080 Series MCU Interface) ![](images/664c464e6c4ef9ecb64cf6171b08457bdcbb746172a1af79c7262986824d2c2c.jpg)
flowchart This diagram illustrates the timing and signal flow relationships between various signal processing stages (CSX, D/CX, WRX, D[17:0] write, RDX, D[17:0] read) through various control signals such as TCHW, TCSH, and TCSF.
Figure 1 Parallel Interface Timing Characteristics (8080 Ceries MCU Interface) Ta=25 °C, VDDI=1.65\~3.7V, VDD=2.5\~4.8V
SignalSymbolParameterMinMaxUnitDescription
D/CXTASTAddress Setup Ttime0ns-
TAHTAddress Hold Time (Write/Read)10ns
CSXTCHWChip Select “H” Pulse Width0ns-
TCSChip Select Setup Time (Write)15ns
TRCSChip Select Setup Time (Read ID)45ns
TRCSFMChip Select Setup time (Read FM)355ns
TCSFChip Select Wait Time (Write/Read)10ns
TCSHChip Select Hold Time10ns
WRXTWCWrite Cycle66ns
TWRHControl Pulse “H” Duration15ns
TWRLControl Pulse “L” Duration15ns
RDX (ID)TRCRead Cycle (ID)160nsWhen Read ID Data
TRDHControl Pulse “H” Duration (ID)90ns
TRDLControl Pulse “L” Duration (ID)45ns
RDX (FM)TRCFMRead Cycle (FM)450nsWhen Read from Frame Memory
TRDHFMControl Pulse “H” Duration (FM)90ns
TRDLFMControl Pulse “L” Duration (FM)355ns
D[17:0]TDSTData Setup Time10nsFor CL=30pF
TDHTData Hold Time10ns
TRATRead Access Time (ID)40ns
TRATFMRead Access Time (FM)340ns
TODHOutput Disable Time2080ns
Table 4 8080 Parallel Interface Characteristics ![](images/8a6c696243eea6ceb27c8d9b444e233fee5fe319663ad129a12896822ed70892.jpg) Figure 2 Rising And Falling Timing for Input And Output Signal ![](images/150c6a07eaea24db93ad0c93e82e847cb0bd5694b99834fc1a12258596fa8995.jpg)
text_image CSX V_IH V_IL T_CSF V_IL V_IH V_IL Min. =5ns T_CHW
Figure 3 Chip Selection (CSX) Timing ![](images/781506a18cf4455aaed7810690e5dda2fc1fc4e9b39017a5df1501b507e8b98f.jpg)
text_image WRX VIH VIL VIL RDX VIH VIL TWRH VIL TWRH/TRDHFM
Figure 4 Write-to-Read And Read-to-Write Timing Note: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. 8.2 Parallel Interface Characteristics: 18, 16, 9 or 8-bit Bus (6800 Series MCU Interface) ![](images/fbe6a83a74fd5268fcdad82bce9e6681a15817f29e59a61ffa8c6a67904a7ca3.jpg)
flowchart This diagram illustrates the timing and signal flow relationships between various signal waveforms (CSX, D/CX, /WX, E, D[17:0] write, RX, E, D[17:0] read) over time intervals such as TCHW, TCS, TCSF, and TAST.
Figure 5 Parallel Interface Timing Characteristics (6800-Series MCU Interface) Ta=25 °C, VDDI=1.65\~3.7V, VDD=2.5\~4.8V
SignalSymbolParameterMinMaxUnitDescription
D/CX $T_{AST}$ Address Setup Time0ns-
$T_{AHT}$ Address Hold Time (Write/Read)10ns
CSX $T_{CHW}$ Chip Select “H” Pulse Width0ns-
$T_{CS}$ Chip Select Setup Time (Write)15ns
$T_{RCS}$ Chip Select Setup Time (Read ID)45ns
$T_{RCSFM}$ Chip Select Setup Time (Read FM)355ns
$T_{CSF}$ Chip Select wait Time (Write/Read)10ns
$T_{CSH}$ Chip Select Hold Time10ns
WRX $T_{WC}$ Write Cycle66ns
$T_{WRH}$ Control Pulse “H” Duration15ns
$T_{WRL}$ Control Pulse “L” Duration15ns
RDX (ID) $T_{RC}$ Read Cycle (ID)160nsWhen Read ID Data
$T_{RDH}$ Control Pulse “H” Duration (ID)90ns
$T_{RDL}$ Control Pulse “L” Duration (ID)45ns
RDX (FM) $T_{RCFM}$ Read Cycle (FM)450nsWhen Read From Frame Memory
$T_{RDHFM}$ Control Pulse “H” Duration (FM)90ns
$T_{RDLFM}$ Control Pulse “L” Duration (FM)355ns
D[17:0] $T_{DST}$ Data Setup Time10nsFor Maximum CL=30pFFor Minimum CL=8pF
$T_{DHT}$ Data Hold Time10ns
$T_{ODH}$ Output Disable Time2080ns
Note: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals Table 5 6800 Parallel Interface Characteristics ## 8.3 Serial Interface Characteristics (3-line Serial) ![](images/7e4ecc2cdc38e56edb5eb35b649a1ec2a57f1d9a06d8c4cda510c0dd2245ef2c.jpg)
text_image CSX VIH VIL TCSS TSCYCW/TSCYCR TCSH TSCC SCL TSHW/TSHR TSLW/TSLR VIH VIL TSDS TSDH SDA VIH VIL TACC TOH VIH VIL SDA (DOUT)
Figure 6 3-line Serial Interface Timing Ta=25 °C, VDDI=1.65\~3.7V, VDD=2.5\~4.8V
SignalSymbolParameterMinMaxUnitDescription
CSXTCSSChip Select Setup Time (Write)15ns
TCSHChip Select Hold Time (Write)15ns
TCSSChip Select Setup Time (Read)60ns
TSCCChip Select Hold Time (Read)65ns
TCHWChip Select “H” pulse width40ns
SCLTSCYCWSerial Clock Cycle (Write)66ns
TSHWSCL “H” Pulse Width (Write)15ns
TSLWSCL “L” Pulse Width (Write)15ns
TSCYCRSerial Clock Cycle (Read)150ns
TSHRSCL “H” Pulse Width (Read)60ns
TSLRSCL “L” Pulse Width (Read)60ns
SDA (DIN) (DOUT)TSDSData Setup Time10nsFor Maximum CL=30pF For Minimum CL=8pF
TSDHData Hold Time10ns
TACCAccess Time1050ns
TOHOutput Disable Time1550ns
Table 6 3-line Serial Interface Characteristics Note : The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. ## 8.4 Serial Interface Characteristics (4-line Serial) ![](images/5c5404aed8d675eb3dbb7a4df2bbd664bf2f2478bc8671b461cbaa3e04dbb9d7.jpg)
flowchart ```mermaid graph LR CSX["CSX"] -->|VIH| VIL["VIL"] CSX -->|VIL| CSX CSX -->|TCSCW/TSCYCR| TCSH["TCSH"] CSX -->|TCHW| TCHW SCL["SCL"] -->|VIH| TDCS["TDCS"] SCL -->|VIL| TDCS SCL -->|TDSW/TSHR| TSHW["TSHW/TSHR"] SCL -->|TSLW/TSLR| TSLW SCL -->|VIH| TSCC["TSCC"] SCL -->|VIL| TSCC SDA["SDA"] -->|VIH| VIL["VIL"] SDA -->|VIL| VIL SDA -->|TSDS| TSDH["TSDH"] SDA -->|TSDH| TSDH D/CX["D/CX"] -->|VIH| VIL["VIL"] DCx["D/CX"] -->|VIL| VIL DCx -->|TDCH| TDCH DCx -->|TACC| TACC DCx -->|TOH| TOH SDA(DOUT) -->|VIH| VIL["VIL"] SDA(DOUT) -->|VIL| VIL ```
Figure 7 4-line Serial Interface Timing Ta=25 °C, VDDI=1.65\~3.7V, VDD=2.5\~4.8V
SignalSymbolParameterMINMAXUnitDescription
CSXTCSSChip Select Setup Time (Write)45ns
TCSHChip Select Hold Time (Write)45ns
TCSSChip Select Setup Time (Read)60ns
TSCCChip Select Hold Time (Read)65ns
TCHWChip Select “H” Pulse Width40ns
SCLTSCYCWSerial Clock Cycle (Write)66ns-Write Command & Data Ram
TSHWSCL “H” Pulse Width (Write)15ns
TSLWSCL “L” Pulse Width (Write)15ns
TSCYCRSerial Clock Cycle (Read)150ns-Read Command & Data Ram
TSHRSCL “H” Pulse Width (Read)60ns
TSLRSCL “L” Pulse Width (Read)60ns
D/CXTDCSD/CX Setup Time10ns
TDCHD/CX Hold Time10ns
SDA (DIN) (DOUT)TSDSData Setup Time10nsFor Maximum CL=30pF For Minimum CL=8pF
TSDHData Hold Time10ns
TACCAccess Time1050ns
TOHOutput Disable Time1550ns
Table 7 4-line Serial Interface Characteristics Note : The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. ## 9 Function Description ## 9.1 Interface Type Selection The selection of given interfaces are done by setting IM2, IM1, and IM0 pins as shown in following table.
P68IM2IM1IMOInterfaceRead Back Selection
-0--3-line Serial InterfaceVia the Read Instruction
01008080 MCU 8-bit ParallelRDX Strobe (8-bit Read Data and 8-bit Read Parameter)
01018080 MCU 16-bit ParallelRDX Strobe (16-bit Read Data and 8-bit Read Parameter)
01108080 MCU 9-bit ParallelRDX Strobe (9-bit Read Data and 8-bit Read Parameter)
01118080 MCU 18-bit ParallelRDX Strobe (18-bit Read Data and 8-bit Read Parameter)
-0--3-line Serial InterfaceVia the Read Instruction
11006800 MCU 8-bit ParallelE Strobe (8-bit Read Data and 8-bit Read Parameter)
11016800 MCU 16-bit ParallelE Strobe (16-bit Read Data and 8-bit Read Parameter)
11106800 MCU 9-bit ParallelE Strobe (9-bit Read Data and 8-bit Read Parameter)
11116800 MCU 18-bit ParallelE Strobe (18-bit Read Data and 8-bit Read Parameter)
Table 8 Interface Type Selection
P68IM2IM1IM0InterfaceRDXWRXD/CXRead back selection
-0--3-line Serial InterfaceNote1Note1SCLD[17:1]: Unused, D0: SDA
01008080 8-bit ParallelRDXWRXD/CXD[17:8]: Unused, D7-D0: 8-bit Data
01018080 16-bit ParallelRDXWRXD/CXD[17:16]: Unused, D15-D0: 16-bit Data
01108080 9-bit ParallelRDXWRXD/CXD[17:9]: Unused, D8-D0: 9-bit Data
01118080 18-bit ParallelRDXWRXD/CXD17-D0: 18-bit Data
-0--3-line Serial InterfaceNote1D/CXSCLD[17:1]: Unused, D0: SDA
11006800 8-bit ParallelEWRXRSD[17:8]: Unused, D7-D0: 8-bit Data
11016800 16-bit ParallelEWRXRSD[17:16]: Unused, D15-D0: 16-bit Data
11106800 9-bit ParallelEWRXRSD[17:9]: Unused, D8-D0: 9-bit Data
11116800 18-bit ParallelEWRXRSD17-D0: 18-bit Data
Table 9 Pin Connection According to Various MCU Interface Note: Unused pins can be open, or connected to DGND or VDDI. ## 9.2 8080-series MCU Parallel Interface (P68 = '0') The MCU can use one of following interfaces: 11-lines with 8-data parallel interface, 12-lines with 9-data parallel interface, 19-line with 16-data parallel interface or 21-lines with 18-data parallel interface. The chip-select CSX (active low) enables/disables the parallel interface. RESX (active low) is an external reset signal. WRX is the parallel data write enable, RDX is the parallel data read enable and D[17:0] is parallel data bus. The LCD driver reads the data at the rising edge of WRX signal. The D/CX is the data/command flag. When D/CX='1', D[17:0] bits is either display data or command parameter. When D/C='0', D[17:0] bits is command. The interface functions of 8080-series parallel interface are given in following table..
IM2IM1IM0InterfaceD/CXRDXWRXRead Back Selection
1008-bit Parallel01↑Write 8-bit Command (D7 to D0)
11↑Write 8-bit Display Data or 8-bit Parameter (D7 to D0)
1↑1Read 8-bit Display Data (D7 to D0)
1↑1Read 8-bit Parameter or Status (D7 to D0)
10116-bit Parallel01↑Write 8-bit Command (D7 to D0)
11↑Write 16-bit Display Data or 8-bit Parameter (D15 to D0)
1↑1Read 16-bit Display Data (D15 to D0)
1↑1Read 8-bit Parameter or Status (D7 to D0)
1109-bit Parallel01↑Write 8-bit Command (D7 to D0)
11↑Write 9-bit Display Data or 8-bit Parameter (D8 to D0)
1↑1Read 9-bit Display Data (D8 to D0)
1↑1Read 8-bit Parameter or Status (D7 to D0)
11118-bit Parallel01↑Write 8-bit Command (D7 to D0)
11↑Write 18-bit Display Data or 8-bit Parameter (D17 to D0)
1↑1Read 18-bit Display Data (D17 to D0)
1↑1Read 8-bit Parameter or Status (D7 to D0)
Table 10 The Function of 8080-series Parallel Interface Note: applied for command code: DAh, DBh, DCh, 04h, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh ## 9.2.1 Write Cycle Sequence The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write cycle (WRX high-low-high sequence) consists of 3 control signals (D/CX, RDX, WRX) and data signals (D[17:0]). D/CX bit is a control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is low (='0') and vice versa it is data (='1'). ![](images/ecfc08124bf26d8b01c2b4fd1974a52e2924a6c3b4fbca223ab145157681c135.jpg) Figure 8 8080-series WRX Protocol Note: WRX is an unsynchronized signal (It can be stopped). ![](images/919ab43914137f54a9f774a6ede91a2dff4559930570cd40fe89a9a00ba2127f.jpg)
flowchart ```mermaid graph LR subgraph sg_1_Byte_Command["1 Byte Command"] S["S"] --> CMD["CMD"] CMD --> PA1["PA1"] PA1 --> CMD CMD --> PA2["PA2"] PA2 --> P["P"] end subgraph sg_2_Byte_Command["2 Byte Command"] CSX["CSX"] --> D/CX["D/CX"] DCx["D/CX"] --> RDX["RDX"] RDX --> WRX["WRX"] WRX --> HostD[""Host D[17:0"] Host to LCD"] HostD --> HostZ[""Driver D[17:0"] LCD to Host"] end subgraph N Byte Command PA1 --> PA2["PA1"] PA2 --> PA2 PA2 --> PA1["PA1"] PA1 --> PA2["PA2"] PA2 --> PA1["PA1"] PA1 --> P["P"] end S --> CMD CMD --> PA1 PA1 --> CMD CMD --> PA2 PA2 --> PA1 PA1 --> P P --> HostZ HostZ --> HostZ ```
Figure 9 8080-series Parallel Bus Protocol, Write to Register or Display RAM ## 9.2.2 Read Cycle Sequence The read cycle (RDX high-low-high sequence) means that the host reads information from LCD driver via interface. The driver sends data (D[17:0]) to the host when there is a falling edge of RDX and the host reads data when there is a rising edge of RDX. ![](images/2f754df3ad1bcacf47eab2d4a575941d68e38f859826450600ee18b16d87bbed.jpg) Figure 10 8080-series RDX Protocol Note: RDX is an unsynchronized signal (It can be stopped). ![](images/bbe2e4eca548b1e9337a497e6eb7667c7cca650da278b10c99f3d3fda0698709.jpg)
flowchart ```mermaid graph LR subgraph Read Parameter direction TB S["S"] --> CMD["CMD"] CMD --> DM["DM"] PA["PA"] --> CMD CMD --> DM & data["DM & data"] DMData["DM & data"] --> Data["Data"] Data --> P["P"] end subgraph Read Display Data direction TB P --> P["P"] P --> D["CX"]["D/CX"] D["CX"] --> RDX["RDX"] RDX --> WRX["WRX"] WRX --> D["17:0"]["D["17:0"]"] D["17:0"] --> HostToLCD[""Host D[17:0"] Host to LCD"] HostToLCD --> DriverToHost[""Driver D[17:0"] LCD to Host"] DriverToHost --> PA1["PA1"] PA1 --> DM["DM"] PA1 --> Hi-Z["Hi-Z"] HiZ["Hi-Z"] --> CMD CMD --> Hi-Z["Hi-Z"] HiZ --> PA1 PA1 --> DM["DM"] DM --> PA1 PA1 --> PAN_2["PAN_2"] PA1 --> PA1 PA1 --> PAN_1["PAN_1"] PAN_2 --> P["P"] P --> HostToLCD HostToLCD --> DriverToHost end ```
Figure 11 8080-series Parallel Bus Protocol, Read Data from Register or Display RAM ## 9.3 6800-series MCU Parallel Interface (P68 = '1') The MCU uses one of following interface: 11-lines with 8-data parallel interface, 12-lines with 9-data parallel interface, 19-lines with 16-data parallel interface, or 21-lines with 18-data parallel interface. The chip-select CSX(active low) enables and disables the parallel interface. RESX (active low) is an external reset signal. The R/WX is the Read/Write flag and D[17:0] is parallel data bus. The LCD driver reads the data at the falling edge of E signal when R/WX= '1' and Writes the data at the falling of the E signal when R/WX='0'. The D/CX is the data/command flag. When D/CX='1', D[17:0] bits are display RAM data or command parameters. When D/C= '0', D[17:0] bits are commands. The 6800-series bi-directional interface can be used for communication between the micro controller and LCD driver. The selection of this interface is done when P68 pin is high state (VDDI). Interface bus width can be selected with IM2, IM1 and IM0. The interface functions of 6800-series parallel interface are given in Table11.
P68IM2IM1IM0InterfaceD/CXR/WXEFunction
11008-bit Parallel00↓Write 8-bit Command (D7 to D0)
10↓Write 8-bit Display Data or 8-bit Parameter (D7 to D0)
11↓Read 8-bit Display Data (D7 to D0)
11↓Read 8-bit Parameter or Status (D7 to D0)
110116-bit Parallel00↓Write 8-bit Command (D7 to D0)
10↓Write 16-bit Display Data or 8-bit Parameter (D15 to D0)
11↓Read 16-bit Display Data (D15 to D0)
11↓Read 8-bit Parameter or Status (D7 to D0)
11109-bit Parallel00↓Write 8-bit Command (D7 to D0)
10↓Write 9-bit Display Data or 8-bit Parameter (D8 to D0)
11↓Read 9-bit Display Data (D8 to D0)
11↓Read 8-bit Parameter or Status (D7 to D0)
111118-bit Parallel00↓Write 8-bit Command (D7 to D0)
10↓Write 18-bit Display Data or 8-bit Parameter (D17 to D0)
11↓Read 18-bit Display Data (D17 to D0)
11↓Read 8-bit Parameter or Status (D7 to D0)
Table 11 The Function of 6800-series Parallel Interface Note: applied for command code: DAh, DBh, DCh, 04h, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh. ## 9.3.1 Write Cycle Sequence The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write cycle (E low-high-low sequence) consists of 3 control signals (D/CX, E, R/WX) and data signals (D[17:0]). D/CX bit is a control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is low (='0') and vice versa it is data (='1'). ![](images/3cc63442b9fdcb5fd2c84eaab5c9827c56154229e938fbdbeb11103cb10dd2c0.jpg)
flowchart ```mermaid graph LR A["R/WX"] -->|“0”| B["E"] B --> C[""D[17:0"]"] C --> D[""The host starts to control D[17:0"] lines when there is a rising edge of the E."] D --> E[""The display writes D[17:0"] lines when there is a falling edge of E."] E --> F[""The host stops to control D[17:0"] lines."] ```
Figure 12 6800-series Write Protocol Note: E is an unsynchronized signal (It can be stopped) ![](images/8feb0d2ab998eda6fb5f03e64eceb60df9d8712fa8a741e2423f306a9581473e.jpg)
flowchart This diagram illustrates the data transmission and reception logic for a 1-byte command system, showing the sequence of commands (D, CX, R/WX, Host, Driver) and their corresponding data paths (CMD, PA1, PA2, P) across a 2-byte command.
Figure 13 6800-series Parallel Bus Protocol, Write to Register or Display RAM ## 9.3.2 Read Cycle Sequence The read cycle (E low-high-low sequence) means that the host reads information from LCD driver via interface. The driver sends data (D[17:0]) to the host when there is a rising edge of E and the host reads data when there is a falling edge of E. ![](images/21be869a88ec3506be06b7b03b08fdd279e99a08834c39b0b45ffb90f82bc134.jpg)
flowchart ```mermaid graph LR A["RWX"] -->|“1”| B["E"] B --> C[""D[17:0"]"] C --> D[""The driver starts to control D[17:0"] lines when there is a rising edge of the E."] D --> E[""The host read D[17:0"] lines when there is a falling edge of RDX."] E --> F[""The driver stops to control D[17:0"] lines."] ```
Figure 14 6800-series Read Protocol Note: E is an unsynchronized signal (It can be stopped) ![](images/e1c33c8719a56debd3fadc676f987a0e250998d8013546ed6fd3efba36b8a437.jpg)
flowchart This diagram illustrates the data flow and signal processing logic for a system, showing how read parameters (D[17:0], RESX, CSX, D/CX, R/WX, E) are processed through various channels (CMD, DM, PA, etc.) to generate signals on D[17:0], D/CX, R/WX, and E pins.
Figure 15 6800-series Parallel Bus Protocol, Read Data form Register or Display RAM ## 9.4 Serial Interface The selection of this interface is done by IM2. See the Table 12.
IM24WSPIInterfaceRead Back Selection
003-line Serial InterfaceVia the Read Instruction (8-bit, 24-bit and 32-bit Read Parameter)
014-line Serial InterfaceVia the Read Instruction (8-bit, 24-bit and 32-bit Read Parameter)
Table 12 Selection of Serial Interface The serial interface is either 3-lines/9-bits or 4-lines/8-bts bi-directional interface for communication between the micro controller and the LCD driver. The 3-lines serial interface use: CSX (chip enable), SCL (serial clock) and SDA (serial data input/output), and the 4-lines serial interface use: CSX (chip enable), D/CX (data/command flag), SCL (serial clock) and SDA (serial data input/output). Serial clock (SCL) is used for interface with MCU only, so it can be stopped when no communication is necessary. ## 9.4.1 Command Write Mode The write mode of the interface means the micro controller writes commands and data to the LCD driver. 3-lines serial data packet contains a control bit D/CX and a transmission byte. In 4-lines serial interface, data packet contains just transmission byte and control bit D/CX is transferred by the D/CX pin. If D/CX is “low”, the transmission byte is interpreted as a command byte. If D/CX is “high”, the transmission byte is stored in the display data RAM (memory write command), or command register as parameter. Any instruction can be sent in any order to the driver. The MSB is transmitted first. The serial interface is initialized when CSX is high. In this state, SCL clock pulse or SDA data have no effect. A falling edge on CSX enables the serial interface and indicates the start of data transmission. ![](images/922b45de7447e8fa5ff8307048807fb8a87fadace63f6a9a91496c823713f858.jpg)
flowchart ```mermaid graph TD subgraph sg_3_line["3-line"] A["D/CX"] --> B["D7"] A --> C["D6"] A --> D["D5"] A --> E["D4"] A --> F["D3"] A --> G["D2"] A --> H["D1"] A --> I["D0"] end subgraph sg_4_line["4-line"] J["D7"] --> K["D6"] J --> L["D5"] J --> M["D4"] J --> N["D3"] J --> O["D2"] J --> P["D1"] J --> Q["D0"] end subgraph sg_3_line_2["3-line"] R["D/CX"] --> S["D7"] R --> T["D6"] R --> U["D5"] R --> V["D4"] R --> W["D3"] R --> X["D2"] R --> Y["D1"] R --> Z["D0"] end subgraph sg_4_line_2["4-line"] AA["D7"] --> AB["D6"] AA --> AC["D5"] AA --> AD["D4"] AA --> AE["D3"] AA --> AF["D2"] AA --> AG["D1"] AA --> AH["D0"] end subgraph sg_4_line_3["4-line"] AI["D7"] --> AJ["D6"] AI --> AK["D5"] AI --> AL["D4"] AI --> AM["D3"] AI --> AN["D2"] AI --> AO["D1"] AI --> AP["D0"] end ```
Figure 16 Serial Interface Data Stream Format When CSX is “high”, SCL clock is ignored. During the high period of CSX the serial interface is initialized. At the falling edge of CSX, SCL can be high or low (see Figure 17). SDA is sampled at the rising edge of SCL. D/CX indicates whether the byte is command (D/CX='0') or parameter/RAM data (D/CX='1'). D/CX is sampled when first rising edge of SCL (3-lines serial interface) or 8th rising edge of SCL (4-lines serial interface). If CSX stays low after the last bit of command/data byte, the serial interface expects the D/CX bit (3-lines serial interface) or D7 (4-lines serial interface) of the next byte at the next rising edge of SCL.. ![](images/c6508fa0bcfebc6f946b9002698456cb516379a2905292e051968a27cb71c45f.jpg)
flowchart ```mermaid graph LR subgraph Host S["S"] --> TB["TB"] TB --> P["P"] end subgraph CSX CSX["CSX"] --> S S --> D/C["D/C"] DC["D/C"] --> D7["D7"] D7 --> D6["D6"] D6 --> D5["D5"] D5 --> D4["D4"] D4 --> D3["D3"] D3 --> D2["D2"] D2 --> D1["D1"] D1 --> D0["D0"] D0 --> D/C["D/C"] DC --> D7["D7"] D7 --> D6["D6"] D6 --> D5["D5"] D5 --> D4["D4"] D4 --> D3["D3"] D3 --> D2["D2"] D2 --> D1["D1"] D1 --> D0["D0"] D0 --> SCL["SCL"] end subgraph SDA SCL --> SCL end subgraph Command SCL --> SCL end subgraph Command_Parameter["Command/Parameter"] SCL --> SCL end ```
Figure 17 3-line Serial Interface Write Protocol (Write to Register with Control Bit in Transmission) ![](images/73c6f052d20d248f217c814e7948d1157b96c9eb21236e3e744ae26c473be987.jpg)
flowchart This diagram illustrates the protocol stack structure for a host system (MCU to driver), showing the sequence of commands and data paths between CSX, SDA, D/CX, and SCL.
Figure 18 4-line Serial Interface Write Protocol (Write to Register with Control Bit in Transmission) ## 9.4.2 Read Functions The read mode of the interface means that the micro controller reads register value from the driver. To achieve read function, the micro controller first has to send a command (read ID or register command) and then the following byte is transmitted in the opposite direction. After that CSX is required to go to high before a new command is send (see the below figure). The driver samples the SDA (input data) at rising edge of SCL, but shifts SDA (output data) at the falling edge of SCL. Thus the micro controller is supported to read at the rising edge of SCL. After the read status command has been sent, the SDA line must be set to tri-state no later than at the falling edge of SCL of the last bit. ## 9.4.3 3-line Serial Protocol 3-line Serial Protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh Command: 8-bit Read): ![](images/fca701c2986779076101cf757a6a4aacb806faeb80ce2d6d56d3094a551bed13.jpg)
flowchart ```mermaid graph LR subgraph Host S["S"] --> TB["TB"] S --> P["P"] P --> S CSX["CSX"] --> S SCL["SCL"] --> S SDA["SDA"] --> D_C["D/C"] D_C --> D7["D7"] D7 --> D6["D6"] D6 --> D5["D5"] D5 --> D4["D4"] D4 --> D3["D3"] D3 --> D2["D2"] D2 --> D1["D1"] D1 --> D0["D0"] Hi_Z["Hi-Z"] --> D7 Hi_Z --> D6 Hi_Z --> D5 Hi_Z --> D4 Hi_Z --> D3 Hi_Z --> D2 Hi_Z --> D1 Hi_Z --> D0 D7 --> D7 D6 --> D6 D5 --> D5 D4 --> D4 D3 --> D3 D2 --> D2 D1 --> D1 D0 --> D0 D7 --> D7 D6 --> D6 D5 --> D5 D4 --> D4 D3 --> D3 D2 --> D2 D1 --> D1 D0 --> D0 end subgraph Driver SDA["SDA (SDO)"] --> Hi_Z["Hi-Z"] Hi_Z --> D7 Hi_Z --> D6 Hi_Z --> D5 Hi_Z --> D4 Hi_Z --> D3 Hi_Z --> D2 Hi_Z --> D1 Hi_Z --> D0 end ```
3-line Serial Protocol (for RDDID Command: 24-bit Read) ![](images/9ac5d5bd785a32410d83d32f7a9625397a776b7deed3a8e0963dc13f5cd0cda4.jpg)
flowchart This diagram illustrates the timing and state transitions of a system involving Host and Driver components, including CSX, SCL, SDA, and D3-D2, with a dummy clock cycle indicated.
3-line Serial Protocol (for RDDST Command: 32-bit Read) ![](images/7da9298b0180f85e721452445302735c265b1dede8f31e223a273d782da18acd.jpg)
flowchart ```mermaid graph LR subgraph Host S["S"] --> TB["TB"] TB --> P["P"] P --> S["S"] end subgraph Driver SDA["SDA"] --> HiZ["Hi-Z"] HiZ --> D31["D31"] D31 --> D30["D30"] D30 --> D29["D29"] D29 --> D28["D28"] D28 --> D3["D3"] D3 --> D2["D2"] D2["D2"] --> D1["D1"] D1 --> D0["D0"] D0 --> HiZ HiZ --> D3 HiZ --> D3 D3 --> D0 D0 --> HiZ HiZ --> D3 D3 --> D2 D2 --> D1 D1 --> D0 end ```
Figure 19 3-line Serial Interface Read Protocol ## 9.4.4 4-line Serial Protocol 4-line Serial Protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh Command: 8-bit Read): ![](images/148aec0e7703adac51afea12a93fcbf21d5a280a736f5d3367fa15a5181a2efc.jpg)
flowchart This diagram illustrates the data flow and synchronization logic between a Host (CSX, SCL, D/CX, SDA) and a Driver (SDA/DOUT), showing transitions between states (S, TB, P, S), clock signals, and data flow patterns.
4-line Serial Protocol (for RDDID Command: 24-bit Read) ![](images/11eae392773c9055cd3e5d992cfd860da94f101621dc97b3e5720f19fe0f9e2e.jpg)
flowchart This diagram illustrates the timing and state transitions of a host system (CSX, SCL, D/CX) and a driver (SDA/DOUT) over time, showing transitions between states such as S, TB, P, S, and D.
4-line Serial Protocol (for RDDST Command: 32-bit Read) ![](images/d85b2f6e3175cd4b1957689b42e41d2e64d6e0a55fbbe46f49abbc310f3218da.jpg)
flowchart ```mermaid graph LR subgraph Host S["S"] --> TB["TB"] S --> P["P"] S --> S["S"] S --> CSX["CSX"] S --> SCL["SCL"] SCL --> D["D"] D --> CX["D/CX"] CX --> O["O"] O --> SDA["SDA (DIN)"] SDA --> D7["D7"] D7 --> D6["D6"] D6 --> D5["D5"] D5 --> D4["D4"] D4 --> D3["D3"] D3 --> D2["D2"] D2 --> D1["D1"] D1 --> D0["D0"] D0 --> HiZ["Hi-Z"] HiZ --> D31["D31"] D31 --> D30["D30"] D30 --> D29["D29"] D29 --> D28["D28"] D28 --> D3["D3"] D3 --> D2["D2"] D2 --> D1["D1"] D1 --> D0["D0"] D0 --> D7["D7"] D7 --> D7 D7 --> SDA SDA --> DOUT["SDA (DOUT)"] DOUT --> HiZ end subgraph Driver HiZ --> D31 D31 --> D30 D30 --> D29 D29 --> D28 D28 --> D3 D3 --> D2 D2 --> D1 D1 --> D0 D0 --> D7 D7 --> D7 end ```
Figure 20 4-line Serial Interface Read Protocol ## 9.5 Data Transfer Break and Recovery If there is a break in data transmission by RESX pulse, while transferring a command or frame memory data or multiple parameter command data, before Bit D0 of the byte has been completed, then driver will reject the previous bits and have reset the interface such that it will be ready to receive command data again when the chip select line (CSX) is next activated after RESX have been HIGH state. See the following example ![](images/4b43babb5a2d31260a1184cfd9856ad4a95323a7e827713267b73a829e07da1a.jpg)
flowchart This diagram illustrates the protocol stack structure for a host driver system, showing the sequence of commands (S, TB, P) and data streams (CSX, RESX, SCL, SDA). It highlights the idle state of SCL and SDA during RESX and the invalid state of SCL and SDA during RESX.
Figure 21 Serial Bus Protocol, Write Mode – Interrupted by RESX If there is a break in data transmission by CSX pulse, while transferring a command or frame memory data or multiple parameter command data, before Bit D0 of the byte has been completed, then driver will reject the previous bits and have reset the interface such that it will be ready to receive the same byte re-transmitted when the chip select line (CSX) is next activated. See the following example ![](images/43a8a872ab4801ad4b00a04f559fba57a77b8fdc97061424be9667293c7f51f6.jpg)
flowchart This diagram illustrates the architecture of a Host Driver (MCU) system, showing the signal flow between CSX, SCL, and SDA components through a transmission block (TB), a break, and a command parameter data transmission.
Figure 22 Serial Bus Protocol, Write Mode – Interrupted by CSX If 1, 2 or more parameter commands are being sent and a break occurs while sending any parameter before the last one and if the host then sends a new command rather than re-transmitting the parameter that was interrupted, then the parameters that were successfully sent are stored and the parameter where the break occurred is rejected. The interface is ready to receive next byte as shown below. ![](images/a43323c34f837635f4a7b2199415628ae2c941bfe821a15e304f0cf8c7565661.jpg) Figure 23 Write Interrupts Recovery (Serial Interface) If a 2 or more parameter commands are being sent and a break occurs by the other command before the last one is sent, then the parameters that were successfully sent are stored and the other parameter of that command remains previous value. ![](images/ede45b78877575a7338b9aa3504ad54d0c4914be5ed4e61982c7e59171cad8ba.jpg)
flowchart ```mermaid graph LR A["CMD1"] --> B["Para11"] B --> C["CMD2"] C --> D["CMD1"] D --> E["Para11"] E --> F["Para12"] F --> G["Para13"] G --> H["Command1"] C -.->|break| B D -.->|Command1 with 1st parameter (para11) should be executed again to write remained parameter (para12, para13)"] ```
Figure 24 Write Interrupts Recovery (Both Serial and Parallel Interface) ## 9.6 Data Transfer Pause It will be possible when transferring a command, frame memory data or multiple parameter data to invoke a pause in the data transmission. If the chip select line is released after a whole byte of a frame memory data or multiple parameter data has been completed, then driver will wait and continue the frame memory data or parameter data transmission from the point where it was paused. If the chip select Line is released after a whole byte of a command has been completed, then the display module will receive either the command's parameters (if appropriate) or a new command when the chip select line is next enabled as shown below. This applies to the following 4 conditions: 1) Command-Pause-Command 2) Command-Pause-Parameter 3) Parameter-Pause-Command 4) Parameter-Pause-Parameter ## 9.6.1 Serial Interface Pause ![](images/349c335e409020dafb59e21a0c8133847e07203ebb23b95b0cae163dc2136b18.jpg)
flowchart ```mermaid graph LR subgraph Host S["S"] --> TB["TB"] TB --> Pause["Pause"] Pause --> TB TB --> P["P"] end subgraph CSX CSX["CSX"] --> S S --> D7["D7"] D7 --> D6["D6"] D6 --> D5["D5"] D5 --> D4["D4"] D4 --> D3["D3"] D3 --> D2["D2"] D2 --> D1["D1"] D1 --> D0["D0"] D0 --> D7["D7"] D7 --> D6["D6"] D6 --> D5["D5"] D5 --> D4["D4"] D4 --> D3["D3"] D3 --> D2["D2"] D2 --> D1["D1"] D1 --> D0["D0"] D0 --> SCL["SCL"] end subgraph SCL SCL --> S S --> S S --> SCL end subgraph Command SCL --> SCL["SCL"] SCL --> SCL SCL --> SCL end subgraph SDA SCL --> SDA["SDA"] SCL --> SDA SDA --> D7 SDA --> D6 SDA --> D5 SDA --> D4 SDA --> D3 SDA --> D2 SDA --> D1 SDA --> D0 SCL --> SCL end subgraph P SCL --> P["P"] P --> P end SCL --> P SCL --> SCL ```
Figure 25 Serial Interface Pause Protocol (Pause by CSX) ## 9.6.2 Parallel Interface Pause ![](images/449b3dbc4d27fe29f4eee487af7111ab8e6e290cef3594795e377f8963cda06b.jpg)
flowchart This diagram illustrates the timing and state transitions of a system across five key components: CSX, D/CX, RDX, WRX, and D[17:0]. It highlights specific events such as 'Pause' and 'Command/Parameter' transitions between states.
Figure 26 Parallel Bus Pause Protocol (Paused by CSX) ## 9.7 Data Transfer Modes The module has three kinds color modes for transferring data to the display RAM. These are 12-bit color per pixel, 16-bit color per pixel and 18-bit color per pixel. The data format is described for each interface. Data can be downloaded to the frame memory by 2 methods. ## 9.7.1 Method 1 The image data is sent to the frame memory in successive frame writes, each time the frame memory is filled, the frame memory pointer is reset to the start point and the next frame is written.
StartStop
Start frameMemory writeFrame 1Image dataFrame 2Image dataFrame 3Image dataAny command
## 9.7.2 Method 2 The image data is sent and at the end of each frame memory download, a command is sent to stop frame memory write. Then start memory write command is sent, and a new frame is downloaded. ![](images/2063661fbb70bf7547ec489996e73b91026b758196a94cdeb44075a8ad4b8aa4.jpg) Note 1: These apply to all data transfer Color modes on both serial and parallel interfaces. Note 2: The frame memory can contain both odd and even number of pixels for both methods. Only complete pixel data will be stored in the frame memory. ## 9.8 Data Color Coding ## 9.8.1 8-bit Parallel Interface (IM2, IM1, IM0= "100") Different display data formats are available for three Colors depth supported by listed below. - 4k Colors, RGB 4,4,4-bit Input. - 65k Colors, RGB 5,6,5-bit Input. - 262k Colors, RGB 6,6,6-bit Input. 9.8.2 8-bit Data Bus for 12-bit/Pixel (RGB 4-4-4-bit Input), 4K-Colors, 3AH= "03h" ![](images/884ca7549a3cddc3c1461d44091d47a00435ad140f750ee4dd4a139f22a87e7e.jpg)
flowchart This diagram illustrates the 8080-series control pins and pixel mapping for a 4096 color data mapping system, showing the sequence of data bits from input to output.
Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data. Note 2: 3-time transfer is used to transmit 1 pixel data with the 12-bit color depth information. Note 3: '-' = Don't care - Can be set to '0' or '1' ## 9.8.3 8-bit Data Bus for 16-bit/Pixel (RGB 5-6-5-bit Input), 65K-Colors, 3AH= "05h" There is 1 pixel (3 sub-pixels) per 2-byte ![](images/9462d6321be18dd5c41bbda4ee7ebf26a678dac85e769b37c85c1d53c1e2b9de.jpg)
flowchart This diagram illustrates the 8080-series control pins for a 65k color data mapping system, showing the bit allocation and data mapping logic.
Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green and MSB=Bit 4, LSB=Bit 0 for Red and Blue data. Note 2: 2-times transfer is used to transmit 1 pixel data with the 16-bit color depth information. Note 3: '-' = Don't care - Can be set to '0' or '1' ## 9.8.4 8-bit Data Bus for 18-bit/Pixel (RGB 6-6-6-bit Input), 262K-Colors, 3AH= "06h" There is 1 pixel (3 sub-pixels) per 3-bytes. ![](images/739a6fd431d22fdfa9ef88fc4bd9e2531da79617fd7a3102bc9c09923da2cd97.jpg)
flowchart ```mermaid graph LR subgraph Control_Pins D7["D7"] -->|0| R1["R1, Bit 5"] D6["D6"] -->|0| R1["R1, Bit 4"] D5["D5"] -->|1| R1["R1, Bit 3"] D4["D4"] -->|0| R1["R1, Bit 2"] D3["D3"] -->|1| R1["R1, Bit 1"] D2["D2"] -->|1| R1["R1, Bit 0"] D1["D1"] -->|0| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| 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-| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| -| ```
Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: '-' = Don't care - Can be set to '0' or '1' ## 9.8.5 16-Bit Parallel Interface (IM2,IM1, IM0= "101") Different display data formats are available for three colors depth supported by listed below. - 4k Colors, RGB 4,4,4-bit Input - 65k Colors, RGB 5,6,5-bit Input - 262k Colors, RGB 6,6,6-bit Input ## 9.8.6 16-bit Data Bus for 12-bit/Pixel (RGB 4-4-4-bit Input), 4K-Colors, 3AH= "03h" There is 1 pixel (3 sub-pixels) per 1 byte ![](images/af3ef450df6180dd16f535265fac576c3f65e8c0f602b0d01eac3c488011f2cb.jpg)
flowchart This diagram illustrates a 8080-series control pin configuration for a 4096 color data mapping system, showing the sequence of data bits (R1-R4) and their mapping to a frame memory.
Note 1: The data order is as follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data. Note 2: 1-times transfer (D11 to D0) is used to transmit 1 pixel data with the 12-bit color depth information. ## 9.8.7 16-bit Data Bus for 16-bit/Pixel (RGB 5-6-5-bit Input), 65K-Colors, 3AH= "05h" There is 1 pixel (3 sub-pixels) per 1 byte ![](images/8c95be61fbd1facd13d28f2275df261be15518f0fdd4cb1826a5f40af4985fdf.jpg)
flowchart ```mermaid graph LR subgraph Control_Pins D15["D15"] --> R1["R1, Bit 4"] D14["D14"] --> R1["R1, Bit 3"] D13["D13"] --> R1["R1, Bit 2"] D12["D12"] --> R1["R1, Bit 1"] D11["D11"] --> R1["R1, Bit 0"] D10["D10"] --> G1["G1, Bit 5"] D9["D9"] --> G1["G1, Bit 4"] D8["D8"] --> G1["G1, Bit 3"] D7["D7"] --> G1["G1, Bit 2"] D6["D6"] --> G1["G1, Bit 1"] D5["D5"] --> G1["G1, Bit 0"] D4["D4"] --> B1["B1, Bit 4"] D3["D3"] --> B1["B1, Bit 3"] D2["D2"] --> B1["B1, Bit 2"] D1["D1"] --> B1["B1, Bit 1"] D0["D0"] --> B1["B1, Bit 0"] end subgraph Mapping Pixel_n["Pixel n"] Pixel_n+1["Pixel n+1"] Pixel_n+2["Pixel n+2"] Pixel_n+3["Pixel n+3"] end Pixel_n -->|16 bits| Mapping PixelN1["Pixel_n+1"] -->|16 bits| Mapping PixelN2["Pixel_n+2"] -->|16 bits| Mapping PixelN3["Pixel_n+3"] -->|16 bits| Mapping Mapping["Look-up table for 65k color data mapping (16 bits to 18 bits)"] -->|18 bits| FrameMemory["Frame memory"] FrameMemory --> R1["R1"] FrameMemory --> G1["G1"] FrameMemory --> B1["B1"] FrameMemory --> R2["R2"] FrameMemory --> G2["G2"] FrameMemory --> B2["B2"] FrameMemory --> R3["R3"] FrameMemory --> G3["G3"] FrameMemory --> B3["B3"] ```
Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for Red and Blue data. Note 2: 1-times transfer (D15 to D0) is used to transmit 1 pixel data with the 16-bit color depth information. Note 3: '-' = Don't care - Can be set to '0' or '1' ## 9.8.8 16-bit Data Bus for 18-bit/Pixel (RGB 6-6-6-bit Input), 262K-Colors, 3AH= "06h" There are 2 pixels (6 sub-pixels) per 3 bytes ![](images/a0dfd286edcec70993fa5e9390be43cfdc8f935731f2f63ff1411b5c10290ba2.jpg)
flowchart This diagram illustrates the 8080-series control pins for a 8-bit frame memory, showing the signal flow from input/output to data processing and final memory layout.
Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: '-' = Don't care - Can be set to '0' or '1' ## 9.8.9 9-Bit Parallel Interface (IM2, IM1, IM0="110") Different display data formats are available for three colors depth supported by listed below. -262k colors, RGB 6,6,6-bit input ## 9.8.10 Write 9-bit Data for RGB 6-6-6-bit Input (262k-color) There is 1 pixel (6 sub-pixels) per 3 bytes ![](images/1a71d85872e4de1a9e4dff0455f7531d46a1f4fe245407d15d6b013c84accd0e.jpg)
flowchart This diagram illustrates the 8080-series control pins for a frame memory system, showing the signal flow from input to output through various bit positions and bit ranges.
Note 1: The data order is as follows, MSB=D8, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3: '-' = Don't care - Can be set to '0' or '1' ## 9.8.11 18-Bit Parallel Interface (IM2, IM1, IM0="111") Different display data formats are available for three colors depth supported by listed below. - 4k Colors, RGB 4,4,4-bit Input - 65k Colors, RGB 5,6,5-bit Input - 262k Colors, RGB 6,6,6-bit Input. ## 9.8.12 18-bit Data Bus for 12-bit/Pixel (RGB 4-4-4-bit Input), 4K-Colors, 3AH="03h" There is 1 pixel (3 sub-pixels) per 1 byte ![](images/b0e86f42177f65297b54c600bb92de36e74d677276b5f379bbc1fa1c3dc742a7.jpg)
flowchart ```mermaid graph LR subgraph Control_Pins direction TB D17["D17"] --> P1["P1"] D16["D16"] --> P2["P2"] D15["D15"] --> P3["P3"] D14["D14"] --> P4["P4"] D13["D13"] --> P5["P5"] D12["D12"] --> P6["P6"] D11["D11"] --> P7["P7"] D10["D10"] --> P8["P8"] D9["D9"] --> P9["P9"] D8["D8"] --> P10["P10"] D7["D7"] --> P11["P11"] D6["D6"] --> P12["P12"] D5["D5"] --> P13["P13"] D4["D4"] --> P14["P14"] D3["D3"] --> P15["P15"] D2["D2"] --> P16["P16"] D1["D1"] --> P17["P17"] D0["D0"] --> P18["P18"] end P1 -->|"12 bits"| Table["Look-Up Table for 4096 Color data mapping (12 bits to 18 bits)"] P2 -->|"12 bits"| Table P3 -->|"12 bits"| Table P4 -->|"12 bits"| Table P5 -->|"12 bits"| Table P6 -->|"12 bits"| Table P7 -->|"12 bits"| Table P8 -->|"12 bits"| Table P9 -->|"12 bits"| Table P10 -->|"12 bits"| Table P11 -->|"12 bits"| Table P12 -->|"12 bits"| Table P13 -->|"12 bits"| Table P14 -->|"12 bits"| Table P15 -->|"12 bits"| Table P16 -->|"12 bits"| Table P17 -->|"12 bits"| Table P18 -->|"12 bits"| Table P19 -->|"12 bits"| Table P20 -->|"12 bits"| Table P21 -->|"12 bits"| Table P22 -->|"12 bits"| Table P23 -->|"12 bits"| Table P24 -->|"12 bits"| Table P25 -->|"12 bits"| Table P26 -->|"12 bits"| Table P27 -->|"12 bits"| Table P28 -->|"12 bits"| Table P29 -->|"12 bits"| Table P30 -->|"12 bits"| Table P31 -->|"12 bits"| Table P32 -->|"12 bits"| Table P33 -->|"12 bits"| Table P34 -->|"12 bits"| Table P35 -->|"12 bits"| Table P36 -->|"12 bits"| Table P37 -->|"12 bits"| Table P38 -->|"12 bits"| Table P39 -->|"12 bits"| Table P40 -->|"12 bits"| Table P41 -->|"12 bits"| Table P42 -->|"12 bits"| Table P43 -->|"12 bits"| Table P44 -->|"12 bits"| Table P45 -->|"12 bits"| Table P46 -->|"12 bits"| Table P47 -->|"12 bits"| Table P48 -->|"12 bits"| Table P49 -->|"12 bits"| Table P50 -->|"12 bits"| Table P51 -->|"12 bits"| Table P52 -->|"12 bits"| Table P53 -->|"12 bits"| Table P54 -->|"12 bits"| Table P55 -->|"12 bits"| Table P56 -->|"12 bits"| Table P57 -->|"12 bits"| Table P58 -->|"12 bits"| Table P59 -->|"12 bits"| Table P60 -->|"12 bits"| Table P61 -->|"12 bits"| Table P62 -->|"12 bits"| Table P63 -->|"12 bits"| Table P64 -->|"12 bits"| Table P65 -->|"12 bits"| Table P66 -->|"12 bits"| Table P67 -->|"12 bits"| Table P68 -->|"12 bits"| Table P69 -->|"12 bits"| Table P70 -->|"12 bits"| Table P71 -->|"12 bits"| Table P72 -->|"12 bits"| Table P73 -->|"12 bits"| Table P74 -->|"12 bits"| Table P75 -->|"12 bits"| Table P76 -->|"12 bits"| Table P77 -->|"12 bits"| Table P78 -->|"12 bits"| Table P79 -->|"12 bits"| Table P80 -->|"12 bits"| Table P81 -->|"12 bits"| Table P82 -->|"12 bits"| Table P83 -->|"12 bits"| Table P84 -->|"12 bits"| Table P85 -->|"12 bits"| Table P86 -->|"12 bits"| Table P87 -->|"12 bits"| Table P88 -->|"12 bits"| Table P89 -->|"12 bits"| Table P90 -->|"12 bits"| Table P91 -->|"12 bits"| Table P92 -->|"12 bits"| Table P93 -->|"12 bits"| Table P94 -->|"12 bits"| Table P95 -->|"12 bits"| Table P96 -->|"12 bits"| Table P97 -->|"12 bits"| Table P98 -->|"12 bits"| Table P99 -->|"12 bits"| Table P100 -->|"12 bits"| Table P101 -->|"12 bits"| Table P102 -->|"12 bits"| Table P103 -->|"12 bits"| Table P104 -->|"12 bits"| Table P105 -->|"12 bits"| Table P106 -->|"12 bits"| Table P107 -->|"12 bits"| Table P108 -->|"12 bits"| Table P109 -->|"12 bits"| Table P110 -->|"12 bits"| Table P111 -->|"12 bits"| Table P112 -->|"12 bits"| Table P113 -->|"12 bits"| Table P114 -->|"12 bits"| Table P115 -->|"12 bits"| Table P116 -->|"12 bits"| Table P117 -->|"12 bits"| Table P118 -->|"12 bits"| Table P119 -->|"12 bits"| Table P120 -->|"12 bits"| Table P121 -->|"12 bits"| Table P122 -->|"12 bits"| Table P123 -->|"12 bits"| Table P124 -->|"12 bits"| Table P125 -->|"12 bits"| Table P126 -->|"12 bits"| Table P127 -->|"12 bits"| Table P128 -->|"12 bits"| Table P129 -->|"12 bits"| Table P130 -->|"12 bits"| Table P131 -->|"12 bits"| Table P132 -->|"12 bits"| Table P133 -->|"12 bits"| Table P134 -->|"12 bits"| Table P135 -->|"12 bits"| Table P136 -->|"12 bits"| Table P137 -->|"12 bits"| Table P138 -->|"12 bits"| Table P139 -->|"12 bits"| Table P140 -->|"12 bits"| Table P141 -->|"12 bits"| Table P142 -->|"12 bits"| Table P143 -->|"12 bits"| Table P144 -->|"12 bits"| Table P145 -->|"12 bits"| Table P146 -->|"12 bits"| Table P147 -->|"12 bits"| Table P148 -->|"12 bits"| Table P149 -->|"12 bits"| Table P150 -->|"12 bits"| Table P151 -->|"12 bits"| Table P152 -->|"12 bits"| Table P153 -->|"12 bits"| Table P154 -->|"12 bits"| Table P155 -->|"12 bits"| Table P156 -->|"12 bits"| Table P157 -->|"12 bits"| Table P158 -->|"12 bits"| Table P159 -->|"12 bits"| Table P160 -->|"12 bits"| Table P161 -->|"12 bits"| Table P162 -->|"12 bits"| Table P163 -->|"12 bits"| Table P164 -->|"12 bits"| Table P165 -->|"12 bits"| Table P166 -->|"12 bits"| Table P167 -->|"12 bits"| Table P168 -->|"12 bits"| Table P169 -->|"12 bits"| Table P170 -->|"12 bits"| Table P171 -->|"12 bits"| Table P172 -->|"12 bits"| Table P173 -->|"12 bits"| Table P174 -->|"12 bits"| Table P175 -->|"12 bits"| Table P176 -->|"12 bits"| Table P177 -->|"12 bits"| Table P178 -->|"12 bits"| Table P179 -->|"12 bits"| Table P180 -->|"12 bits"| Table P181 -->|"12 bits"| Table P182 -->|"12 bits"| Table P183 -->|"12 bits"| Table P184 -->|"12 bits"| Table P185 -->|"12 bits"| Table P186 -->|"12 bits"| Table P187 -->|"12 bits"| Table P188 -->|"12 bits"| Table P189 -->|"12 bits"| Table P190 -->|"12 bits"| Table P191 -->|"12 bits"| Table P192 -->|"12 bits"| Table P193 -->|"12 bits"| Table P194 -->|"12 bits"| Table P195 -->|"12 bits"| Table P196 -->|"12 bits"| Table P197 -->|"12 bits"| Table P198 -->|"12 bits"| Table P199 -->|"12 bits"| Table P200 -->|"12 bits"| Table P201 -->|"12 bits"| Table P202 -->|"12 bits"| Table P203 -->|"12 bits"| Table P204 -->|"12 bits"| Table P205 -->|"12 bits"| Table P206 -->|"12 bits"| Table P207 -->|"12 bits"| Table P208 -->|"12 bits"| Table P209 -->|"12 bits"| Table P210 -->|"12 bits"| Table P211 -->|"12 bits"| Table P212 -->|"12 bits"| Table P213 -->|"12 bits"| Table P214 -->|"12 bits"| Table P215 -->|"12 bits"| Table P216 -->|"12 bits"| Table P217 -->|"12 bits"| Table P218 -->|"12 bits"| Table P219 -->|"12 bits"| Table P220 -->|"12 bits"| Table P221 -->|"12 bits"| Table P222 -->|"12 bits"| Table P223 -->|"12 bits"| Table P224 -->|"12 bits"| Table P225 -->|"12 bits"| Table P226 -->|"12 bits"| Table P227 -->|"12 bits"| Table P228 -->|"12 bits"| Table P229 -->|"12 bits"| Table P230 -->|"12 bits"| Table P231 -->|"12 bits"| Table P232 -->|"12 bits"| Table P233 -->|"12 bits"| Table P234 -->|"12 bits"| Table P235 -->|"12 bits"| Table P236 -->|"12 bits"| Table P237 -->|"12 bits"| Table P238 -->|"12 bits"| Table P239 -->|"12 bits"| Table P240 -->|"12 bits"| Table P241 -->|"12 bits"| Table P242 -->|"12 bits"| Table P243 -->|"12 bits"| Table P244 -->|"12 bits"| Table P245 -->|"12 bits"| Table P246 -->|"12 bits"| Table P247 -->|"12 bits"| Table P248 -->|"12 bits"| Table P249 -->|"12 bits"| Table P250 -->|"12 bits"| Table P251 -->|"12 bits"| Table P252 -->|"12 bits"| Table P253 -->|"12 bits"| Table P254 -->|"12 bits"| Table P255 -->|"12 bits"| Table P256 -->|"12 bits"| Table P257 -->|"12 bits"| Table P258 -->|"12 bits"| Table P259 -->|"12 bits"| Table P260 -->|"12 bits"| Table P261 -->|"12 bits"| Table P262 -->|"12 bits"| Table P263 -->|"12 bits"| Table P264 -->|"12 bits"| Table P265 -->|"12 bits"| Table P266 -->|"12 bits"| Table P267 -->|"12 bits"| Table P268 -->|"12 bits"| Table P269 -->|"12 bits"| Table P270 -->|"12 bits"| Table P271 -->|"12 bits"| Table P272 -->|"12 bits"| Table P273 -->|"12 bits"| Table P274 -->|"12 bits"| Table P275 -->|"12 bits"| Table P276 -->|"12 bits"| Table P277 -->|"12 bits"| Table P278 -->|"12 bits"| Table P279 -->|"12 bits"| Table P280 -->|"12 bits"| Table P281 -->|"12 bits"| Table P282 -->|"12 bits"| Table P283 -->|"12 bits"| Table P284 -->|"12 bits"| Table P285 -->|"12 bits"| Table P286 -->|"12 bits"| Table P287 -->|"12 bits"| Table P288 -->|"12 bits"| Table P289 -->|"12 bits"| Table P290 -->|"12 bits"| Table P291 -->|"12 bits"| Table P292 -->|"12 bits"| Table P293 -->|"12 bits"| Table P294 -->|"12 bits"| Table P295 -->|"12 bits"| Table P296 -->|"12 bits"| Table P297 -->|"12 bits"| Table P298 -->|"12 bits"| Table P299 -->|"12 bits"| Table P300 -->|"12 bits"| Table P301 -->|"12 bits"| Table P302 -->|"12 bits"| Table P303 -->|"12 bits"| Table P304 -->|"12 bits"| Table P305 -->|"12 bits"| Table P306 -->|"12 bits"| Table P307 -->|"12 bits"| Table P308 -->|"12 bits"| Table P309 -->|"12 bits"| Table P310 -->|"12 bits"| Table P311 -->|"12 bits"| Table P312 -->|"12 bits"| Table P313 -->|"12 bits"| Table P314 -->|"12 bits"| Table P315 -->|"12 bits"| Table P316 -->|"12 bits"| Table P317 -->|"12 bits"| Table P318 -->|"12 bits"| Table P319 -->|"12 bits"| Table P320 -->|"12 bits"| Table P321 -->|"12 bits"| Table P322 -->|"12 bits"| Table P323 -->|"12 bits"| Table P324 -->|"12 bits"| Table P325 -->|"12 bits"| Table P326 -->|"12 bits"| Table P327 -->|"12 bits"| Table P328 -->|"12 bits"| Table P329 -->|"12 bits"| Table P330 -->|"12 bits"| Table P331 -->|"12 bits"| Table P332 -->|"12 bits"| Table P333 -->|"12 bits"| Table P334 -->|"12 bits"| Table P335 -->|"12 bits"| Table P336 -->|"12 bits"| Table P337 -->|"12 bits"| Table P338 -->|"12 bits"| Table P339 -->|"12 bits"| Table P340 -->|"12 bits"| Table P341 -->|"12 bits"| Table P342 -->|"12 bits"| Table P343 -->|"12 bits"| Table P344 -->|"12 bits"| Table P345 -->|"12 bits"| Table P346 -->|"12 bits"| Table P347 -->|"12 bits"| Table P348 -->|"12 bits"| Table P349 -->|"12 bits"| Table P350 -->|"12 bits"| Table P351 -->|"12 bits"| Table P352 -->|"12 bits"| Table P353 -->|"12 bits"| Table P354 -->|"12 bits"| Table P355 -->|"12 bits"| Table P356 -->|"12 bits"| Table P357 -->|"12 bits"| Table P358 -->|"12 bits"| Table P359 -->|"12 bits"| Table P360 -->|"12 bits"| Table P361 -->|"12 bits"| Table P362 -->|"12 bits"| Table P363 -->|"12 bits"| Table P364 -->|"12 bits"| Table P365 -->|"12 bits"| Table P366 -->|"12 bits"| Table P367 -->|"12 bits"| Table P368 -->|"12 bits"| Table P369 -->|"12 bits"| Table P370 -->|"12 bits"| Table P371 -->|"12 bits"| Table P372 -->|"12 bits"| Table P373 -->|"12 bits"| Table P374 -->|"12 bits"| Table P375 -->|"12 bits"| Table P376 -->|"12 bits"| Table P377 -->|"12 bits"| Table P378 -->|"12 bits"| Table P379 -->|"12 bits"| Table P380 -->|"12 bits"| Table P381 -->|"12 bits"| Table P382 -->|"12 bits"| Table P383 -->|"12 bits"| Table P384 -->|"12 bits"| Table P385 -->|"12 bits"| Table P386 -->|"12 bits"| Table P387 -->|"12 bits"| Table P388 -->|"12 bits"| Table P389 -->|"12 bits"| Table P390 -->|"12 bits"| Table P391 -->|"12 bits"| Table P392 -->|"12 bits"| Table P393 -->|"12 bits"| Table P394 -->|"12 bits"| Table P395 -->|"12 bits"| Table P396 -->|"12 bits"| Table P397 -->|"12 bits"| Table P398 -->|"12 bits"| Table P399 -->|"12 bits"| Table P400 -->|"12 bits"| Table P401 -->|"12 bits"| Table P402 -->|"12 bits"| Table P403 -->|"12 bits"| Table P404 -->|"12 bits"| Table P405 -->|"12 bits"| Table P406 -->|"12 bits"| Table P407 -->|"12 bits"| Table P408 -->|"12 bits"| Table P409 -->|"12 bits"| Table P410 -->|"12 bits"| Table P411 -->|"12 bits"| Table P412 -->|"12 bits"| Table P413 -->|"12 bits"| Table P414 -->|"12 bits"| Table P415 -->|"12 bits"| Table P416 -->|"12 bits"| Table P417 -->|"12 bits"| Table P418 -->|"12 bits"| Table P419 -->|"12 bits"| Table P420 -->|"12 bits"| Table P421 -->|"12 bits"| Table P422 -->|"12 bits"| Table P423 -->|"12 bits"| Table P424 -->|"12 bits"| Table P425 -->|"12 bits"| Table P426 -->|"12 bits"| Table P427 -->|"12 bits"| Table P428 -->|"12 bits"| Table P429 -->|"12 bits"| Table P430 -->|"12 bits"| Table P431 -->|"12 bits"| Table P432 -->|"12 bits"| Table P433 -->|"12 bits"| Table P434 -->|"12 bits"| Table P435 -->|"12 bits"| Table P436 -->|"12 bits"| Table P437 -->|"12 bits"| Table P438 -->|"12 bits"| Table P439 -->|"12 bits"| Table P440 -->|"12 bits"| Table P441 -->|"12 bits"| Table P442 -->|"12 bits"| Table P443 -->|"12 bits"| Table P444 -->|"12 bits"| Table P445 -->|"12 bits"| Table P446 -->|"12 bits"| Table P447 -->|"12 bits"| Table P448 -->|"12 bits"| Table P449 -->|"12 bits"| Table P450 -->|"12 bits"| Table P451 -->|"12 bits"| Table P452 -->|"12 bits"| Table P453 ```
Note 1: The data order is as follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data. Note 2: 1-times transfer is used to transmit 1 pixel data with the 12-bit color depth information. ## 9.8.13 18-bit Data Bus for 16-bit/Pixel (RGB 5-6-5-bit Input), 65K-Colors, 3AH="05h" There is 1 pixel (3 sub-pixels) per 1 byte ![](images/895b648941171bad60add9c973e5df1f3dc640624ed1c9e05b2ba044f53d5d0c.jpg)
flowchart ```mermaid graph LR subgraph Input A["RESX"] --> B[""IM[2:0"]"] B --> C["CSX"] C --> D["D/CX"] D --> E["WRX"] E --> F["RDX"] end subgraph Control G["D17"] --> H["D17"] H --> I["D16"] I --> J["D15"] J --> K["D14"] K --> L["D13"] L --> M["D12"] M --> N["D11"] N --> O["D10"] O --> P["D9"] P --> Q["D8"] Q --> R["D7"] R --> S["D6"] S --> T["D5"] T --> U["D4"] U --> V["D3"] V --> W["D2"] W --> X["D1"] X --> Y["D0"] end subgraph Mapping Z["Pixel n"] -->|16 bits| AA["Look-up table for 65k color data mapping (16 bits to 18 bits)"] AA -->|16 bits| AB["Frame memory"] AB --> AC["R1, G1, B1, R2, G2, B2, R3, G3, B3"] end ```
Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for Red and Blue data. Note 2: 1-time transfer is used to transmit 1 pixel data with the 16-bit color depth information. ## 9.8.14 18-bit Data Bus for 18-bit/Pixel (RGB 6-6-6-bit Input), 262K-Colors, 3AH="06h" There is 1 pixel (3 sub-pixels) per 1 byte ![](images/17ec8bdfbd52961b86fc8b001d488c7ccc8c5ec50920b188cb7f1792ac3aded9.jpg)
flowchart ```mermaid graph LR subgraph Input A["RESX"] -->|1"| B[""IM[2:0"]"111"] B --> C["CSX"] C --> D["D/CX"] D --> E["WRX"] E --> F["RDX"] end subgraph Control G["D17"] --> H["R1, Bit 5"] H --> I["R2, Bit 5"] I --> J["R3, Bit 5"] J --> K["R4, Bit 5"] L["D16"] --> M["R1, Bit 4"] M --> N["R2, Bit 4"] N --> O["R3, Bit 4"] O --> P["R4, Bit 4"] Q["D15"] --> R["R1, Bit 3"] R --> S["R2, Bit 3"] S --> T["R3, Bit 3"] T --> U["R4, Bit 3"] V["D14"] --> W["R1, Bit 2"] W --> X["R2, Bit 2"] X --> Y["R3, Bit 2"] Y --> Z["R4, Bit 2"] AA["D13"] --> AB["R1, Bit 1"] AB --> AC["R2, Bit 1"] AC --> AD["R3, Bit 1"] AD --> AE["R4, Bit 1"] AF["D12"] --> AG["R1, Bit 0"] AG --> AH["R2, Bit 0"] AH --> AI["R3, Bit 0"] AI --> AJ["R4, Bit 0"] AK["D11"] --> AL["G1, Bit 5"] AL --> AM["G2, Bit 5"] AM --> AN["G3, Bit 5"] AN --> AO["G4, Bit 5"] AP["D10"] --> AQ["G1, Bit 4"] AQ --> AR["G2, Bit 4"] AR --> AS["G3, Bit 4"] AS --> AT["G4, Bit 4"] AU["D9"] --> AV["G1, Bit 3"] AV --> AW["G2, Bit 3"] AW --> AX["G3, Bit 3"] AX --> AY["G4, Bit 3"] AZ["D8"] --> BA["G1, Bit 2"] BA --> AC["G2, Bit 2"] AC --> AD["G3, Bit 2"] AD --> AE["G4, Bit 2"] AF["D7"] --> AG["0"] AG --> AH["G1, Bit 1"] AH --> AI["G2, Bit 1"] AI --> AJ["G3, Bit 1"] AJ --> AK["G4, Bit 1"] AL["D6"] --> AM["0"] AM --> ANF["G1, Bit 0"] ANF --> AO["G2, Bit 0"] AO --> AP["G3, Bit 0"] AP --> AQY["G4, Bit 0"] AQY --> AR["D5"] AR --> ASF["1"] ASF --> ABF["B1, Bit 5"] ABF --> ACF["B2, Bit 5"] ACF --> ABG["B3, Bit 5"] ABG --> ACH["B4, Bit 5"] ACH --> ADY["0"] ADY --> AEY["B1, Bit 4"] AEY --> AFS["B2, Bit 4"] AFS --> AFG["B3, Bit 4"] AFG --> AHI["B4, Bit 4"] AHI --> ADZ["D3"] ADZ --> AEZ["B1, Bit 3"] AEZ --> AFB["B2, Bit 3"] AFB --> AFG["B3, Bit 3"] AFG --> AHI["B4, Bit 3"] AHI --> ADY["1"] ADY --> AEY["B1, Bit 2"] AEY --> AFGF["B2, Bit 2"] AFGF --> AFGF["B3, Bit 2"] AFGF --> AFGFF["B4, Bit 2"] AFGFF --> ADYF["0"] ADY --> AEYF["B1, Bit 1"] AEYF --> AFGFF["B2, Bit 1"] AFGFF --> AFGFFF["B3, Bit 1"] AFGFFF["A0"] --> AEYF["B1, Bit 0"] AEYF --> AFGFFF["B2, Bit 0"] AFGFFF["A0"] --> AFGFFFF["B2, Bit 0"] AFGFFFF["A0"] --> AFGFFFFF["B3, Bit 0"] AFGFFFF["A0"] --> AFGFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A0"] --> AFGFFFFFF["B4, Bit 0"] AFGFFFFF["A ```
Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Read, Green and Blue data. Note 2: 1-times transfer (D17o D0) is used to transmit 1 pixel data with the 18-bit color depth information. ## 9.8.15 3-line Serial Interface Different display data formats are available for three colors depth supported by the LCM listed below. 4k Colors, RGB 4-4-4-bit Input 65k Colors, RGB 5-6-5-bit Input 262k Colors, RGB 6-6-6-bit Input 9.8.16 Write Data for 12-bit/Pixel (RGB 4-4-4-bit Input), 4K-Colors, 3AH="03h" ![](images/b0d8df130b911ef01bc2ab210464e2c90077e5ada11a18f8e486abbadee60d1a.jpg)
flowchart ```mermaid graph TD A["RESX"] -->|1"| B["IM2"] C["CSX"] -->|1"| D["SDA"] B -->|IM2=IM1=IMO="0"| E["SCL"] D -->|1 Pixel n| F["Look-up table for 4096 color data mapping (12 bits to 18 bits)"] F -->|12 bits| G["Frame memory"] G -->|18 bits| H["SCL"] ```
Note 1: Pixel data with the 12-bit color depth information Note 2: The most significant bits are: Rx3, Gx3 and Bx3 Note 3: The least significant bits are: Rx0, Gx0 and Bx0 9.8.17 Write Data for 16-bit/Pixel (RGB 5-6-5-bit Input), 65K-Colors, 3AH="05h" ![](images/f63dd94de518b05818246b2cea7c0b093a53d758b86697d08b154771c257ad80.jpg)
flowchart ```mermaid graph TD RESX["RESX"] --> SDA["SDA"] IM2["IM2=IM1=IM0="0""] --> SDA CSX["CSX"] --> SDA SDA --> SCL["SCL"] SCL --> Lookup["Look-up table for 65k color data mapping (16 bits to 18 bits)"] Lookup --> FrameMemory["Frame memory"] FrameMemory --> R1["R1"] FrameMemory --> G1["G1"] FrameMemory --> B1["B1"] FrameMemory --> R2["R2"] FrameMemory --> G2["G2"] FrameMemory --> B2["B2"] FrameMemory --> R3["R3"] FrameMemory --> G3["G3"] FrameMemory --> B3["B3"] ```
Note 1: Pixel data with the 16-bit color depth information Note 2: The most significant bits are: Rx4, Gx5 and Bx4 Note 3: The least significant bits are: Rx0, Gx0 and Bx0 9.8.18 Write Data for 18-bit/Pixel (RGB 6-6-6-bit Input), 262K-Colors, 3AH="06h" ![](images/69260010a6bd4eab722b818e2d8fef60f14e53ba28a2022437d1a63173ded954.jpg)
text_image RESX "1" IM2 IM2=IM1=IM0="0" CSX SDA D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0 Pixel n SCL Frame memory 18 bits R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: Pixel data with the 18-bit color depth information Note 2: The most significant bits are: Rx5, Gx5 and Bx5 Note 3: The least significant bits are: Rx0, Gx0 and Bx0 ## 9.8.19 4-line Serial Interface Different display data formats are available for three colors depth supported by the LCM listed below. 4k Colors, RGB 4-4-4-bit Input 65k Colors, RGB 5-6-5-bit Input 262k Colors, RGB 6-6-6-bit Input 9.8.20 Write Data for 12-bit/Pixel (RGB 4-4-4-bit Input), 4K-Colors, 3AH="03h" ![](images/41e88ad01d5f0119e8b1c837a627b38e117cd0ade3e03342404b48838bb64f2a.jpg)
flowchart ```mermaid graph TD RESX["RESX"] -->|1"| SDA["SDA"] IM2["IM2"] -->|1"| SDA CSX["CSX"] -->|1"| SDA D/CX["D/CX"] -->|1"| SDA SDA -->|Pixel n| LookupTable["Look-up table for 4096 color data mapping (12 bits to 18 bits)"] SCL["SCL"] -->|12 bits| LookupTable LookupTable -->|18 bits| FrameMemory["Frame memory"] FrameMemory -->|12 bits| SDA FrameMemory -->|18 bits| LookupTable ```
Note 1. pixel data with the 12-bit color depth information Note 2. The most significant bits are: Rx3, Gx3 and Bx3 Note 3. The least significant bits are: Rx0, Gx0 and Bx0 9.8.21 Write Data for 16-bit/Pixel (RGB 5-6-5-bit Input), 65K-Colors, 3AH="05h" ![](images/1fb8139c3f39df05bb34d1f9a0971df78d65495e33f7760b534682afae908568.jpg)
flowchart ```mermaid graph TD RESX["RESX"] -->|1"| SDA["SDA"] IM2["IM2"] -->|1", P68="0", IM2=IM1=IM0="0"| SDA CSX["CSX"] -->|1"| SDA D/CX["D/CX"] -->|1"| SDA SDA -->|Pixel n| SCL["SCL"] SCL -->|16 bits| LookupTable["Look-up table for 65k color data mapping (16 bits to 18 bits)"] LookupTable -->|16 bits| SCL SCL -->|16 bits| FrameMemory["Frame memory"] FrameMemory -->|18 bits| LookupTable ```
Note 1. pixel data with the 16-bit color depth information Note 2. The most significant bits are: Rx4, Gx5 and Bx4 Note 3. The least significant bits are: Rx0, Gx0 and Bx0 9.8.22 Write Data for 18-bit/Pixel (RGB 6-6-6-bit Input), 262K-Colors, 3AH="06h" ![](images/9b83dbe13662a8b81ba3f56c3e0e4e70c8a6166e80ad3de20d8850a80464b567.jpg)
text_image RESX IM2 CSX D/CX SDA Pixel n SCL Frame memory 18 bits R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1. pixel data with the 18-bit color depth information Note 2. The most significant bits are: Rx5, Gx5 and Bx5 Note 3. The least significant bits are: Rx0, Gx0 and Bx0 ## 9.9 Display Data RAM ## 9.9.1 Configuration (GM[1:0] = "00") The display module has an integrated 132x162x18-bit graphic type static RAM. This 384,912-bit memory allows storing on-chip a 132xRGBx162 image with an 18-bpp resolution (262K-color). There will be no abnormal visible effect on the display when there is a simultaneous Panel Read and Interface Read or Write to the same location of the Frame Memory. ![](images/f921d3962620b6f58950dde8cb691ed98ce083e11a9de94fcb1e86f86ce18735.jpg)
flowchart ```mermaid graph LR subgraph Host Interface MCU["MCU I/F"] LUT["LUT"] RowCounter["Row address counter"] ColumnCounter["Column address counter"] end subgraph Display RAM RAM["Display data RAM (132 x 162 x 18-bits)"] end TF_LCD["TF-LCD panel (132 x RGB x 162)"] LineCounter["Line address counter"] ScanCounter["Scan address counter"] MCU --> LUT LUT --> RowCounter RowCounter --> RAM ColumnCounter --> RAM RAM --> TF_LCD LineCounter --> TF_LCD TF_LCD --> TF_LCD ```
Figure 27 Display Data RAM Organization ## 9.9.2 Memory to Display Address Mapping ## 9.9.3 When using 128RGB x 160 resolution (GM[1:0] = "11", SMX=SMY=SRGB= '0') ![](images/5f13e3cfc873bddef651003d1afd65705966bed42875156246ba5cf00aa7f5a9.jpg) Note RA = Row Address, CA = Column Address SA = Scan Address MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command ML = Scan direction parameter, D4 parameter of MADCTL command RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command ## 9.9.4 When using 132RGB x 132resolution (GM[1:0] = "01", SMX=SMY=SRGB= '0') ![](images/af82946873a93f73f23523ce5017b91d626c59d326422452ef3bf0d538ce5b54.jpg) Note RA = Row Address, CA = Column Address SA = Scan Address MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command ML = Scan direction parameter, D4 parameter of MADCTL command RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command ## 9.9.5 When using 132RGB x 162 resolution (GM[1:0] = "00", SMX=SMY=SRGB= '0') ![](images/fa468c9e5f38bbfe05b54f4402eb0c06819c2a0b71f0e9cf3eccc80a3b8af474.jpg) Note RA = Row Address, CA = Column Address SA = Scan Address MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command ML = Scan direction parameter, D4 parameter of MADCTL command RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command ## 9.9.6 Normal Display On or Partial Mode On ## 9.9.7 When using 128RGB x 160 resolution (GM[1:0] = "11") In this mode, the content of the frame memory within an area where column pointer is 00h to 7Fh and page pointer is 00h to 9Fh is displayed. To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0). 1). Example for Normal Display On (MX=MY=ML='0', SMX=SMY='0') ![](images/be0cfa071dbae433090fea70b4bc978ebdc1202ac2ab6c185d97e05f679d9ee4.jpg)
heatmap | Time Interval | 128 Columns (Frame RAM) | 128 Columns (LCD Panel) | | :--- | :--- | :--- | | 00h | 00, 01 | 00, 01, 02, 03 | | 01h | 10, 11 | 10, 11, 12, 13 | | 02h | 20, 21 | 20, 21, 22 | | 03h | 30, 31 | 30, 31, 32 | | 04h | 40, 41 | 40, 41, 42 | | 05h | 50, 51 | 50, 51 | | 06h | 60 | 60 | | 07h | 70 | 70 | | 08h | 80 | 80 | | 09h | 90 | 90 | | 10h | 100 | 100 | | 11h | 110 | 110 | | 12h | 120 | 120 | | 13h | 130 | 130 | | 14h | 140 | 140 | | 15h | 150 | 150 | | 16h | 160 | 160 |
2). Example for Partial Display On (PSL[7:0]=04h, PEL[7:0]=9Bh, MX=MV=ML='0', SMX=SMY='0') ![](images/5a440fbd6fd010d5577a7fa8627e2f7e705ccca4f54a24f557287eaaef55a8ee.jpg)
text_image 128 Columns Scan Order 128 Columns 160 Lines 00h 01h ---- ---- 76h 77h ---- 7Fh 83h 00 01 01h 02h | 10 11 | 20 21 | 30 31 | 40 41 | 50 51 | 60 | 128 x 160 x18bit Frame RAM U0 U1 V0 V1 W0 W1 W2 X0 X1 X2 Y0 Y1 Y2 Y3 YW YX YY YZ 9Fh Z0 Z1 Z2 Z3 ZW ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX ZX 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## 9.9.8 When using 128RGB x 160 resolution (GM[1:0] = "01") In this mode, the content of the frame memory within an area where column pointer is 00h to 83h and page pointer is 00h to 83h is displayed. To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0). 1). Example for Normal Display On (MX=MY=ML='0', SMX=SMY='0') ![](images/f6903cf03ee87b187a51cb2710e51a869d24ec46dd87b847e667d63c0af77d48.jpg)
heatmap | Time Interval | Column 00h | Column 01h | Column 02h | Column 03h | Column 0W | Column 0X | Column 0Y | Column 0Z | | --- | --- | --- | --- | --- | --- | --- | --- | --- | | 00h | 00 | 01 | 02 | 03 | 0W | 0X | 0Y | 0Z | | 01h | 10 | 11 | 12 | 13 | 1W | 1X | 1Y | 1Z | | 02h | 20 | 21 | 22 | 23 | 2X | 2Y | 2Z | 3 | | 03h | 30 | 31 | 32 | 33 | 3X | 3Y | 3Z | 4 | | 04h | 40 | 41 | 42 | 43 | 4X | 4Y | 4Z | 5 | | 05h | 50 | 51 | 52 | 53 | 5Y | 5Z | 6 | 6Z | | 06h | 60 | 61 | 62 | 63 | 6 | 6 | 6 | 6 | | 07h | 7 | 7 | 7 | 7 | 7 | 7 | 7 | 7 | | 08h | S0 | S1 | S2 | S3 | S | SZ | SZ | SZ | | 09h | U0 | U1 | U2 | U3 | UY | UZ | UY | UZ | | 10h | V0 | V1 | V2 | V3 | VX | VY | VZ | VZ | | 11h | W0 | W1 | W2 | W3 | WX | WY | WZ | WZ | | 12h | X0 | X1 | X2 | X3 | XX | XY | XZ | XZ | | 13h | Y0 | Y1 | Y2 | Y3 | YW | YX | YZ | YZ | | 14h | Z0 | Z1 | Z2 | Z3 | ZW | ZX | ZY | ZZ | | 15h | 130 | 131 | 132 | 132 | 132 | 132 | 132 | 132 |
2). Example for Partial Display On (PSL[7:0]=00h, PEL[7:0]=83h, MX=MV=ML='0', SMX=SMY='0') ![](images/3ce39d0c1f7c98353ecbd6cea73f2498f4b99d21f5df16479f88144e8e165680.jpg)
heatmap | Row | Column 00h | Column 01h | Column 02 | Column 03 | Column 0W | Column 0X | Column 0Y | Column 82h | Column 83h | | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | | 1 | 00h | 01 | 02 | 03 | 0W | 0X | 0Y | 0Z | 1 | | 2 | 10 | 11 | 12 | 13 | 1W | 1X | 1Y | 1Z | 2 | | 3 | 20 | 21 | 22 | — | — | 2X | 2Y | 2Z | 3 | | 4 | 30 | 31 | 32 | — | — | 3X | 3Y | 3Z | — | | 5 | 40 | 41 | 42 | — | — | 4X | 4Y | 4Z | — | | 6 | 50 | 51 | — | — | — | — | 5Y | 5Z | — | | 7 | 60 | — | — | — | — | — | — | 6Z | — | | 8 | — | — | — | — | 132 x 132 x18 bit Frame RAM | — | — | — | — | | 9 | — | — | — | — | — | — | — | — | — | | 10 | — | — | — | — | — | — | — | — | — | | 11 | — | — | — | — | — | — | — | — | — | | 12 | — | — | — | — | — | — | — | — | — | | 13 | — | — | — | — | — | — | — | — | — | | 14 | — | — | — | — | — | — | — | — | — | | 15 | — | — | — | — | — | — | — | — | — | | 16 | — | — | — | — | — | — | — | — | — | | 17 | — | — | — | — | — | — | — | — | — | | 18 | — | — | — | — | — | — | — | — | — | | 19 | — | — | — | — | — | — | — | — | — | | 20 | — | — | — | — | — | — | — | — | — | | 21 | — | — | — | — | — | — | — | — | — | | 22 | — | — | — | — | — | — | — | — | — | | 23 | — | — | — | — | — | — | — | — | — | | 24 | — | — | — | — | — | — | — | — | — | | 25 | — | — | — | — | — | — | — | — | — | | 26 | — | — | — | — | — | — | — | — | — | | 27 | — | — | — | — | — | — | — | — | — | | 28 | — | — | — | — | — | — | — | — | — | | 29 | — | — | — | — | — | — | — | — | — | | 30 | — | — | — | — | — | — | — | — | — | | 31 | — | — | — | — | — | — | — | — | — | | 32 | — | — | — | — | — | — | — | — | — | | 33 | — | — | — | — | — | — | — | — | — | | 34 | — | — | — | — | — | — | — | — | — | | 35 | — | — | — | — | — | — | — | — | — | | 36 | — | — | — | — | — | — | — | — | — | | 37 | — | — | — | — | — | — | — | — | — | | 38 | — | — | — | — | — | — | — | — | — | | 39 | — | — | — | — | — | — | — | — | — | | 40 | — | — | — | — | — | — | — | — | — | | 41 | — | — | — | — | — | — | — | — | — | | 42 | — | — | — | — | — | — | — | — | — | | 43 | — | — | — | — | — | — | — | — | — | | 44 | — | — | — | — | — | — | — | — | — | | 45 | — | — | — | — | — | — | — | — | — | | 46 | — | — | — | — | — | — | — | — | — | | 47 | — | — | — | — | — | — | — | — | — | | 48 | — | — | — | — | — | — | — | — | — | | 49 | — | — | — | — | — | — | — | — | — | | 50 | — | — | — | — | — | — | — | — | — | | 51 | — | — | — | — | — | — | — | — | — | | 52 | — | — | — | — | — | — | — | — | — | | 53 | — | — | — | — | — | — | — | — | — | | 54 | — | — | — | — | — | — | — | — | — | | 55 | — | — | — | — | — | — | — | — | — | | 56 | — | — | — | — | — | — | — | — | — | | 57 | — | — | — | — | — | — | — | — | — | | 58 | — | — | — | — | — | — | — | — | — | | 59 | — | — | — | — | — | — | — | — | — | | 60 | — | — | — | — | — | — | — | — | — | | 61 | — | — | — | — | — | — | — | — | — | | 62 | — | — | — | — | — | — | — | — | — | | 63 | — | — | — | — | — | — | — | — | — | | 64 | — | — | — | — | — | — | — | — | — | | 65 | — | — | — | — | — | — | — | — | — | | 66 | — | — | — | — | — | — | — | — | — | | 67 | — | — | — | — | — | — | — | — | — | | 68 | — | — | — | — | — | — | — | — | — | | 69 | — | — | — | — | — | — | — | — | — | | 70 | — | — | — | — | — | — | — | — | — | | 71 | — | — | — | — | — | — | — | — | — | | 72 | — | — | — | — | — | — | — | — | — | | 73 | — | — | — | — | — | — | — | — | — | | 74 | — | — | — | — | — | — | — | — | — | | 75 | — | — | — | — | — | — | — | — | — | | 76 | — | — | — | — | — | — | — | — | — | | 77 | — | — | — | — | — | — | — | — | — | | 78 | — | — | — | — | — | — | — | — | — | | 79 | — | — | — | — | — | — | — | — | — | | 80 | — | — | — | — | — | — | — | — | — | | 81 | — | — | — | — | — | — | — | — | — | | 82 | — | — | — | — | — | — | — | — | — | | 83 | — | — | — | — | — | — | — | — | — | | 84 | — | — | — | — | — | — | — | — | — | | 85 | — | — | — | — | — | — | — | — | — | | 86 | — | — | — | — | — | — | — | — | — | | 87 | — | — | — | — | — | — | — | — | — | | 88 | — | — | — | — | — | — | — | — | — | | 89 | — | — | — | — | — | — | — | — | — | | 90 | — | — | — | — | — | — | — | — | — | | 91 | — | — | — | — | — | — | — | — | — | | 92 | — | — | — | — | — | — | — | — | — | | 93 | — | — | — | — | — | — | — | — | — | | 94 | — | — | — | — | — | — | — | — | — | | 95 | — | — | — | — | — | — | — | — | — | | 96 | — | — | — | — | — | — | — | — | — | | 97 | — | — | — | — | — | — | — | — | — | | 98 | — | — | — | — | — | — | — | — | — | | 99 | — | — | — | — | — | — | — | — | — | | 100 | — | — | — | — | — | — | — | — | — |
## 9.9.9 When using 132RGB x 162 resolution (GM[1:0] = "00") In this mode, contents of the frame memory within an area where column pointer is 00h to 83h and page pointer is 00h to A1h is displayed. To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0) 1). Example for Normal Display On (MX=MY=ML='0', SMX=SMY='0') ![](images/bea0d2303b9b8a72d3a437e60d09c4eb103d0764dddb156f244c276cce722037.jpg)
text_image 132 Columns Scan Order 132 Columns 162 Lines 00h 01h ---- ---- ---- 81h 83h 00 01 02 03 0W 0X 0Y 0Z 01h 10 11 12 13 1W 1X 1Y 1Z 02h 20 21 22 2X 2Y 2Z | 30 31 32 3X 3Y 3Z | 40 41 42 4X 4Y 4Z | 50 51 5Y 5Z | 60 61 62 | 132 x 162 x18 bit Frame RAM S0 132RGB x 162 LCD Panel U0 U1 132RGB x 162 UY UZ S0 132RGB x 162 UZ 132RGB x 162 U0 U1 132RGB x 162 UY UZ U0 V1 V2 VX VY VZ V0 V1 V2 VX VY VZ W0 W1 W2 WX WY WZ X0 X1 X2 XY XZ XZ Y0 Y1 Y2 Y3 YW YX YY YZ Z0 Z1 Z2 Z3 ZW ZX ZY ZZ 162 160 161 162 G1 G2 G3 G160 G161 G162 Non-Display area =4 lines Display area =155 lines Non-Display area =4lines
2). Example for Partial Display On (PSL[7:0]=04h, PEL[7:0]=9Dh, MX=MV=ML='0', SMX=SMY='0') ![](images/93dc8d8a847a0329891177e3c05accaa4e426cf78fee9a49b5ebeabcdd2345f3.jpg)
text_image 132 Columns Scan Order 132 Columns 162 Lines 00h 01h ---- ---- ---- ---- 81h 83h 00h 01 02 03 0W 0X 0Y 0Z 01h 10 11 12 13 1W 1X 1Y 1Z 02h 20 21 22 23 2X 2Y 2Z | 30 31 32 33 3X 3Y 3Z | 40 41 42 43 4X 4Y 4Z | 50 51 52 53 5Y 5Z | 60 61 62 63 64 65 66 67 | 70 71 72 73 74 75 76 77 78 | 80 81 82 83 84 85 86 87 88 | 90 91 92 93 94 95 96 97 98 | 100 11 12 13 14 15 16 17 18 | 190 191 192 193 194 195 196 197 | 280 281 282 283 284 285 286 287 288 | 370 371 372 373 374 375 376 377 378 | 460 461 462 463 464 465 466 467 468 | 550 551 552 553 554 555 556 557 558 | 640 641 642 643 644 645 646 647 648 | 730 731 732 733 734 735 736 737 738 | 820 821 822 823 824 825 826 827 828 | 910 911 912 913 914 915 916 917 918 | 1000 101 102 103 104 105 106 107 108 | 110 111 112 113 114 115 116 117 118 | 120 121 122 123 124 125 126 127 128 | 130 131 132 133 134 135 136 137 138 | 140 141 142 143 144 145 146 147 148 | 150 151 152 153 154 155 156 157 158 | 160 161 162 163 164 165 166 167 168 132 RGB x 162 LCD Panel Display area=162 lines G1 G2 G3 G160 G161 G162
## 9.10 Address Counter The address counter sets the addresses of the display data RAM for writing and reading. Data is written pixel-wise into the RAM matrix of DRIVER. The data for one pixel or two pixels is collected (RGB 6-6-6-bit), according to the data formats. As soon as this pixel-data information is complete the “Write access” is activated on the RAM. The locations of RAM are addressed by the address pointers. The address ranges are X=0 to X=131 (83h) and Y=0 to Y=161 (A1h). Addresses outside these ranges are not allowed. Before writing to the RAM, a window must be defined that will be written. The window is programmable via the command registers XS, YS designating the start address and XE, YE designating the end address. For example the whole display contents will be written, the window is defined by the following values: XS=0 (0h) YS=0 (0h) and XE=127 (83h), YE=161 (A1h). In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps around to YS and X increments to address the next column. In horizontal addressing mode (V=0), the X-address increments after each byte, after the last X-address (X=XE), X wraps around to XS and Y increments to address the next row. After the every last address (X=XE and Y=YE) the address pointers wrap around to address (X=XS and Y=YS). For flexibility in handling a wide variety of display architectures, the commands “CASET, RASET and MADCTL” (see section 10 command list), define flags MX and MY, which allows mirroring of the X-address and Y-address. All combinations of flags are allowed. Section 9.10 show the available combinations of writing to the display RAM. When MX, MY and MV will be changed the data bust be rewritten to the display RAM. For each image condition, the controls for the column and row counters apply as section 9.11 below
ConditionColumn CounterRow Counter
When RAMWR/RAMRD command is acceptedReturn to “Start Column (XS)”Return to “Start Row (YS)”
Complete Pixel Read / Write actionIncrement by 1No change
The Column counter value is larger than “End Column (XE)”Return to “Start Column (XS)”Increment by 1
The Column counter value is larger than “End Column (XE)” and the Row counter value is larger than “End Row (YE)”Return to “Start Column (XS)”Return to “Start Row (YS)”
## 9.11 Memory Data Write/ Read Direction The data is written in the order illustrated above. The Counter which dictates where in the physical memory the data is to be written is controlled by “Memory Data Access Control” Command, bits B5 (MV), B6 (MX), B7 (MY) as described below. ![](images/c72a2509bc2434abb7cad4c4da27c755cefd8b562a289c20da8322da3381bf59.jpg)
flowchart ```mermaid graph LR A["B"] --> B["Panel"] A --> E["E"] ```
Figure 28 Data Streaming order 9.11.1 When 128RGBx160 (GM= "11")
MVMXMYCASETRASET
000Direct to Physical Column PointerDirect to Physical Row Pointer
001Direct to Physical Column PointerDirect to (159-Physical Row Pointer)
010Direct to (127-Physical Column Pointer)Direct to Physical Row Pointer
011Direct to (127-Physical Column Pointer)Direct to (159-Physical Row Pointer)
100Direct to Physical Row PointerDirect to Physical Column Pointer
101Direct to (159-Physical Row Pointer)Direct to Physical Column Pointer
110Direct to Physical Row PointerDirect to (127-Physical Column Pointer)
111Direct to (159-Physical Row Pointer)Direct to (127-Physical Column Pointer)
9.11.2 When 132RGBx132 (GM= "01")
MVMXMYCASETRASET
000Direct to Physical Column PointerDirect to Physical Row Pointer
001Direct to Physical Column PointerDirect to (131-Physical Row Pointer)
010Direct to (131-Physical Column Pointer)Direct to Physical Row Pointer
011Direct to (131-Physical Column Pointer)Direct to (131-Physical Row Pointer)
100Direct to Physical Row PointerDirect to Physical Column Pointer
101Direct to (131-Physical Row Pointer)Direct to Physical Column Pointer
110Direct to Physical Row PointerDirect to (131-Physical Column Pointer)
111Direct to (131-Physical Row Pointer)Direct to (131-Physical Column Pointer)
9.11.3 When 132RGBx162 (GM= "00")
MVMXMYCASETRASET
000Direct to Physical Column PointerDirect to Physical Row Pointer
001Direct to Physical Column PointerDirect to (161-Physical Row Pointer)
010Direct to (131-Physical Column Pointer)Direct to Physical Row Pointer
011Direct to (131-Physical Column Pointer)Direct to (161-Physical Row Pointer)
100Direct to Physical Row PointerDirect to Physical Column Pointer
101Direct to (161-Physical Row Pointer)Direct to Physical Column Pointer
110Direct to Physical Row PointerDirect to (131-Physical Column Pointer)
111Direct to (161-Physical Row Pointer)Direct to (131-Physical Column Pointer)
Note: Data is always written to the Frame Memory in the same order, regardless of the Memory Write Direction set by MADCTL bits B7 (MY), B6 (MX), B5 (MV). The write order for each pixel unit is
D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
R5R4R3R2R1R0G5G4G3G2G1G0B5B4B3B2B1B0
One pixel unit represents 1 column and 1page counter value on the Frame Memory. 9.11.4 Frame Data Write Direction According to the MADCTL Parameters (MV, MX and MY)
Display Data DirectionMADCTL ParameterImage in the Host (MPU)Image in the Driver (DDRAM)
MVMXMY
Normal000
Y-Mirror001
X-Mirror010
X-Mirror Y-Mirror011
X-Y Exchange100
X-Y Exchange Y-Mirror101
X-Y Exchange X-Mirror110
X-Y ExchangeX-MirrorY-Mirror111
## 9.11.5 Scroll Address Circuit The circuit associates lines on DDRAM with Gate output. ST7735S processes signals for the liquid crystal display on 1-line basis. Thus, when specifying a specific area in the area scroll display or partial display, you must designate it in line. ## 9.11.6 Vertical Scroll Mode There is just one types of vertical scrolling, which are determined by the commands “Vertical Scrolling Definition” (33h) and “Vertical Scrolling Start Address” (37h) ![](images/e07f89371b2213bdde529c28c233f8c9e05c890ad72577a6c9cd2a275fba6fe2.jpg) ![](images/6afd31835a0e81259f0a898e3992fde040a8982b80ec6e5a1c0bfc5806da2210.jpg)
flowchart ```mermaid graph LR A["TFA"] --> B["VSA"] B --> C["BFA"] ```
Original ![](images/77fa1021d3a5ab142f152378ca70d8769efc8d3a4b580012c9367393b9730375.jpg)
text_image TFA VSA BFA
Rolling scrolling When Vertical Scrolling Definition Parameters (TFA+VSA+BFA) =162. In this case, 'rolling' scrolling is applied as shown below. All the memory contents will be used. Example 1) Panel size=132(RGB) x 162, TFA =3, VSA=157, BFA=2, SSA=6, MADCTR (ML) =0: Rolling Scroll ![](images/031053408307e21bdc5aa2215ddc799012c9302943b58ab1d342713e61fac8fd.jpg)
flowchart ```mermaid graph LR subgraph TFA ["TFA"] A1["00h 00h 01h 02 03 0W 0X 0Y 0Z\n01h 10 11 12 13 1W 1X 1Y 1Z\n02h 20 21 22 2 2X 2Y 2Z\n30 31 32 3X 3Y 3Z\n40 41 42 4X 4Y 4Z\n50 51 52 5Y 5Z\n60 61 62 63 64 65 66 67\n70 71 72 73 74 75 76 77 78\n80 81 82 83 84 85 86 87\n90 91 92 93 94 95 96\n100 110 120 130 140 150 160\n170 180 190 200 210 220 230 240 250 260 270 280 290 300 310 320 330 340 350 360 370 380 390 400 410 420 430 440 450 460 470 480 490 500 510 520 530 540 550 560 570 580 590 600 610 620 630 640 650 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 860 870 880 890 900 910 920 930 940 950 960 970 980 990 1000 1010 1020 1030 1040 1050 1060 1070 1080 1090 1100 1110 1120 1130 1140 1150 1160 1170 1180 1190 1200 1210 1220 1230 1240 1250 1260 1270 1280 1290 1300 1310 1320 1330 1340 1350 1360 1370 1380 1390 1400 1410 1420 1430 1440 1450 1460 1470 1480 1490 1500 1510 1520 1530 1540 1550 1560 1570 1580 1590 1600 1610 1620 1630 1640 1650 1660 1670 1680 1690 1700 1710 1720 1730 1740 1750 1760 1770 1780 1790 1800 1810 1820 1830 1840 1850 1860 1870 1880 1890 1900 1910 1920 1930 1940 1950 1960 1970 1980 1990 2000 2010 2020 2030 2040 2050 2060 2070 2080 2090 2100 2110 2120 2130 2140 2150 2160 2170 2180 2190 2200 2210 2220 2230 2240 2250 2260 2270 2280 2290 2300 2310 2320 2330 2340 2350 2360 2370 2380 2390 2400 2410 2420 2430 2440 2450 2460 2470 2480 2490 2500 2510 2520 2530 2540 2550 2560 2570 2580 2590 2600 2610 2620 2630 2640 2650 2660 2670 2680 2690 2700 2710 2720 2730 2740 2750 2760 2770 2780 2790 2800 2810 2820 2830 2840 2850 2860 2870 2880 2890 2900 2910 2920 2930 2940 2950 2960 2970 2980 2990 3000 3010 3020 3030 3040 3050 3060 3070 3080 3090 3100 3110 3120 3130 3140 3150 3160 3170 3180 3190 3200 3210 3220 3230 3240 3250 3260 3270 3280 3290 3300 3310 3320 3330 3340 3350 3360 3370 3380 3390 3400 3410 3420 3430 3440 3450 3460 3470 3480 3490 3500 3510 3520 3530 3540 3550 3560 3570 3580 3590 3600 3610 3620 3630 3640 3650 3660 3670 3680 3690 3700 3710 3720 3730 3740 3750 3760 3770 3780 3790 3800 3810 3820 3830 3840 3850 3860 3870 3880 3890 3900 3910 3920 3930 3940 3950 3960 3970 3980 3990 4000 4010 4020 4030 4040 4050 4060 4070 4080 4090 4100 4110 4120 4130 4140 4150 4160 4170 4180 4190 4200 4210 4220 4230 4240 4250 4260 4270 4280 4290 4300 4310 4320 4330 4340 4350 4360 4370 4380 4390 4400 4410 4420 4430 4440 4450 4460 4470 4480 4490 4500 4510 4520 4530 4540 4550 4560 4570 4580 4590 4600 4610 4620 4630 4640 4650 4660 4670 4680 4690 4700 4710 4720 4730 4740 4750 4760 4770 4780 4790 4800 4810 4820 4830 4840 4850 4860 4870 4880 4890 4900 4910 4920 4930 4940 4950 4960 4970 4980 4990 5000 5010 5020 5030 5040 5050 5060 5070 5080 5090 5100 5110 5120 5130 5140 5150 5160 5170 5180 5190 5200 5210 5220 5230 5240 5250 5260 5270 5280 5290 5300 5310 5320 5330 5340 5350 5360 5370 5380 5390 5400 5410 5420 5430 5440 5450 5460 5470 5480 5490 5500 5510 5520 5530 5540 5550 5560 5570 5580 5590 5600 5610 5620 5630 5640 5650 5660 5670 5680 5690 5700 5710 5720 5730 5740 5750 5760 5770 5780 5790 5800 5810 5820 5830 5840 5850 5860 5870 5880 5890 5900 5910 5920 5930 5940 5950 5960 5970 5980 5990 6000 6010 6020 6030 6040 6050 6060 6070 6080 6090 6100 6110 6120 6130 6140 6150 6160 6170 6180 6190 6200 6210 6220 6230 6240 6250 6260 6270 6280 6290 6300 6310 6320 6330 6340 6350 6360 6370 6380 6390 6400 6410 6420 6430 6440 6450 6460 6470 6480 6490 6500 6510 6520 6530 6540 6550 6560 6570 6580 6590 6600 6610 6620 6630 6640 6650 6660 6670 6680 6690 6700 6710 6720 6730 6740 6750 6760 6770 6780 6790 6800 6810 6820 6830 6840 6850 6860 6870 6880 6890 6900 6910 6920 6930 6940 6950 6960 6970 6980 6990 7000 7010 7020 7030 7040 7050 7060 7070 7080 7090 7100 7110 7120 7130 7140 7150 7160 7170 7180 7190 7200 7210 7220 7230 7240 7250 7260 7270 7280 7290 7300 7310 7320 7330 7340 7350 7360 7370 7380 7390 7400 7410 7420 7430 7440 7450 7460 7470 7480 7490 7500 7510 7520 7530 7540 7550 7560 7570 7580 7590 7600 7610 7620 7630 7640 7650 7660 7670 7680 7690 7700 7710 7720 7730 7740 7750 7760 7770 7780 7790 7800 7810 7820 7830 7840 7850 7860 7870 7880 7890 7900 7910 7920 7930 7940 7950 7960 7970 7980 7990 8000 8010 8020 8030 8040 8050 8060 8070 8080 8090 8100 8110 8120 8130 8140 8150 8160 8170 8180 8190 8200 8210 8220 8230 8240 8250 8260 8270 8280 8290 8300 8310 8320 8330 8340 8350 8360 8370 8380 8390 8400 8410 8420 8430 8440 8450 8460 8470 8480 8490 8500 8510 8520 8530 8540 8550 8560 8570 8580 8590 8600 8610 8620 8630 8640 8650 8660 8670 8680 8690 8700 8710 8720 8730 8740 8750 8760 8770 8780 8790 8800 8810 8820 8830 8840 8850 8860 8870 8880 8890 8900 8910 8920 8930 8940 8950 8960 8970 8980 8990 9000 9010 9020 9030 9040 9050 9060 9070 9080 9090 9100 9110 9120 9130 9140 9150 9160 9170 9180 9190 9200 9210 9220 9230 9240 9250 9260 9270 9280 9290 9300 9310 9320 9330 9340 9350 9360 9370 9380 9390 9400 9410 9420 9430 9440 9450 9460 9470 9480 9490 9500 9510 9520 9530 9540 9550 9560 9570 9580 9590 9600 9610 9620 9630 9640 9650 9660 9670 9680 9690 9700 9710 9720 9730 9740 9750 9760 9770 9780 9790 9800 9810 9820 9830 9840 9850 9860 9870 9880 9890 9900 9910 9920 9930 9940 9950 9960 9970 9980 9990 10000 1010 1020 1030 1040 1050 1060 1070 1080 1090 1100 1110 1120 1130 1140 1150 1160 1170 1180 1190 1200 1210 1220 1230 1240 1250 1260 1270 1280 1290 1300 1310 1320 1330 1340 1350 1360 1370 1380 1390 1400 1410 1420 1430 1440 1450 1460 1470 1480 1490 1500 1510 1520 1530 1540 1550 1560 1570 1580 1590 1600 1610 1620 1630 1640 1650 1660 1670 1680 1690 1700 1710 1720 1730 1740 1750 1760 1770 1780 1790 1800 1810 1820 1830 1840 1850 1860 1870 1880 1890 1900 1910 1920 1930 1940 1950 1960 1970 1980 1990 2000 2010 2020 2030 2040 2050 2060 2070 2080 2090 2100 2110 2120 2130 2140 2150 2160 2170 2180 2190 2200 2210 2220 2230 2240 2250 2260 2270 2280 2290 2300 2310 2320 2330 2340 2350 2360 2370 2380 2390 2400 2410 2420 2430 2440 2450 2460 2470 2480 2490 2500 2510 2520 2530 2540 2550 2560 2570 2580 2590 2600 2610 2620 2630 2640 2650 2660 2670 2680 2690 2700 2710 2720 2730 2740 2750 2760 2770 2780 2790 2800 2810 2820 2830 2840 2850 2860 2870 2880 2890 2900 2910 2920 2930 2940 2950 2960 2970 2980 2990 3000 3010 3020 3030 3040 3050 3060 3070 3080 3090 3100 3110 3120 3130 3140 3150 3160 3170 3180 3190 3200 3210 3220 3230 3240 3250 3260 3270 3280 3290 3300 3310 3320 3330 3340 3350 3360 3370 3380 3390 3400 3410 3420 3430 3440 3450 3460 3470 3480 3490 3500 3510 3520 3530 3540 3550 3560 3570 3580 3590 3600 3610 3620 3630 3640 3650 3660 3670 3680 3690 3700 3710 3720 3730 3740 3750 3760 3770 3780 3790 3800 3810 3820 3830 3840 3850 3860 3870 3880 3890 3900 3910 3920 3930 3940 3950 3960 3970 3980 3990 4000 4010 4020 4030 4040 4050 4060 4070 4080 4090 4100 4110 4120 4130 4140 4150 4160 4170 4180 4190 4200 4210 4220 4230 4240 4250 4260 4270 4280 4290 4300 4310 4320 4330 4340 4350 4360 4370 4380 4390 4400 4410 4420 4430 4440 4450 4460 4470 4480 4490 4500 4510 4520 ```
Example 2) Panel size=132(RGB) x 162, TFA =3, VSA=157, BFA=2, SSA=6, MADCTR (ML) =1: Rolling Scroll. ![](images/d9bee2d88bfa8bf34fc0082e00927c86d3355d1bdaa7b3a2eec1f07b5e919c39.jpg)
flowchart ```mermaid graph LR subgraph BFA A1["00h 00h 01h 02 03 0W 0X 0Y 0Z"] --> B1["G1 161"] B1 --> C1["G2 160"] C1 --> D1["G3 159"] end subgraph VSA E1["00h 01h 02 03 0W 0X 0Y 0Z"] --> F1["U0 U1 U2"] F1 --> G1["UX UY UZ"] G1 --> H1["VX VY VZ"] H1 --> I1["WX WY WZ"] I1 --> J1["2Y 2Z"] J1 --> K1["3Z"] end subgraph TFA L1["00h 01h 02 03 0W 0X 0Y 0Z"] --> M1["U0 U1 U2"] M1 --> N1["VX VY VZ"] N1 --> O1["WX WY WZ"] O1 --> P1["2Y 2Z"] P1 --> Q1["3Z"] end B1 -.->|SSA| C1 C1 -.->|SSA| D1["G160 2"] D1 -.->|SSA| E1 E1 -.->|SSA| F1 F1 -.->|SSA| G1 G1 --> H1["G161 1"] H1 --> I1["G162 0"] I1 --> J1["XW ZX ZY ZZ"] ```
## 9.11.7 Vertical Scroll Example There are 2 types of vertical scrolling, which are determined by the commands “Vertical Scrolling Definition” (33h) and “Vertical Scrolling Start Address” (37h). ## 9.11.8 Case 1: TFA + VSA + BFA<162 N/A. Do not set TFA + VSA + BFA<162. In that case, unexpected picture will be shown. ## 9.11.9 Case 2: TFA + VSA + BFA=162 (Rolling Scrolling) Example 2-a) When MADCTR parameter ML="0", TFA=0, VSA=162, BFA=0 and VSCSAD=40 ![](images/8c50d8cbc92a37141d9b41fd39abf2e422e2cfd1a1d851c10139f2fe45c329c9.jpg)
flowchart ```mermaid graph LR A["Memory Physical Axis (0,0)"] --> B["Frame Memory"] C["VSCSAD"] --> B B --> D["Physical Line Pointer"] D --> E["Display Axis (0,0)"] E --> F["Display"] F --> G["Increment VSCSAD"] G --> H["Display Axis (0,0)"] H --> I["Display"] I --> J["VSCSAD"] ```
Example 2-b) When MADCTR parameter ML="1", TFA=10, VSA=152, BFA=0 and VSCSAD=30 ![](images/44cf6749c954eb1253e63cbfa4466b52474f604ced0005e189de44815a57815d.jpg)
flowchart ```mermaid graph LR subgraph FrameMemory A["Memory Physical Axis (0,0)"] --> B["Frame Memory"] C["VSCSAD"] --> B D["TFA"] --> B end subgraph Display E["Display Axis (0,0)"] --> F["Display"] G["TFA"] --> F end subgraph Increment H["Increment VSCSAD"] --> I["Display"] end subgraph FrameMemory J["Memory Physical Axis (0,0)"] --> K["Frame Memory"] L["VSCSAD"] --> K M["TFA"] --> K end subgraph Display N["Display Axis (0,0)"] --> O["Display"] P["TFA"] --> O end ```
## 9.12 Tearing Effect Output Line The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled or disabled by the Tearing Effect Line Off & On commands. The mode of the Tearing Effect signal is defined by the parameter of the Tearing Effect Line On command. The signal can be used by the MPU to synchronize Frame Memory Writing when displaying video images. ## 9.12.1 Tearing Effect Line Modes Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only: ![](images/f91fa9ca08044223b6d8ef2aed881f1f6ccdee2258e0e7dba09f622c5134888e.jpg)
text_image Vertical timing scale T_{vdl} T_{vdh}
tvdh= The LCD display is not updated from the Frame Memory tvdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above) Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking Information, there is one V-sync and 162 H-sync pulses per field. ![](images/a1a386e7687349b9c5caa44b88c3e330a890bd61843c7f7cb65b1a538b88db6f.jpg)
text_image Vertical timing scale V-sync Thdl Thdh Invisible line 1st line 2nd line 161th line 162th line V-sync
thdh= The LCD display is not updated from the Frame Memory thdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above) ![](images/c94c4c2f0296e568e6e80325c32b612b5d76a876def6f869f09be3be28ea5dd1.jpg)
flowchart ```mermaid graph LR subgraph Bottom_line ["Bottom line"] A["Start"] --> B["Step Up"] B --> C["End"] end subgraph Top_line ["Top line"] D["Start"] --> E["Step Up"] E --> F["Step Down"] F --> G["End"] end subgraph sg_2nd_line_2nd_line["2nd_line [\"2nd line\"]"] H["Start"] --> I["Start"] I --> J["Step Up"] J --> K["End"] end subgraph TE Mode 2 ["TE mode 2"] L["Start"] --> M["Step Up"] M --> N["End"] N --> O["End"] end subgraph TE Mode 1 ["TE mode 1"] P["Start"] --> Q["End"] Q --> R["End"] end T["T_vdh"] -.->|Timing| R ```
Note: During Sleep In Mode, the Tearing Output Pin is active Low. ## 9.12.2 Tearing Effect Line Timings The Tearing Effect signal is described below: ![](images/9bfa8f42b501b04215c4b7c5492693ee3d32c56c4f4a300b93d22348d62e5d5e.jpg)
text_image Tvdl Tvdh Vertical Horizontal Thdl Thdh
SymbolParameterminmaxunitdescription
tvdlVertical Timing Low Duration13-ms
tvdhVertical Timing High Duration1000-μs
thdlHorizontal Timing Low Duration33-μs
thdhHorizontal Timing Low Duration25500μs
Table 13 AC characteristics of Tearing Effect Signal Idle Mode Off (Frame Rate = 60 Hz, Ta=25℃) Note: The timings in Table 9.10.1 apply when MADCTL ML=0 and ML=1 The signal's rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns. ![](images/5b56aa842b54c5085a6e836a9983086d8848b41c6b121c1ac933eed589e37c01.jpg) The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to avoid Tearing Effect: 9.12.3 Example 1: MPU Write is faster than panel read ![](images/0596bf0aaf4bfcc15078c64e242a1c1d22e97377e6acb1faa38bde567677b3a2.jpg)
flowchart This diagram illustrates the signal processing workflow for a microcontroller (MCU) to memory, showing the timing of the TE output signal and memory to LCD over time.
Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical sync pulse of the Tearing Effect Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame refresh has a complete new image: Data to be sent ![](images/c96e6f1c0ca62c97332a6185f229495f9fca7466c4f39cf3c40f5354b8318e58.jpg)
text_image B
Image on LCD a ![](images/67c239f52c1a769e26a9c9c12924d6e58ba602bb62d344a67129eac048a92dc0.jpg)
text_image A
b ![](images/3708b6529913f0554749536bd8945f375caffbed1dce3e764ef160ee77a4d1d8.jpg)
text_image R
C ![](images/dd7f58d34684fb17ca31d478e3d7f035a20356e3d52e26304206a0f2653c45a1.jpg)
text_image B
d ![](images/81520bd3f508b5e2865cf10aa43a309db69bb327bab34eabbae65720fe04abf3.jpg)
text_image B
9.12.4 Example 2: MPU Write is slower than panel read ![](images/c9510e9eb6133f51773b9a30b4dcc65eb9bd6a077c43a65c7cabc28eba9bdb99.jpg)
state_timeline | Signal | Start | End | | --- | --- | --- | | MCU to memory | 1st | 162nd | | TE output signal | 1st | 162nd | | Memory to LCD | 1st | 162nd |
The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync pulse of the Tearing Effect Output Line. This allows time for the image to download behind the Panel Read pointer and finishing download during the subsequent Frame before the Read Pointer “catches” the MPU to Frame memory write position. Data to be sent ![](images/8116b81d52bbb2b2c5a6cb651f2dd217fe5501c5c42b27b5478af8288afce72c.jpg)
text_image B
Image on LCD ![](images/24161721d436cfe171a9fba7bd56e204572d3bfb5d4a90ad74bc70328e1243ad.jpg) ## 9.13 Power ON/OFF Sequence VDDI and VDD can be applied in any order VDD and VDDI can be powered down in any order During power off, if LCD is in the Sleep Out mode, VDD and VDDI must be powered down minimum 120msec after RESX has been released. During power off, if LCD is in the Sleep In mode, VDDI or VDD can be powered down minimum 0msec after RESX has been released. CSX can be applied at any timing or can be permanently grounded. RESX has priority over CSX. Note 1: There will be no damage to the display module if the power sequences are not met. Note 2: There will be no abnormal visible effects on the display panel during the Power On/Off Sequences. Note 3: There will be no abnormal visible effects on the display between end of Power On Sequence and before receiving Sleep Out command. Also between receiving Sleep In command and Power Off Sequence. Note 4: If RESX line is not held stable by host during Power On Sequence as defined in the sequence below, then it will be necessary to apply a Hardware Reset (RESX) after Host Power On Sequence is complete to ensure correct operation. Otherwise function is not guaranteed. The power on/off sequence is illustrated below ![](images/0d3a396d6c9bf75ce814d6ba1cf43f3ab63dbd229b40d4dfe4e9f73262687c34.jpg)
flowchart ```mermaid graph LR subgraph VDD VDD1["VDDI"] -->|Timing when the latter signal rises up to 90% of its typical value. e.g. When VDD comes later, this timing is defined at the cross point of 90% of 2.75V, not 90% of 2.6V| VDD1 end subgraph CSX CSX["CSX"] -->|H or L| VDD1 CSX -->|H or L| CSX CSX -->|H or L| RESX end subgraph RESX RESX["RESX"] -->|Power down in sleep-out mode| RESX RESX -->|Power down in sleep-in mode| RESX end VDD1 -.->|TrPW = +/- no limit| CSX CSX -.->|TrPW-CSX = +/- no limit| CSX CSX -.->|TrPW-RESX = + no limit| RESX RESX -.->|TrPW-RESX = + no limit| RESX RESX -.->|TrPW-RESX1 = min 120ms| CSX RESX -.->|TrPW-RESX = + no limit| CSX CSX -.->|TfpW-CSX = +/- no limit| CSX CSX -.->|TfpW-RESX2 = min 0ms| RESX ```
## 9.13.1 Uncontrolled Power Off The uncontrolled power-off means a situation which removed a battery without the controlled power off sequence. It will neither damage the module or the host interface. If uncontrolled power-off happened, the display will go blank and there will not any visible effect on the display (blank display) and remains blank until “Power On Sequence” powers it up. ## 9.14 Power Level Definition ## 9.14.1 Power Level 6 level modes are defined they are in order of Maximum Power consumption to Minimum Power Consumption 1. Normal Mode On (full display), Idle Mode Off, Sleep Out. In this mode, the display is able to show maximum 262,144 colors. 2. Partial Mode On, Idle Mode Off, Sleep Out. In this mode part of the display is used with maximum 262,144 colors. 3. Normal Mode On (full display), Idle Mode On, Sleep Out. In this mode, the full display area is used but with 8 colors. 4. Partial Mode On, Idle Mode On, Sleep Out. In this mode, part of the display is used but with 8 colors. 5. Sleep In Mode In this mode, the DC: DC converter, internal oscillator and panel driver circuit are stopped. Only the MCU interface and memory works with VDDI power supply. Contents of the memory are safe. 6. Power Off Mode In this mode, both VDD and VDDI are removed. Note: Transition between modes 1-5 is controllable by MCU commands. Mode 6 is entered only when both Power supplies are removed. 9.14.2 Power Flow Chart ![](images/62b4f9625a098d79897da82768e49b616a98d45021467752eb9f6ed748883c1b.jpg)
flowchart This flowchart illustrates the sleep states and power flow of a sleep-on sequence system, showing transitions between normal and partial display modes on idle modes.
## 9.15 Reset Table ## 9.15.1 Reset Table(Default Value, GM[1:0]="11", 128RGB x 160)
ItemAfter Power OnAfter H/W ResetAfter S/W Reset
Frame MemoryRandomNo ChangeNo Change
Sleep In/OutInInIn
Display On/OffOffOffOff
Display Mode (Normal/Partial)NormalNormalNormal
Display Inversion On/OffOffOffOff
Display Idle Mode On/OffOffOffOff
Column: Start Address (XS)0000h0000h0000h
Column: End Address (XE)007Fh007Fh007Fh (127d) (when MV=0)009Fh (159d) (when MV=1)
Row: Start Address (YS)0000h0000h0000h
Row: End Address (YE)009Fh009Fh009Fh (159d) (when MV=0)007Fh (127d) (when MV=1)
Gamma settingGC0GC0GC0
RGB for 4k and 65k Color ModeRandom valuesRandom valuesNo Change
Partial: Start Address (PSL)0000h0000h0000h
Partial: End Address (PEL)009Fh009Fh009Fh
Scroll: Top Fixed Area (TFA)0000h0000h0000h
Scroll: Scroll Area (VSA)00A0h00A0h00A0h
Scroll: Bottom Fixed Area (BFA)0000h0000h0000h
Scroll Start Address (SSA)0000h0000h0000h
Tearing: On/OffOffOffOff
Tearing Effect Mode (*1)0 (Mode1)0 (Mode1)0 (Mode1)
Memory Data Access Control (MY/MX/MV/ML/RGB)0/0/0/0/00/0/0/0/0No Change
Interface Pixel Color Format6 (18-Bit/Pixel)6 (18-Bit/Pixel)No Change
RDDPM08h08h08h
RDDMADCTL00h00hNo Change
RDDCOLMOD6 (18-Bit/Pixel)6 (18-Bit/Pixel)No Change
RDDIM00h00h00h
RDDSM00h00h00h
ID2NV valueNV valueNV value
ID3NV valueNV valueNV value
Note: TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only 9.15.2 Reset Table (GM[1:0]="01", 132RGB x 132)
ItemAfter Power OnAfter H/W ResetAfter S/W Reset
Frame memoryRandomNo ChangeNo Change
Sleep In/OutInInIn
Display On/OffOffOffOff
Display Mode (Normal/Partial)NormalNormalNormal
Display Inversion On/OffOffOffOff
Display Idle Mode On/OffOffOffOff
Column: Start Address (XS)0000h0000h0000h
Column: End Address (XE)0083h0083h0083h (131d) (when MV=0)0083h (131d) (when MV=1)
Row: Start Address (YS)0000h0000h0000h
Row: End Address (YE)0083h0083h0083h (131d) (when MV=0)0083h (131d) (when MV=1)
Gamma SettingGC0GC0GC0
RGB for 4k and 65k Color ModeSee Section 9.17See Section 9.17No Change
Partial: Start Address (PSL)0000h0000h0000h
Partial: End Address (PEL)0083h0083h0083h
Tearing: On/OffOffOffOff
Scroll: Top Fixed Area (TFA)0000h0000h0000h
Scroll: Scroll Area (VSA)0084h0084h0084h
Scroll: Bottom Fixed Area (BFA)0000h0000h0000h
Scroll Start Address (SSA)0000h0000h0000h
Tearing Effect Mode (*1)0 (Mode1)0 (Mode1)0 (Mode1)
Memory Data Access Control (MY/MX/MV/ML/RGB)0/0/0/0/00/0/0/0/0No Change
Interface Pixel Color Format6 (18-Bit/Pixel)6 (18-Bit/Pixel)No Change
RDDPM08h08h08h
RDDMADCTL00h00hNo Change
RDDCOLMOD6 (18-Bit/Pixel)6 (18-Bit/Pixel)No Change
RDDIM00h00h00h
RDDSM00h00h00h
ID2NV valueNV valueNV value
ID3NV valueNV valueNV value
Note: TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only 9.15.3 Reset Table (GM[1:0]="00", 132RGB x 162)
ItemAfter Power OnAfter H/W ResetAfter S/W Reset
Frame memoryRandomNo ChangeNo Change
Sleep In/OutInInIn
Display On/OffOffOffOff
Display mode (normal/partial)NormalNormalNormal
Display Inversion On/OffOffOffOff
Display Idle Mode On/OffOffOffOff
Column: Start Address (XS)0000h0000h0000h
Column: End Address (XE)0083h0083h0083h (131d) (when MV=0)00A1h (161d) (when MV=1)
Row: Start Address (YS)0000h0000h0000h
Row: End Address (YE)00A1h00A1h00A1h (161d) (when MV=0)0083h (131d) (when MV=1)
Gamma settingGC0GC0GC0
RGB for 4k and 65k Color ModeRandom valuesRandom valuesNo Change
Partial: Start Address (PSL)0000h0000h0000h
Partial: End Address (PEL)00A2h00A2h00A2h
Scroll: Top Fixed Area (TFA)0000h0000h0000h
Scroll: Scroll Area (VSA)0084h0084h0084h
Scroll: Bottom Fixed Area (BFA)0000h0000h0000h
Scroll Start Address (SSA)0000h0000h0000h
Tearing: On/OffOffOffOff
Tearing Effect Mode (*1)0 (Mode1)0 (Mode1)0 (Mode1)
Memory Data Access Control (MY/MX/MV/ML/RGB)0/0/0/0/00/0/0/0/0No Change
Interface Pixel Color Format6 (18-Bit/Pixel)6 (18-Bit/Pixel)No Change
RDDPM08h08h08h
RDDMADCTL00h00hNo Change
RDDCOLMOD6 (18-Bit/Pixel)6 (18-Bit/Pixel)No Change
RDDIM00h00h00h
RDDSM00h00h00h
ID2NV valueNV valueNV value
ID3NV valueNV valueNV value
Note: TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only ## 9.16 Module Input/Output Pins ## 9.16.1 Output or Bi-directional (I/O) Pins
Output or Bi-directional pinsAfter Power OnAfter Hardware ResetAfter Software Reset
TELowLowLow
D7 to D0 (Output driver)High-Z (Inactive)High-Z (Inactive)High-Z (Inactive)
Input pinsDuring Power On ProcessAfter Power OnAfter Hardware ResetAfter Software ResetDuring Power Off Process
RESXSee 9.14Input validInput validInput validSee 9.14
CSXInput invalidInput validInput validInput validInput invalid
D/CXInput invalidInput validInput validInput validInput invalid
WRXInput invalidInput validInput validInput validInput invalid
RDXInput invalidInput validInput validInput validInput invalid
D7 to D0Input invalidInput validInput validInput validInput invalid
Note: There will be no output from D7-D0 during Power On/Off sequence, Hardware Reset and Software Reset. ## 9.17 Reset Timing ![](images/169e0ee32c3b9a01acbd5103c6c912e6cfa6176d104a984143e6937711b69932.jpg)
flowchart ```mermaid graph LR A["RESX"] -->|Shorter than 5us| B["Normal operation"] B --> C["Resetting"] C --> D["Initial condition\n(Default for HW reset)"] C -->|T_RESW| E["RESX"] C -->|T_REST| F["Initial condition\n(Default for HW reset)"] ```
Related PinsSymbolParameterMINMAXUnit
RESXtRESWReset Pulse Duration10-us
tRESTReset Cancel-5ms
120ms
Table 14 Reset Timing ## Notes: 1. The reset cancel includes also required time for loading ID bytes, VCOM setting and other settings from NVM (or similar device) to registers. This loading is done every time when there is HW reset cancel time (tRT) within 5 ms after a rising edge of RESX. 2. Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below:
RESX PulseAction
Shorter than 5usReset Rejected
Longer than 9usReset
Between 5us and 9usReset Starts
3. During the Resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120 ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep In -mode.) and then return to Default condition for Hardware Reset. 4. Spike Rejection also applies during a valid reset pulse as shown below: ![](images/266158f78fecef8d496f371350f16eb8103c870efb50a9e9c96dd98c9a4359cf.jpg)
text_image 10μs Reset is accepted 10μs 20ns Less than 20ns width positive spike will be rejected.
5. When Reset applied during Sleep In Mode. 6. When Reset applied during Sleep Out Mode. 7. It is necessary to wait 5msec after releasing RESX before sending commands. Also Sleep Out command cannot be sent for 120msec. ## 9.18 Color Depth Conversion Look Up Tables 9.18.1 65536 Color to 262,144 Color
ColorLook Up Table OutputFrame Memory Data (6-bits)RGBSET ParameterLook Up Table Input Data
65k Color (5-bits)
REDR005 R004 R003 R002 R001 R000100000
R015 R014 R013 R012 R011 R010200001
R025 R024 R023 R022 R021 R020300010
R035 R034 R033 R032 R031 R030400011
R045 R044 R043 R042 R041 R040500100
R055 R054 R053 R052 R051 R050600101
R065 R064 R063 R062 R061 R060700110
R075 R074 R073 R072 R071 R070800111
R085 R084 R083 R082 R081 R080901000
R095 R094 R093 R092 R091 R0901001001
R105 R104 R103 R102 R101 R1001101010
R115 R114 R113 R112 R111 R1101201011
R125 R124 R123 R122 R121 R1201301100
R135 R134 R133 R132 R131 R1301401101
R145 R144 R143 R142 R141 R1401501110
R155 R154 R153 R152 R151 R1501601111
R165 R164 R163 R162 R161 R1601710000
R175 R174 R173 R172 R171 R1701810001
R185 R184 R183 R182 R181 R1801910010
R195 R194 R193 R192 R191 R1902010011
R205 R204 R203 R202 R201 R2002110100
R215 R214 R213 R212 R211 R2102210101
R225 R224 R223 R222 R221 R2202310110
R235 R234 R233 R232 R231 R2302410111
R245 R244 R243 R242 R241 R2402511000
R255 R254 R253 R252 R251 R2502611001
R265 R264 R263 R262 R261 R2602711010
R275 R274 R273 R272 R271 R2702811011
R285 R284 R283 R282 R281 R2802911100
R295 R294 R293 R292 R291 R2903011101
R305 R304 R303 R302 R301 R3003111110
R315 R314 R313 R312 R311 R3103211111
GREENG005 G004 G003 G002 G001 G00033000000
G015 G014 G013 G012 G011 G01034000001
G025 G024 G023 G022 G021 G02035000010
G035 G034 G033 G032 G031 G03036000011
G045 G044 G043 G042 G041 G04037000100
G055 G054 G053 G052 G051 G05038000101
G065 G064 G063 G062 G061 G06039000110
G075 G074 G073 G072 G071 G07040000111
G085 G084 G083 G082 G081 G08041001000
G095 G094 G093 G092 G091 G09042001001
G105 G104 G103 G102 G101 G10043001010
G115 G114 G113 G112 G111 G11044001011
G125 G124 G123 G122 G121 G12045001100
G135 G134 G133 G132 G131 G13046001101
G145 G144 G143 G142 G141 G14047001110
G155 G154 G153 G152 G151 G15048001111
G165 G164 G163 G162 G161 G16049010000
G175 G174 G173 G172 G171 G17050010001
G185 G184 G183 G182 G181 G18051010010
G195 G194 G193 G192 G191 G19052010011
G205 G204 G203 G202 G201 G20053010100
G215 G214 G213 G212 G211 G21054010101
G225 G224 G223 G222 G221 G22055010110
G235 G234 G233 G232 G231 G23056010111
G245 G244 G243 G242 G241 G24057011000
G255 G254 G253 G252 G251 G25058011001
G265 G264 G263 G262 G261 G26059011010
G275 G 274 G273 G272 G271 G27060011011
G285 G 284 G283 G282 G281 G28061011100
G295 G 294 G293 G292 G291 G29062011101
G305 G 304 G303 G302 G301 G30063011110
G315 G 314 G313 G312 G311 G31064011111
G325 G324 G323 G322 G321 G32065100000
G335 G334 G333 G332 G331 G33066100001
G345 G344 G343 G342 G341 G34067100010
G355 G354 G353 G352 G351 G35068100011
G365 G364 G363 G362 G361 G36069100100
G375 G374 G373 G372 G371 G37070100101
G385 G384 G383 G382 G381 G38071100110
G395 G394 G393 G392 G391 G39072100111
G405 G404 G403 G402 G401 G40073101000
G415 G414 G413 G412 G411 G41074101001
G425 G424 G423 G422 G421 G42075101010
G435 G434 G433 G432 G431 G43076101011
G445 G444 G443 G442 G441 G44077101100
G455 G454 G453 G452 G451 G45078101101
G465 G464 G463 G462 G461 G46079101110
G475 G474 G473 G472 G471 G47080101111
G485 G484 G483 G482 G481 G48081110000
G495 G494 G493 G492 G491 G49082110001
G505 G504 G503 G502 G501 G50083110010
G515 G514 G513 G512 G511 G51084110011
G525 G524 G523 G522 G521 G52085110100
G535 G534 G533 G532 G531 G53086110101
G545 G544 G543 G542 G541 G54087110110
G555 G554 G553 G552 G551 G55088110111
G565 G564 G563 G562 G561 G56089111000
G575 G574 G573 G572 G571 G57090111001
G585 G584 G583 G582 G581 G58091111010
G595 G594 G593 G592 G591 G59092111011
G605 G604 G603 G602 G601 G60093111100
G615 G614 G613 G612 G611 G61094111101
G625 G624 G623 G622 G621 G62095111110
G635 G634 G633 G632 G631 G63096111111
ColorLook Up Table OutputFrame Memory Data (6-bits)RGBSET ParameterLook Up Table Input Data
65k Color (5-bits)
BLUEB005 B004 B003 B002 B001 B0009700000
B015 B014 B013 B012 B011 B0109800001
B025 B024 B023 B022 B021 B0209900010
B035 B034 B033 B032 B031 B03010000011
B045 B044 B043 B042 B041 B04010100100
B055 B054 B053 B052 B051 B05010200101
B065 B064 B063 B062 B061 B06010300110
B075 B074 B073 B072 B071 B07010400111
B085 B084 B083 B082 B081 B08010501000
B095 B094 B093 B092 B091 B09010601001
B105 B104 B103 B102 B101 B10010701010
B115 B114 B113 B112 B111 B11010801011
B125 B124 B123 B122 B121 B12010901100
B135 B134 B133 B132 B131 B13011001101
B145 B144 B143 B142 B141 B14011101110
B155 B154 B153 B152 B151 B15011201111
B165 B164 B163 B162 B161 B16011310000
B175 B174 B173 B172 B171 B17011410001
B185 B184 B183 B182 B181 B18011510010
B195 B194 B193 B192 B191 B19011610011
B205 B204 B203 B202 B201 B20011710100
B215 B214 B213 B212 B211 B21011810101
B225 B224 B223 B222 B221 B22011910110
B235 B234 B233 B232 B231 B23012010111
B245 B244 B243 B242 B241 B24012111000
B255 B254 B253 B252 B251 B25012211001
B265 B264 B263 B262 B261 B26012311010
B275 B274 B273 B272 B271 B27012411011
B285 B284 B283 B282 B281 B28012511100
B295 B294 B293 B292 B291 B29012611101
B305 B304 B303 B302 B301 B30012711110
B315 B314 B313 B312 B311 B31012811111
9.18.2 4096 Color to 262,144 Color
ColorLook Up Table OutputFrame Memory Data (6-bits)RGBSET ParameterLook Up Table Input Data
4k Color (4-bits)
REDR005 R004 R003 R002 R001 R00010000
R015 R014 R013 R012 R011 R01020001
R025 R024 R023 R022 R021 R02030010
R035 R034 R033 R032 R031 R03040011
R045 R044 R043 R042 R041 R04050100
R055 R054 R053 R052 R051 R05060101
R065 R064 R063 R062 R061 R06070110
R075 R074 R073 R072 R071 R07080111
R085 R084 R083 R082 R081 R08091000
R095 R094 R093 R092 R091 R090101001
R105 R104 R103 R102 R101 R100111010
R115 R114 R113 R112 R111 R110121011
R125 R124 R123 R122 R121 R120131100
R135 R134 R133 R132 R131 R130141101
R145 R144 R143 R142 R141 R140151110
R155 R154 R153 R152 R151 R150161111
R165 R164 R163 R162 R161 R16017Not used
||
R315 R314 R313 R312 R311 R31032
GREENG005 G004 G003 G002 G001 G000330000
G015 G014 G013 G012 G011 G010340001
G025 G024 G023 G022 G021 G020350010
G035 G034 G033 G032 G031 G030360011
G045 G044 G043 G042 G041 G040370100
G055 G054 G053 G052 G051 G050380101
G065 G064 G063 G062 G061 G060390110
G075 G074 G073 G072 G071 G070400111
G085 G084 G083 G082 G081 G080411000
G095 G094 G093 G092 G091 G090421001
G105 G104 G103 G102 G101 G100431010
G115 G114 G113 G112 G111 G110441011
G125 G124 G123 G122 G121 G120451100
G135 G134 G133 G132 G131 G130461101
G145 G144 G143 G142 G141 G140471110
G155 G154 G153 G152 G151 G150481111
G165 G164 G163 G162 G161 G16049Not used
||
G635 G634 G633 G632 G631 G63096
BLUEB005 B004 B003 B002 B001 B000970000
B015 B014 B013 B012 B011 B010980001
B025 B024 B023 B022 B021 B020990010
B035 B034 B033 B032 B031 B0301000011
B045 B044 B043 B042 B041 B0401010100
B055 B054 B053 B052 B051 B0501020101
B065 B064 B063 B062 B061 B0601030110
B075 B074 B073 B072 B071 B0701040111
B085 B084 B083 B082 B081 B0801051000
B095 B094 B093 B092 B091 B0901061001
B105 B104 B103 B102 B101 B1001071010
B115 B114 B113 B112 B111 B1101081011
B125 B124 B123 B122 B121 B1201091100
B135 B134 B133 B132 B131 B1301101101
B145 B144 B143 B142 B141 B1401111110
B155 B154 B153 B152 B151 B1501121111
B165 B164 B163 B162 B161 B160113Not used
||
B315 B314 B313 B312 B311 B310128
## 9.19 Sleep Out-Command and Self-Diagnostic Functions of the Display Module ## 9.19.1 Register Loading Detection Sleep Out-command (See section 0 “Sleep Out (11h)”) is a trigger for an internal function of the display module, which indicates, if the display module loading function of factory default values from MTP (or similar device) to registers of the display controller is working properly. There are compared factory values of the MTP and register values of the display controller by the display controller. If those both values (MTP and register values) are same, there is inverted (=increased by 1) a bit, which is defined in command 0 “Read Display Self-Diagnostic Result (0Fh)” (=RDDSDR) (The used bit of this command is D7). If those both values are not same, this bit (D7) is not inverted (= increased by 1). The flow chart for this internal function is following: ![](images/1ba165dfb393dd895abfafb6dd98328e7f4e1fd6014d1eb041273487ccce74c5.jpg)
flowchart ```mermaid graph TD A["Sleep in (10h)"] --> B["Sleep out mode"] C["Power on sequence\nHW reset\nSW reset"] --> D["RDDSDR's D7=0"] B --> E["Sleep out (11h)"] D --> E E --> F["Compares MTP and register values"] F --> G{"Are MTP and register values same?"} G -->|No| H["Loading values from MTP to registers"] H --> B G -->|Yes| I["D7 inverted"] I --> H ```
Note: There is not compared and loaded register values, which can be changed by user (00h to AFh and DAh to DDh), by the display module. ## 9.19.2 Functionality Detection Sleep Out-command (See section 0 “Sleep Out (11h)”) is a trigger for an internal function of the display module, which indicates, if the display module is still running and meets functionality requirements. The internal function (= the display controller) is comparing, if the display module is still meeting functionality requirements (only Booster voltage level). If functionality requirement is met, there is inverted (= increased by 1) a bit, which defined in command 0 “Read Display Self- Diagnostic Result (0Fh)” (= RDDSDR) (The used bit of this command is D6). If functionality requirement is not same, this bit (D6) is not inverted (= increased by 1). The flow chart for this internal function is following: ![](images/819f0e8da11f4a348899e5219b58949c1f080500e3276b69228226fc24c1d67b.jpg)
flowchart ```mermaid graph TD A["Sleep in (10h)"] --> B["Sleep out mode"] A --> C["Sleep in mode"] B --> D["Sleep out (11h)"] C --> D D --> E["Checks Booster voltage levels and other functionalities"] E --> F{"Is functionality requirement met?"} F -->|No| G["D6 inverted"] F -->|Yes| G H["Power on sequence\nHW reset\nSW reset"] --> I["RDDSDR's D6=0"] G --> I ```
Note: There is needed 120msec after Sleep Out -command, when there is changing from Sleep In -mode to Sleep Out -mode, before there is possible to check if functionality requirements are met and a value of RDDSDR's D6 is valid. Otherwise, there is 5msec delay for D6's value, when Sleep Out -command is sent in Sleep Out -mode. ## 9.19.3 Chip Attachment Detection (Optional) Sleep Out-command (See section 0 “Sleep Out (11h)”) is a trigger for an internal function of the display module, which indicates, if a chip or chips (e.g. driver, etc.) of the display module is/are attached to the circuit route of a flex foil or display glass ITO. There is inverted (= increased by 1) a bit, which is defined in command 0 “Read Display Self- Diagnostic Result (0Fh)” (= RDDSDR) (The used bit of this command is D5), if the chip or chips is/are attached to the circuit route of the flex or display glass. If this chip is or those chips are not attached to the circuit route of the flex or display glass, this bit (D5) is not inverted (= increased by 1). The following figure is for reference purposes; how this chip attachment can be implemented e.g. there are connected together 2 bumps via route of ITO or the flex foil on 4 corners of the driver (chip). ![](images/224298e921bb4184201d7232299b4a987ea9a181bbc15446b4d397d7f1ce7f75.jpg)
flowchart ```mermaid graph LR A["Routing Between Bumps"] --> B["Through view of driver to bumps"] B --> C["Routing Between Bumps"] C --> D["Substrate or flex foil"] ```
The flow chart for this internal function is following: ![](images/a09069b9e94e1eb1cc63702dd67f5365db2a61d6bdee611803fc42c626696989.jpg)
flowchart ```mermaid graph TD A["Sleep In (10h)"] --> B["Sleep Out Mode"] C["Power on sequence\nHW reset\nSW reset"] --> D["RDDSDR D5=0"] B --> E["Sleep Out (11h)"] D --> E E --> F["Check, if chip is attached to route"] F --> G{"Is chip attached to Routes ?"} G -->|No| B G -->|Yes| H["D5 inverted"] H --> I[" ```
## 9.19.4 Display Glass Break Detection (Optional) Sleep Out-command (See section 0 “Sleep Out (11h)”) is a trigger for an internal function of the display module, which indicates, if the display glass of the display module is broken or not. There is inverted (= increased by 1) a bit, which is defined in command 0 “Read Display Self-Diagnostic Result (0Fh)” (= RDDSDR) (The used bit of this command is D4), if the display glass is not broken. If this display glass is broken, this bit (D4) is not inverted (= increased by 1). The following figure is a reference, how this glass break detection can be implemented e.g. there is connected together 2 bumps via route of ITO. This route of ITO is the nearest route of the edge of the display glass. ![](images/a6ccf5248850ab9232f1ee6a627cd5d5e9b413c3d9f48146d8ec580bf2d8e46a.jpg) The flow chart for this internal function is following: ![](images/ff65a24c67799893c730fd652ccdfd9211a6c65f86fad9f483c2577802c176c3.jpg)
flowchart ```mermaid graph TD A["Sleep In (10h)"] --> B["Sleep Out Mode"] C["Power on sequence\nHW reset\nSW reset"] --> D["RDDSDR D4=0"] B --> E["Sleep Out (11h)"] D --> E E --> F["Check, if display glass is broken"] F --> G{"Is the display glass Broken ?"} G -->|Yes| B G -->|No| H["D4 inverted"] H --> I[" ```
## 10 COMMAND ## 10.1 System Function Command List and Description Table 15 System Function Command List (1)
InstructionReferD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HexFunction
NOP00↑1-00000000(00h)No Operation
SWRESET00↑1-00000001(01h)Software Reset
RDDID00↑1-00000100(04h)Read Display ID
11↑---------Dummy Read
11↑-ID17ID16ID15ID14ID13ID12ID11ID10ID1 Read
11↑-1ID26ID25ID24ID23ID22ID21ID20ID2 Read
11↑-ID37ID36ID35ID34ID33ID32ID31ID30ID3 Read
RDDST00↑1-00001001(09h)Read Display Status
11↑---------Dummy Read
11↑-BSTONMYMXMVMLRGBMHST24-
11↑-ST23IFPF2IFPF1IFPF0IDMONPTLONSLOUTNORON-
11↑-VSSONST14INVONST12ST11DISONTEONGCS2-
11↑-GCS1GCS0TEMST4ST3ST2ST1ST0-
RDDPM00↑1-00001010(0Ah)Read Display Power Mode
11↑---------Dummy Read
11↑-BSTONIDMONPTLONSLPOUTNORONDISON---
RDD MADCTL00↑1-00001011(0Bh)Read Display MADCTL
11↑---------Dummy Read
11↑-MYMXMVMLRGBMH---
RDD COLMOD00↑1-00001100(0Ch)Read Display Pixel Format
11↑---------Dummy Read
11↑-0000-IFPF2IFPF1IFPF0-
RDDIM00↑1-00001101(0Dh)Read Display Image Mode
11↑---------Dummy Read
11↑-VSSOND6INVON--GCS2GCS1GCS0-
RDDSM00↑1-00001110(0Eh)Read Display Signal Mode
11↑---------Dummy Read
11↑-TEONTEM-------
RDDSDR00↑1-00001111(0Fh)Read Display Self-diagnostic result
11↑---------Dummy Read
11↑-RELDFUNDATTDBRD-----
“-”: Don't care Table 16 System Function Command List (2)
InstructionReferD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HexFunction
SLPIN00↑1-00010000(10h)Sleep In & Booster Off
SLPOUT00↑1-00010001(11h)Sleep Out & Booster On
PTLON00↑1-00010010(12h)Partial Mode On
NORON00↑1-00010011(13h)Partial Off (Normal)
INVOFF00↑1-00100000(20h)Display Inversion Off (Normal)
INVON00↑1-00100001(21h)Display Inversion On
GAMSET00↑1-00100110(26h)Gamma Curve Select
1↑1-----GC3GC2GC1GC0-
DISPOFF00↑1-00101000(28h)Display Off
DISPON00↑1-00101001(29h)Display On
CASET00↑1-00101010(2Ah)Column Address Set
1↑1-XS15XS14XS13XS12XS11XS10XS9XS8X Address Start: 0≤XS≤X
1↑1-XS7XS6XS5XS4XS3XS2XS1XS0
1↑1-XE15XE14XE13XE12XE11XE10XE9XE8X Address End: S≤XE≤X
1↑1-XE7XE6XE5XE4XE3XE2XE1XE0
RASET00↑1-00101011(2Bh)Row Address Set
1↑1-YS15YS14YS13YS12YS11YS10YS9YS8Y Address Start: 0≤YS≤Y
1↑1-YS7YS6YS5YS4YS3YS2YS1YS0
1↑1-YE15YE14YE13YE12YE11YE10YE9YE8Y Address End:S≤YE≤Y
1↑1-YE7YE6YE5YE4YE3YE2YE1YE0
RAMWR00↑1-00101100(2Ch)Memory Write
1↑1-D7D6D5D4D3D2D1D0Write Data
RGBSET00↑1-00101101(2Dh)LUT for 4k,65k,262k Color display
1↑1---R005R004R003R002R001R000Red Tone 0
1↑1---:::::::
1↑1---Ra5Ra4Ra3Ra2Ra1Ra0Red Tone “a”
1↑1---G005G004G003G002G001G000Green Tone 0
1↑1---:::::::
1↑1---Gb5Gb4Gb3Gb2Gb1Gb0Green Tone “b”
1↑1---B005B004B003B002B001B000Blue Tone 0
1↑1---:::::::
1↑1---Bc5Bc4Bc3Bc2Bc1Bc0Blue Tone “c”
RAMRD00↑1-00101110(2Eh)Memory Read
11↑---------Dummy Read
11↑-D7D6D5D4D3D2D1D0Read Data
“-”: Don't care Table 17 System Function command List (3)
InstructionReferD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HexFunction
PTLAR10.1.250↑1-00110000(30h)Partial Start/End Address Set
1↑1-PSL15PSL14PSL13PSL12PSL11PSL10PSL9PSL8Partial Start Address (0,1,2,..P)
1↑1-PSL7PSL6PSL5PSL4PSL3PSL2PSL1PSL0
1↑1-PEL15PEL14PEL13PEL12PEL11PEL10PEL9PEL8Partial End Address (0,1,2,..,P)
1↑1-PEL7PEL6PEL5PEL4PEL3PEL2PEL1PEL0
SCRLAR10.1.260↑1-00110011(33h)Scroll area set
1↑1---------Top fixed area (0,1,2,..,161)
1↑1-TFA7TFA6TFA5TFA4TFA3TFA2TFA1TFA0
1↑1---------Vertical scroll area (0,1,2,..,161)
1↑1-VSA7VSA6VSA5VSA4VSA3VSA2VSA1VSA0
1↑1---------Bottom fixed area (0,1,2,..,161)
1↑1-BFA7BFA6BFA5BFA4BFA3BFA2BFA1BFA0
TEOFF10.1.270↑1-00110100(34h)Tearing effect line off
TEON10.1.280↑1-00110101(35h)Tearing Effect Mode Set & on
1↑1--------TEMMode1: TEM="0" Mode2: TEM="1"
MADCTL10.1.290↑1-00110110(36h)Memory Data Access Control
1↑1-MYMXMVMLRGBMH---
VSCSAD10.1.300↑1-00110111(37h)Scroll Start Address of RAM
111--------SSA=0,1,2,...,161
111-SSA7SSA6SSA5SSA4SSA3SSA2SSA1SSA0
IDMOFF10.1.310↑1-00111000(38h)Idle Mode Off
IDMON10.1.320↑1-00111001(39h)Idle Mode On
COLMOD10.1.330↑1-00111010(3Ah)Interface Pixel Format
1↑1------IFPF2IFPF1IFPF0Interface Format
RDID110.1.340↑1-11011010(DAh)Read ID1
11↑---------Dummy Read
11↑-ID17ID16ID15ID14ID13ID12ID11ID10Read Parameter
RDID210.1.350↑1-11011011(DBh)Read ID2
11↑---------Dummy Read
11↑-1ID26ID25ID24ID23ID22ID21ID20Read Parameter
RDID310.1.360↑1-11011100(DCh)Read ID3
11↑---------Dummy Read
11↑-ID37ID36ID35ID34ID33ID32ID31ID30Read Parameter
“-”: Don't care Note 1: After the H/W reset by RESX pin or S/W reset by SWRESET command, each internal register becomes default state (Refer "RESET TABLE" section) Note 2: Undefined commands are treated as NOP (00 h) command. Note 3: B0 to D9 and DA to F are for factory use of driver supplier. Note 4: Commands 10h, 12h, 13h, 20h, 21h, 26h, 28h, 29h, 30h, 33h, 36h (ML parameter only), 37h, 38h and 39h are updated during V-sync when Module is in Sleep Out Mode to avoid abnormal visual effects. During Sleep In mode, these commands are updated immediately. Read status (09h), Read Display Power Mode (0Ah), Read Display MADCTL (0Bh), Read Display Pixel Format (0Ch), Read Display Image Mode (0Dh), Read Display Signal Mode (0Eh). 10.1.1 NOP (00h)
00HNOP (No Operation)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
NOP0↑1-00000000(00h)
ParameterNo Parameter-
DescriptionThis command is empty command.
“-” Don’t care 10.1.2 SWRESET (01h): Software Reset
01HSWRESET (Software Reset)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
SWRESET0↑1-00000001(01h)
ParameterNo Parameter-
Description“-” Don’t care-If Software Reset is applied during Sleep In mode, it will be necessary to wait 120msec before sending next command.-The display module loads all default values to the registers during 120msec.-If Software Reset is applied during Sleep Out or Display On Mode, it will be necessary to wait 120msec before sending next command.
Flow Chart
10.1.3 RDDID (04h): Read Display ID
04HRDDID (Read Display ID)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
RDDID0↑1-00000100(04h)
$1^{st}$ Parameter11↑----------
$2^{nd}$ Parameter11↑-ID17ID16ID15ID14ID13ID12ID11ID10
$3^{rd}$ Parameter11↑-1ID26ID25ID24ID23ID22ID21ID20
$4^{th}$ Parameter11↑-ID37ID36ID35ID34ID33ID32ID31ID30
Description-This read byte returns 24-bit display identification information.-The 1st parameter is dummy data-The 2nd parameter (ID17 to ID10): LCD module's manufacturer ID.-The 3rd parameter (ID26 to ID20): LCD module/driver version ID-The 4th parameter (ID37 to UD30): LCD module/driver ID.-Commands RDID1/2/3(DAh, DBh, DCh) read data correspond to the parameters 2,3,4 of the command 04h, respectively."-" Don't care
DefaultStatusDefault Value
ID1ID2ID3
Power On Sequence0x7CNV ValueNV Value
S/W Reset0x7CNV ValueNV Value
H/W Reset0x7CNV ValueNV Value
Flow Chart
10.1.4 RDDST (09h): Read Display Status
09HRDDST (Read Display Status)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
RDDST0↑1-00001001(09h)
$1^{st}$ Parameter11↑----------
$2^{nd}$ Parameter11↑-BSTONMYMXMVMLRGBMHST24
$3^{rd}$ Parameter11↑-ST23IFPF2IFPF1IFPF0IDMONPTLONSLOUTNORON
$4^{th}$ Parameter11↑-ST15ST14INVONST12ST11DISONTEONGCS2
$5^{th}$ Parameter11↑-GCS1GCS0TEMST4ST3ST2ST1ST0
DescriptionThis command indicates the current status of the display as described in the table below:
BitDescriptionValue
BSTONBooster Voltage Status‘1’ =Booster on,‘0’ =Booster off
MYRow Address Order (MY)‘1’ =Decrement, (Bottom to Top, when MADCTL (36h) D7='1')‘0’ =Increment, (Top to Bottom, when MADCTL (36h) D7='0')
MXColumn Address Order (MX)‘1’ =Decrement, (Right to Left, when MADCTL (36h) D6='1')‘0’ =Increment, (Left to Right, when MADCTL (36h) D6='1')
MVRow/Column Exchange (MV)‘1’ = Row/column exchange, (when MADCTL (36h) D5='1')‘0’ = Normal, (when MADCTL (36h) D5='0')
MLScan Address Order (ML)‘0’ =Decrement,(LCD refresh Top to Bottom, when MADCTL (36h) D4='0')‘1’=Increment,(LCD refresh Bottom to Top, when MADCTL (36h) D4='1')
RGBRGB/ BGR Order (RGB)‘1’ =BGR, (When MADCTL (36h) D3='1')‘0’ =RGB, (When MADCTL (36h) D3='0')
MHHorizontal Order‘0’ =Decrement,(LCD refresh Left to Right, when MADCTL (36h) D2='0')‘1’ =Increment,(LCD refresh Right to Left, when MADCTL (36h) D2='1')
ST24For Future Use‘0'
ST23For Future Use‘0'
IFPF2Interface Color Pixel Format Definition“011” = 12-bit / pixel,“101” = 16-bit / pixel,“110” = 18-bit / pixel, others are no define
IFPF1
IFPF0
IDMONIdle Mode On/Off‘1’ = On, “0” = Off
PTLONPartial Mode‘1’ = On, “0” = Off
SLPOUTSleep In/Out‘1’ = Out, “0” = In
NORONDisplay Normal Mode On/Off‘1’ = Normal Display,‘0’ = Partial Display
ST15Vertical Scrolling‘1’ = Scroll on, “0” = Scroll off
ST14Horizontal Scroll‘0'
INVONInversion Status‘1’ = On, “0” = Off
ST12All Pixels On (Not‘0'
ST11All Pixels Off (Not‘0'
DISONDisplay On/Off‘1’ = On, “0” = Off
TEONTearing effect line‘1’ = On, “0” = Off
GCSEL2Gamma Curve Selection“000” = GC0“001” = GC1“010” = GC2“011” = GC3
GCSEL1
GCSEL0
TEMTearing effect line‘0’ = mode1, ‘1’ = mode2
ST4For Future Use‘0’
ST3For Future Use‘0’
ST2For Future Use‘0’
ST1For Future Use‘0’
ST0For Future Use‘0’
“-” Don’t care
Default
StatusDefault Value (ST31 to ST0)
ST[31-24]ST[23-16]ST[15-8]ST[7-0]
Power On Sequence0000-00000110-00010000-00000000-0000
S/W Reset0xxx0xx000xxx-00010000-00000000-0000
H/W Reset0000-00000110-00010000-00000000-0000
Flow Chart
10.1.5 RDDPM (0Ah): Read Display Power Mode
0AHRDDPM (Read Display Power Mode)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
RDDPM0↑1-00001010(0Ah)
$1^{st}$ Parameter11↑----------
$2^{nd}$ Parameter11↑BSTONIDMONPTLONSLPOUTNORONDISOND1D0
DescriptionThis command indicates the current status of the display as described in the table below:“-“ Don’t care
BitDescriptionValue
BSTONBooster Voltage Status‘1’ =Booster on,‘0’ =Booster off
IDMONIdle Mode On/Off‘1’ = Idle Mode On,‘0’ = Idle Mode Off
PTLONPartial Mode On/Off‘1’ = Partial Mode On,‘0’ = Partial Mode Off
SLPONSleep In/Out‘1’ = Sleep Out,‘0’ = Sleep In
NORONDisplay Normal Mode On/Off‘1’ = Normal Display,‘0’ = Partial Display
DISONDisplay On/Off‘1’ = Display On,‘0’ = Display Off
D1Not Used‘0’
D0Not Used‘0’
Default
StatusDefault Value (D7 to D0)
Power On Sequence0000_1000(08h)
S/W Reset0000_1000(08h)
H/W Reset0000_1000(08h)
Flow Chart
10.1.6 RDDMADCTL (0Bh): Read Display MADCTL
0BHRDDMADCTL (Read Display MADCTL)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
RDDMADCTL0↑1-00001011(0Bh)
$1^{st}$ Parameter11↑----------
$2^{nd}$ Parameter11↑MYMXMVMLRGBMHD1D0
DescriptionThis command indicates the current status of the display as described in the table below:“-” Don’t care
BitDescriptionValue
MXColumn Address Order‘1’ = Right to Left (When MADCTL B6=‘1’)‘0’ = Left to Right (When MADCTL B6=‘0’)
MYRow Address Order‘1’ = Bottom to Top (When MADCTL B7=‘1’)‘0’ = Top to Bottom (When MADCTL B7=‘0’)
MVRow/Column Order (MV)‘1’ = Row/column exchange (MV=1)‘0’ = Normal (MV=0)
MLVertical Refresh Order‘1’ =LCD Refresh Bottom to Top‘0’ =LCD Refresh Top to Bottom
RGBRGB/BGR Order‘1’ =BGR, “0”=RGB
MHHorizontal Refresh OrderLCD horizontal refresh direction control‘0’ = LCD horizontal refresh Left to right‘1’ = LCD horizontal refresh right to left
D1Not Used‘0’
D0Not Used‘0’
Default
StatusDefault Value (D7 to D0)
Power On Sequence0000_0000 (00h)
S/W ResetNo change
H/W Reset0000_0000 (00h)
Flow Charte l :
10.1.7 RDDCOLMOD (0Ch): Read Display Pixel Format
0CHRDDCOLMOD (Read Display Pixel Format)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
RDDCOLMOD0↑1-00001100(0Ch)
1stParameter11↑----------
2ndParameter11↑-0000-IFPF2IFPF1IFPF0
DescriptionThis command indicates the current status of the display as described in the table below:
IFPF[2:0]MCU Interface Color Format
01112-bit/pixel
10116-bit/pixel
11018-bit/pixel
111No used
Others are no define and invalid“-” Don’t care
Default
StatusDefault Value
IFPF[2:0]
Power On Sequence0110 (18 bits/pixel)
S/W ResetNo Change
H/W Reset0110 (18 bits/pixel)
Flow Chart
10.1.8 RDDIM (0Dh): Read Display Image Mode
0DHRDDIM (0Dh): Read Display Image Mode
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
RDDIM0↑1-00001101(0Dh)
$1^{st}$ Parameter11↑----------
$2^{nd}$ Parameter11↑-VSSOND6INVOND4D3GCS2GCS1GCS0
DescriptionThis command indicates the current status of the display as described in the table below:“-“ Don’t care
BitDescriptionValue
VSSONReversed“0”
D6Reversed“0”
INVONInversion On/Off“1” = Inversion is On,“0” = Inversion is Off
D4All Pixels On“0” (Not used)
D3All Pixels Off“0” (Not used)
GCS2GCS1GCS0Gamma CurveSelection“000” = GC0,“001” = GC1,“010” = GC2,“011” = GC3, "100” to “111” = Not defined
Default
StatusDefault Value(D7 to D0)
Power On Sequence0000_0000 (00h)
S/W Reset0000_0000 (00h)
H/W Reset0000_0000 (00h)
Flow Chart
10.1.9 RDDSM (0Eh): Read Display Signal Mode
0EHRDDSM (0Eh): Read Display Signal Mode
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
RDDSM0↑1-00001110(0Eh)
$1^{st}$ Parameter11↑----------
$2^{nd}$ Parameter11↑-TEONTEMD5D4D3D2D1D0
DescriptionThis command indicates the current status of the display as described in the table below:“-” Don’t care
BitDescriptionValue
TEONTearing Effect Line On/Off“1” = On,“0” = Off
TEMTearing effect line mode“1” = Mode2,“0” = Mode1
D5Not Used“1” = On,“0” = Off
D4Not Used“1” = On,“0” = Off
D3Not Used“1” = On,“0” = Off
D2Not Used“1” = On,“0” = Off
D1Not Used“1” = On,“0” = Off
D0Not Used“1” = On,“0” = Off
Default
StatusDefault Value(D7~D0)
Power On Sequence0000_0000 (00h)
S/W Reset0000_0000 (00h)
H/W Reset0000_0000 (00h)
Flow Chart
10.1.10 RDDSDR (0Fh): Read Display Self-Diagnostic Result
0FHRDDSDR (0Fh): Read Display Self-Diagnostic Result
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
RDDSDR0↑1-00001111(0Fh)
1stParameter11↑----------
2ndParameter11↑-RELDFUNDATTDBRDD3D2D1D0
DescriptionThis command indicates the current status of the display as described in the table below:“-” Don’t care
BitDescriptionValue
RELDRegister Loading DetectionSee Section 9.19.1
FUNDFunctionality DetectionSee Section 9.19.2
ATTDChip Attachment DetectionSee Section 9.19.3
BRDDisplay Glass Break DetectionSee Section 9.19.4
D3Not Used“0”
D2Not Used“0”
D1Not Used“0”
D0Not Used“0”
DefaultStatusDefault Value(D7~D0)
Power On Sequence0000_0000 (00h)
S/W Reset0000_0000 (00h)
H/W Reset0000_0000 (00h)
Flow Chart
BitDescriptionValue
RELDRegister Loading DetectionSee Section 9.19.1
FUNDFunctionality DetectionSee Section 9.19.2
ATTDChip Attachment DetectionSee Section 9.19.3
BRDDisplay Glass Break DetectionSee Section 9.19.4
D3Not Used“0”
D2Not Used“0”
D1Not Used“0”
D0Not Used“0”
StatusDefault Value(D7~D0)
Power On Sequence0000_0000 (00h)
S/W Reset0000_0000 (00h)
H/W Reset0000_0000 (00h)
10.1.11 SLPIN (10h): Sleep In
10HSLPIN (Sleep In)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
SLPIN0↑1-00010000(10h)
ParameterNo Parameter-
Description-This command causes the LCD module to enter the minimum power consumption mode.-In this mode the DC/DC converter is stopped, Internal display oscillator is stopped, and panel scanning is stopped.
Restriction-This command has no effect when module is already in Sleep In mode. Sleep In Mode can only be exit by the Sleep Out Command (11h).-When IC is in Sleep Out or Display On mode, it is necessary to wait 120msec before sending next command because of the stabilization timing for the supply voltages and clock circuits.
Default
StatusDefault Value
Power On SequenceSleep In Mode
S/W ResetSleep In Mode
H/W ResetSleep in Mode
Flow Chart
10.1.12 SLPOUT (11h): Sleep Out
11HSLPOUT (Sleep Out)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
SLPOUT0↑1-00010001(11h)
ParameterNo Parameter-
Description-This command turns off sleep mode.-In this mode the DC/DC converter is enabled, Internal display oscillator is started, and panel scanning is started.
Restriction-This command has no effect when module is already in sleep out mode. Sleep Out Mode can only be exit by the Sleep In Command (10h).-When IC is in Sleep In mode, it is necessary to wait 120msec before sending next command because of the stabilization timing for the supply voltages and clock circuits.-When IC is in Sleep Out or Display On mode, it is necessary to wait 120msec before sending next command due to the download of default value of registers and the execution of self-diagnostic function.
Default
StatusDefault Value
Power On SequenceSleep In Mode
S/W ResetSleep In Mode
H/W ResetSleep in Mode
Flow Chart[IMAGE]
10.1.13 PTLON (12h): Partial Display Mode On
12HPTLON (12h): Partial Display Mode On
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
PTLON0↑1-00010010(12h)
ParameterNo Parameter-
Description-This command turns on Partial mode. The partial mode window is described by the Partial Area command (30h)-To leave Partial mode, the Normal Display Mode On command (13h) should be written."-" Don't care
DefaultStatusDefault Value
Power On SequenceNormal Mode On
S/W ResetNormal Mode On
H/W ResetNormal Mode On
Flow ChartSee Partial Area (30h)
10.1.14 NORON (13h): Normal Display Mode On
13HNORON (Normal Display Mode On)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
NORON0↑1-00010011(13h)
ParameterNo Parameter-
Description-This command returns the display to normal mode.-Normal display mode on means Partial mode off.-Exit from NORON by the Partial mode On command (12h)"-" Don't care
DefaultStatusDefault Value
Power On SequenceNormal Mode On
S/W ResetNormal Mode On
H/W ResetNormal Mode On
Flow ChartSee Partial Area Definition Descriptions for details of when to use this command
10.1.15 INVOFF (20h): Display Inversion Off
20HIVNOFF (Normal Display Mode Off)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
INVOFF0↑1-00100000(20h)
ParameterNo Parameter-
Description-This command is used to recover from display inversion mode. "- " Don't care (Example)
DefaultStatusDefault Value
Power On SequenceDisplay Inversion off
S/W ResetDisplay Inversion off
H/W ResetDisplay Inversion off
Flow Chart
10.1.16 INVON (21h): Display Inversion On
21HIVNOFF (Display Inversion On)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
INVON0↑1-00100001(21h)
ParameterNo Parameter-
Description-This command is used to enter into display inversion mode-To exit from Display Inversion On, the Display Inversion Off command (20h) should be written."-" Don't care (Example)Top-Left (0,0) Memory Display
DefaultStatusDefault Value
Power On SequenceDisplay Inversion off
S/W ResetDisplay Inversion off
H/W ResetDisplay Inversion off
Flow ChartLegendCommandParameterDisplayActionModeSequential transter
10.1.17 GAMSET (26h): Gamma Set
26HGAMSET (Gamma Set)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
GAMSET0↑1-00100110(26h)
Parameter1↑1-----GC3GC2GC1GC0
Description-This command is used to select the desired Gamma curve for the current display. A maximum of 4 curves can be selected. The curve is selected by setting the appropriate bit in the parameter as described in the Table.
GC [7:0]ParameterCurve Selected
GS=1GS=0
01hGC0Gamma Curve 1 (G2.2)Gamma Curve 1 (G1.0)
02hGC1Gamma Curve 2 (G1.8)Gamma Curve 2 (G2.5)
04hGC2Gamma Curve 3 (G2.5)Gamma Curve 3 (G2.2)
08hGC3Gamma Curve 4 (G1.0)Gamma Curve 4 (G1.8)
Note: All other values are undefined.
DefaultStatusDefault Value
Power On Sequence01h
S/W Reset01h
H/W Reset01h
Flow Chart
10.1.18 DISPOFF (28h): Display Off
28HDISPOFF (Display Off)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
DISPOFF0↑1-00101000(28h)
ParameterNo Parameter-
Description- This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is disabled and blank page inserted. - This command makes no change of contents of frame memory. - This command does not change any other status. - There will be no abnormal visible effect on the display. - Exit from this command by Display On (29h)
DefaultStatusDefault Value
Power On SequenceDisplay off
S/W ResetDisplay off
H/W ResetDisplay off
Flow Chart
10.1.19 DISPON (29h): Display On
29HDISPON (Display On)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
DISPON0↑1-00101001(29h)
ParameterNo Parameter-
Description- This command is used to recover from DISPLAY OFF mode. - Output from the Frame Memory is enabled. - This command makes no change of contents of frame memory. - This command does not change any other status.
DefaultStatusDefault Value
Power On SequenceDisplay off
S/W ResetDisplay off
H/W ResetDisplay off
Flow Chart
10.1.20 CASET (2Ah): Column Address Set
2AHCASET(Column Address Set)_
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
CASET(2Ah)0↑1-00101010(2Ah)
$1^{st}$ Parameter1↑1-XS15XS14XS13XS12XS11XS10XS9XS8
$2^{nd}$ Parameter1↑1-XS7XS6XS5XS4XS3XS2XS1XS0
$3^{rd}$ Parameter1↑1-XE15XE14XE13XE12XE11XE10XE9XE8
$4^{th}$ Parameter1↑1-XE7XE6XE5XE4XE3XE2XE1XE0
Description-The value of XS [7:0] and XE [7:0] are referred when RAMWR command comes.-Each value represents one column line in the Frame Memory.
RestrictionXS [15:0] always must be equal to or less than XE [15:0]When XS [15:0] or XE [15:0] is greater than maximum address like below, data of out of range will be ignored.1. 128X160 memory base (GM = '11')(Parameter range: 0 < XS [15:0] < XE [15:0] < 127 (007Fh)): MV="0")(Parameter range: 0 < XS [15:0] < XE [15:0] < 159 (009Fh)): MV="1")2. 132X132 memory base (GM = '01')(Parameter range: 0 < XS [15:0] < XE [15:0] < 131 (0083h)): MV="0")(Parameter range: 0 < XS [15:0] < XE [15:0] < 131 (0083h)): MV="1")3. 132X162 memory base (GM = '00')(Parameter range: 0 < XS [15:0] < XE [15:0] < 131 (0083h)): MV="0")(Parameter range: 0 < XS [15:0] < XE [15:0] < 161 (00A1h)): MV="1")
Default
GM StatusStatusDefault Value
XS [7:0]XE [7:0] (MV='0')XE [7:0] (MV='1')
GM='11'(128x160 Memory Base)Power On Sequence0000h007Fh (127)
S/W Reset0000h007Fh (127)009Fh (159)
H/W Reset0000h007Fh (127)
GM='01'(132x132 Memory Base)Power On Sequence0000h0083h (131)
S/W Reset0000h0083h (131)0083h (131)
H/W Reset0000h0083h (131)
GM='00'(132x162 Memory Base)Power On Sequence0000h0083h (131)
S/W Reset0000h0083h (131)00A1h (161)
H/W Reset0000h0083h (131)
Flow Chart
10.1.21 RASET (2Bh): Row Address Set
2BHRASET (Row Address Set)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
RASET (2Bh)0↑1-00101011(2Bh)
$1^{st}$ Parameter1↑1-YS15YS14YS13YS12YS11YS10YS9YS8
$2^{nd}$ Parameter1↑1-YS7YS6YS5YS4YS3YS2YS1YS0
$3^{rd}$ Parameter1↑1-YE15YE14YE13YE12YE11YE10YE9YE8
$4^{th}$ Parameter1↑1-YE7YE6YE5YE4YE3YE2YE1YE0
DescriptionThe value of YS [7:0] and YE [7:0] are referred when RAMWR command comes.Each value represents one column line in the Frame Memory.
RestrictionYS [15:0] always must be equal to or less than YE [15:0]When YS [15:0] or YE [15:0] are greater than maximum row address like below, data of out of range will be ignored.1. 128X160 memory base (GM = '11')(Parameter range: 0 < YS [15:0] < YE [15:0] < 159 (009Fh)): MV="0"(Parameter range: 0 < YS [15:0] < YE [15:0] < 127 (007Fh)): MV="1"2. 132X132 memory base (GM = '00')(Parameter range: 0 < YS [15:0] < YE [15:0] < 131 (00A1h)): MV="0"(Parameter range: 0 < YS [15:0] < YE [15:0] < 131 (0083h)): MV="1"3. 132X162 memory base (GM = '00')(Parameter range: 0 < YS [15:0] < YE [15:0] < 161 (00A1h)): MV="0"(Parameter range: 0 < YS [15:0] < YE [15:0] < 131 (0083h)): MV="1"
Default
GM statusStatusDefault Value
YS [15:0]YE [15:0] (MV='0')YE [15:0] (MV='1')
GM='11' (128x160 memory base)Power On Sequence0000h009Fh (159)
S/W Reset0000h009Fh (159)007Fh (127)
H/W Reset0000h009Fh (159)
GM='01' (132x132 Memory Base)Power On Sequence0000h0083h (131)
S/W Reset0000h0083h (131)0083h (131)
H/W Reset0000h0083h (131)
GM='00' (132x162 memory base)Power On Sequence0000h00A1h (161)
S/W Reset0000h00A1h (161)0083h (131)
H/W Reset0000h00A1h (161)
Flow Chart
10.1.22 RAMWR (2Ch): Memory Write
2CHRAMWR (Memory Write)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
RAMWR0↑1-00101100(2Ch)
1st Parameter1↑1D17-8D7D6D5D4D3D2D1D0
|1↑1|||||||||
Nth Parameter1↑1D17-8D7D6D5D4D3D2D1D0
DescriptionIn all color modes, there is no restriction on length of parameters.1. 128X160 memory base (GM = '11')128x160x18-bit memory can be written by this commandMemory range: (0000h, 0000h) -> (007Fh, 09Fh)2. 132x132 memory base (GM = '01')132x132x18-bit memory can be written on this command.Memory range: (0000h, 0000h) -> (0083h, 0083h)3. 132x162 memory base (GM = '00')132x162x18-bit memory can be written on this command.Memory range: (0000h, 0000h) -> (0083h, 00A1h)
DefaultStatusDefault Value
Power On SequenceContents of memory is set randomly
S/W ResetContents of memory is not cleared
H/W ResetContents of memory is not cleared
Flow Chart
10.1.23 RGBSET (2Dh): Color Setting for 4K, 65K and 262K
2DHRGBSET (Color Set for 4K, 65K, 262K and 16.7M)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
RGBSET0↑1-00101101(2Dh)
1st Parameter1↑1---R005R004R003R002R001R000
|1↑1---Rnn5Rnn4Rnn3Rnn2Rnn1Rnn0
|1↑1---R315R314R313R312R311R310
|1↑1---G005G004G003G002G001G000
|1↑1---Gnn5Gnn4Gnn3Gnn2Gnn1Gnn0
|1↑1---G635G634G633G632G631G630
|1↑1---B005B004B003B002B001B000
|1↑1---Bnn5Bnn4Bnn3Bnn2Bnn1Bnn0
128th Parameter1↑1---B315B314B313B312B311B310
DescriptionThis command is used to define the LUT for 12bits-to-16bits / 16-bit-to- 18bits color depth conversations.128-Bytes must be written to the LUT regardless of the color mode. Only the values in Section 9.18 are referred.In this condition, 4K-color (4-4-4) and 65K-color(5-6-5) data input are transferred 6(R)-6(G)-6(B) through RGB LUT table.This command has no effect on other commands/parameters and Contents of frame memory.Visible change takes effect next time the Frame Memory is written to.Do not send any command before the last data is sent or LUT is not defined correctly.
DefaultStatusDefault Value
Power On SequenceRandom
S/W ResetContents of the look-up table protected
LUTR
Flow Chart
10.1.24 RAMRD (2Eh): Memory Read
2EHRAMHD (Memory Read)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
RAMHD0↑1-00101110(2Eh)
$1^{st}$ Parameter11↑---------
$2^{nd}$ Parameter11↑D17-8D7D6D5D4D3D2D1D0
|11↑|||||||||
(N+1)th Parameter11↑D17-8D7D6D5D4D3D2D1D0
Description-This command is used to transfer data from frame memory to MCU.-When this command is accepted, the column register and the row register are reset to the Start Column/Start Row positions.-The Start Column/Start Row positions are different in accordance with MADCTL setting.-Then D[17:0] is read back from the frame memory and the column register and the row register incremented as section 9.10-Frame Read can be cancelled by sending any other command.-The data color coding is fixed to 18-bit in reading function. Please see section 9.8 "Data color coding" for color coding (18-bit cases), when there is used 8, 9, 16 and 18-bit data lines for image data.Note1: The Command 3Ah should be set to 66h when reading pixel data from frame memory. Please check the LUT in chapter 9.17 when using memory read function.
DefaultStatusDefault Value
Power On SequenceContents of memory is set randomly
S/W ResetContents of memory is not cleared
H/W ResetContents of memory is not cleared
Flow Chart
10.1.25 PTLAR (30h): Partial Area
30HPTLAR (Partial Area)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
PTLAR0↑1-00110000(30h)
1st Parameter1↑1-PSL15PSL14PSL13PSL12PSL11PSL10PSL9PSL8
2nd Parameter1↑1-PSL7PSL6PSL5PSL4PSL3PSL2PSL1PSL0
3rd Parameter1↑1-PEL15PEL14PEL13PEL12PEL11PEL10PEL9PEL8
4th Parameter1↑1-PEL7PEL6PEL5PEL4PEL3PEL2PEL1PEL0
Description-This command defines the partial mode's display area.-There are 4 parameters associated with this command, the first defines the Start Row (PSL) and the second the End Row (PEL), as illustrated in the figures below. PSL and PEL refer to the Frame Memory row address counter.-If End Row > Start Row, when MADCTL ML='0'-If End Row > Start Row, when MADCTL ML='1'-If End Row < Start Row, when MADCTL ML='0'-If End Row = Start Row then the Partial Area will be one row deep.
DefaultStatusDefault Value
PSL [15:0]PEL [15:0]
GM[1:0]“xx”GM[1:0]="11"GM[1:0]="01"GM[1:0]="00"
Power On Sequence0000h009Fh0083h00A1h
S/W Reset0000h009Fh0083h00A1h
H/W Reset0000h009Fh0083h00A1h
Flow Chart2. Leave Partial Mode1.1
StatusDefault Value
PSL [15:0]PEL [15:0]
GM[1:0]“xx”GM[1:0]="11"GM[1:0]="01"GM[1:0]="00"
Power On Sequence0000h009Fh0083h00A1h
S/W Reset0000h009Fh0083h00A1h
H/W Reset0000h009Fh0083h00A1h
2. Leave Partial Mode Legend 10.1.26 SCRLAR (33h): Scroll Area Set
33HSCRLAR (Scroll Area)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
SCRLAR0↑1-00110011(33h)
$1^{st}$ parameter1↑1-TFA15TFA14TFA13TFA12TFA11TFA10TFA9TFA8-
$2^{nd}$ parameter1↑1-TFA7TFA6TFA5TFA4TFA3TFA2TFA1TFA0-
$3^{rd}$ parameter1↑1-VSA15VSA14VSA13VSA12VSA11VSA10VSA9VSA8-
$4^{th}$ parameter1↑1-VSA7VSA6VSA5VSA4VSA3VSA2VSA1VSA0-
$5^{th}$ parameter1↑1-BFA15BFA14BFA13BFA12BFA11BFA10BFA9BFA8-
$6^{nd}$ parameter1↑1-BFA7BFA6BFA5BFA4BFA3BFA2BFA1BFA0-
Description-This command just defines the Vertical Scrolling Area of the display and not performs vertical scroll-When MADCTR B4=0-The $1^{st}$ & $2^{nd}$ parameter TFA [15:0] describes the Top Fixed Area (in No. of lines from Top of the Frame Memory and Display).-The $3^{rd}$ & $4^{th}$ parameter VSA [15:0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address) The first line appears immediately after the bottom most line of the Top Fixed Area.-The $4^{th}$ & $5^{th}$ parameter BFA [6:0] describes the Bottom Fixed Area (in No. of lines from Bottom of the Frame Memory and Display).TFA, VSA and BFA refer to the Frame Memory Line Pointer
RestrictionThe condition is (TFA+VSA+BFA) = 162, otherwise Scrolling mode is undefined.In Vertical Scroll Mode, MADCTR parameter MV should be set to '0'-this only affects the Frame Memory Write.TFA[15:0], VSA[15:0] and BFA[15:0] is based on line unit.TFA[15:0]= 0000h, 0001h, 0002h, 0003h, ..., 00A2hVSA[15:0]= 0000h, 0001h, 0002h, 0003h, ..., 00A2hBFA[15:0]= 0000h, 0001h, 0002h, 0003h, ..., 00A2h
Register AvailabilityStatusAvailability
Normal Mode On, Idle Mode Off, Sleep OutYes
Normal Mode On, Idle Mode On, Sleep OutYes
Partial Mode On, Idle Mode Off, Sleep OutYes
Partial Mode On, Idle Mode On, Sleep OutYes
Sleep InYes
DefaultStatusDefault Value GM[1:0]=“11”
Power On SequenceTFA[15:0]=0000hVSA[15:0]=00A0hBFA[15:0]=0000h
S/W ResetTFA[15:0]=0000hVSA[15:0]=00A0hBFA[15:0]=0000h
H/W ResetTFA[15:0]=0000hVSA[15:0]=00A0hBFA[15:0]=0000h
StatusDefault Value GM[1:0]=“01”
Power On SequenceTFA[15:0]=0000hVSA[15:0]=0084hBFA[15:0]=0000h
S/W ResetTFA[15:0]=0000hVSA[15:0]=0084hBFA[15:0]=0000h
H/W ResetTFA[15:0]=0000hVSA[15:0]=0084hBFA[15:0]=0000h
StatusDefault Value GM[1:0]=“00”
Power On SequenceTFA[15:0]=0000hVSA[15:0]=00A2hBFA[15:0]=0000h
S/W ResetTFA[15:0]=0000hVSA[15:0]=00A2hBFA[15:0]=0000h
H/W ResetTFA[15:0]=0000hVSA[15:0]=00A2hBFA[15:0]=0000h
Flow Chart1. TO Enter Vertical Scroll Mode:
Only required for non-rolling scrolling
10.1.27 TEOFF (34h): Tearing Effect Line OFF
34HTEOFF (Tearing Effect Line OFF)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
TEOFF0↑1-00110100(34h)
ParameterNo Parameter-
Description-This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line.
DefaultStatusDefault Value
Power On SequenceOFF
S/W ResetOFF
H/W ResetOFF
Flow Chart
10.1.28 TEON (35h): Tearing Effect Line ON
35HTEON (Tearing Effect Line ON)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
TEON0↑1-00110101(35h)
Parameter1↑1-0000000TEM
Description-This command is used to turn ON the Tearing Effect output signal from the TE signal line.-This output is not affected by changing MADCTL bit ML.-The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect Output Line:-When TEM ='0': The Tearing Effect output line consists of V-Blanking information only
-When TEM ='1': The Tearing Effect output Line consists of both V-Blanking and H-Blanking information
Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low.
DefaultStatusDefault Value
Power On SequenceTearing effect off & TEM=0
S/W ResetTearing effect off & TEM=0
H/W ResetTearing effect off & TEM=0
Flow Chart
10.1.29 MADCTL (36h): Memory Data Access Control
36HMADCTL (Memory Data Access Control)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
MADCTL0↑1-00110110(36h)
Parameter1↑1-MYMXMVMLRGBMH--
Description-This command defines read/ write scanning direction of frame memory.
BitNAMEDESCRIPTION
MYRow Address OrderThese 3bits controls MCU to memory write/read direction.
MXColumn Address Order
MVRow/Column Exchange
MLVertical Refresh OrderLCD vertical refresh direction control‘0’ = LCD vertical refresh Top to Bottom‘1’ = LCD vertical refresh Bottom to Top
RGBRGB-BGR ORDERColor selector switch control‘0’ =RGB color filter panel,‘1’ =BGR color filter panel)
MHHorizontal Refresh OrderLCD horizontal refresh direction control‘0’ = LCD horizontal refresh Left to right‘1’ = LCD horizontal refresh right to left
-Bit Assignment
![](images/b23975b301e2222a84b61c2da71f4a75086a59180d6f4e72412f098983111220.jpg)
DefaultStatusDefault Value
Power On SequenceMY=0,MX=0,MV=0,ML=0,RGB=0,MH=0
S/W ResetNo Change
H/W ResetMY=0,MX=0,MV=0,ML=0,RGB=0,MH=0
Flow Chart
10.1.30 VSCSAD: Vertical Scroll Start Address of RAM (37h)
37HSCRLAR (Scroll Area)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
VSCSAD0↑1-00110111(37h)
Parameter11↑1-00000000
Parameter21↑1-SSA7SSA6SSA5SSA4SSA3SSA2SSA1SSA0-
Description-This command is used together with Vertical Scrolling Definition (33h).-These two commands describe the scrolling area and the scrolling mode.-The Vertical Scrolling Start Address command has one parameter which describes which line in the Frame Memory will be written as the first line after the last line of the Top Fixed Area on the display as illustrated below:-This command Start the scrolling.-Exit from V-scrolling mode by commands Partial mode On (12h) or Normal mode On (13h)[WWW6W]SCNOTE: When new Pointer position and Picture Data are sent, the result on the display will happen at the next Panel Scan to avoid tearing effect.SSA refers to the Frame Memory line Pointer
RestrictionSince the value of the Vertical Scrolling Start Address is absolute (with reference to the Frame Memory), it must not enter the fixed area (defined by Vertical Scrolling Definition (33h)-otherwise undesirable image will be displayed on the Panel.SSA [6:0] is based on line unit.SSA [6:0] = 00h, 01h, 02h, 03h, ..., A1h
Register AvailabilityStatusAvailability
Normal Mode On, Idle Mode Off, Sleep OutYes
Normal Mode On, Idle Mode On, Sleep OutYes
Partial Mode On, Idle Mode Off, Sleep OutNo
Partial Mode On, Idle Mode On, Sleep OutNo
Sleep InYes
Default
Status
Power On Sequence
S/W Reset
H/W Reset
Flow ChartSee Vertical Scrolling Definition (33h) description.
10.1.31 IDMOFF (38h): Idle Mode Off
38HIDMOFF (Idle Mode Off)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
IDMOFF0↑1-00111000(38h)
ParameterNo Parameter-
Description-This command is used to recover from Idle mode on. -In the idle off mode, 1. LCD can display 4096, 65k or 262k colors. 2. Normal frame frequency is applied.
DefaultStatusDefault Value
Power On SequenceIdle Mode Off
S/W ResetIdle Mode Off
HWDRIdle Mode Off
Flow Chart
10.1.32 IDMON (39h): Idle Mode On
39HIDMON (Idle Mode On)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
IDMOFF0↑1-00111001(39h)
ParameterNo Parameter-
Description-This command is used to enter into Idle mode on.-There will be no abnormal visible effect on the display mode change transition.-In the idle on mode,1. Color expression is reduced. The primary and the secondary colors using MSB of each R,G and B in the Frame Memory, 8 color depth data is displayed.2. 8-Color mode frame frequency is applied.3. Exit from IDMON by Idle Mode Off (38h) command (Example)Top-Left (0,0)
ColorR5 R4 R3 R2 R1 R0G5 G4 G3 G2 G1 G0B5 B4 B3 B4 B1 B0
Black0xxxx0xxxx0xxxx
Blue0xxxx0xxxx1xxxx
Red1xxxx0xxxx0xxxx
Magenta1xxxx0xxxx1xxxx
Green0xxxx1xxxx0xxxx
Cyan0xxxx1xxxx1xxxx
Yellow1xxxx1xxxx0xxxx
White1xxxx1xxxx1xxxx
Register AvailabilityStatusAvailability
Normal Mode On, Idle Mode Off, Sleep OutYes
Normal Mode On, Idle Mode On, Sleep OutYes
Partial Mode On, Idle Mode Off, Sleep OutNo
Partial Mode On, Idle Mode On, Sleep OutNo
Sleep InYes
DefaultStatusDefault Value
Power On SequenceIdle Mode Off
S/W ResetIdle Mode Off
H/W ResetIdle Mode Off
Flow Chart
10.1.33 COLMOD (3Ah): Interface Pixel Format
3AHCOLMOD (3Ah): Interface Pixel Format
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
COLMOD0↑1-00111010(3Ah)
Parameter1↑1------IFPF2IFPF1IFPF0
DescriptionThis command is used to define the format of RGB picture data, which is to be transferred via the MCU interface. The formats are shown in the table:
IFPF[2:0]MCU Interface Color Format
011312-bit/pixel
101516-bit/pixel
110618-bit/pixel
1117No used
Note1: In 12-bit/Pixel, 16-bit/Pixel or 18-bit/Pixel mode, the LUT is applied to transfer data into the Frame Memory.Note2: The Command 3Ah should be set at 55h when writing 16-bit/pixel data into frame memory, but 3Ah should be re-set to 66h when reading pixel data from frame memory. Please check the LUT in chapter 9.17 when using memory read function.
Register AvailabilityStatusAvailability
Normal Mode On, Idle Mode Off, Sleep OutYes
Normal Mode On, Idle Mode On, Sleep OutYes
Partial Mode On, Idle Mode Off, Sleep OutNo
Partial Mode On, Idle Mode On, Sleep OutNo
Sleep InYes
DefaultStatusDefault Value
IFPF[2:0]VIPF[3:0]
Power On Sequence0110(18-bit/Pixel)0110(18-bit/Pixel)
S/W ResetNo ChangeNo Change
H/W Reset0110(18-bit/Pixel)0110(18-bit/Pixel)
Flow Chart
10.1.34 RDID1 (DAh): Read ID1 Value
DAHRDID1 (Read ID1 Value)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
RDID10↑1-11011010(DAh)
1st Parameter11↑----------
2nd Parameter11↑-ID17ID16ID15ID14ID13ID12ID11ID10
Description-This read byte returns 8-bit LCD module's manufacturer ID-The 1st parameter is dummy data-The 2nd parameter (ID17 to ID10): LCD module's manufacturer ID.NOTE: See command RDDID (04h), 2nd parameter.
Register AvailabilityStatusAvailability
Normal Mode On, Idle Mode Off, Sleep OutYes
Normal Mode On, Idle Mode On, Sleep OutYes
Partial Mode On, Idle Mode Off, Sleep OutNo
Partial Mode On, Idle Mode On, Sleep OutNo
Sleep InYes
DefaultStatusDefault Value
Power On Sequence0x7C
S/W Reset0x7C
H/W Reset0x7C
Flow Chart
10.1.35 RDID2 (DBh): Read ID2 Value
DBHRDID2 (Read ID2 Value)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
RDID20↑1-11011011(DBh)
$1^{st}$ Parameter11↑----------
$2^{nd}$ Parameter11↑-1ID26ID25ID24ID23ID22ID21ID20
Description-This read byte returns 8-bit LCD module/driver version ID-The $1^{st}$ parameter is dummy data-The $2^{nd}$ parameter (ID26 to ID20): LCD module/driver version ID-Parameter Range: ID=80h to FFh
ID26 to ID20VersionChanges
80h
81h
82h
83h
NOTE: See command RDDID (04h), $3^{rd}$ parameter.
Register AvailabilityStatusAvailability
Normal Mode On, Idle Mode Off, Sleep OutYes
Normal Mode On, Idle Mode On, Sleep OutYes
Partial Mode On, Idle Mode Off, Sleep OutNo
Partial Mode On, Idle Mode On, Sleep OutNo
Sleep InYes
DefaultStatusDefault Value
Power On SequenceNV Value
S/W ResetNV Value
H/W ResetNV Value
Flow ChartLegend
Legend ![](images/ab4f8733957a2140a58011bb06e7b972f9b1de82c752980abdd05f83a7d47956.jpg) 10.1.36 RDID3 (DCh): Read ID3 Value
DCHRDID3 (Read ID2 Value)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
RDID30↑1-11011100(DCh)
1stParameter11↑----------
2ndParameter11↑-ID37ID36ID35ID34ID33ID32ID31ID30
Description-This read byte returns 8-bit LCD module/driver ID.-The 1stparameter is dummy data-The 2ndparameter (ID37 to ID30): LCD module/driver ID.NOTE: See command RDDID (04h), 4thparameter.
Register AvailabilityStatusAvailability
Normal Mode On, Idle Mode Off, Sleep OutYes
Normal Mode On, Idle Mode On, Sleep OutYes
Partial Mode On, Idle Mode Off, Sleep OutNo
Partial Mode On, Idle Mode On, Sleep OutNo
Sleep InYes
DefaultStatusDefault Value
Power On SequenceNV Value
S/W ResetNV Value
H/W ResetNV Value
Flow Chart
## 10.2 Panel Function Command List and Description Table 18 Panel Function Command List (1)
InstructionReferD/CXWRXRDXD23-8D7D6D5D4D3D2D1D0HexFunction
FRMCTR100↑1-10110001(B1h)In Normal Mode (Full Colors)
1↑1-RTNA3RTNA2RTNA1RTNA0RTNA Set 1-line Period FPA: Front Porch BPA: Back Porch
1↑1-FPA5FPA4FPA3FPA2FPA1FPA0
1↑1-BPA5BPA4BPA3BPA2BPA1BPA0
FRMCTR200↑1-10110010(B2h)In Idle Mode (8-colors)
1↑1-RTNB3RTNB2RTNB1RTNB0RTNB: Set 1-line Period FPB: Front Porch BPB: Back Porch
1↑1-FPB5FPB4FPB3FPB2FPB1FPB0
1↑1-BPB5BPB4BPB3BPB2BPB1BPB0
FRMCTR300↑1-10110011(B3h)In Partial Mode + Full Colors
1↑1-RTNC3RTNC2RTNC1RTNC0RTNC,RTND: Set 1-line Period FPC,FPD: Front Porch BPC,BPD: Back Porch
1↑1-FPC5FPC4FPC3FPC2FPC1FPC0
1↑1-BPC5BPC4BPC3BPC2BPC1BPC0
1↑1-RTND3RTND2RTND1RTND0
1↑1-FPD5FPD4FPD3FPD2FPD1FPD0
1↑1-BPD5BPD4BPD3BPD2BPD1BPD0
INVCTR00↑1-10110100(B4h)Display Inversion Control
1↑1-00000NLANLBNLCNLA,NLB,NLC Set Inversion
Table 19 Panel Function Command List (2)
InstructionReferD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HexFunction
PWCTR100↑1-11000000(C0h)Power Control Setting
1↑1-AVDD[2]AVDD[1]AVDD[0]VRHP4VRHP3VRHP2VRHP1VRHP0VRH: Set the GVDD Voltage
1↑1-000VRHN4VRHN3VRHN2VRHN1VRHN0
1↑1MODE[1]MODE[0]000100
PWCTR200↑1-11000001(C1h)Power Control Setting
1↑1-VGH25[1]VGH25[0]--VGLSEL[1]VGLSEL[0]VGHBT[1]VGHBT[0]BT: Set VGH/ VGL Voltage
PWCTR300↑1-11000010(C2h)In Normal Mode (Full Colors)
1↑1-DCA9DCA8SAPA2SAPA1SAPA0APA2APA1APA0APA: Adjust the Operational AmplifierDCA: Adjust the Booster Voltage
-DCA7DCA6DCA5DCA4DCA3DCA2DCA1DCA0
PWCTR400↑1-11000011(C3h)In Idle Mode (8-colors)
1↑1-DCB9DCB8SAPB2SAPB1SAPB0APB2APB1APB0APB: Adjust the Operational AmplifierDCB: Adjust the Booster Voltage
-DCB7DCB6DCB5DCB4DCB3DCB2DCB1DCB0
PWCTR500↑1-11000100(C4h)In Partial Mode + Full colors
1↑1-DCC9DCC8SAPC2SAPC1SAPC0APC2APC1APC0APC: Adjust the Operational AmplifierDCC: Adjust the Booster Circuit for Idle mode
1↑1-DCC7DCC6DCC5DCC4DCC3DCC2DCC1DCC0
VMCTR100↑1-11000101(C5h)VCOM Control 1
1↑1---VCOMS5VCOMS4VCOMS3VCOMS2VCOMS1VCOMS0VCOM Voltage Control
VMOFCTR00↑1-11000111(C7h)Set VCOM Offset control
1↑1----VMF4VMF3VMF2VMF1VMF0
WRID200↑1-11010001(D1h)Set LCM Version Code
1↑1--ID2[6]ID2[5]ID2[4]ID2[3]ID2[2]ID2[1]ID2[0]
“-”: Don't care Note 1: C0h to C7h are fixed for about power controller Table 20 Panel Function Command List (3)
InstructionReferD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HexFunction
WRID300↑1-11010010(D2h)Customer Project Code
1↑1-ID37ID36ID35ID34ID33ID32ID31ID30Set the Project Code at ID3
NVCTR100↑1-11011001(D9)NVM Control Status
1↑1-0VMF_ENID2_EN0000EXT_R
NVCTR200↑1-11011110(Deh)NVM Read Command
1↑1-11110101F5
1↑1-10100101A5Action Code
NVCTR300↑1-11011111(DFh)NVM Write Command Action Code
1↑1-NVM_CMD7NVM_CMD6NVM_CMD5NVM_CMD4NVM_CMD3NVM_CMD2NVM_CMD1NVM_CMD0
1↑1-10100101A5
“-”: Don't care Note 1: The D1h to D3h registers are fixed for about ID code setting. Note 2: The D9h, Deh and DFh registers are used for NV Memory function controller. (Ex: write, clear, etc.) Table 21 Panel Function Command List (4)
InstructionReferD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HexFunction
GAMCTRP100↑1-11100000(E0h)Set
1↑1---VRFP[5]VRFP[4]VRFP[3]VRFP[2]VRFP[1]VRF0P[0]Gamma Adjustment (+ Polarity)
1↑1---VOS0P[5]VOS0P[4]VOS0P[3]VOS0P[2]VOS0P[1]VOS0P[0]
1↑1---PKP0[5]PKP0[4]PKP0[3]PKP0[2]PKP0[1]PKP0[0]
1↑1---PKP1[5]PKP1[4]PKP1[3]PKP1[2]PKP1[1]PKP1[0]
1↑1---PKP2[5]PKP2[4]PKP2[3]PKP2[2]PKP2[1]PKP2[0]
1↑1---PKP3[5]PKP3[4]PKP3[3]PKP3[2]PKP3[1]PKP3[0]
1↑1---PKP4[5]PKP4[4]PKP4[3]PKP4[2]PKP4[1]PKP4[0]
1↑1---PKP5[5]PKP5[4]PKP5[3]PKP5[2]PKP5[1]PKP5[0]
1↑1---PKP6[5]PKP6[4]PKP6[3]PKP6[2]PKP6[1]PKP6[0]
1↑1---PKP7[5]PKP7[4]PKP7[3]PKP7[2]PKP7[1]PKP7[0]
1↑1---PKP8[5]PKP8[4]PKP8[3]PKP8[2]PKP8[1]PKP8[0]
1↑1PKP9[5]PKP9[4]PKP9[3]PKP9[2]PKP9[1]PKP9[0]
1↑1---SELV0P[5]SELV0P[4]SELV0P[3]SELV0P[2]SELV0P[1]SELV0P[0]
1↑1---SELV1P[5]SELV1P[4]SELV1P[3]SELV1P[2]SELV1P[1]SELV1P[0]
1↑1---SELV62P[5]SELV62P[4]SELV62P[3]SELV62P[2]SELV62P[1]SELV62P[0]
1↑1---SELV63P[5]SELV63P[4]SELV63P[3]SELV63P[2]SELV63P[1]SELV63P[0]
GAMCTRN100↑1-11100001(E1h)Set
1↑1---VRF0N[5]VRF0N[4]VRF0N[3]VRF0N[2]VRF0N[1]VRF0N[0]Gamma Adjustment (- Polarity)
1↑1---VOS0N[5]VOS0N[4]VOS0N[3]VOS0N[2]VOS0N[1]VOS0N[0]
1↑1---PKN0[5]PKN0[4]PKN0[3]PKN0[2]PKN0[1]PKN0[0]
1↑1---PKN1[5]PKN1[4]PKN1[3]PKN1[2]PKN1[1]PKN1[0]
1↑1---PKN2[5]PKN2[4]PKN2[3]PKN2[2]PKN2[1]PKN2[0]
1↑1---PKN3[5]PKN3[4]PKN3[3]PKN3[2]PKN3[1]PKN3[0]
1↑1---PKN4[5]PKN4[4]PKN4[3]PKN4[2]PKN4[1]PKN4[0]
1↑1---PKN5[5]PKN5[4]PKN5[3]PKN5[2]PKN5[1]PKN5[0]
1↑1---PKN6[5]PKN6[4]PKN6[3]PKN6[2]PKN6[1]PKN6[0]
1↑1---PKN7[5]PKN7[4]PKN7[3]PKN7[2]PKN7[1]PKN7[0]
1↑1---PKN8[5]PKN8[4]PKN8[3]PKN8[2]PKN8[1]PKN8[0]
1↑1-PKN9[5]PKN9[4]PKN9[3]PKN9[2]PKN9[1]PKN9[0]
1↑1---SELV0N[5]SELV0N[4]SELV0N[3]SELV0N[2]SELV0N[1]SELV0N[0]
1↑1---SELV1N[5]SELV1N[4]SELV1N[3]SELV1N[2]SELV1N[1]SELV1N[0]
1↑1---SELV62N[5]SELV62N[4]SELV62N[3]SELV62N[2]SELV62N[1]SELV62N[0]
1↑1---SELV63N[5]SELV63N[4]SELV63N[3]SELV63N[2]SELV63N[1]SELV63N[0]
1↑1-11011000(FCh)Gate clock Variable
1↑1-GCV Enable1GCV Enable00Clk_VariableClk_Variable00
“-”: Don't care Note 1: E0-E1 registers are fixed for adjusting Gamma 10.2.1 FRMCTR1 (B1h): Frame Rate Control (In normal mode/ Full colors)
B1HFRMCTR1 (Frame Rate Control)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
FRMCTR10↑1-10110001(B1h)
$1^{st}$ Parameter1↑1-----RTNA 3RTNA 2RTNA 1RTNA 0
$2^{nd}$ Parameter1↑1---FPA5FPA4FPA3FPA2FPA1FPA0
$3^{rd}$ Parameter1↑1---BPA5BPA4BPA3BPA2BPA1BPA0
Description-Set the frame frequency of the full colors normal mode.- Frame rate=fosc/((RTNA x 2 + 40) x (LINE + FPA + BPA +2))-fosc = 850kHz-FPA > 0, BPA > 0
DefaultStatusDefault Value
GM[1:0] = "00"GM[1:0] = "01"GM[1:0] = "11"
Power On Sequence05h/3Ah/3Ah08h/3Bh/3Bh05h/3Ch/3Ch
S/W Reset05h/3Ah/3Ah08h/3Bh/3Bh05h/3Ch/3Ch
H/W Reset05h/3Ah/3Ah08h/3Bh/3Bh05h/3Ch/3Ch
Flow Chart
10.2.2 FRMCTR2 (B2h): Frame Rate Control (In Idle mode/ 8-colors)
B2HFRMCTR2 (Frame Rate Control)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
FRMCTR20↑1-10110010(B2h)
1stparameter1↑1-----RTNB3RTNB2RTNB1RTNB0
2ndparameter1↑1---FPB5FPB4FPB3FPB2FPB1FPB0
3rdparameter1↑1---BPB5BPB4BPB3BPB2BPB1BPB0
Description-Set the frame frequency of the Idle mode.- Frame rate=fosc/((RTNA x 2 + 40) x (LINE + FPB + BPB +2))-fosc = 850kHz-FPB > 0, BPB > 0
DefaultStatusDefault Value
GM[1:0] = "00"GM[1:0] = "01"GM[1:0] = "11"
Power On Sequence05h/3Ah/3Ah08h/3Bh/3Bh05h/3Ch/3Ch
S/W Reset05h/3Ah/3Ah08h/3Bh/3Bh05h/3Ch/3Ch
H/W Reset05h/3Ah/3Ah08h/3Bh/3Bh05h/3Ch/3Ch
Flow Chart
10.2.3 FRMCTR3 (B3h): Frame Rate Control (In Partial mode/ full colors)
B3HFRMCTR3 (Frame Rate Control)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
FRMCTR30↑1-10110011(B3h)
1stparameter1↑1-----RTNCRTNCRTNCRTNC
2ndparameter1↑1---FPC5FPC4FPC3FPC2FPC1FPC0
3rdparameter1↑1---BPC5BPC4BPC3BPC2BPC1BPC0
4thparameter1↑1-----RTNDRTNDRTNDRTND
5thparameter1↑1---FPD5FPD4FPD3FPD2FPD1FPD0
6thparameter1↑1---BPD5BPD4BPD3BPD2BPD1BPD0
Description-Set the frame frequency of the Partial mode/ full colors.- 1stparameter to 3rdparameter are used in dot inversion mode.- 4thparameter to 6thparameter are used in column inversion mode.- Frame rate=fosc/((RTNA x 2 + 40) x (LINE + FPC + BPC +2))-fosc = 850kHz-FPC > 0, BPC > 0
DefaultStatusDefault Value
GM[1:0] = "00"GM[1:0] = "01"GM[1:0] = "11"
Power On Sequence05h/3Ah/3Ah08h/3Bh/3Bh05h/3Ch/3Ch
05h/3Ah/3Ah08h/3Bh/3Bh05h/3Ch/3Ch
S/W Reset05h/3Ah/3Ah08h/3Bh/3Bh05h/3Ch/3Ch
05h/3Ah/3Ah08h/3Bh/3Bh05h/3Ch/3Ch
H/W Reset05h/3Ah/3Ah08h/3Bh/3Bh05h/3Ch/3Ch
05h/3Ah/3Ah08h/3Bh/3Bh05h/3Ch/3Ch
Flow Chart
10.2.4 INVCTR (B4h): Display Inversion Control
B4HINVCTR (Display Inversion Control)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
INVCTR0↑1-10110100(B4h)
Parameter1↑1-00000NLANLBNLC
Description-Display Inversion mode control-NLA: Inversion setting in full colors normal mode (Normal mode on)
NLAInversion setting in full Colors normal mode
0Dot Inversion
1Column Inversion
-NLB: Inversion setting in Idle mode (Idle mode on)
NLBInversion setting in Idle mode
0Dot Inversion
1Column Inversion
-NLC: Inversion setting in full colors partial mode (Partial mode on / Idle mode off)
NLCInversion setting in full Colors partial mode
0Dot Inversion
1Column Inversion
DefaultStatusDefault Value
B4h
Power On Sequence07h
S/W Reset07h
H/W Reset07h
Flow Chart
10.2.5 PWCTR1 (C0h): Power Control 1
C0HPWCTR1 (Power Control 1)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
PWCTR10↑1-11000000(C0h)
$1^{st}$ parameter1↑1-AVDD[2]AVDD[1]AVDD[0]VRHP4VRHP3VRHP2VRHP1VRHP0
$2^{nd}$ parameter1↑1-000VRHN4VRHN3VRHN2VRHN1VRHN0
$3^{rd}$ parameter1↑1-MODE[1]MODE[0]0001VRHN5VRHP5
Description
Register AvailabilityStatusAvailability
Normal Mode On, Idle Mode Off, Sleep OutYes
Normal Mode On, Idle Mode On, Sleep OutYes
Partial Mode On, Idle Mode Off, Sleep OutYes
Partial Mode On, Idle Mode On, Sleep OutYes
Sleep InYes
Default
StatusDefault Value
C0h
Power On SequenceA8h/08h/84h
S/W ResetA8h/08h/84h
H/W ResetA8h/08h/84h
Flow Chart
10.2.6 PWCTR2 (C1h): Power Control 2
C1HPWCTR2 (Power Control 2)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
PWCTR20↑1-11000001(C1h)
1stparameter1↑1VGH25[1]VGH25[0]--VGLSEL[1]VGLSEL[0]VGHBT[1]VGHBT[0]
Description-Set the VGH and VGL supply power level
VGH25[1:0]V25
002.1
012.2
102.3
112.4
VGHBT[1:0]VGH
002*AVDD+VGH25-0.5
013*AVDD-0.5
103*AVDD+VGH25-0.5
11Don't use this setting, reserve for testing.
VGLSEL[1:0]VGL
00-7.5
01-10
10-12.5
11-13
Restriction-The deviation value of VGH/ VGL between with Measurement and Specification: Max <= 1V-VGH-VGL <= 32V
Register AvailabilityStatusAvailability
Normal Mode On, Idle Mode Off, Sleep OutYes
Normal Mode On, Idle Mode On, Sleep OutYes
Partial Mode On, Idle Mode Off, Sleep OutYes
Partial Mode On, Idle Mode On, Sleep OutYes
Sleep InYes
Default
StatusDefault Value
C1h
Power On SequenceC0h
S/W ResetC0h
H/W ResetC0h
Flow Chart
10.2.7 PWCTR3 (C2h): Power Control 3 (in Normal mode/ Full colors)
C2HPWCTR3 (Power Control 3)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
PWCTR30↑1-11000010(C2h)
$1^{st}$ 1↑1-DCA9DCA8SAPA2SAPA1SAPA0APA2APA1APA0
$2^{nd}$ 1↑1-DCA7DCA6DCA5DCA4DCA3DCA2DCA1DCA0
Description-Set the amount of current in Operational amplifier in normal mode/full colors.-Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver.
AP[2:0]Amount of Current in Operational Amplifier
000Operation of the operational amplifier stops
001Small
010Medium Low
011Medium
100Medium High
101Large
110Reserved
111Reserved
SAP[2:0]Amount of Current in Operational Amplifier
000Operation of the operational amplifier stops
001Small
010Medium Low
011Medium
100Medium High
101Large
110Reserved
111Reserved
-Set the Booster circuit Step-up cycle in Normal mode/ full colors.
DCA[9:8]DCA[7:6]DCA[5:4]DCA[3:2]DCA[1:0]
00BCLK/1BCLK/3BCLK/1BCLK/1BCLK/1
01BCLK/3BCLK/1BCLK/3BCLK/3BCLK/3
10BCLK/2BCLK/4BCLK/2BCLK/2BCLK/2
11BCLK/4BCLK/2BCLK/4BCLK/4BCLK/4
Note: BCLK is Clock frequency for Booster circuit
Register AvailabilityStatusAvailability
Normal Mode On, Idle Mode Off, Sleep OutYes
Normal Mode On, Idle Mode On, Sleep OutYes
Partial Mode On, Idle Mode Off, Sleep OutYes
Partial Mode On, Idle Mode On, Sleep OutYes
Sleep InYes
Default
StatusDefault Value
C2h
Power On Sequence0Ah/00h
S/W Reset0A h/00h
H/W Reset0A h/00h
Flow Chart
10.2.8 PWCTR4 (C3h): Power Control 4 (in Idle mode/ 8-colors)
C3HPWCTR4 (Power Control 4)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
PWCTR40↑1-11000011(C3h)
1stparameter1↑1-DCB9DCB8SAPB2SAPB1SAPB0APB2APB1APB0
2ndparameter1↑1-DCB7DCB6DCB5DCB4DCB3DCB2DCB1DCB0
Description-Set the amount of current in Operational amplifier in Idle mode/8 colors.-Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver.
AP[2:0]Amount of Current in Operational Amplifier
000Operation of the operational amplifier stops
001Small
010Medium Low
011Medium
100Medium High
101Large
110Reserved
111Reserved
SAP[2:0]Amount of Current in Operational Amplifier
000Operation of the operational amplifier stops
001Small
010Medium Low
011Medium
100Medium High
101Large
110Reserved
111Reserved
-Set the Booster circuit Step-up cycle in Idle mode/8 colors.
DCB[9:8]DCB[7:6]DCB[5:4]DCB[3:2]DCB[1:0]
00BCLK/1BCLK/3BCLK/1BCLK/1BCLK/1
01BCLK/3BCLK/1BCLK/3BCLK/3BCLK/3
10BCLK/2BCLK/4BCLK/2BCLK/2BCLK/2
11BCLK/4BCLK/2BCLK/4BCLK/4BCLK/4
Note: BCLK is Clock frequency for Booster circuit
Register AvailabilityStatusAvailability
Normal Mode On, Idle Mode Off, Sleep OutYes
Normal Mode On, Idle Mode On, Sleep OutYes
Partial Mode On, Idle Mode Off, Sleep OutYes
Partial Mode On, Idle Mode On, Sleep OutYes
Sleep InYes
Default
StatusDefault Value
C3h
Power On Sequence8Ah/26h
S/W Reset8Ah/26h
H/W Reset8Ah/26h
Flow Chart
10.2.9 PWCTR5 (C4h): Power Control 5 (in Partial mode/ full-colors)
C4HPWCTR5 (Power Control 5)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
PWCTR50↑1-11000100(C4h)
$1^{st}$ parameter1↑1-DCC9DCC8SAPC2SAPC1SAPC0APC2APC1APC0
$2^{nd}$ parameter1↑1-DCC7DCC6DCC5DCC4DCC3DCC2DCC1DCC0
Description-Set the amount of current in Operational amplifier in Partial mode/ full-colors.-Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver.
AP[2:0]Amount of Current in Operational Amplifier
000Operation of the operational amplifier stops
001Small
010Medium Low
011Medium
100Medium High
101Large
110Reserved
111Reserved
SAP[2:0]Amount of Current in Operational Amplifier
000Operation of the operational amplifier stops
001Small
010Medium Low
011Medium
100Medium High
101Large
110Reserved
111Reserved
-Set the Booster circuit Step-up cycle in Partial mode/ full-colors.
DCC[9:8]DCC[7:6]DCC[5:4]DCC[3:2]DCC[1:0]
00BCLK/1BCLK/3BCLK/1BCLK/1BCLK/1
01BCLK/3BCLK/1BCLK/3BCLK/3BCLK/3
10BCLK/2BCLK/4BCLK/2BCLK/2BCLK/2
11BCLK/4BCLK/2BCLK/4BCLK/4BCLK/4
Note: BCLK is Clock frequency for Booster circuit
Register AvailabilityStatusAvailability
Normal Mode On, Idle Mode Off, Sleep OutYes
Normal Mode On, Idle Mode On, Sleep OutYes
Partial Mode On, Idle Mode Off, Sleep OutYes
Partial Mode On, Idle Mode On, Sleep OutYes
Sleep InYes
Default
Flow Chart
10.2.10 VMCTR1 (C5h): VCOM Control 1
C5HVMCTR1 (VCOM Control 1)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
VMCTR10↑1-11000101(C5h)
$1^{st}$ parameter1↑1---VCOMS 5VCOMS 4VCOMS 3VCOMS 2VCOMS 1VCOMS 0
DescriptionVCOM voltage setting.
VCOMS [5:0]VCOMVCOMS [5:0]VCOMVCOMS [5:0]VCOMVCOMS [5:0]VCOM
0000000-0.42516010000-0.82532100000-1.22548110000-1.625
1000001-0.4517010001-0.8533100001-1.2549110001-1.65
2000010-0.47518010010-0.87534100010-1.27550110010-1.675
3000011-0.519010011-0.935100011-1.351110011-1.7
4000100-0.52520010100-0.92536100100-1.32552110100-1.725
5000101-0.5521010101-0.9537100101-1.3553110101-1.75
6000110-0.57522010110-0.97538100110-1.37554110110-1.775
7000111-0.623010111-139100111-1.455110111-1.8
8001000-0.62524011000-1.02540101000-1.42556111000-1.825
9001001-0.6525011001-1.0541101001-1.4557111001-1.85
10001010-0.67526011010-1.07542101010-1.47558111010-1.875
11001011-0.727011011-1.143101011-1.559111011-1.9
12001100-0.72528011100-1.12544101100-1.52560111100-1.925
13001101-0.7529011101-1.1545101101-1.5561111101-1.95
14001110-0.77530011110-1.17546101110-1.57562111110-1.975
15001111-0.831011111-1.247101111-1.663111111-2
Register AvailabilityStatusAvailability
Normal Mode On, Idle Mode Off, Sleep OutYes
Normal Mode On, Idle Mode On, Sleep OutYes
Partial Mode On, Idle Mode Off, Sleep OutYes
Partial Mode On, Idle Mode On, Sleep OutYes
Sleep InYes
Default
StatusDefault Value
C5h
Power On Sequence05h
S/W Reset05h
H/W Reset05h
Flow Chart
10.2.11 VMOFCTR (C7h): VCOM Offset Control
C7HVMOFCTR (VCOM Offset Control)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
VMOFCTR0↑1-11000111(C7h)
Parameter1↑1----VMF4VMF3VMF2VMF1VMF0
Description-Set VCOM Voltage level for reduce the flicker issue-Before use command 0xC7, the bit VMF_EN of command 0xD9 must be enabled (set to 1).
VMF[4]VMF[3:0]VCOM Output Level
00000“VCOMS”+16d
00001“VCOMS”+15d
0||
01110“VCOMS”+2d
01111“VCOMS”+1d
10000“VCOMS”
10001“VCOMS”-1d
10010“VCOMS”-2d
1||
11110“VCOMS”-14d
11111“VCOMS”-15d
- 1d=25mV, 2d=50mV 3d=75mv....
Register AvailabilityStatusAvailability
Normal Mode On, Idle Mode Off, Sleep OutYes
Normal Mode On, Idle Mode On, Sleep OutYes
Partial Mode On, Idle Mode Off, Sleep OutYes
Partial Mode On, Idle Mode On, Sleep OutYes
Sleep InYes
DefaultStatusDefault Value
C7h
Power On Sequence10h
S/W Reset10h
H/W Reset10h
Flow Chart
10.2.12 WRID2 (D1h): Write ID2 Value
D1HWRID2 (Write ID2 Value)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
WRID20↑1-11010001(D1h)
Parameter1↑1--ID26ID25ID24ID23ID22ID21ID20-
Description-Write 7-bit data of LCD module version to save it to NVM. -The parameter ID2[6:0] is LCD Module version ID.
Flow Chart
10.2.13 WRID3 (D2h): Write ID3 Value
D2HWRID3 (Write ID3 Value)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
WRID30↑1-11010010(D2h)
Parameter1↑1-ID37ID36ID35ID34ID33ID32ID31ID30-
Description-Write 8-bit data of project code module to save it to NVM.-The parameter ID3[7:0] is product project ID.
Flow Chart
10.2.14 NVFCTR1 (D9h): NVM Control Status
D9HNVFCTR1 (NV Memory Function Controller 1)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
NVFCTR10↑1-11001001(D9h)
Parameter11↑-0VMF_ENID2_EN0000EXT_R
Description-NVM control status
BitValue
VMF_EN“1” = Command C7h Enable; “0” = Command C7h Disable
ID2_EN“1” = Command D1h Enable; “0” = Command D1h Disable
EXT_RRead: Extension Command Status, “1” for Enable, “0” for Disable.
DefaultStatusDefault Value (D9h)
Power On Sequence00h
S/W Reset00h
H/W Reset00h
Flow Chart
10.2.15 NVFCTR2 (Deh): NVM Read Command
DEHNVFCTR1 (NV Memory Function Controller 2)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
NVFCTR20↑1-11011110(Deh)
1stParameter1↑111110101F5
2ndParameter1↑110100101A5
DescriptionNVM Read CommandNOTE: “-” Don’t care
Flow Chart
10.2.16 NVFCTR3 (DFh): NVM Write Command
DFHNVFCTR1 (NV Memory Function Controller 3)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
NVFCTR10↑1-11011111(DFh)
1stParameter1↑1NVM_CMD7NVM_CMD6NVM_CMD5NVM_CMD4NVM_CMD3NVM_CMD2NVM_CMD1NVM_CMD0
2ndParameter1↑110100101A5
Description-NVM Write Command-NVM_CMD[7:0] : Select to Program/Erase ; Program command : 3Ah ; Erase command : C5hNOTE: “-” Don’t care
Flow Chart
10.2.17 GMCTRP1 (E0h): Gamma ('+'polarity) Correction Characteristics Setting
E0HGMCTRP0 (Gamma ‘+’Polarity Correction Characteristics Setting)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
GMCTRP10↑1-11100000(E0h)
$1^{st}$ Parameter1↑1---VRF0P[5]VRF0P[4]VF0P[3]VRF0P[2]VRF0P[1]VRF0P[0]
$2^{nd}$ Parameter1↑1---VOS0P[5]VOS0P[4]VOS0P[3]VOS0P[2]VOS0P[1]VOS0P[0]
$3^{rd}$ Parameter1↑1---PK0P[5]PK0P[4]PK0P[3]PK0P[2]PK0P[1]PK0P[0]
$4^{th}$ Parameter1↑1---PK1P[5]PK1P[4]PK1P[3]PK1P[2]PK1P[1]PK1P[0]
$5^{th}$ Parameter1↑1---PK2P[5]PK2P[4]PK2P[3]PK2P[2]PK2P[1]PK2P[0]
$6^{th}$ Parameter1↑1---PK3P[5]PK3P[4]PK3P[3]PK3P[2]PK3P[1]PK3P[0]
$7^{th}$ Parameter1↑1---PK4P[5]PK4P[4]PK4P[3]PK4P[2]PK4P[1]PK4P[0]
$8^{th}$ Parameter1↑1---PK5P[5]PK5P[4]PK5P[3]PK5P[2]PK5P[1]PK5P[0]
$9^{th}$ Parameter1↑1---PK6P[5]PK6P[4]PK6P[3]PK6P[2]PK6P[1]PK6P[0]
$10^{th}$ Parameter1↑1---PK7P[5]PK7P[4]PK7P[3]PK7P[2]PK7P[1]PK7P[0]
$11^{th}$ Parameter1↑1---PK8P[5]PK8P[4]PK8P[3]PK8P[2]PK8P[1]PK8P[0]
$12^{th}$ Parameter1↑1---PK9P[5]PK9P[4]PK9P[3]PK9P[2]PK9P[1]PK9P[0]
$13^{th}$ Parameter1↑1---SELV0P[5]SELV0P[4]SELV0P[3]SELV0P[2]SELV0P[1]SELV0P[0]
$14^{th}$ Parameter1↑1---SELV1P[5]SELV1P[4]SELV1P[3]SELV1P[2]SELV1P[1]SELV1P[0]
$15^{th}$ Parameter1↑1---SELV62P[5]SELV62P[4]SELV62P[3]SELV62P[2]SELV62P[1]SELV62P[0]
$16^{th}$ Parameter1↑1---SELV63P[5]SELV63P[4]SELV63P[3]SELV63P[2]SELV63P[1]SELV63P[0]
Description
Register GroupPositive PolaritySet-up Contents
High Level adjustmentVRF0P[5:0]Variable resistor VRHP
Mid Level AdjustmentSELV0P[5:0]The voltage of V0 grayscale is selected by the 64 to 1
SELV1P[5:0]The voltage of V1 grayscale is selected by the 64 to 1
PK0P[5:0]The voltage of V3 grayscale is selected by the 64 to 1
PK1P[5:0]The voltage of V4 grayscale is selected by the 64 to 1
PK2P[5:0]The voltage of V12 grayscale is selected by the 64 to 1
PK3P[5:0]The voltage of V20 grayscale is selected by the 64 to 1
PK4P[5:0]The voltage of V28 grayscale is selected by the 64 to 1
PK5P[5:0]The voltage of V36 grayscale is selected by the 64 to 1
PK6P[5:0]The voltage of V44 grayscale is selected by the 64 to 1
PK7P[5:0]The voltage of V52 grayscale is selected by the 64 to 1
PK8P[5:0]The voltage of V56 grayscale is selected by the 64 to 1
PK9P[5:0]The voltage of V60 grayscale is selected by the 64 to 1
SELV62P[5:0]The voltage of V62 grayscale is selected by the 64 to 1
SELV63P[5:0]The voltage of V63 grayscale is selected by the 64 to 1
Low Level AdjustmentVOS0P[5:0]Variable Resistor VRLP
Flow ChartLegend
10.2.18 GMCTRN1 (E1h): Gamma '-'polarity Correction Characteristics Setting
E1HGMCTRP0 (Gamma ‘+’Polarity Correction Characteristics Setting)
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
GMCTRP10↑1-11100001(E1h)
$1^{st}$ Parameter1↑1---VRF0N[5]VRF0N[4]VF0N[3]VRF0N[2]VRF0N[1]VRF0N[0]
$2^{nd}$ Parameter1↑1---VOS0N[5]VOS0N[4]VOS0N[3]VOS0N[2]VOS0N[1]VOS0N[0]
$3^{rd}$ Parameter1↑1---PK0N[5]PK0N[4]PK0N[3]PK0N[2]PK0N[1]PK0N[0]
$4^{th}$ Parameter1↑1---PK1N[5]PK1N[4]PK1N[3]PK1N[2]PK1N[1]PK1N[0]
$5^{th}$ Parameter1↑1---PK2N[5]PK2N[4]PK2N[3]PK2N[2]PK2N[1]PK2N[0]
$6^{th}$ Parameter1↑1---PK3N[5]PK3N[4]PK3N[3]PK3N[2]PK3N[1]PK3N[0]
$7^{th}$ Parameter1↑1---PK4N[5]PK4N[4]PK4N[3]PK4N[2]PK4N[1]PK4N[0]
$8^{th}$ Parameter1↑1---PK5N[5]PK5N[4]PK5N[3]PK5N[2]PK5N[1]PK5N[0]
$9^{th}$ Parameter1↑1---PK6N[5]PK6N[4]PK6N[3]PK6N[2]PK6N[1]PK6N[0]
$10^{th}$ Parameter1↑1---PK7N[5]PK7N[4]PK7N[3]PK7N[2]PK7N[1]PK7N[0]
$11^{th}$ Parameter1↑1---PK8N[5]PK8N[4]PK8N[3]PK8N[2]PK8N[1]PK8N[0]
$12^{th}$ Parameter1↑1---PK9[5]PK9N[4]PK9N[3]PK9N[2]PK9N[1]PK9N[0]
$13^{th}$ Parameter1↑1---SELV0N[5]SELV0N[4]SELV0N[3]SELV0N[2]SELV0N[1]SELV0N[0]
$14^{th}$ Parameter1↑1---SELV1N[5]SELV1N[4]SELV1N[3]SELV1N[2]SELV1N[1]SELV1N[0]
$15^{th}$ Parameter1↑1---SELV62N[5]SELV62N[4]SELV62N[3]SELV62N[2]SELV62N[1]SELV62N[0]
$16^{th}$ Parameter1↑1---SELV63N[5]SELV63N[4]SELV63N[3]SELV63N[2]SELV63N[1]SELV63N[0]
Description
Register GroupNegative PolaritySet-up Contents
High level adjustmentVRF0N[5:0]Variable resistor VRHN
Mid Level AdjustmentSELV0N[5:0]The voltage of V0 grayscale is selected by the 64 to 1
SELV1N[5:0]The voltage of V1 grayscale is selected by the 64 to 1
PK0N[5:0]The voltage of V3 grayscale is selected by the 64 to 1
PK1N[5:0]The voltage of V4 grayscale is selected by the 64 to 1
PK2N[5:0]The voltage of V12 grayscale is selected by the 64 to 1
PK3N[5:0]The voltage of V20 grayscale is selected by the 64 to 1
PK4N[5:0]The voltage of V28 grayscale is selected by the 64 to 1
PK5N[5:0]The voltage of V36 grayscale is selected by the 64 to 1
PK6N[5:0]The voltage of V44 grayscale is selected by the 64 to 1
PK7N[5:0]The voltage of V52 grayscale is selected by the 64 to 1
PK8N[5:0]The voltage of V56 grayscale is selected by the 64 to 1
PK9N[5:0]The voltage of V60 grayscale is selected by the 64 to 1
SELV62N[5:0]The voltage of V62 grayscale is selected by the 64 to 1
SELV63N[5:0]The voltage of V63 grayscale is selected by the 64 to 1
Low Level AdjustmentVOS0N[5:0]Variable Resistor VRLN
Flow Chart
10.2.19 GCV(FCh): Gate Pump Clock Frequency Variable
FCHGate Pump Clock Frequency Variable
Inst / ParaD/CXWRXRDXD17-8D7D6D5D4D3D2D1D0HEX
NVFCTR10↑1-11011001(FCh)
Parameter11↑-GCV_Enable1GCV_Enable00Clk_VariableClk_Variable00
Description-Automatic adjust gate pumping clock for saving power consumption.
Clk_Variable[1:0]Save Power Ability
00Small
01Medium
10High
11Large
DefaultStatusDefault Value (FCh)
Power On Sequence80h
S/W Reset80h
H/W Reset80h
Flow Chart
Clk_Variable[1:0]Save Power Ability
00Small
01Medium
10High
11Large
StatusDefault Value (FCh)
Power On Sequence80h
S/W Reset80h
H/W Reset80h
## 11 Power Sturcture ## 11.1 Driver IC Operating Voltage Specification ![](images/6f2364631c2218b44412d68689860c7926d74e50f94d371370cd7f89bcd92439.jpg)
flowchart ```mermaid graph LR A["VDD=2.5 V ~ 4.8V"] --> B["Charge Pump Reference Voltage"] C["AGND=0V"] --> D["Internal Reference Voltage"] B --> E["VGH=10V ~ 15V"] B --> F["AVDD=4.5 V ~ 5.2V"] B --> G["GVDD = 3.15V~5V"] D --> H["VCOM = -0.425V~-2V"] D --> I["VCL = -1.8 ~ -VDD"] D --> J["GVCL = -3.15V~-5V"] D --> K["AVCL = -4.25 ~ -4.95V"] D --> L["VGL=-13V~-7.5V"] E --> L F --> L G --> L H --> L I --> L J --> L K --> L L --> M["2.4ms interval"] M --> D ```
Fig 15 Power Booster Level Note: Sleep out flow: AVDD, GVDD, GVCL, VCOM switch on -> 2.4ms -> AVCL, VGH, VGL, VCL switch on -> 78.6ms ![](images/21eda12298aee7b86faa605214f138c168a0fb41c0586903667c6256cc62c8cd.jpg) scan 2 blank frames Sleep in flow: Scan 2 blank frames -> All analog power ## 11.2 Power Booster Circuit ![](images/da7a00026d691596d955aec75fa981deec453d2a885ee34a8a4a95752d841d46.jpg)
flowchart ```mermaid graph LR A["VDD"] --> B["Reference Voltage generator"] B --> C["AVDD"] C --> D["AGND"] D --> E["VCI1"] E --> F["Source Output Circuit Block"] F --> G["Gray reference Circuit Block (Gamma)"] G --> H["AVDD"] H --> I["AGND"] I --> J["AVCL"] J --> K["AGND"] K --> L["VCOM"] L --> M["VCL"] M --> N["Charge Pump 5"] N --> O["VDD"] O --> P["VCI1"] P --> Q["Charge Pump 2"] Q --> R["VDD"] R --> S["Charge Pump 4"] S --> T["VDD"] T --> U["Reference Voltage generator"] U --> V["VDDI"] V --> W["G1 / G162"] ```
## 12 Gamma Structure ## 12.1 Structure of Grayscale Amplifier 16 voltage levels (VIN0-VIN15) between GVDD(GVCL) and VSS are determined by the high/ mid/ low level adjustment registers. Each mid-adjustment level is split into 64 levels again by the internal ladder resistor network. As a result, grayscale amplifier generates 64 voltage levels ranging from V0 to V63 and outputs one of 64 levels. ![](images/d4ca711dc78979a1cc56760a53f1f2627d442a399ea8caa3a5decc9c26a43c84.jpg) 12.2 Gamma Voltage Formula (Positive/ Negative Polarity)
Gray LevelVoltage Formula (Positive)Voltage Formula (Negative)
0VINP0VINP0
1VINP1VINP1
2VINP2VINP2
3VINP3VINP3
4VINP4VINP4
5V4-(V4-V12)*(4/32)V4-(V4-V12)*(4/32)
6V4-(V4-V12)*(8/32)V4-(V4-V12)*(8/32)
7V4-(V4-V12)*(12/32)V4-(V4-V12)*(12/32)
8V4-(V4-V12)*(16/32)V4-(V4-V12)*(16/32)
9V4-(V4-V12)*(20/32)V4-(V4-V12)*(20/32)
10V4-(V4-V12)*(24/32)V4-(V4-V12)*(24/32)
11V4-(V4-V12)*(28/32)V4-(V4-V12)*(28/32)
12VINP5VINP5
13V12-(V12-V20)*(4/32)V12-(V12-V20)*(4/32)
14V12-(V12-V20)*(8/32)V12-(V12-V20)*(8/32)
15V12-(V12-V20)*(12/32)V12-(V12-V20)*(12/32)
16V12-(V12-V20)*(16/32)V12-(V12-V20)*(16/32)
17V12-(V12-V20)*(20/32)V12-(V12-V20)*(20/32)
18V12-(V12-V20)*(24/32)V12-(V12-V20)*(24/32)
19V12-(V12-V20)*(28/32)V12-(V12-V20)*(28/32)
20VINP6VINP6
21V20-(V20-V28)*(4/32)V20-(V20-V28)*(4/32)
22V20-(V20-V28)*(8/32)V20-(V20-V28)*(8/32)
23V20-(V20-V28)*(12/32)V20-(V20-V28)*(12/32)
24V20-(V20-V28)*(16/32)V20-(V20-V28)*(16/32)
25V20-(V20-V28)*(20/32)V20-(V20-V28)*(20/32)
26V20-(V20-V28)*(24/32)V20-(V20-V28)*(24/32)
27V20-(V20-V28)*(28/32)V20-(V20-V28)*(28/32)
28VINP7VINP7
29V28-(V28-V36)*(4/32)V28-(V28-V36)*(4/32)
30V28-(V28-V36)*(8/32)V28-(V28-V36)*(8/32)
31V28-(V28-V36)*(12/32)V28-(V28-V36)*(12/32)
32V28-(V28-V36)*(16/32)V28-(V28-V36)*(16/32)
33V28-(V28-V36)*(20/32)V28-(V28-V36)*(20/32)
34V28-(V28-V36)*(24/32)V28-(V28-V36)*(24/32)
35V28-(V28-V36)*(28/32)V28-(V28-V36)*(28/32)
36VINP8VINP8
37V36-(V36-V44)*(4/32)V36-(V36-V44)*(4/32)
38V36-(V36-V44)*(8/32)V36-(V36-V44)*(8/32)
39V36-(V36-V44)*(12/32)V36-(V36-V44)*(12/32)
40V36-(V36-V44)*(16/32)V36-(V36-V44)*(16/32)
41V36-(V36-V44)*(20/32)V36-(V36-V44)*(20/32)
42V36-(V36-V44)*(24/32)V36-(V36-V44)*(24/32)
43V36-(V36-V44)*(28/32)V36-(V36-V44)*(28/32)
44VINP9VINP9
45V44-(V44-V52)*(4/32)V44-(V44-V52)*(4/32)
46V44-(V44-V52)*(8/32)V44-(V44-V52)*(8/32)
47V44-(V44-V52)*(12/32)V44-(V44-V52)*(12/32)
48V44-(V44-V52)*(16/32)V44-(V44-V52)*(16/32)
49V44-(V44-V52)*(20/32)V44-(V44-V52)*(20/32)
50V44-(V44-V52)*(24/32)V44-(V44-V52)*(24/32)
51V44-(V44-V52)*(28/32)V44-(V44-V52)*(28/32)
52VINP10VINP10
53V52-(V52-V56)*(1/4)V52-(V52-V56)*(1/4)
54V52-(V52-V56)*(2/4)V52-(V52-V56)*(2/4)
55V52-(V52-V56)*(3/4)V52-(V52-V56)*(3/4)
56VINP11VINP11
57V56-(V56-V60)*(1/4)V56-(V56-V60)*(1/4)
58V56-(V56-V60)*(2/4)V56-(V56-V60)*(2/4)
59V56-(V56-V60)*(3/4)V56-(V56-V60)*(3/4)
60VINP12VINP12
61VINP13VINP13
62VINP14VINP14
63VINP15VINP15
## 13 Example Connection with Panel Direction and Different Resolution ## 13.1 Application of Connection with Panel Direction Case 1: (This is default case) - $1^{\mathrm{st}}$ Pixel is at Left Top of the panel - RGB Filter Order = RGB ![](images/7eb8006296a6a26b6316ba9e9fab305f27925c802c282579494d77440b0b1e84.jpg)
flowchart ```mermaid graph LR A["G1"] -->|P1| B["G161"] B -->|P2| C["G1"] C -->|P3| D["G161"] D -->|P130| E["G160"] E -->|P131| F["G162"] F -->|P132| G["G162"] G -->|G2| H["G2"] H -->|G4| I["G4"] I -->|G159| J["G159"] J -->|G161| K["G161"] K -->|1st pixel| L["G1"] L -->|1st pixel| M["G1"] ```
- Direction default setting (H/W) - Display direction control (S/W) - X-Mirror control by MX - Y-Mirror control by MY - XY-Exchange control by MV $$ \mathrm{SMX} = ^ {\prime} 0 ^ {\prime} $$ $$ \mathrm{SMY} = ^ {\prime} 0 ^ {\prime} $$ $$ \mathrm{SRGB} = ^ {\prime} 0 ^ {\prime} $$ $$ \mathrm{S1} = \text {Filter R} $$ $$ \mathrm{S2} = \text {Filter G} $$ $$ \mathrm{S3} = \text {Filter B} $$ ![](images/3ee636ea7bebeeb74946a6e1d64ff03abebaf351c8b90c657ae8a60ea8dcd29f.jpg)
text_image IC (Bump down) LCD Front side CF Glass TFT Glass
## Case 2: - $1^{\mathrm{st}}$ Pixel is at Left Top of the panel - RGB Filter Order = BGR ![](images/fb299768348ac925d4d16e8d5da9c0ad05440a3e93e38f079021ecd75b60e922.jpg)
flowchart ```mermaid graph LR A["G1"] -->|P1| B["1st pixel"] B --> C["G2"] C --> D["G4"] D --> E["G160"] E --> F["G161"] F --> G["G162"] G --> H["G162"] H --> I["G161"] I --> J["G159"] J --> K["G3"] K --> L["G1"] ```
- Direction default setting (H/W) - Display direction control (S/W) - X-Mirror control by MX - Y-Mirror control by MY - XY-Exchange control by MV $$ \mathrm{SMX} = ^ {\prime} 0 ^ {\prime} $$ $$ \mathrm{SMY} = ^ {\prime} 0 ^ {\prime} $$ $$ \mathrm{SRGB} = ^ {\prime} 1 ^ {\prime} $$ $$ \mathrm{S1} = \text {Filter B} $$ $$ \mathrm{S2} = \text {Filter G} $$ $$ \mathrm{S3} = \text {Filter R} $$ ![](images/b14bbfc9c0a5fb015fba131b7f47e4e2fc2689302d9d5cf84ef5a7a31c84d9fc.jpg)
text_image IC (Bump down) LCD Front side CF Glass TFT Glass
## Case 3: - $1^{\mathrm{st}}$ Pixel is at Right Bottom of the panel - RGB Filter Order = RGB ![](images/ec541180d5d008cb1ef0a87593b37d463de9cc20de94475cec8a1467530f3426.jpg)
text_image Driver IC (bump down) G161 G1 S1 S396 G2 G162 P1 P2 P3 P130 P131 P132 G1 G2 G3 G4 G159 G160 G161 1st pixel G162
- Direction default setting (H/W) - Display direction control (S/W) - X-Mirror control by MX - Y-Mirror control by MY - XY-Exchange control by MV $$ \mathrm{SMX} = ^ {\prime} 1 ^ {\prime} $$ $$ \mathrm{SMY} = ^ {\prime} 1 ^ {\prime} $$ $$ \mathrm{SRGB} = ^ {\prime} 0 ^ {\prime} $$ $$ \mathrm{S1} = \text {Filter R} $$ $$ \mathrm{S2} = \text {Filter G} $$ $$ \mathrm{S3} = \text {Filter B} $$ ![](images/89ef60762cda2d9f7b7e3b3858c1a7dc637f7742c68b2b1f2fc97e6e7b7edb64.jpg)
text_image IC (Bump down) LCD Front side CF Glass TFT Glass
## Case 4: - $1^{\mathrm{st}}$ Pixel is at Right Bottom of the panel - RGB Filter Order = BGR ![](images/9102ffed2e68dd9bf257dbfd60582ae683a91777d7ea61f50718d2a6e81a4594.jpg)
text_image Driver IC (bump down) G161 G1 S1 S396 G2 G162 P1 P2 P3 P130 P131 P132 G1 G2 G3 G4 G159 G160 G161 G162 1st pixel
- Direction default setting (H/W) - Display direction control (S/W) - X-Mirror control by MX - Y-Mirror control by MY - XY-Exchange control by MV $$ \mathrm{SMX} = ^ {\prime} 1 ^ {\prime} $$ $$ \mathrm{SMY} = ^ {\prime} 1 ^ {\prime} $$ $$ \mathrm{SRGB} = ^ {\prime} 1 ^ {\prime} $$ $$ \mathrm{S1} = \text {Filter B} $$ $$ \mathrm{S2} = \text {Filter G} $$ $$ \mathrm{S3} = \text {Filter R} $$ ![](images/6e47dd4ebe36093522825ce3876b2fbe2551a28ee57482cf0b00f3495be5e3bb.jpg)
text_image IC (Bump down) LCD Front side CF Glass TFT Glass
## 13.2 Application of Connection with Different Resolution Case1 of Resolution (128RGB x 160) (GM[1:0] = "11") RAM Size=128 x 160 x 18-bit (Used) Display Size = 128RGB x 160 1). Example for SMX=SMY='0' ![](images/9cb88db7ccf5a4f9167a4e2fa1735fd00d6b7269c32328e20c893788b8ec7ee8.jpg)
text_image GRAM size = 128x 160x 18-bits (0, 0) 00h 01h 02h 7Eh 7Fh 83h 00h 01h 02h (127, 159) 9Fh A1h Driver IC (bump down) G161 G3 S7 S390 G2 G160 P1 P2 P3 P126 P127 P128 G2 G3 G4 G157 G159 G160 - Direction default setting (H/W) SMX = '0' SMY = '0' SRGB = '0' - Display direction control (S/W) - X-Mirror control by MX - Y-Mirror control by MY - XY-Exchange control by MV
2). Example for SMX=SMY='1' ![](images/661adcb67703a05101a412c13db6df638f40b3cc1dd781e36dcecfe59553b4d8.jpg)
text_image GRAM size = 128 x 160 x 18-bits (0, 0) 00h 01h 02h 7Eh 7Fh 83h 00h 01h 02h (127, 159) 9Fh A1h Driver IC (bump down) G161 G3 S7 S390 G2 G160 G2 1st pixel G3 G4 G157 G159 G160 - Display direction control (S/W) - X-Mirror control by MX - Y-Mirror control by MY - XY-Exchange control by MV - Direction default setting (H/W) SMX ='1' SMY ='1' SRGB ='0'
Case2 of Resolution (132RGB x 132) (GM[1:0] = "01") RAM size=132 x 132 x 18-bit (Used) Display size = 132RGB x 132 1). Example for SMX=SMY='0' ![](images/f6c8ca059ec025c9d60d6e615fe951a1c7401b0ee1b4656b8f32bfb52d4b1e89.jpg)
flowchart ```mermaid graph LR subgraph Left_Process A["00h 00h 01h 02h 82h 83h"] --> B["Display direction control (S/W)\nX-Mirror control by MX\nY-Mirror control by MY\nXY-Exchange control by MV"] end subgraph Right_Process B --> C["Driver IC (bump down)\nG1 1st pixel"] C --> D["Direction default setting (H/W)\nSMX = '0'\nSMY = '0'\nSRGB = '0'"] end ```
2). Example for SMX=SMY='1' ![](images/b5c103bf0e7b60e8efdd94b6ea6e0e3bcec5083561ea4027296f51f4d24ab523.jpg)
flowchart ```mermaid graph LR subgraph Initial_Process A["Display direction control (S/W)\nX-Mirror control by MX\nY-Mirror control by MY\nXY-Exchange control by MV"] --> B["(131, 131)"] end subgraph Driver_IC B --> C["1st pixel"] C --> D["Driver IC (bump down)"] end subgraph Final_Process E["Direction default setting (H/W)\nSMX = '1'\nSMY = '1'\nSRGB = '0'"] --> F["Driver IC (bump down)"] end ```
Case3 of Resolution (132RGB x 162) (GM[1:0] = "00") RAM Size=132 x 162 x 18-bit (Used) Display Size = 132RGB x 162 1). Example for SMX=SMY='0' ![](images/66e7378c694df620ea374b286deb068df506cad03eca9ee6ad35998a20638f52.jpg)
text_image GRAM size = 13/2 x 16/2 x 18-bits (0, 0) 00h 01h 02h 82h 83h 00h 01h 02h (131, 161) A0h A1h - Display direction control (S/W) - X-Mirror control by MX - Y-Mirror control by MY - XY-Exchange control by MV Driver IC (bump down) G161 G3 S7 S390 G2 G160 P1 P2 P3 P130 P131 P132 G2 1st pixel G3 G15 9 G16 0 G16 1 - Direction default setting (H/W) SMX = '0' SMY = '0' SRGB = '0'
2). Example for SMX=SMY='1' ![](images/83ec30befacc41ef50bf53afd20250dfb6ccfeef38f97e11b93c280eba8c585e.jpg)
flowchart This diagram illustrates a memory layout and data flow for a 18-bit RAM, showing the interaction between a grid and a driver IC (bump down) with directional control logic.
## 13.3 Microprocessor Interface Applications ## 13.3.1 8080-Series MCU Interface for 8-bit Data Bus (P68=0, IM2, IM1, IM0="100") 80 Serial MPU 8-Bit Bus ![](images/29d7c89baa34488cf0540ae2866a37a3783be32f64425fd688a6fdc88cebe9dd.jpg)
text_image MPU VDDI GND Driver IC SPI4W IM2 IM1 IM0 RESX CSX D/CX RDX WRX D7 to D0 GND RESX CSX D/CX (SCL) RDX (E) WRX (R/WX) D7 to D0 D17 to D8 P68
## 13.3.2 8080-Series MCU Interface for 16-bit Data Bus (P68=0, IM2, IM1, IM0="101") 80 Serial MPU 16-Bit Bus ![](images/fd7884bdd300c9545fd5689898a1ccb47befa6c57b635ba890ebad3b21029e82.jpg)
text_image MPU VDDI GND Driver IC SPI4W IM2 IM1 IMO RESX CSX D/CX RDX WRX D15 to D0 GND D/CX (SCL) RDX (E) WRX (R/WX) D15 to D0 D17 to D16 P68
## 13.3.3 8080-Series MCU Interface for 9-bit Data Bus (P68=0, IM2, IM1, IM0="110") 80 Serial MPU 9-Bit Bus ![](images/2acb16ffe5b4406fce997f6fdda7d71148bb1478d420ffd6724e38d059882cfe.jpg)
text_image MPU VDDI GND Driver IC SPI4W IM2 IM1 IM0 RESX CSX D/CX RDX WRX D8 to D0 GND RESX CSX D/CX (SCL) RDX (E) WRX (R/WX) D8 to D0 D17 to D9 P68
13.3.4 8080-Series MCU Interface for 18-bit Data Bus (P68=0, IM2, IM1, IM0="111") 80 Serial MPU 18-Bit Bus ![](images/d2c7b295e3535c73ce2a23637a618a8c1bda2b907111da36ccf018fc7b196fcc.jpg)
text_image MPU VDDI GND Driver IC SPI4W IM2 IM1 IMO RESX CSX D/CX RDX WRX D17 to D0 GND RESX CSX D/CX (SCL) RDX (E) WRX (R/WX) D17 to D0 P68
13.3.5 6800-Series MCU Interface for 8-bit Data Bus (P68=1, IM2, IM1, IM0="100") 68 Serial MPU 8-Bit Bus ![](images/a4ff01fa0723727849d6829ab086faa9f011376c9ca449cbaf4a36fc779168c4.jpg)
text_image MPU VDDI GND Driver IC SPI4W IM2 IM1 IMO RESX CSX D/CX E R/WX D7 to D0 GND VDDI D/CX (SCL) RDX (E) WRX (R/WX) D7 to D0 D17 to D8 P68
13.3.6 6800-Series MCU Interface for 16-bit Data Bus (P68=1, IM2, IM1, IM0="101") 68 Serial MPU 16-Bit Bus ![](images/1d6958a680b018342295a42fcfa517d70e672c81bc42720e440391506507c231.jpg)
text_image MPU VDDI GND Driver IC SPI4W IM2 IM1 IM0 RESX CSX D/CX E R/WX D15 to D0 GND VDDI RESX CSX D/CX (SCL) RDX (E) WRX (R/WX) D15 to D0 D17 to D16 P68
13.3.7 6800-Series MCU Interface for 9-bit Data Bus (P68=1, IM2, IM1, IM0="110") 68 Serial MPU 9-Bit Bus ![](images/681b019f67321cb5b8f0f0a7e4409ed6c9a187b2dea358f8eb4e79ab8338ffbb.jpg)
text_image MPU VDDI GND Driver IC SPI4W IM2 IM1 IM0 RESX CSX D/CX E R/WX D8 to D0 GND VDDI RESX CSX D/CX (SCL) RDX (E) WRX (R/WX) D8 to D0 D17 to D9 P68
13.3.8 6800-Series MCU Interface for 18-bit Data Bus (P68=1, IM2, IM1, IM0="111") 68 Serial MPU 18-Bit Bus ![](images/e006faad0d9444eab3051fc1baa51fdbd9e1a3231106d5e519efa4ff99244523.jpg)
text_image MPU VDDI GND SP14W IM2 IM1 IM0 RESX CSX D/CX E R/WX D17 to D0 Driver IC RESX CSX D/CX (SCL) RDX (E) WRX (R/WX) D17 to D0 VDDI P68
13.3..9 3-Line Serial MCU Interface (IM2, IM1, IM0="000", SPI4W=0) 3-Pin Serial Mode ![](images/12cf329e064956c862da56a811b83a35a13b54a7d64bb52fbe8651777959a0ae.jpg)
text_image MPU Driver IC SPI4W IM2 IM1 IM0 GND RESX CSX GND-I RESX CSX RDX,WRX SCL SDA D/CX (SCL) SDA(D0) D17 to D1 GND
13.3.10 4-Line Serial MCU Interface (IM2, IM1, IM0="000", SPI4W=1) 4-Pin Serial Mode ![](images/7238156e6fd754811bf0c991d77f81df9e8f005d58e593c7aae68cd405804d6e.jpg)
text_image MPU VDDI Driver IC SPI4W IM2 IM1 IM0 GND RESX CSX GND·I RESX CSX RDX D/CX SCL SDA WRX(D/CX) D/CX (SCL) SDA(D0) D17 to D1 GND
14 Revision History
ST7735S Specification Revision History
VersionDateDescription
1.02011/06/10First issue.
1.12011/11/21Modify ID1 Value.