## GD5F2GQ5xExxG

## DATASHEET

2G-bit 2K+128BPageSize with E Version

## Contents

1 FEATURE ....

2 GENERAL DESCRIPTION ......

2.1 PRODUCT LIST .....

2.2 CONNECTION DIAGRAM. . 8

2.3 PIN DESCRIPTION..... 9

2.4 BLOCK DIAGRAM ......

3 MEMORY MAPPING... ..10

4 ARRAY ORGANIZATION....... 11

5 DEVICE OPERATION.... .12

5.1 SPI MODES....... ..... 12

5.2 HOLD MODE...... ..... 13

5.3 WRITE PROTECTION.... .. 13

5.4 POWER OFF TIMING ... . 14

6 COMMANDS DESCRIPTION ... .15

7 WRITE OPERATIONS .....

7.1 WRITE ENABLE (WREN) (06H) ..... . 17

7.2 WRITE DISABLE (WRDI) (04H)... . 17

8 READ OPERATIONS..... ..18

8.1 PAGE READ ....... ..... 18

8.2 PAGE READ TO CACHE (13H) . . 19

8.3 CACHE READ FUNCTION (31H/3FH).. . 20

8.4 READ FROM CACHE (03H OR 0BH)......

8.5 READ FROM CACHE X2 (3BH) .... .... 26

8.6 READ FROM CACHE X4 (6BH) ...... . 27

8.7 READ FROM CACHE DUAL IO (BBH) . .. 28

8.8 READ FROM CACHE QUAD IO (EBH).....

8.9 READ FROM CACHE QUAD I/O DTR (EEH) . .. 30

8.10 READ ID (9FH)...... .... 31

8.11 READ UID . 32

8.12 READ PARAMETER PAGE.....

## 9 PROGRAM OPERATIONS.... ..38

9.1 PAGE PROGRAM ........ .... 38  
9.2 PROGRAM LOAD (PL) (02H)... .. 39  
9.3 PROGRAM LOAD X4 (PL X4) (32H) ......  
9.4 PROGRAM EXECUTE (PE) (10H) . . 41  
9.5 PROGRAM EXECUTE BACKGROUND (10H + ADDRESS + 15H).. ..... 42  
9.6 INTERNAL DATA MOVE .. . 44  
9.7 PROGRAM LOAD RANDOM DATA (84H) ..... ...... 45  
9.8 PROGRAM LOAD RANDOM DATA X4 (C4H/34H)...... ...... 46

## 10 ERASE OPERATIONS .. ..47

10.1 BLOCK ERASE (D8H) . . 47

## 11 RESET OPERATIONS.....

11.1 SOFT RESET (FFH) . .. 48  
11.2 ENABLE POWER ON RESET (66H) AND POWER ON RESET (99H).. ..... 49

## 12 FEATURE OPERATIONS...... .50

12.1 GET FEATURES (0FH) AND SET FEATURES (1FH) . . 50  
12.2 STATUS REGISTER AND DRIVER REGISTER.. . 53  
12.3 OTP REGION....... .... 54  
12.4 ASSISTANT BAD BLOCK MANAGEMENT ... .. 55  
12.5 BLOCK PROTECTION.. .. 56  
12.6 INTERNAL ECC.. . 57

## 13 POWER ON TIMING..... .59

## 14 ABSOLUTE MAXIMUM RATINGS ....

## 15 CAPACITANCE MEASUREMENT CONDITIONS..... ....61

## 16 DC CHARACTERISTIC .... .....62

## 17 AC CHARACTERISTICS ....... .....63

## 18 PERFORMANCE AND TIMING ....

## 19 ORDERING INFORMATION... ...66

20 PACKAGE INFORMATION..... ....67  
REVISION HISTORY .... ....70

## 1 FEATURE

◆ 2Gb SLC NAND Flash

◆ Page Size

\- Internal ECC On (ECC\_EN=1, default):

Page Size：2048-Byte+64-Byte

\- Internal ECC Off (ECC\_EN=0):

Page Size：2048-Byte+128-Byte

◆ Standard, Dual, Quad SPI,DTR

\- Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#

\- Dual SPI: SCLK, CS#, SIO0, SIO1, WP#, HOLD#

\- Quad SPI: SCLK, CS#, SIO0, SIO1, SIO2, SIO3

\- DTR(Double Transfer Rate) Read : SCLK, CS#, SIO0, SIO1, SIO2, SIO3, DQS

◆ High Speed Clock Frequency

\- 3.3V: 104MHz for fast read with 30pF load

\- 1.8V: 80MHz for fast read with 30pF load

\- 3.3V: Quad I/O Data transfer up to 416Mbits/s

\- 1.8V: Quad I/O Data transfer up to 320Mbits/s

◆ Software/Hardware Write Protection

\- Write protect all/portion of memory via software

\- Register protection with WP# Pin

◆ Single Power Supply Voltage

\- Full voltage range for 1.8V: 1.7V \~ 2.0V

\- Full voltage range for 3.3V: 2.7V \~ 3.6V

◆ Advanced security Features

\- 8K-Byte OTP Region

◆ Program/Erase/Read Speed

\- Page Program time: 300us typical

\- Block Erase time: 3ms typical

\- Page read time: 60us maximum

◆ Low Power Consumption

\- 30mA maximum active current

\- 50uA maximum standby current

◆ Enhanced access performance

\- 2Kbyte cache for fast random read

\- Cache read and cache program

◆ Advanced Feature for NAND

\- Factory good block0

◆ Reliability- Factory good block0

\- P/E cycles with ECC: 100K

\- Data retention: 10 Years

◆ Internal ECC

\- 4bits /528Byte

Note: (1) ECC is on default, which can be disable by user.

## 2 GENERAL DESCRIPTION

SPI (Serial Peripheral Interface) NAND Flash provides an ultra-cost effective while high density non-volatile memory storage solution for embedded systems, based on an industry-standard NAND Flash memory core. It is an attractive alternative to SPI-NOR and standard parallel NAND Flash, with advanced features.

• Total pin count is 8, including VCC and GND  
• Density 2Gb  
• Superior write performance and cost per bit over SPI-NOR  
• Significant low cost than parallel NAND

This low-pin-count NAND Flash memory follows the industry-standard serial peripheral interface, and always remains the same pin out from one density to another. The command sets resemble common SPI-NOR command sets, modified to handle NAND specific functions and added new features. GigaDevice SPI NAND is an easy-to-integrate NAND Flash memory, with specified designed features to ease host management:

• User-selectable internal ECC. ECC parity is generated internally during a page program operation. When a page is read to the cache register, the ECC parity is detected and corrects the errors when necessary. The device outputs corrected data and returns an ECC error status.  
• Internal data move or copy back with internal ECC. The device can be easily refreshed and manage garbage collection task, without need of shift in and out of data. This command string can only be used on blocks with the same parity attribute.  
• Power on Read with internal ECC. The device will automatically read first page of fist block to cache after power on, then host can directly read data from cache for easy boot. Also the data is promised correct by internal ECC when ECC enabled.

It is programmed and read in page-based operations, and erased in block-based operations. Data is transferred to or from the NAND Flash memory array, page by page, to a data register and a cache register. The cache register is closest to I/O control circuits and acts as a data buffer for the I/O data; the data register is closest to the memory array and acts as a data buffer for the NAND Flash memory array operation. The cache register functions as the buffer memory to enable page and random data READ/WRITE and copy back operations. These devices also use a SPI status register that reports the status of device operation.

## 2.1 Product List

Please contact GigaDevice regional sales for the latest product selection and available form factors

<table><tr><td>Product Number</td><td>Density</td><td>Voltage</td><td>Package Type</td><td>Temperature</td></tr><tr><td>GD5F2GQ5REYIG</td><td>2Gbit</td><td>1.7V to 2.0V</td><td>WSON8(8*6mm)</td><td>-40°C to 85°C</td></tr><tr><td>GD5F2GQ5REBIG</td><td>2Gbit</td><td>1.7V to 2.0V</td><td>TFBGA24(5*5 Ball Array)</td><td>-40°C to 85°C</td></tr><tr><td>GD5F2GQ5REZIG</td><td>2Gbit</td><td>1.7V to 2.0V</td><td>TFBGA24(4*6 Ball Array)</td><td>-40°C to 85°C</td></tr><tr><td>GD5F2GQ5UEYIG</td><td>2Gbit</td><td>2.7V to 3.6V</td><td>WSON8(8*6mm)</td><td>-40°C to 85°C</td></tr><tr><td>GD5F2GQ5UEBIG</td><td>2Gbit</td><td>2.7V to 3.6V</td><td>TFBGA24(5*5 Ball Array)</td><td>-40°C to 85°C</td></tr><tr><td>GD5F2GQ5UEZIG</td><td>2Gbit</td><td>2.7V to 3.6V</td><td>TFBGA24(4*6 Ball Array)</td><td>-40°C to 85°C</td></tr><tr><td>GD5F2GQ5REYFG*</td><td>2Gbit</td><td>1.7V to 2.0V</td><td>WSON8(8*6mm)</td><td>-40°C to 85°C</td></tr><tr><td>GD5F2GQ5REBFG*</td><td>2Gbit</td><td>1.7V to 2.0V</td><td>TFBGA24(5*5 Ball Array)</td><td>-40°C to 85°C</td></tr><tr><td>GD5F2GQ5REZFG*</td><td>2Gbit</td><td>1.7V to 2.0V</td><td>TFBGA24(4*6 Ball Array)</td><td>-40°C to 85°C</td></tr><tr><td>GD5F2GQ5UEYFG*</td><td>2Gbit</td><td>2.7V to 3.6V</td><td>WSON8(8*6mm)</td><td>-40°C to 85°C</td></tr><tr><td>GD5F2GQ5UEBFG*</td><td>2Gbit</td><td>2.7V to 3.6V</td><td>TFBGA24(5*5 Ball Array)</td><td>-40°C to 85°C</td></tr><tr><td>GD5F2GQ5UEZFG*</td><td>2Gbit</td><td>2.7V to 3.6V</td><td>TFBGA24(4*6 Ball Array)</td><td>-40°C to 85°C</td></tr><tr><td>GD5F2GQ5REYJG</td><td>2Gbit</td><td>1.7V to 2.0V</td><td>WSON8(8*6mm)</td><td>-40°C to 105°C</td></tr><tr><td>GD5F2GQ5REBJG</td><td>2Gbit</td><td>1.7V to 2.0V</td><td>TFBGA24(5*5 Ball Array)</td><td>-40°C to 105°C</td></tr><tr><td>GD5F2GQ5REZJG</td><td>2Gbit</td><td>1.7V to 2.0V</td><td>TFBGA24(4*6 Ball Array)</td><td>-40°C to 105°C</td></tr><tr><td>GD5F2GQ5UEYJG</td><td>2Gbit</td><td>2.7V to 3.6V</td><td>WSON8(8*6mm)</td><td>-40°C to 105°C</td></tr><tr><td>GD5F2GQ5UEBJG</td><td>2Gbit</td><td>2.7V to 3.6V</td><td>TFBGA24(5*5 Ball Array)</td><td>-40°C to 105°C</td></tr><tr><td>GD5F2GQ5UEZJG</td><td>2Gbit</td><td>2.7V to 3.6V</td><td>TFBGA24(4*6 Ball Array)</td><td>-40°C to 105°C</td></tr></table>

Note: (1) Industrial+: F grade has implemented additional test flows to ensure higher product quality than I grade.

## 2.2 CONNECTION DIAGRAM

Figure 2-1.Connect Diagram  
![](images/aabcb50ecd150cac1381cae03d26d2043e276d1247bf7ba20937e6ab3390da9f.jpg)

![](images/b196abbdc8befa63ccd45faeb7c5c8adae6ca3a07fa73a08d3dce0ccd02f3d92.jpg)

<details>
<summary>text_image</summary>

Top View
A1 A2 A3 A4
NC NC NC NC
B1 B2 B3 B4
NC SCLK VSS VCC
C1 C2 C3 C4
NC CS# DQS WP#(SIO2)
D1 D2 D3 D4
NC SO(SIO1) SI(SIO0) HOLD# (SIO3)
E1 E2 E3 E4
NC NC NC NC
F1 F2 F3 F4
NC NC NC NC
</details>

24-BALL TFBGA (4x6 ball array)

## 2.3 PIN DESCRIPTION

<table><tr><td>Pin Name</td><td>I/O</td><td>Description</td></tr><tr><td>CS#</td><td>I</td><td>Chip Select input, active low</td></tr><tr><td>SO/SIO1</td><td>I/O</td><td>Serial Data Output / Serial Data Input Output 1</td></tr><tr><td>WP#/SIO2</td><td>I/O</td><td>Write Protect, active low / Serial Data Input Output 2</td></tr><tr><td>VSS</td><td>Ground</td><td>Ground</td></tr><tr><td>SI/SIO0</td><td>I/O</td><td>Serial Data Input / Serial Data Input Output 0</td></tr><tr><td>SCLK</td><td>I</td><td>Serial Clock input</td></tr><tr><td>HOLD#/SIO3</td><td>I/O</td><td>Hold Input/Serial Data Input Output 3</td></tr><tr><td>DQS (only for BGA24)</td><td>O</td><td>Data Strobe Signal Output</td></tr><tr><td>VCC</td><td>Supply</td><td>Power Supply</td></tr><tr><td>NC</td><td></td><td>Not Connect, Not internal connection; can be driven or floated.</td></tr></table>

Note：  
1. CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on.  
2. If the DQS Function is not used, this pin must be floating.

## 2.4 BLOCK DIAGRAM

Figure 2-2.Block Diagram  
![](images/ceba4f83b170efebf3759e0c718679d5ae2af33e9bea308e57867c09d42e091a.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph TD
  A["DQS"] --> B["Serial NAND controller"]
  C["SCLK"] --> B
  D["SI/SIO0"] --> B
  E["SO/SIO1"] --> B
  F["CS#"] --> B
  G["HOLD#/SIO3"] --> B
  H["WP#/SIO2"] --> B
  B --> I["Cache memory"]
  I --> J["NAND memory core"]
  J --> K["Status register"]
  L["Vcc"] --> M["Output"]
  N["Vss"] --> M
```
</details>

## 3 MEMORY MAPPING

For 2G  
![](images/f3958476281234049cbc69364b427e40440d9777400cec28188cdaf1e02c88dc.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph LR
  subgraph Blocks
  A["Blocks\nRA<16:6>"] --> B["0"]
  A --> C["1"]
  A --> D["2"]
  D --> E["2047"]
  end

  subgraph Pages
  F["Pages\nRA<5:0>"] --> G["0"]
  F --> H["1"]
  H --> I["63"]
  end

  subgraph Bytes
  J["Bytes\nCA<11:0>"] --> K["0"]
  J --> L["1"]
  J --> M["2"]
  M --> N["2175"]
  end
```
</details>

Note:  
1. CA: Column Address. The 12-bit address is capable of addressing from 0 to 4095 bytes; however, only bytes 0 through 2175 are valid. Bytes 2176 through 4095 of each page are “out of bounds,” do not exist in the device, and cannot be addressed.  
2. RA: Row Address. RA<5:0>selects a page inside a block, and RA<16:6>selects a block.

## 4 ARRAY ORGANIZATION

Table 3-1.Array Organization

<table><tr><td>Each device has</td><td rowspan="2">Each block has</td><td rowspan="2">Each page has</td><td rowspan="2"></td></tr><tr><td>2Gb</td></tr><tr><td>256M+16M</td><td>128K+8K</td><td>2K+128</td><td>bytes</td></tr><tr><td>2048 x 64</td><td>64</td><td>-</td><td>pages</td></tr><tr><td>2048</td><td>-</td><td>-</td><td>blocks</td></tr></table>

Figure 3-1. Array Organization

![](images/fc43d0e740b6032fe3d47e5bf3dc4ee18e86164889ab96549816ee6b0dca0319.jpg)

<details>
<summary>text_image</summary>

Cache Register
2048 128
Data Register
2048 128
Per device:
2Gb: 2048 blocks
1 page = (2K + 128) bytes
1 block = (2K + 128) bytes x 64 pages
= (128K + 8K) bytes
1 device = (128K + 8K) bytes x 2048 blocks
= 2Gb
</details>

Internal ECC = OFF

![](images/453b6115979aa006cbf329e3cafc825f3357ee26a83e5f45a17271ac0299de19.jpg)

<details>
<summary>text_image</summary>

Cache Register
2048 64
Data Register
2048 64
Per device:
2Gb: 2048 blocks
1 block
SO
SI
1 page = (2K + 64) bytes
1 block = (2K + 64) bytes x 64 pages
= (128K + 4K) bytes
1 device = (128K + 4K) bytes x 2048 blocks
= 2Gb
</details>

Internal ECC = ON

## Note:

1.When Internal ECC is enabled，user can program the first 64 bytes of the entire 128 bytes spare area and the last 64 bytes of the whole spare area cannot be programed，user can read the entire 128 Byte spare area.  
2.When Internal ECC is disabled，user can read and program the entire 128 bytes spare area.

## 5 DEVICE OPERATION

## 5.1 SPI Modes

SPI NAND supports two SPI modes:

• CPOL = 0, CPHA = 0 (Mode 0)  
• CPOL = 1, CPHA = 1 (Mode 3)

Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK for both modes. All timing diagrams shown in this data sheet are mode 0. See Figure5-1 for more details.

Figure 5-1. SPI Modes Timing Diagram  
![](images/5adddb568ef448df4679e84c8dbeb3c7ac66462b4314ad576c31571a21816932.jpg)  
Note: While CS# is HIGH, keep SCLK at VCC or GND (determined by mode 0 or mode 3). Do not toggle SCLK until CS# is driven LOW.  
We recommend that the user pull CS# to high when user don’t use SPI flash, otherwise the flash is always in the read state, which is not good for flash.  
When CS# is high and SCLK at VCC or GND state, the device is in idle state.

## Standard SPI

SPI NAND Flash features a standard serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO).

## Dual SPI

SPI NAND Flash supports Dual SPI operation when using the x2 and dual IO commands. These commands allow data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: SIO0 and SIO1.

## Quad SPI

SPI NAND Flash supports Quad SPI operation when using the x4 and Quad IO commands. These commands allow data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: SIO0 and SIO1, and WP# and HOLD# pins become SIO2 and SIO3.

## DTR Quad SPI

The device supports DTR Quad SPI operation when using the “DTR Quad I/O Fast Read” command.

These command allow data to be transferred to or from the device at eight times the rate of the standard SPI, and data output will be latched on both rising and falling edges of the serial clock. When using the DTR Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. DTR Quad SPI commands require the Quad Enable bit (QE) in Status Register to be enable. The device has the DQS pin (Only for BGA24 Package). A data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver

## 5.2 HOLD Mode

The HOLD# function is only available when QE=0. If QE=1, the HOLD# functions is disabled, the pin acts as dedicated data I/O pin.

The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of reading, programming, or erasing in progress.

The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).

The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and then CS# must be at low.

Figure5-2. Hold Condition  
![](images/26cc48d89db717a20fc4ba65d779836eafd444f616474db40cd1a1f0f15f8085.jpg)

<details>
<summary>text_image</summary>

CS#
SCLK
HOLD#
HOLD→
HOLD→
</details>

## 5.3 Write Protection

SPI NAND provides Hardware Protection Mode besides the Software Mode. Write Protect (WP#) prevents the block lock bits (BP0, BP1, BP2 and INV, CMP) from being over written. If the BRWD bit is set to 1 and WP# is LOW, the block protect bits cannot be altered.

To enable the Write Protection, the Quad Enable bit (QE) of feature (B0[0]) must be set to 0.

## 5.4 Power Off Timing

Please do not turn off the power before Write/Erase operation is completed. Avoid using the device when the battery is low. Power shortage and/or power failure before Write/Erase operation is complete will cause loss of data and/or damage to data.

## 6 COMMANDS DESCRIPTION

Table 6-1. Commands Set

<table><tr><td>Command Name</td><td>Byte1</td><td>Byte2</td><td>Byte3</td><td>Byte4</td><td>Byte5</td><td>Byte6</td><td>Byte 7</td></tr><tr><td>Write Enable</td><td>06H</td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>Write Disable</td><td>04H</td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>Get Features</td><td>0FH</td><td>A7-A0</td><td>D7-D0</td><td> $Wrap^{(7)}$ </td><td></td><td></td><td></td></tr><tr><td>Set Feature</td><td>1FH</td><td>A7-A0</td><td>D7-D0</td><td></td><td></td><td></td><td></td></tr><tr><td>Page Read (to cache)</td><td>13H</td><td>A23-A16</td><td>A15-A8</td><td>A7-A0</td><td></td><td></td><td></td></tr><tr><td>Next Page Read (to cache)</td><td>31H</td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>Next Page Cache Read Random</td><td>13H</td><td>A23-A16</td><td>A15-A8</td><td>A7-A0</td><td>31H</td><td></td><td></td></tr><tr><td>Last Page Read (to cache)</td><td>3FH</td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>Read From Cache</td><td>03H/0BH</td><td>A15-A8</td><td> $A7-A0^{(2)}$ </td><td> $Dummy^{(1)}$ </td><td>D7-D0</td><td></td><td></td></tr><tr><td>Read From Cache x 2</td><td>3BH</td><td>A15-A8</td><td> $A7-A0^{(2)}$ </td><td> $Dummy^{(1)}$ </td><td>D7-D0</td><td></td><td></td></tr><tr><td>Read From Cache x 4</td><td>6BH</td><td>A15-A8</td><td> $A7-A0^{(2)}$ </td><td> $Dummy^{(1)}$ </td><td>D7-D0</td><td></td><td></td></tr><tr><td>Read From Cache Dual IO</td><td>BBH</td><td>A15-A8</td><td> $A7-A0^{(2)}$ </td><td> $Dummyx2^{(1)}$ </td><td>D7-D0</td><td></td><td></td></tr><tr><td>Read From Cache Quad IO</td><td>EBH</td><td>A15-A8</td><td> $A7-A0^{(2)}$ </td><td> $Dummyx4^{(1)}$ </td><td>D7-D0</td><td></td><td></td></tr><tr><td>Read From Cache Quad I/O DTR</td><td>EEH</td><td>A31-A24</td><td>A23-A16</td><td>A15-A8</td><td> $A7-A0^{(2)}$ </td><td>Dummy $x8^{(1)}$ </td><td>D7-D0</td></tr><tr><td> $Read ID^{(4)}$ </td><td>9FH</td><td>Dummy</td><td>MID</td><td>DID</td><td></td><td></td><td></td></tr><tr><td>Read parameter page</td><td>13H</td><td>00H</td><td>00H</td><td>04H</td><td></td><td></td><td></td></tr><tr><td>Read UID</td><td>13H</td><td>00H</td><td>00H</td><td>06H</td><td></td><td></td><td></td></tr><tr><td>Program Load</td><td>02H</td><td>A15-A8</td><td> $A7-A0^{(3)}$ </td><td>D7-D0</td><td>Next byte</td><td></td><td></td></tr><tr><td>Program Load x4</td><td>32H</td><td>A15-A8</td><td> $A7-A0^{(3)}$ </td><td>D7-D0</td><td>Next byte</td><td></td><td></td></tr><tr><td>Program Execute</td><td>10H</td><td>A23-A16</td><td>A15-A8</td><td>A7-A0</td><td></td><td></td><td></td></tr><tr><td>Program Execute Background</td><td>10H</td><td>A23-A16</td><td>A15-A8</td><td>A7-A0</td><td>15H</td><td></td><td></td></tr><tr><td>Program Load Random Data</td><td>84H</td><td>A15-A8</td><td> $A7-A0^{(3)}$ </td><td>D7-D0</td><td>Next byte</td><td></td><td></td></tr><tr><td>Program Load Random Data x4</td><td>C4H/34H</td><td>A15-A8</td><td> $A7-A0^{(3)}$ </td><td>D7-D0</td><td>Next byte</td><td></td><td></td></tr><tr><td>Block Erase(128K)</td><td>D8H</td><td>A23-A16</td><td>A15-A8</td><td>A7-A0</td><td></td><td></td><td></td></tr><tr><td> $Reset^{(5)}$ </td><td>FFH</td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td>Enable Power on Reset</td><td>66h</td><td></td><td></td><td></td><td></td><td></td><td></td></tr><tr><td> $Power on Reset^{(6)}$ </td><td>99h</td><td></td><td></td><td></td><td></td><td></td><td></td></tr></table>

## Note:

1. The dummy has 8 clock.  
03H/0BH/3BH/6BH has 1 byte dummy. BBH has 2 bytes dummy.  
EBH has 4 bytes dummy. EEH has 8 bytes dummy.

2. The A15-A0 (03H/0BH/3BH/6BH) has 16 clock, include 4 clock dummy.

The A15-A0 (BBH) has 8 clock, include 2 clock dummy.

The A15-A0 (EBH) has 4 clock, include 1 clock dummy.

The A31-A0 (EEH) has 4 clock, include 2.5 clock dummy.

3. The A15-A0 has 16 clock, include 4 clock dummy.  
4. MID is Manufacture ID (C8h for GigaDevice), DID is Device ID.  
5. Reset command:

• Reset will reset PAGE READ/PROGRAM/ERASE operation.  
• Reset will reset status register bits P\_FAIL/E\_FAIL/WEL/OIP/CBSY/ECCS/ECCSE.  
6. Power on reset:

Retrieve status register and data in cache to power on status.

7. The output would be updated by real-time, until CS# is driven high.

## 7 WRITE OPERATIONS

## 7.1 Write Enable (WREN) (06H)

The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to following operations that change the contents of the memory array:

• Page program  
• OTP program/OTP protection  
• Block erase

The WEL bit can be cleared after a reset command.

Figure 7-1.Write Enable Timing Diagram  
![](images/343f7b3c31c7222d5f6f45041cdcd903fbb8b6f15ea145f0a79be413b11bbf7b.jpg)

<details>
<summary>text_image</summary>

CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI
06H
High-Z
SO
</details>

## 7.2 Write Disable (WRDI) (04H)

The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The WEL bit is reset by following condition:

• Page program  
• OTP program/OTP protection  
• Block erase

Figure 7-2.Write Disable Timing Diagram  
![](images/7441b7c3bb1b3d617b08706cc77d8099c3e619b8f2ad82d6751a3fd0bf589a1c.jpg)

<details>
<summary>text_image</summary>

CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI
04H
High-Z
SO
</details>

## 8 READ OPERATIONS

## 8.1 Page Read

The PAGE READ (13H) command transfers the data from the NAND Flash array to the cache register. The command sequence is as follows:

• 13H (PAGE READ to cache)  
• 0FH (GET FEATURES command to read the status)  
• 03H or 0BH (Read from cache)/3BH (Read from cache x2)/6BH (Read from cache x4)/BBH/EBH/EEH (Read from cache DTR x4)

The PAGE READ command requires a 24-bit address. After the block/page addresses are registered, the device starts the transfer from the main array to the cache register, and is busy for tRD time. During this time, the GET FEATURE (0FH) command can be issued to monitor the status. Followed the page read operation, the RANDOM DATA READ (03H/0BH/3BH/6BH/EEH) command must be issued in order to read out the data from cache. The output data starts at the initial address specified in the command, once it reaches the ending boundary of whole page section, the output will wrap around from the beginning boundary until CS# is pulled high to terminate this operation. Refer waveforms to view the entire READ operation.

Note:(1) The command 6BH (Read from cache x4)/EBH (Read from cache Quad IO)/EEH (Read from cache Quad IO DTR) is only available with the QE enable.  
(2) When user read to the end of 64-Byte spare area, it won’t wrap around from the beginning boundary and an additional 64Byte ECC code will be read. (Internal ECC enabled)

## 8.2 Page Read to Cache (13H)

The command page read to cache is read the data from flash array to cache register.

Figure 8-1.Page Read to cache Timing Diagram  
![](images/4af5305727b1bb17fb0a9669a56b6401806a645327f604a28dc2c9743ba940ea.jpg)

## 8.3 Cache Read Function (31H/3FH)

A “Cache Read” function has been implemented in SPI series to improve the overall read throughput. It is possible to transfer the data from array to the Data Register simultaneously while a Read Data command is being performed to read out data from the Cache Register.

When multiple pages of data is to be read out sequentially, the host should issue a “Page Read to Cache (13h)” command followed by a Page Address which specifies the starting page of the data(1). Once the command is accepted, the host should use “Get Feature (0Fh)” to check the OIP bit value to determine if the internal operation has completed or not.

Prior to issuing a Read Data command (i.e. 03h/0Bh/3Bh/6Bh/BBh/EBh) to read out the data in the Cache Register, the host can issue a “Next Page Cache Read (31h)” command to initiate the Cache Read operation. There is not necessary to provide any Page Address since the device will automatically increment the Page Address specified earlier by “Page Read to Cache (13h)” instruction. After the “Next Page Cache Read” (31h) command issued, the device starts to transfer data from data register to cache register for tCBSYR. And CBSY bit (through GET FEATURE command to check this status bit) goes to 1 from 0.

While the device is transferring the next page array data to the Data Register, the host can now use Read From Cache command to shift out the current page data inside the Cache Register. Once CBSY bit becomes 0, the host can issue a Read Data command to shift out the Cache Register data, then issue “Next Page Cache Read (31h)” again to read the next page in the array.

If the current page address is the last page of a block or the last page of the data being read out, the host should issue “Last Page Cache Read (3Fh)” instead of “Next Page Cache Read (31h)”, and proceed with the last Read from cache command. If the data being read out is more than one block, another “Page Read to Cache (13h)” command is needed to specify the first page of the next block and initiate the “Cache Read” operation again in the next block.

Table 8-1.Cache Read instruction description

<table><tr><td>Instruction</td><td>Command Code</td><td>Description</td></tr><tr><td>Next Page Cache Read</td><td>31h</td><td>Issue prior to current page “Read From Cache” and read next page data into Data Register.</td></tr><tr><td>Next Page Cache Read Random</td><td>13h+addr+31h</td><td>Issue prior to current page “Read From Cache” and read special page data into Data Register.</td></tr><tr><td>Last Page Cache Read</td><td>3Fh</td><td>Issue prior to last page “Read From Cache” at the end of a block or the end of the data being read.</td></tr></table>

## Notes:

1. Upon powered up, SPI NAND will automatically load Block-0/Page-0 data into the Cache Register. If this is the starting page of the data that is to be read out, it is not necessary to issue a “Page Read to Cache (13h)” command to initiate the “Cache Read” operation.  
2. Before issuing 31h/3Fh, CBSY bit must be checked to make sure CBSY=0, device is not performing any internal operations.

The command sequence is as follows:

• 13H (PAGE READ to cache)  
• 0FH (GET FEATURES command to read the status until OIP status bit is changed from 1 to 0)  
• 31H (NEXT PAGE CACHE READ command to transfer data from data register to cache register and kick off the next page transfer from array to data register)  
• 0FH (GET FEATURES command to read the status until CBSY=0)  
• 03H or 0BH (Read from cache)/3BH (Read from cache x2)/6BH (Read from cache x4)/BBH/EBH/EEH (Read from cache DTR x4)  
• 3FH (LAST PAGE CACHE READ command to end the read page cache sequence and copy a last page from the data register to cache register)  
• 0FH (GET FEATURES command to read the status until CBSY=0)  
• 03H or 0BH (Read from cache)/3BH (Read from cache x2)/6BH (Read from cache x4)/BBH/EBH/EEH (Read from cache DTR x4)

Figure 8-2.Cache Read operation flow chart  
![](images/e3503671df72f45ed106fb3d776cc9470593584d6bad0a8b281258044b32c694.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph TD
  Start["Start Cache Read"] --> PageRead["Page Read\n(Page N)"]
  PageRead --> CheckIOIP{"OIP=0?"}
  CheckIOIP -->|N| NextPageRead["Next Page Read\n(Page n+1)"]
  CheckIOIP -->|Y| NextPageRead
  NextPageRead --> CheckCBSY{"CBSY=0?"}
  CheckCBSY -->|N| NextPageRead
  CheckCBSY -->|Y| ReadData["Read Data\n(Page N)"]
  ReadData --> N+1["N=N+1"]
  N1["N+1"] --> CheckEOB{"N=EOB or EOD?"}
  CheckEOB -->|N| NextPageRead
  CheckEOB -->|Y| ReadData
  ReadData --> Done["Done"]
  NextPageRead --> CheckCBSY{"CBSY=0?"}
  CheckCBSY -->|N| LastPageRead["Last Page Read\n(Page M)"]
  LastPageRead --> CheckCBSY
  CheckCBSY -->|Y| ReadData
  ReadData --> Done
  CheckCBSY -->|N| LastPageRead
  CheckCBSY -->|Y| ReadData
```
</details>

Figure 8-3.Page Read to Cache Timing Diagram  
![](images/ea8cff647c04b2e0ac8d1a3060e1bd9d9c4f50cbd06ce45c8542cc1559200a18.jpg)

<details>
<summary>text_image</summary>

CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI
31H
SO
High-Z
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SLK
tCS
Get Feature
1 byte address
SI
0FH
7 6 5 4 3 2 1 0
SO
High-Z
MSB
CS#
16 17 18 19 20 21 22 23 24
SCLK
SI
Data byte
SO
7 6 5 4 3 2 1 0 7
MSB
</details>

Figure 8-4.Page Read to Cache Timing Diagram

![](images/ea764a257b8125933e6403664d7a9d31cec67e8730b18b3daeafca6a3145a3f4.jpg)

<details>
<summary>text_image</summary>

CS#
0 1 2 3 4 5 6 7 8 9 10
SCLK
Command
24-bit address
SI
13H
23 22 21
3 2 1 0
31H
SO
High-Z
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SLK
tCS
Get Feature
1 byte address
SI
0FH
7 6 5 4 3 2 1 0
SO
High-Z
MSB
CS#
16 17 18 19 20 21 22 23 24
SCLK
SI
Data byte
SO
7 6 5 4 3 2 1 0 7
MSB
</details>

Figure 8-5.Page Read to Cache Timing Diagram  
![](images/31c34d53aa5fbde9fac6df83c5c12c8dbd4bfd5158ed1898f585f3103e18bb97.jpg)

<details>
<summary>text_image</summary>

CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI
3FH
SO
High-Z
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SLK
tCS
Get Feature
1 byte address
SI
0FH
7 6 5 4 3 2 1 0
SO
High-Z
MSB
CS#
16 17 18 19 20 21 22 23 24
SCLK
SI
Data byte
SO
7 6 5 4 3 2 1 0 7
MSB
</details>

Figure 8-6.Page Read to Cache Timing Diagram  
![](images/339900a74423153c5c2f48ae3b9f82a7f463ca764e808410d077aa8b6ca0c835.jpg)

<details>
<summary>text_image</summary>

CS#
0 1 2 3 4 5 6 7 8 9 10
SCLK
Page Read
24-bit address
tRD
Cache Read
0 1 2 3 4 5 6 7
SI
13H
MSB
3 2 1 0
SO
High-Z
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SCLK
tCBSYR
Read From Cache
Dummy<3:0>
A11-A0
Dummy byte
Data byte 0
SI
03H
0 0 0 0 11 10
SO
High-Z
MSB
CS#
0 1 2 3 4 5 6 7
SCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SI
31H
tCBSYR
Read From Cache
Dummy<3:0>
A11-A0
Dummy byte
Data byte 0
SO
High-Z
CS#
32 33 34 35 36 37 38 39
SCLK
Data byte 0
SI
3FH
Last Page Read
tCBSYR
Read From Cache
03H
SO
7 6 5 4 3 2 1 0
MSB
CS#
8 9 10 11 12 13 14
SCLK
Dummy<3:0>
A11-A0
Dummy byte
Data byte 0
Data byte 1
Data byte N
SI
0 0 0 0 11 10
3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 
</details>

## Note：

1. Command 03h/0Bh/3Bh/6Bh/BBh/EBh is available to read out the data in the Cache Register.  
2. For high speed performance, we recommend to use EBh to read out the data in the Cache Register. (Please refer to 8.8 Read From Cache Quad IO)  
3. We recommend to use GET FEATURES command (0Fh) to read the status until CBSY=0.

## 8.4 Read From Cache (03H or 0BH)

The command sequence is shown below.

Figure 8-7.Read From Cache Timing Diagram  
![](images/09c5172dc7c3328e5e10b532a26a7e97ffd02c5da26241e7ee3520222914159f.jpg)

<details>
<summary>text_image</summary>

CS#
SCLK
Command
Dummy<3:0>
A11-A0
SI
03H or 0BH
0 0 0 0 11 10
3 2 1 0
SO
High-Z
CS#
SCLK
Dummy byte
SI
7 6 5 4 3 2 1 0
Data byte 0
SO
7 6 5 4 3 2 1 0
Data byte 1
MSB
MSB
</details>

## 8.5 Read From Cache x2 (3BH)

The command sequence is shown below.

Figure 8-8.Read From Cache x2 Timing Diagram  
![](images/c935e090628694cb5b7c2d5b5e5cdd970504fbe6ce4b4164ea41e6d1a37437bf.jpg)

<details>
<summary>text_image</summary>

CS#
SCLK
Command
Dummy<3:0>
A11-A0
SI/SIO0
3BH
0 0 0 0 11 10
3 2 1 0
SO/SIO1
High-Z
CS#
SCLK
Dummy byte
SI/SIO0
7 6 5 4 3 2 1 0
6 4 2 0
6 4 2 0
6 4 2
SO/SIO1
Data byte 0
Data byte 1
MSB
MSB
7 5 3 1
7 5 3 1
7 5 3
</details>

## 8.6 Read From Cache x4 (6BH)

The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read from cache x4 command. The command sequence is shown below.

Figure 8-9.Read From Cache x4 Timing Diagram  
![](images/4654ffcb1c75a72cebdd19cdd5562ac345b2d2f84f37efb7cce5ac83a3043823.jpg)

<details>
<summary>text_image</summary>

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 22 23
SCLK
Command Dummy<3:0> A11-A0
SI(SIO0) 6BH 0 0 0 0 11 10 3 2 1 0
SO(SIO1) High-Z
WP#(SIO2) High-Z
HOLD#(SIO3) High-Z
CS#
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK Dummy byte
SI(SIO0) 7 6 5 4 3 2 1 0 4 0 4 0 4 0 4 0 4
SO(SIO1) 5 1 5 1 5 1 5 1 5
WP#(SIO2) 6 2 6 2 6 2 6 2 6
HOLD#(SIO3) 7 3 7 3 7 3 7 3 7
Byte0 Byte1 Byte2 Byte3
</details>

## 8.7 Read From Cache Dual IO (BBH)

The Read from Cache Dual I/O command (BBH) is similar to the Read form Cache x2 command (3BH) but with the capability to input the 4 Dummy bits, followed by a 12-bit column address for the starting byte address and dummy bytes by SIO0 and SIO1, each bit being latched in during the rising edge of SCLK, then the cache contents are shifted out 2-bit per clock cycle from SIO0 and SIO1. The first address byte can be at any location. The address increments automatically to the next higher address after each byte of data shifted out. The command sequence is shown below.

Figure 8-10.Read From Cache Dual IO Timing Diagram  
![](images/e2e726866d1895649ec7e388b5035a8500e43a91b7baa3d45c2c7f0637baad86.jpg)

<details>
<summary>text_image</summary>

CS#
SCLK
Command
Dummy
<3:0>
A11-A0
BBH
Dummy
SI(SIO0)
SO(SIO1)
CS#
SCLK
SI(SIO0)
SO(SIO1)
Data
byte 0
Data
byte 1
Data
byte 2
Data
byte 3
Data
byte 0
Data
byte 1
Data
byte 2
Data
byte 3
</details>

## 8.8 Read From Cache Quad IO (EBH)

The Read from Cache Quad IO command is similar to the Read from Cache x4 command but with the capability to input the 4 dummy bits, followed a 12-bit column address for the starting byte address and dummy bytes by SIO0, SIO1, SIO3, SIO4, each bit being latched in during the rising edge of SCLK, then the cache contents are shifted out 4-bit per clock cycle from SIO0, SIO1, SIO2, SIO3. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read from cache quad IO command. The command sequence is shown below.

Figure 8-11.Read From Cache Quad IO Timing Diagram  
![](images/b4f48eb41fe925af5d8eefab289e736bdec20ce1083c66cc7aabc2b65ef62d11.jpg)

<details>
<summary>text_image</summary>

CS#
SCLK
Command Dummy
3:0
SI(SIO0) EBH
SO(SIO1)
WP#(SIO2)
HOLD#(SIO3)
A11 - A0 Dummy Byte0 Byte1
</details>

## 8.9 Read From Cache Quad I/O DTR (EEH)

The DTR QIO command enables Double Transfer Rate throughput on quad I/O of Serial Flash in read mode. A Quad Enable (QE) bit of status Register must be set to “1” before sending the DTR QIO command. The address (interleave on 4 I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on 4 I/O pins) shift out on both rising and falling edge of SCLK. The 8-bit address can be latched-in at one clock, and 8-bit data can be read out at one clock, which means four bits at rising edge of clock, the other four bits at falling edge of clock.

The first address Byte can be at any location. The address is automatically increased to the next higher address after each Byte data is shifted out, so the whole page can be read out at a single DTR QIO command. The address counter rolls over to 0 when the highest address has been reached.

Figure 8-12.Read From Cache Quad I/O DTR Timing Diagram  
![](images/65b603938a3331f3f449c2c6ed5cd6aa5126d90244b8116c97c76afa4d3407f1.jpg)

<details>
<summary>text_image</summary>

CS#
SCLK
Command
EEH
SI(IO0)
Dummy
<19:0>
Dummy
4 0 4 0
SO(IO1)
0 0 0 0 0 9 5 1
5 1 5 1
DQS
IO2
0 0 0 0 0 10 6 2
6 2 6 2
IO3
0 0 0 0 0 11 7 3
A11-A0
Byte 0Byte 1
19 20
</details>

## Note:

Please contact GigaDevice when there is a need to use the EEh command for DTR.

The max clock rate for DTR depends on the tCLQV (clock to data output valid). Per datasheet, with output load capacitance of 30pf, the tCLQV is about 11ns. This will limit the max rate to 45Mhz.

However, in general, most of PCB designs have output loading much less than 30pf. Lower output loading will in turn shorten the tCLQV and result in higher max clock rate.

GigaDevice recommend customers measure the tCLQV and then set the clock rate to match the SPI host data sampling data setup time and hold time.

## 8.10 Read ID (9FH)

The READ ID command is used to identify the NAND Flash device.

• With address 00H, the READ ID command outputs the Manufacturer ID and the device ID. See Table 8-2 for details.

Figure 8-13.Read ID Timing Diagram  
![](images/4fdbdfd9298bda9175599f45dc0d85b9a37c97dcb8ce4fdf5f0e2037c6691d9f.jpg)

<details>
<summary>text_image</summary>

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCLK
Command
Dummy
SI
9FH
7 6 5 4 3 2 1 0
SO
High-Z
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI
Manufacturer ID
Device ID
SO
7 6 5 4 3 2 1 0
MSB
MSB
</details>

Table 8-2. READ ID Table

<table><tr><td>Part No</td><td>MID</td><td>DID1</td></tr><tr><td>GD5F2GQ5UExxG</td><td>C8H</td><td>52H</td></tr><tr><td>GD5F2GQ5RExxG</td><td>C8H</td><td>42H</td></tr></table>

## 8.11 Read UID

The Read Unique ID function is used to retrieve the 16 bytes unique ID (UID) for the device. The unique ID when combined with the device manufacturer shall be unique.

The UID data may be stored within the Flash array. To allow the host to determine if the UID is without bit errors, the UID is returned with its complement. If the XOR of the UID and its bit-wise complement is all ones, then the UID is valid. To accommodate robust retrieval of the UID in the case of bit errors, sixteen copies of the UID and the corresponding complement are stored by the target. For example, reading byte 32-63 returns to the host another copies of the UID and its complement.

<table><tr><td>Bytes</td><td>Value</td></tr><tr><td>0-15</td><td>UID</td></tr><tr><td>16-31</td><td>UID complement (bit-wise)</td></tr></table>

## Sequence is as follows:

1. Use Set Feature command to set B0 register, to enable OTP\_EN.  
2. Use Get Feature command to get data from B0 register and check if the OTP\_EN is enable.  
3. Use Page Read to Cache (13h) command with address 24’h000006h, read data from array to cache.  
4. Use 0FH (GET FEATURES command) read the status.  
5. User can use Read from cache command (03H/0BH), read 16 bytes UID from cache.

Figure 8-14. Read UID to cache and Get Feature command Timing Diagram  
![](images/64d79f7353b7ae65411a1c43d8d7b3d0a12c6e96df699da85b21a00f2133abad.jpg)

<details>
<summary>text_image</summary>

CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCLK
SI
Command
24-bit address
13H
000006H
SO
High-Z
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SLK
tCS
Get Feature
1 byte address
SI
0FH
7 6 5 4 3 2 1 0
SO
High-Z
MSB
CS#
16 17 18 19 20 21 22 23 24
SCLK
SI
Data byte
SO
7 6 5 4 3 2 1 0 7
MSB
</details>

## 8.12 Read Parameter Page

The Read Parameter Page function retrieves the data structure that describes the chip’s organization, features, timing and other behavioral parameters. This data structure enables the host processor to automatically recognize the SPI-NAND Flash configuration of a device. A minimum of three copies of the parameter page are stored in the device. The Read from Cache command can be used to change the location of data output.

Sequences as follows:

1. Use Set Feature command to set B0 register, to enable OTP\_EN.  
2. Use Get Feature command to get data from B0 register and check if the OTP\_EN is enable.  
3. Use Page Read to Cache (13h) command with address 24’h000004. Load parameter page from array to cache.  
4. Use 0Fh (GET FEATURES command) read the status  
5. User can use Read from cache command (03h/0Bh), read parameter page from cache.

Figure 8-15. Read parameter page to cache and Get Feature command Timing Diagram  
![](images/09ca7246ee158e984bf4611476216ff1782ecd917d21b0a0ccc3d34b29398ee8.jpg)

Parameter page table as follow

<table><tr><td>Byte</td><td>O/M</td><td colspan="3">Description</td><td>3.3V/1.8V</td></tr><tr><td rowspan="5">0-3</td><td rowspan="5">M</td><td colspan="3">Parameter page signature</td><td>4FH</td></tr><tr><td colspan="3">Byte 0: 4FH, “O”</td><td>4EH</td></tr><tr><td colspan="3">Byte 1: 4EH, “N”</td><td>46H</td></tr><tr><td colspan="3">Byte 2: 46H, “F”</td><td>49H</td></tr><tr><td colspan="3">Byte 3: 49H, “I”</td><td></td></tr><tr><td rowspan="2">4-5</td><td rowspan="2">M</td><td colspan="3">Revision number</td><td>00H</td></tr><tr><td colspan="3">0-15 Reserved (0)</td><td>00H</td></tr><tr><td rowspan="2">6-7</td><td rowspan="2">M</td><td colspan="3">Features supported</td><td>00H</td></tr><tr><td colspan="3">0-15 Reserved (0)</td><td>00H</td></tr><tr><td rowspan="2">8-9</td><td rowspan="2">M</td><td rowspan="2" colspan="3">Reserved (0)</td><td>00H</td></tr><tr><td>00H</td></tr><tr><td rowspan="3">10-31</td><td rowspan="3"></td><td rowspan="3" colspan="3">Reserved (0)</td><td>00H</td></tr><tr><td>...</td></tr><tr><td>00H</td></tr><tr><td></td><td></td><td colspan="3">Manufacturer Information block</td><td></td></tr><tr><td rowspan="12">32-43</td><td rowspan="12">M</td><td rowspan="12" colspan="3">Device manufacturer (12 ASCII characters)“GIGADEVICE ”</td><td>47H</td></tr><tr><td>49H</td></tr><tr><td>47H</td></tr><tr><td>41H</td></tr><tr><td>44H</td></tr><tr><td>45H</td></tr><tr><td>56H</td></tr><tr><td>49H</td></tr><tr><td>43H</td></tr><tr><td>45H</td></tr><tr><td>20H</td></tr><tr><td>20H</td></tr><tr><td rowspan="14">44-63</td><td rowspan="14">M</td><td colspan="3">Device model (20 ASCII characters)</td><td>47H</td></tr><tr><td>Device Model</td><td>ORGANIZATION</td><td>VCC RANGE</td><td>44H</td></tr><tr><td>“GD5F2GQ5U”</td><td>X4</td><td>2.7v ~ 3.6v</td><td>35H</td></tr><tr><td rowspan="11">“GD5F2GQ5R”</td><td rowspan="11">X4</td><td rowspan="11">1.7v ~ 2.0v</td><td>46H</td></tr><tr><td>32H</td></tr><tr><td>47H</td></tr><tr><td>51H</td></tr><tr><td>35H</td></tr><tr><td>55H/52H</td></tr><tr><td>20H</td></tr><tr><td>20H</td></tr><tr><td>20H</td></tr><tr><td>20H</td></tr><tr><td>20H</td></tr></table>

<table><tr><td></td><td></td><td></td><td>20H20H20H20H20H</td></tr><tr><td>64</td><td>M</td><td>JEDEC manufacturer ID“C8”</td><td>C8H</td></tr><tr><td>65-66</td><td>O</td><td>Date code</td><td>00H00H</td></tr><tr><td>67-79</td><td></td><td>Reserved</td><td>00H00H00H</td></tr><tr><td></td><td></td><td>Memory organization block</td><td></td></tr><tr><td>80-83</td><td>M</td><td>Number of data bytes per page</td><td>00H08H00H00H</td></tr><tr><td>84-85</td><td>M</td><td>Number of spare bytes per page</td><td>80H00H</td></tr><tr><td>86-89</td><td>M</td><td>Number of data bytes per partial page</td><td>00H02H00H00H</td></tr><tr><td>90-91</td><td>M</td><td>Number of spare bytes per partial page</td><td>20H00H</td></tr><tr><td>92-95</td><td>M</td><td>Number of pages per block</td><td>40H00H00H00H</td></tr><tr><td>96-99</td><td>M</td><td>Number of blocks per logical unit</td><td>00H08H00H00H</td></tr><tr><td>100</td><td>M</td><td>Number of logical units</td><td>01H</td></tr><tr><td>101</td><td>M</td><td>Reserved</td><td>00H</td></tr><tr><td>102</td><td>M</td><td>Number of bits per cell</td><td>01H</td></tr><tr><td>103-104</td><td>M</td><td>Bad blocks maximum per logical unit</td><td>28H00H</td></tr><tr><td>105-106</td><td>M</td><td>Block endurance</td><td>01H05H</td></tr><tr><td>107</td><td>M</td><td>Guaranteed valid blocks at beginning of target</td><td>01H</td></tr><tr><td>108-109</td><td>M</td><td>Block endurance for guaranteed valid blocks</td><td>00H00H</td></tr><tr><td>110</td><td>M</td><td>Number of programs per page</td><td>04H</td></tr><tr><td>111</td><td>M</td><td>Partial programming attributes5-7 Reserved4 1 = partial page layout is partial page data followed by partial page spare1-3 Reserved0 1 = partial page programming has constraints</td><td>00H</td></tr><tr><td>112</td><td>M</td><td>Number of bits ECC correctability</td><td>00H</td></tr><tr><td>113</td><td>M</td><td>Number of interleaved address bits4-7 Reserved (0)0-3 Number of interleaved address bits</td><td>00H</td></tr><tr><td>114</td><td>O</td><td>Interleaved operation attributes4-7 Reserved (0)3 Address restrictions for program cache2 1 = program cache supported1 1 = no block address restrictions0 Overlapped / concurrent interleaving support</td><td>00H</td></tr><tr><td>115-127</td><td></td><td>Reserved</td><td>00H...00H</td></tr><tr><td></td><td></td><td>Electrical parameters block</td><td></td></tr><tr><td>128</td><td>M</td><td>I/O capacitance</td><td>06H</td></tr><tr><td>129-130</td><td>M</td><td>IO clock support3-1 5 Reserved (0)2 1 = supports 80MHz1 1 = supports 104MHz0 1 = supports 120MHz</td><td>02H/04H00H</td></tr><tr><td>131-132</td><td>O</td><td>Reserved (0)</td><td>00H00H</td></tr><tr><td>133-134</td><td>M</td><td>tPROG Maximum page program time (us)</td><td>58H02H</td></tr><tr><td>135-136</td><td>M</td><td>tBERS Maximum block erase time (us)</td><td>88H13H</td></tr><tr><td>137-138</td><td>M</td><td>tR Maximum page read time (us)</td><td>3CH00H</td></tr><tr><td>139-140</td><td>M</td><td>Reserved</td><td>00H00H</td></tr><tr><td>141-163</td><td></td><td>Reserved</td><td>00H</td></tr><tr><td></td><td></td><td>Vendor block</td><td></td></tr><tr><td>164-165</td><td>M</td><td>Vendor specific Revision number</td><td>00H</td></tr><tr><td>166-253</td><td></td><td>Vendor specific</td><td>00H</td></tr><tr><td>254-255</td><td>M</td><td>Integrity CRC</td><td>Set on test</td></tr><tr><td></td><td></td><td>Redundant parameter pages</td><td></td></tr><tr><td>256-511</td><td>M</td><td>Value of bytes 0-255</td><td></td></tr><tr><td>512-767</td><td>M</td><td>Value of bytes 0-255</td><td></td></tr><tr><td>768+</td><td>O</td><td>Additional redundant parameter pages</td><td></td></tr></table>

## Notes:

1. “O” Stands for Optional, “M” for Mandatory  
2. The Integrity CRC (Cycling Redundancy Check) field is used to verify that the contents of the parameters page were transferred correctly to the host. Please refer to ONFI 1.0 specifications for details. The CRC shall be calculated using the following 16-bit generator polynomial: $\mathsf { G } ( \mathsf { X } ) = \mathsf { X } ^ { 1 6 } + \mathsf { X } ^ { 1 5 } + \mathsf { X } ^ { 2 } + 1$ ，This polynomial in hex may be represented as 8005h.  
3．The CRC value shall be initialized with a value of 4F4Eh before the calculation begins. There is no XOR applied to the final CRC value after it is calculated. There is no reversal of the data bytes or the CRC calculated value.

<table><tr><td>Device Model</td><td>ORGANIZATION</td><td>VCC RANGE</td><td>CRC value B254/B255</td></tr><tr><td>“GD5F2GQ5UxxxG”</td><td>X4</td><td>2.7v ~ 3.6v</td><td>5BH/05H</td></tr><tr><td>“GD5F2GQ5RxxxG”</td><td>X4</td><td>1.7v ~ 2.0v</td><td>96H/48H</td></tr></table>

## 9 PROGRAM OPERATIONS

## 9.1 Page Program

The PAGE PROGRAM operation sequence programs 1 byte to whole page bytes of data within a page. The page program sequence is as follows:

• 02H (PROGRAM LOAD)/32H (PROGRAM LOAD x4)  
• 06H (WRITE ENABLE)  
• 10H (PROGRAM EXECUTE)  
• 0FH (GET FEATURE command to read the status)

Firstly, a PROGRAM LOAD (02H/32H) command is issued. PROGRAM LOAD consists of an 8-bit Op code, followed by 4 dummy bits and a 12-bit column address, then the data bytes to be programmed. The Program address should be in sequential order in a block. The data bytes are loaded into a cache register that is whole page long. If more than one page data are loaded, then those additional bytes are ignored by the cache register. The command sequence ends when CS# goes from LOW to HIGH. Figure 9-1 shows the PROGRAM LOAD operation. Secondly, prior to performing the PROGRAM EXECUTE operation, a WRITE ENABLE (06H) command must be issued. As with any command that changes the memory contents, the WRITE ENABLE must be executed in order to set the WEL bit. If this command is not issued, then the rest of the program sequence is ignored.

## Note:

1. The contents of Cache Register don’t reset when Program Random Load (84h) command and RESET (FFh) command.  
2. When Program Execute (10h) command was issued just after Program Load (02h) command, the 0xFF is output to the address that data was not loaded by Program Load (02h) command.  
3. When Program Execute (10h) command was issued just after Program Load Random Data (84h) command, the contents of Cache Register are output to the NAND array.  
4. The Program address should be in sequential order in a block.  
5. Program Load x4 is only available with the QE enable.

## 9.2 Program Load (PL) (02H)

The command sequence is shown below.

Figure 9-1. Program Load Timing Diagram  
![](images/96a851b255ea13b19d69011401becadc5fda55a205daa3061da824f5d39269bb.jpg)

<details>
<summary>text_image</summary>

CS#
SCLK
SI
Command
Dummy<3:0>
A11-A0
02H
0 0 0 0 1 10
3 2 1 0
CS#
SCLK
SI
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Data byte 0
Data byte 1
Data byte N
MSB
</details>

Note: When internal ECC disabled the Data Byte is 2176, when internal ECC enabled the Data Byte is 2112.

## 9.3 Program Load x4 (PL x4) (32H)

The Program Load x4 command (32H) is similar to the Program Load command (02H) but with the capability to input the data bytes by four pins: SIO0, SIO1, SIO2, and SIO3. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the program load x4 command. The command sequence is shown below.

Figure 9-2. Program Load x4 Timing Diagram  
![](images/b660c2be6cd0f35871a725005cd39d61d55e0712c188b10f3060221330d68b26.jpg)  
Note: When internal ECC disabled the Data Byte is 2176, when internal ECC enabled the Data Byte is 2112.

## 9.4 Program Execute (PE) (10H)

After the data is loaded, a PROGRAM EXECUTE (10H) command must be issued to initiate the transfer of data from the cache registers to the main array. PROGRAM EXECUTE consists of an 8-bit Op code, followed by a 24-bit address. After the page/block address is registered, the memory device starts the transfer from the cache register to the main array, and is busy for tPROG time. This operation shown in Figure 9-3. During this busy time, the status register can be polled to monitor the status of the operation (refer to Status Register). When the operation completes successfully, the next series of data can be loaded with the PROGRAM LOAD command.

Figure 9-3. Program Execute Timing Diagram  
![](images/23355b92f7c8598e09f40a15770d923a15aee870f89915343a1335487c3e83b6.jpg)

## 9.5 Program Execute Background (10h + address + 15h)

A “Cache Program” function has been implemented in SPI series to improve the overall program throughput. It is possible to program the data from Data Register to array the simultaneously while a Load Data command is being performed to write data to the Cache Register.

When multiple pages of data is to be program sequentially, the host should issue a “Program Load (02h)” command followed by a Column Address and data written. When the command is accepted, the host should use Program Execute Background（10h+address+15h）to initial the internal program operation, then the CBSY becomes 1.

Once the CBSY becomes 0, user can issue again the “Program Load (02h)” command followed by a Page Address and data written. Then user can send Program Execute Background command to continue the cache program.

When the last page of one block to be program and the OIP bit is 0, the program execute command (10h+address) should be used to finish the last program operation.

The program execute command (10h+address+15h) is allowed to cross blocks before reaching the last block.

Figure 9-4. Program Execute Background Operation Flow Chart  
![](images/305761c95e760f28ce942527a3b942b95011ae4b7b7fb6b139818940ca41ae56.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph TD
  Start(["Start cache Program"]) --> PageN["Page N"]
  PageN --> PageLoad["Page Load\n(Page N)"]
  PageLoad --> Background["Program execute background"]
  Background --> CBSY{"CBSY = 0 ? (tCBSYW)"}
  CBSY -->|N| Background
  CBSY -->|Y| PageN1["Page N+1"]
  PageN1 --> LastPage{"Last Page"}
  LastPage -->|N| PageLoad
  LastPage -->|Y| PageLoad
  PageLoad --> OIP{"OIP = 0 ?"}
  OIP -->|N| PageLoad
  OIP -->|Y| ProgramExecute["Program Execute"]
  ProgramExecute --> Done["Done"]
```
</details>

Figure 9-5. Program Execute Background Timing  
![](images/58ae5c4adb2ba5406689db21c0730acd47b49e05982433f44acabd1fbf1353e2.jpg)

<details>
<summary>text_image</summary>

CS#
SCLK
SI
02H
22 23
Command
Dummy<3:0>,A11-A0
Data 0
Data N
SO
High-Z
CS#
SCLK
SI
10H
23 22
30 31 32 33 38 39
Command
24-bit address
Page addr M
Command
tCBSYW
Command
15H
02H
SO
High-Z
CS#
SCLK
SI
8 9
22 23
Dummy<3:0>,A11-A0
Data 0
Data N
Wait OIP Ready
0 1 4 5 6
24-bit address
Page addr N
tPROG
SO
High-Z
CS#
SCLK
SI
10H
23 22
30 31
Command
1 0
1 0
SO
High-Z
</details>

## 9.6 Internal Data Move

The INTERNAL DATA MOVE command sequence programs or replaces data in a page with existing data. The INTERNAL DATA MOVE command sequence is as follows:

• 13H (PAGE READ to cache)  
• Optional 84H/C4H/34H (PROGRAM LOAD RANDOM DATA)  
• 06H (WRITE ENABLE)  
• 10H (PROGRAM EXECUTE)  
• 0FH (GET FEATURE command to read the status)

Prior to performing an internal data move operation, the target page content must be read out into the cache register by issuing a PAGE READ (13H) command. The PROGRAM LOAD RANDOM DATA (84H/C4H) command can be issued, if user wants to update bytes of data in the page. New data is loaded in the 12-bit column address. If the random data is not sequential, another PROGRAM LOAD RANDOM DATA (84H/C4H) command must be issued with the new column address. After the data is loaded, the WRITE ENABLE command must be issued, and then PROGRAMEXECUTE (10H) command can be issued to start the programming operation. Only the block with the same parity attribute can use the command.

## 9.7 Program Load Random Data (84H)

The Program Load Random Data command programs or replaces data in a page with existing data. This command consists of an 8-bit Op code, followed by 4 dummy bits, and a 12-bit column address. New data is loaded in the column address provided with the 12 bits. If the random data is not sequential, then another PROGRAM LOAD RANDOM DATA (84H) command must be issued with a new column address, see Figure 9-6 for details.

Figure 9-6. Program Load Random Data Timing Diagram  
![](images/3a5cd052e863303d1a72acb4cfc8001882b3bba1c697960e9933f0d3ced6b269.jpg)

<details>
<summary>text_image</summary>

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 22 23
SCLK
Command Dummy<3:0> A11 - A0
SI 84H 0 0 0 0 1 1 10 3 2 1 0
CS#
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Data byte 0 Data byte 1 Data byte N
SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
MSB
</details>

## 9.8 Program Load Random Data x4 (C4H/34H)

The Program Load Random Data x4 command (C4H/34H) is similar to the Program Load Random Data command (84H) but with the capability to input the data bytes by four pins: SIO0, SIO1, SIO2, and SIO3. The command sequence is shown below. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable for the program load random data x4 command. See Figure 9-7 for details.

Figure 9-7. Program Load Random Data x4 Timing Diagram  
![](images/d2689b1999b01197d306d53971378631bbe3472f017cbb2affe7c340e362d484.jpg)

<details>
<summary>text_image</summary>

CS#
SCLK
Command Dummy<3:0> A11 - A0 Byte 0 Byte 1
SI(SIO0) C4H/34H 0 0 0 0 11 1 0 4 0 4 0 4 0 4 0
SO(SIO1)
WP#(SIO2)
HOLD#(SIO3)
CS#
SCLK
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SI(SIO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0
SO(SIO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1
WP#(SIO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2
HOLD#(SIO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3
</details>

## 10ERASE OPERATIONS

## 10.1 Block Erase (D8H)

The BLOCK ERASE (D8H) command is used to erase at the block level. The BLOCK ERASE command (D8H) operates on one block at a time. The command sequence for the BLOCK ERASE operation is as follows:

• 06H (WRITE ENBALE command)  
• D8H (BLOCK ERASE command)  
• 0FH (GET FEATURES command to read the status register)

Prior to performing the BLOCK ERASE operation, the WRITE ENABLE (06H) command must be issued. As with any command that changes the memory contents, the WRITE ENABLE command must be executed in order to set the WEL bit. If the WRITE ENABLE command is not issued, then the rest of the erase sequence is ignored. The WRITE ENABLE command must be followed by the BLOCK ERASE (D8H) command. This command requires a 24-bit address. After the row address is registered, the control logic automatically controls timing and erase-verify operations. The device is busy for tBERS time during the BLOCK ERASE operation. The GET FEATURES (0FH) command can be used to monitor the status of the operation.

Figure10-1. Block Erase Timing Diagram  
![](images/f921480c0cb742615c5a7244738d62e37798d90a0da0dbed5107f7f047e9df06.jpg)

## 11 RESET OPERATIONS

## 11.1 Soft Reset (FFH)

The RESET (FFH) command stops all operations and the status. For example, in case of a program or erase or read operation, the reset command can make the device enter the idle state.

During a cache program or cache read, a reset can also stops the previous operation and the pending operation.

Figure11-1. Reset Timing Diagram  
![](images/15f15746a12a6271d2735432e42186d37c619e700e811c711153eda6a69acecc.jpg)

<details>
<summary>text_image</summary>

CS#
SCLK
SI
FFH
SO
High-Z
CS#
0 1 2 3 4 5 6 7
SLK
tCS
get feature
Status register address
SI
0FH
7 6 5 4 3 2 1 0
SO
High-Z
MSB
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCLK
SI
Status register data out
Status register data out
SO
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
MSB
MSB
</details>

Note: The Register bit value after soft reset refers to Table 12-2. Register bit Descriptions.

## 11.2 Enable Power on Reset (66H) and Power on Reset (99H)

If the Power on Reset command is accepted, any on-going internal operation will be terminated and the device will return to its default power-on state and lose all the current feature settings.

The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in SPI mode. The “Reset (99H)” command sequence as follow: CS# goes low -> Sending Enable Reset command ->CS# goes high ->CS# goes low.->Sending Reset command ->CS# goes high. Once the Reset command is accepted by the device, the device will take approximately tVSL to reset. During this period, no command will be accepted. It is recommended to check the OIP bit in Status Register before issuing any other command sequence. The contents of the memory location being programmed or the block being erased are no longer valid.

Figure11-2. Reset Timing Diagram  
![](images/b5cf335087123fa59f61f0fcb0621602888481ae28eab8e186d1d981f87357aa.jpg)

<details>
<summary>text_image</summary>

CS#
0 1 2 3 4 5 6 7
SCLK
Command
SI
66H
Command
99H
SO
High-Z
High-Z
</details>

## 12FEATURE OPERATIONS

## 12.1 Get Features (0FH) and Set Features (1FH)

The GET FEATURES (0FH) and SET FEATURES (1FH) commands are used to monitor the device status and alter the device behavior. These commands use a 1-byte feature address to determine which feature is to be read or modified. Feature such as OTP can be enabled or disabled by setting specific feature bits (shown in the below table).The status registers (C0H/F0H) is mostly read, except WEL, which is a writable bit with the WRITE ENABLE (06H) command.

When a feature (A0H/B0H/D0H) is set, it remains active until the device is power cycled or the feature is written to. Unless otherwise specified in the following table, once the device is set, it remains set, even if a RESET (FFH) command is issued.

Table 12-1. Features Settings

<table><tr><td>Register</td><td>Addr.</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr><tr><td>Protection</td><td>A0H</td><td>BRWD</td><td>Reserved</td><td>BP2</td><td>BP1</td><td>BP0</td><td>INV</td><td>CMP</td><td>Reserved</td></tr><tr><td>Feature</td><td>B0H</td><td>OTP_PRT</td><td>OTP_EN</td><td>Reserved</td><td>ECC_EN</td><td>Reserved</td><td>Reserved</td><td>Reserved</td><td>QE</td></tr><tr><td>Status</td><td>C0H</td><td>Reserved</td><td>Reserved</td><td>ECCS1</td><td>ECCS0</td><td>P_FAIL</td><td>E_FAIL</td><td>WEL</td><td>OIP</td></tr><tr><td>Feature</td><td>D0H</td><td>Reserved</td><td>DS_IO[1]</td><td>DS_IO[0]</td><td>Reserved</td><td>Reserved</td><td>Reserved</td><td>Reserved</td><td>Reserved</td></tr><tr><td>Status</td><td>F0H</td><td>Reserved</td><td>Reserved</td><td>ECCSE1</td><td>ECCSE0</td><td>BPS</td><td>Reserved</td><td>Reserved</td><td>CBSY</td></tr></table>

Note: 1. If BRWD is enabled and WP# is LOW, then the block lock register cannot be changed.  
2. If QE is enabled, the quad IO operations can be executed.  
3. All the reserved bits must be held low when the feature is set.  
4. These registers A0H/B0H/D0H are write/read type, and Registers C0H/F0H are read only.  
5. The OTP\_PRT is non-volatile, others bits are volatile.  
6. The Register Bit default value after power-up refers to Table 12-2. Register Bit Descriptions.

Table 12-2. Register Bit Descriptions

<table><tr><td>Bit</td><td>Bit Name</td><td>After Power up or Power on Reset(66H-99H)</td><td>After Reset command (FFH)</td><td>Description</td></tr><tr><td>BRWD</td><td>Block register write disable</td><td>0</td><td>No Change</td><td>Which is used combined with WP#, If BRWD is high enabled and WP# is LOW, then the Protection register cannot be changed</td></tr><tr><td>BP2</td><td rowspan="2">Block</td><td>1</td><td rowspan="5">No Change</td><td rowspan="5">Used combination, refer to chapter Block Protection</td></tr><tr><td>BP1</td><td>1</td></tr><tr><td>BP0</td><td>Protection</td><td>1</td></tr><tr><td>INV</td><td rowspan="2">bits</td><td>0</td></tr><tr><td>CMP</td><td>0</td></tr><tr><td>OTP_PRT</td><td>OTP</td><td>0</td><td rowspan="3">No Change</td><td rowspan="3">Used combination, refer to chapter OTP Region</td></tr><tr><td rowspan="2">OTP_EN</td><td>Region</td><td>0</td></tr><tr><td>bits</td><td>Before OTP Set</td></tr><tr><td rowspan="3">ECC_EN</td><td>ECC</td><td rowspan="3">1</td><td rowspan="3">No Change</td><td rowspan="3">The device offers data corruption protection by offering optional internal ECC. READs and PROGRAMs with internal ECC can be enabled or disabled by setting feature bit ECC_EN. ECC is enabled by default when device powered on, so the default READ and PROGRAM commands operate with internal ECC in the “active” state when ECC enable.</td></tr><tr><td>Enable</td></tr><tr><td>Latch</td></tr><tr><td rowspan="2">QE</td><td>The Quad</td><td rowspan="2">0</td><td rowspan="2">No Change</td><td rowspan="2">This bit indicates that whether the quad IO operations can be executed. If QE is set to 1, the quad IO operations can be executed.</td></tr><tr><td>Enable bit</td></tr><tr><td>ECCS0</td><td rowspan="4">ECC Status</td><td rowspan="4">Page 0 Status</td><td>0</td><td rowspan="4">ECCS provides ECC status as the following table. ECCS and ECCSE are set to 00b either following a RESET, or at the beginning of the READ. They are then updated after the device completes a valid READ operation. ECCS and ECCSE are invalid if internal ECC is disabled (via a SET FEATURES command to reset ECC_EN to 0). After power-on RESET, ECC status is set to reflect the contents of block 0, page 0.</td></tr><tr><td>ECCS1</td><td>0</td></tr><tr><td>ECCSE0</td><td>0</td></tr><tr><td>ECCSE1</td><td>0</td></tr><tr><td>P_FAIL</td><td>Program Fail</td><td>0</td><td>0</td><td>This bit indicates that a program failure has occurred (P_FAIL =1). It will also be set if the user attempts to program a protected region, including the OTP area. This bit is cleared during the PROGRAM EXECUTE command sequence or a RESET command (P_FAIL = 0).</td></tr><tr><td>E_FAIL</td><td>Erase Fail</td><td>0</td><td>0</td><td>This bit indicates that an erase failure has occurred (E_FAIL = 1). It will also be set if the user attempts to erase a locked region. This bit is cleared (E_FAIL = 0) at the start of the BLOCK ERASE command sequence or the RESET command.</td></tr><tr><td>WEL</td><td>Write Enable Latch</td><td>0</td><td>0</td><td>This bit indicates the current status of the write enable latch (WEL) and must be set (WEL = 1), prior to issuing a PROGRAM EXECUTE or BLOCK ERASE command. It is set by issuing the WRITE ENABLE command. WEL can also be disabled (WEL = 0), by issuing the WRITE DISABLE command.</td></tr><tr><td>OIP</td><td>Operation In Progress</td><td>0</td><td>0</td><td>This bit is set (OIP = 1) when a PROGRAM EXECUTE, PAGE READ, BLOCK ERASE, or RESET command is executing, indicating the device is busy. When the bit is 0, the interface is in the ready state.</td></tr><tr><td>DS_IO[0] DS_IO[1]</td><td>Driven Strength register</td><td>00</td><td>No Change</td><td>IO driver strength setting. Default is 00b.</td></tr><tr><td>BPS</td><td>Block Protection Status</td><td>1</td><td>No Change</td><td>Block protection statusBPS is 1, selected block is protectedBPS is 0, selected block is unprotected.</td></tr><tr><td>CBSY</td><td>Cache Busy status bit</td><td>0</td><td>0</td><td>CBSY is to indicate whether cache is busy, non-available for data read or data load. This bit is the status, which indicates if the cache is busy or ready, 1 is busy, 0 is ready.</td></tr></table>

Figure12-1. Get Features Timing Diagram  
![](images/755b7da828ecf51f8b7bb32f3e782c4fe37dd23584f907ad1032a5bba08b0251.jpg)

<details>
<summary>text_image</summary>

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
SI
Command
1 byte address
0FH
MSB
Data byte
SO
High-Z
MSB
7 6 5 4 3 2 1 0
MSB
</details>

Figure12-2. Set Features Timing Diagram  
![](images/84a2b2bbda5fd48f94be290045d18e4ed46209ceb284bdc5da7ff6d48b8195a8.jpg)

<details>
<summary>text_image</summary>

CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
SI
Command
1 byte address
Data byte
1FH
MSB
MSB
High-Z
SO
</details>

## 12.2 Status Register and Driver Register

The NAND Flash device has the status registers (C0H/F0H) that software can read during the device operation for operation state query. The status register can be read by issuing the GET FEATURES (0FH) command, followed by the feature address C0H or F0H (see FEATURE OPERATION). The Output Driver Register can be set and read by issuing the SET FEATURE (0FH) and GET FEATURE command followed by the feature address D0H (see FEATURE OPERATION).

Table 12-3.ECC Error Bits Descriptions

<table><tr><td>ECCS1</td><td>ECCS0</td><td>ECCSE1</td><td>ECCSE0</td><td>Description</td></tr><tr><td>0</td><td>0</td><td>x</td><td>x</td><td>No bit errors were detected during the previous read algorithm</td></tr><tr><td>0</td><td>1</td><td>0</td><td>0</td><td>Bit errors(=1) were detected and corrected</td></tr><tr><td>0</td><td>1</td><td>0</td><td>1</td><td>Bit errors (=2) were detected and corrected.</td></tr><tr><td>0</td><td>1</td><td>1</td><td>0</td><td>Bit errors (=3) were detected and corrected.</td></tr><tr><td>0</td><td>1</td><td>1</td><td>1</td><td>Bit errors (=4) were detected and corrected.</td></tr><tr><td>1</td><td>1</td><td>x</td><td>x</td><td>Reserved</td></tr><tr><td>1</td><td>0</td><td>x</td><td>x</td><td>Bit errors greater than ECC capability(4 bits) and not corrected</td></tr></table>

12-4. Driver Register Bits Descriptions

<table><tr><td>DS_IO[1]</td><td>DS_IO[0]</td><td>Driver Strength</td></tr><tr><td>0</td><td>0</td><td>100%</td></tr><tr><td>0</td><td>1</td><td>75%</td></tr><tr><td>1</td><td>0</td><td>50%</td></tr><tr><td>1</td><td>1</td><td>25%</td></tr></table>

## 12.3 OTP Region

The serial device offers a protected, One-Time Programmable NAND Flash memory area. 4 full pages are available on the device. Customers can use the OTP area as they prefer, like programming serial numbers, or other data, for permanent storage. When delivered from factory, feature bit OTP\_PRT is 0. To access the OTP feature, the user must set feature bits OTP\_EN/OTP\_PRT by SET FEATURES command. When the OTP is ready for access, only pages 00h–03H can be programmed in sequential order by PROGRAM LOAD (02H) and PROGRAM EXECUTE (10H) commands (when not yet protected), and read out by PAGE READ (13H) command and output data by READ from CACHE(03H/0BH/3BH/6BH). When ECC is enabled, data written in the OTP area is ECC protected.

Table 12-5.OTP States

<table><tr><td>OTP_PRT</td><td>OTP_EN</td><td>State</td></tr><tr><td>x</td><td>0</td><td>Normal Operation</td></tr><tr><td>0</td><td>1</td><td>Access OTP region, read and program data</td></tr><tr><td>1</td><td>1</td><td>1. When the device power on state OTP_PRT is 0, user can set feature bit OTP_PRT and OTP_EN to 1, then issue PROGRAM EXECUTE (10H) to lock OTP, and after that OTP_PRT will permanently remain 1.2. When the device power on state OTP_PRT is 1, user can only read the OTP region data</td></tr></table>

Note: The OTP space cannot be erased and after it has been protected, it cannot be programmed again, please use this function carefully.

Access to OTP data

• Issue the SET FEATURES command (1FH)  
• Set feature bit OTP\_EN  
• Issue the PAGE PROGRAM (only when OTP\_PRT is 0) or PAGE READ command

Protect OTP region

Only when the following steps are completed, the OTP\_PRT will be set and users can get this feature out with 0FH command.

• Issue the SET FEATURES command (1FH)  
• Set feature bit OTP\_EN and OTP\_PRT  
• 06H (WRITE ENABLE)  
• Issue the PROGRAM EXECUTE (10H) command.

## 12.4 Assistant Bad Block Management

As a NAND Flash, the device may have blocks that are invalid when shipped from the factory, and a minimum number of valid blocks (NVB) of the total available blocks are specified. An invalid block is one that contains at least one page that has more bad bits than can be corrected by the minimum required ECC. Additional bad blocks may develop with use. However, the total number of available blocks will not fall below NVB during the endurance life of the product.

Although NAND Flash memory devices may contain bad blocks, they can be used reliably in systems that provide badblock management and error-correction algorithms, which ensure data integrity. Internal circuitry isolates each block from other blocks, so the presence of a bad block does not affect the operation of the rest of the NAND Flash array.

NAND Flash devices are shipped from the factory erased. The factory identifies invalid blocks before shipping by programming the Bad Block Mark (00h) to the first spare area location in each bad block. This method is compliant with ONFI Factory Defect Mapping requirements. See the following table for the bad-block mark.

System software should initially check the first spare area location for non-FFH data on the first page of each block prior to performing any program or erase operations on the NAND Flash device. A bad-block table can then be created, enabling system software to map around these areas. Factory testing is performed under worst-case conditions. Because invalid blocks may be marginal, it may not be possible to recover the bad-block marking if the block is erased.

To simplify the system requirement and guard the data integration, GigaDevice SPI NAND provides assistant Management options as below.

Table 12-6. Bad Block Mark information (2Gb)

<table><tr><td>Description</td><td>Requirement</td></tr><tr><td>Minimum number of valid blocks (NVB)</td><td>2008</td></tr><tr><td>Total available blocks per die</td><td>2048</td></tr><tr><td>First spare area location</td><td>Byte 2048</td></tr><tr><td>Bad-block mark</td><td>00h(use non FFH to check)</td></tr></table>

## 12.5 Block Protection

The block lock feature provides the ability to protect the entire device, or ranges of blocks, from the PROGRAM and ERASE operations. After power-up, the device is in the “locked” state, i.e., feature bits BP0, BP1and BP2 are set to 1, INV, CMP and BRWD are set to 0. To unlock all the blocks, or a range of blocks, the SET FEATURES command must be issued to alter the state of protection feature bits. When BRWD is set and WP# is LOW, none of the writable protection feature bits can be set. Also, when a PROGRAM/ERASE command is issued to a locked block, status bit OIP remains 0. When an ERASE command is issued to a locked block, the erase failure, status bit E\_FAIL set to 1. When a PROGRAM command is issued to a locked block, program failure, status bit P\_FAIL set to 1.

To enable the Write Protection (WP#), the Quad Enable bit (QE) of feature (B0[0]) must be set to 0.

Table 12-7. Block Lock Register Block Protect Bits (2Gb)

<table><tr><td rowspan="2">CMP</td><td rowspan="2">INV</td><td rowspan="2">BP2</td><td rowspan="2">BP1</td><td rowspan="2">BP0</td><td>Protect Row Address</td><td>Protect Rows</td></tr><tr><td>2Gb</td><td></td></tr><tr><td>x</td><td>x</td><td>0</td><td>0</td><td>0</td><td>NONE</td><td>None—all unlocked</td></tr><tr><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1F800h ~ 1FFFFh</td><td>Upper 1/64 locked</td></tr><tr><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>1F000h ~ 1FFFFh</td><td>Upper 1/32 locked</td></tr><tr><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1E000h ~ 1FFFFh</td><td>Upper 1/16 locked</td></tr><tr><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1C000h ~ 1FFFFh</td><td>Upper 1/8 locked</td></tr><tr><td>0</td><td>0</td><td>1</td><td>0</td><td>1</td><td>18000h ~ 1FFFFh</td><td>Upper 1/4 locked</td></tr><tr><td>0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>10000h ~ 1FFFFh</td><td>Upper 1/2 locked</td></tr><tr><td>x</td><td>x</td><td>1</td><td>1</td><td>1</td><td>0000h ~ 1FFFFh</td><td>All locked (default)</td></tr><tr><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0000h ~7FFh</td><td>Lower 1/64 locked</td></tr><tr><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>0000h ~FFFh</td><td>Lower 1/32 locked</td></tr><tr><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td><td>0000h ~ 1FFFh</td><td>Lower 1/16 locked</td></tr><tr><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0000h ~ 3FFFh</td><td>Lower 1/8 locked</td></tr><tr><td>0</td><td>1</td><td>1</td><td>0</td><td>1</td><td>0000h ~ 7FFFh</td><td>Lower 1/4 locked</td></tr><tr><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0000h ~ FFFFh</td><td>Lower 1/2 locked</td></tr><tr><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0000h ~ 1F7FFh</td><td>Lower 63/64 locked</td></tr><tr><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0000h ~ 1FFFFh</td><td>Lower31/32 locked</td></tr><tr><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>0000h ~ 1DFFFh</td><td>Lower 15/16 locked</td></tr><tr><td>1</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0000h ~ 1BFFFh</td><td>Lower7/8 locked</td></tr><tr><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0000h ~ 17FFFh</td><td>Lower3/4 locked</td></tr><tr><td>1</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0000h ~ 003Fh</td><td>Block0</td></tr><tr><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0800h ~ 1FFFFh</td><td>Upper 63/64 locked</td></tr><tr><td>1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1000h ~ 1FFFFh</td><td>Upper31/32 locked</td></tr><tr><td>1</td><td>1</td><td>0</td><td>1</td><td>1</td><td>2000h ~ 1FFFFh</td><td>Upper 15/16 locked</td></tr><tr><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>4000h ~ 1FFFFh</td><td>Upper7/8 locked</td></tr><tr><td>1</td><td>1</td><td>1</td><td>0</td><td>1</td><td>8000h ~ 1FFFFh</td><td>Upper3/4 locked</td></tr><tr><td>1</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0000h ~ 003Fh</td><td>Block0</td></tr></table>

When WP# is not LOW, user can issue bellows commands to alter the protection states as want.  
• Issue SET FEATURES register write (1FH)  
• Issue the feature bit address (A0h) and the feature bits combination as the table

## 12.6 Internal ECC

The device offers data corruption protection by offering optional internal ECC. READs and PROGRAMs with internal ECC can be enabled or disabled by setting feature bit ECC\_EN. ECC is enabled by default when device powered on, so the default READ and PROGRAM commands operate with internal ECC in the “active” state when ECC enable.

To enable/disable ECC, perform the following command sequence:

• Issue the SET FEATURES command (1FH) to set the feature bit ECC\_EN:

1. To enable ECC, Set ECC\_EN to 1.  
2. To disable ECC, Clear ECC\_EN to 0.

During a PROGRAM operation, the device calculates an ECC code on the 2k page in the cache register, before the page is written to the NAND Flash array.

During a READ operation, the page data is read from the array to the cache register, where the ECC code is calculated and compared with the ECC code value read from the array. If error bits are detected (error bits≤4 bits), the error is corrected in the cache register. Only corrected data is output on the I/O bus. The ECC status bit indicates whether or not the error correction was successful. The ECC Protection table below shows the ECC protection scheme used throughout a page.

The ECC protection format as follow:

• User meta data I is not protected by internal ECC and User meta data II is protected by internal ECC.

Any data wrote to the ECC parity data area are ignored when ECC enabled.

Table 12-8. The Distribution of ECC Segment and Spare Area in a Page

<table><tr><td colspan="4">Main Area(2KB)</td><td colspan="8">Spare Area(128B)</td></tr><tr><td colspan="4">User data</td><td colspan="4">User meta data(I+II)</td><td colspan="4">ECC Parity Data</td></tr><tr><td>Main0</td><td>Main1</td><td>Main2</td><td>Main3</td><td>Spare0</td><td>Spare1</td><td>Spare2</td><td>Spare3</td><td>Spare0</td><td>Spare1</td><td>Spare2</td><td>Spare3</td></tr><tr><td>(512B)</td><td>(512B)</td><td>(512B)</td><td>(512B)</td><td>(4B+12B)</td><td>(4B+12B)</td><td>(4B+12B)</td><td>(4B+12B)</td><td>(16B)</td><td>(16B)</td><td>(16B)</td><td>(16B)</td></tr></table>

Table 12-9. ECC Protection and Spare Area

<table><tr><td>Min Byte Address</td><td>Max Byte Address</td><td>ECC Protected</td><td>Area</td><td>Description</td></tr><tr><td>000H</td><td>1FFH</td><td>Yes</td><td>Main 0</td><td>User data 0</td></tr><tr><td>200H</td><td>3FFH</td><td>Yes</td><td>Main 1</td><td>User data 1</td></tr><tr><td>400H</td><td>5FFH</td><td>Yes</td><td>Main 2</td><td>User data 2</td></tr><tr><td>600H</td><td>7FFH</td><td>Yes</td><td>Main 3</td><td>User data 3</td></tr><tr><td>800H</td><td>803H</td><td>No</td><td>Spare 0</td><td>User meta 0 data I</td></tr><tr><td>804H</td><td>80FH</td><td>Yes</td><td>Spare 0</td><td>User meta 0 data II</td></tr><tr><td>810H</td><td>813H</td><td>No</td><td>Spare 1</td><td>User meta 1 data I</td></tr><tr><td>814H</td><td>81FH</td><td>Yes</td><td>Spare 1</td><td>User meta 1 data II</td></tr><tr><td>820H</td><td>823H</td><td>No</td><td>Spare 2</td><td>User meta 2 data I</td></tr><tr><td>824H</td><td>82FH</td><td>Yes</td><td>Spare 2</td><td>User meta 2 data II</td></tr><tr><td>830H</td><td>833H</td><td>No</td><td>Spare 3</td><td>User meta 3 data I</td></tr><tr><td>834H</td><td>83FH</td><td>Yes</td><td>Spare 3</td><td>User meta 3 data II</td></tr><tr><td>840H</td><td>84FH</td><td>Yes</td><td>Spare 0</td><td>ECC Parity Data</td></tr><tr><td>850H</td><td>85FH</td><td>Yes</td><td>Spare 1</td><td>ECC Parity Data</td></tr><tr><td>860H</td><td>86FH</td><td>Yes</td><td>Spare 2</td><td>ECC Parity Data</td></tr><tr><td>870H</td><td>87FH</td><td>Yes</td><td>Spare 3</td><td>ECC Parity Data</td></tr></table>

## Note

1. 800H is reserved for initial bad block mark.  
2. When Internal ECC is enabled, user cannot program the Address 840H\~87FH, but user can read the Address 840H\~87FH.  
When Internal ECC is disabled, the whole page area is open for user. And we recommend the user to provide external ECC protection.

## 13POWER ON TIMING

Figure13-1. Power on Timing Sequence  
![](images/fc2ca4121a17b855a4c8a71f284d70319d2bc8b9fca9d2b20f302b19c512cd19.jpg)

<details>
<summary>line</summary>

| Metric | Description |
| --- | --- |
| Vcc(max) | Maximum voltage threshold |
| Vcc(min) | Minimum voltage threshold |
| VWI | Minimum voltage threshold |
| tVSL | Time-voltage duration between Vcc(min) and Vcc(max) |
| Device is fully accessible | Accessible device status |
</details>

Table 13-1. Power-On Timing and Write Inhibit Threshold for 1.8V/3.3V

<table><tr><td>Symbol</td><td colspan="2">Parameter</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td>tVSL</td><td colspan="2">VCC(min) To CS# Low</td><td>1</td><td></td><td>ms</td></tr><tr><td rowspan="2">VWI</td><td rowspan="2">Write Inhibit Voltage</td><td>1.8V</td><td rowspan="2"></td><td>1.4</td><td rowspan="2">V</td></tr><tr><td>3.3V</td><td>2.5</td></tr></table>

## 14ABSOLUTE MAXIMUM RATINGS

Table 14-1.Absolute Maximum Ratings

<table><tr><td>Parameter</td><td>Value</td><td>Unit</td></tr><tr><td>Ambient Operating Temperature</td><td>-40 to 105</td><td>°C</td></tr><tr><td>Storage Temperature</td><td>-65 to 150</td><td>°C</td></tr><tr><td>Applied Input / Output Voltage</td><td>-0.6 to VCC+0.4</td><td>V</td></tr><tr><td>VCC(3.3V)</td><td>-0.6 to 4.0</td><td>V</td></tr><tr><td>VCC(1.8V)</td><td>-0.6 to 2.5</td><td>V</td></tr></table>

Figure14-1. Input Test Waveform and Measurement Level

Maximum Negative Overshoot Waveform  
![](images/5ab9164ef39545ab8995032a9593308a8e83278273c448fa9d38eccfff56b99c.jpg)

<details>
<summary>text_image</summary>

Vss
20ns
20ns
Vss-2.0V
20ns
</details>

Maximum Positive Overshoot Waveform  
![](images/36919d0fe4bdd81447f6d77ddf3e347ad916ab43a2f5d3ba7c47afd64a7e6893.jpg)

<details>
<summary>text_image</summary>

Vcc + 2.0V
20ns
20ns
20ns
</details>

## 15CAPACITANCE MEASUREMENT CONDITIONS

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td><td>Conditions</td></tr><tr><td>CIN</td><td>Input Capacitance</td><td></td><td></td><td>6</td><td>pF</td><td>VIN=0V</td></tr><tr><td>COUT</td><td>Output Capacitance</td><td></td><td></td><td>8</td><td>pF</td><td>VOUT=0V</td></tr><tr><td>CL</td><td>Load Capacitance</td><td colspan="3">30</td><td>pF</td><td></td></tr><tr><td></td><td>Input Rise And Fall time</td><td></td><td></td><td>5</td><td>ns</td><td></td></tr><tr><td></td><td>Input Pulse Voltage</td><td colspan="3">0.1VCC to 0.8VCC</td><td>V</td><td></td></tr><tr><td></td><td>Input Timing Reference Voltage</td><td colspan="3">0.2VCC to 0.7VCC</td><td>V</td><td></td></tr><tr><td></td><td>Output Timing Reference Voltage</td><td colspan="3">0.5VCC</td><td>V</td><td></td></tr></table>

Figure15-1. Input Test Waveform and Measurement Level  
![](images/e9b06380ede32fb2048221570af522de84505438d4d429602d78b8d5248f9ea0.jpg)

<details>
<summary>text_image</summary>

0.8VCC
0.7VCC
0.2VCC
0.1VCC
AC Measurement Level
Output timing reference level
0.5VCC
</details>

Note: Input pulse rise and fall time are<5ns

## 16DC CHARACTERISTIC

(T= -40℃\~85℃/-40℃\~105℃, VCC=2.7\~3.6V)

<table><tr><td>Symbol</td><td>Parameter</td><td>Test Condition</td><td>Min.</td><td>Typ.</td><td>Max.</td><td>Unit.</td></tr><tr><td> $I_{LI}$ </td><td>Input Leakage Current</td><td></td><td></td><td></td><td>±2</td><td>μA</td></tr><tr><td> $I_{LO}$ </td><td>Output Leakage Current</td><td></td><td></td><td></td><td>±2</td><td>μA</td></tr><tr><td> $I_{CC1}$ </td><td>Standby Current</td><td>CS#=VCC, $V_{IN}$ =VCC or VSS</td><td></td><td></td><td>50</td><td>μA</td></tr><tr><td> $I_{CC2}$ </td><td>Operating Current (Read)</td><td>CLK=0.1VCC / 0.9VCCat 104MHz,Q=Open(*1,*2,*4 I/O)</td><td></td><td></td><td>30</td><td>mA</td></tr><tr><td> $I_{CC3}$ </td><td>Operating Current (Program)</td><td></td><td></td><td></td><td>30</td><td>mA</td></tr><tr><td> $I_{CC4}$ </td><td>Operating Current (Erase)</td><td></td><td></td><td></td><td>30</td><td>mA</td></tr><tr><td> $V_{IL}$ </td><td>Input Low Voltage</td><td></td><td>-0.5</td><td></td><td>0.2VCC</td><td>V</td></tr><tr><td> $V_{IH}$ </td><td>Input High Voltage</td><td></td><td>0.8VCC</td><td></td><td>VCC+0.4</td><td>V</td></tr><tr><td> $V_{OL}$ </td><td>Output Low Voltage</td><td> $I_{OL}$ =1.6mA</td><td></td><td></td><td>0.4</td><td>V</td></tr><tr><td> $V_{OH}$ </td><td>Output High Voltage</td><td> $I_{OH}$ =-100μA</td><td>VCC-0.2</td><td></td><td></td><td>V</td></tr></table>

(T= -40℃\~85℃/-40℃\~105℃, VCC=1.7\~2.0V)

<table><tr><td>Symbol</td><td>Parameter</td><td>Test Condition</td><td>Min.</td><td>Typ.</td><td>Max.</td><td>Unit.</td></tr><tr><td> $I_{LI}$ </td><td>Input Leakage Current</td><td></td><td></td><td></td><td>±2</td><td>μA</td></tr><tr><td> $I_{LO}$ </td><td>Output Leakage Current</td><td></td><td></td><td></td><td>±2</td><td>μA</td></tr><tr><td> $I_{CC1}$ </td><td>Standby Current</td><td>CS#=VCC, $V_{IN}$ =VCC or VSS</td><td></td><td></td><td>50</td><td>μA</td></tr><tr><td> $I_{CC2}$ </td><td>Operating Current (Read)</td><td>CLK=0.1VCC / 0.9VCCat 80MHz,Q=Open(*1,*2,*4 I/O)</td><td></td><td></td><td>30</td><td>mA</td></tr><tr><td> $I_{CC3}$ </td><td>Operating Current (Program)</td><td></td><td></td><td></td><td>30</td><td>mA</td></tr><tr><td> $I_{CC4}$ </td><td>Operating Current (Erase)</td><td></td><td></td><td></td><td>30</td><td>mA</td></tr><tr><td> $V_{IL}$ </td><td>Input Low Voltage</td><td></td><td>-0.5</td><td></td><td>0.2VCC</td><td>V</td></tr><tr><td> $V_{IH}$ </td><td>Input High Voltage</td><td></td><td>0.8VCC</td><td></td><td>VCC+0.4</td><td>V</td></tr><tr><td> $V_{OL}$ </td><td>Output Low Voltage</td><td> $I_{OL}$ =1.6mA</td><td></td><td></td><td>0.4</td><td>V</td></tr><tr><td> $V_{OH}$ </td><td>Output High Voltage</td><td> $I_{OH}$ =-100μA</td><td>VCC-0.2</td><td></td><td></td><td>V</td></tr></table>

Note: Value guaranteed by design and/or characterization, not 100% tested in production

## 17AC CHARACTERISTICS

(T= -40℃\~85℃/-40℃\~105℃, VCC=1.7\~2.0V/2.7\~3.6V, CL=30pF)

<table><tr><td rowspan="2">Symbol</td><td rowspan="2">Parameter</td><td colspan="2">1.8V</td><td colspan="2">3.3V</td><td rowspan="2">Unit.</td></tr><tr><td>Min.</td><td>Max.</td><td>Min.</td><td>Max.</td></tr><tr><td>FC1</td><td>Serial Clock Frequency</td><td></td><td>80</td><td></td><td>104</td><td>MHz</td></tr><tr><td>FC2*</td><td>Serial Clock Frequency for DTR</td><td></td><td>45</td><td></td><td>45</td><td>MHZ</td></tr><tr><td>tCH</td><td>Serial Clock High Time</td><td>4</td><td></td><td>4</td><td></td><td>ns</td></tr><tr><td>tCL</td><td>Serial Clock Low Time</td><td>4</td><td></td><td>4</td><td></td><td>ns</td></tr><tr><td>tCLCH</td><td>Serial Clock Rise Time (Slew Rate)</td><td>0.2</td><td></td><td>0.2</td><td></td><td>V/ns</td></tr><tr><td>tCHCL</td><td>Serial Clock Fall Time (Slew Rate)</td><td>0.2</td><td></td><td>0.2</td><td></td><td>V/ns</td></tr><tr><td>tCHSH</td><td>CS# Active Hold Time</td><td>5</td><td></td><td>5</td><td></td><td>ns</td></tr><tr><td>tSHCH</td><td>CS# Not Active Setup Time</td><td>5</td><td></td><td>5</td><td></td><td>ns</td></tr><tr><td>tSLCH</td><td>CS# Active Setup Time</td><td>7</td><td></td><td>5</td><td></td><td>ns</td></tr><tr><td>tCHSL</td><td>CS# Not Active Hold Time</td><td>5</td><td></td><td>5</td><td></td><td>ns</td></tr><tr><td>tSHSL/tCS</td><td>CS# High Time</td><td>20</td><td></td><td>20</td><td></td><td>ns</td></tr><tr><td>tSHQZ</td><td>Output Disable Time</td><td></td><td>20</td><td></td><td>20</td><td>ns</td></tr><tr><td>tCLQX</td><td>Output Hold Time</td><td>2</td><td></td><td>2</td><td></td><td>ns</td></tr><tr><td>tDVCH</td><td>Data In Setup Time</td><td>2</td><td></td><td>2</td><td></td><td>ns</td></tr><tr><td>tCHDX</td><td>Data In Hold Time</td><td>2</td><td></td><td>2</td><td></td><td>ns</td></tr><tr><td>tHLCH</td><td>Hold# Low Setup Time (relative to Clock)</td><td>5</td><td></td><td>5</td><td></td><td>ns</td></tr><tr><td>tHHCH</td><td>Hold# High Setup Time (relative to Clock)</td><td>5</td><td></td><td>5</td><td></td><td>ns</td></tr><tr><td>tCHHL</td><td>Hold# High Hold Time (relative to Clock)</td><td>5</td><td></td><td>5</td><td></td><td>ns</td></tr><tr><td>tCHHH</td><td>Hold# Low Hold Time (relative to Clock)</td><td>5</td><td></td><td>5</td><td></td><td>ns</td></tr><tr><td>tHLQZ</td><td>Hold# Low To High-Z Output</td><td></td><td>15</td><td></td><td>15</td><td>ns</td></tr><tr><td>tHHQX</td><td>Hold# High To Low-Z Output</td><td></td><td>15</td><td></td><td>15</td><td>ns</td></tr><tr><td>tCLQV</td><td>Clock Low To Output Valid</td><td></td><td>11</td><td></td><td>9</td><td>ns</td></tr><tr><td>tWHSL</td><td>WP# Setup Time Before CS# Low</td><td>20</td><td></td><td>20</td><td></td><td>ns</td></tr><tr><td>tSHWL</td><td>WP# Hold Time After CS# High</td><td>100</td><td></td><td>100</td><td></td><td>ns</td></tr></table>

## Note:

1. Value guaranteed by design and/or characterization, not 100% tested in production  
2. Please contact GigaDevice when there is a need to use the EEh command for DTR.

The max clock rate for DTR depends on the tCLQV (clock to data output valid). Per datasheet, with output load capacitance of 30pf, the tCLQV is about 11ns. This will limit the max rate to 45Mhz.

However, in general, most of PCB designs have output loading much less than 30pf. Lower output loading will in turn shorten the tCLQV and result in higher max clock rate.

GigaDevice recommend customers measure the tCLQV and then set the clock rate to match the SPI host data sampling data setup time and hold time.

## 18PERFORMANCE AND TIMING

<table><tr><td>Symbol</td><td>Parameter</td><td>Min.</td><td>Typ.</td><td>Max.</td><td>Unit.</td></tr><tr><td>tRST</td><td>CS# High To Next Command After Reset(FFh)</td><td></td><td></td><td>500</td><td>us</td></tr><tr><td>tRD</td><td>Read From Array</td><td></td><td></td><td>25</td><td>us</td></tr><tr><td>tRD_ECC</td><td>Read From Array with ECC</td><td></td><td>45</td><td>60</td><td>us</td></tr><tr><td>tPROG</td><td>Page Programming Time</td><td></td><td>300</td><td>600</td><td>us</td></tr><tr><td>tPROG_ECC</td><td>Page Programming Time with ECC</td><td></td><td>400</td><td>600</td><td>us</td></tr><tr><td>tBERS</td><td>Block Erase Time</td><td></td><td>3</td><td>5</td><td>ms</td></tr><tr><td>tCBSYW</td><td>Cache busy time for Cache Program</td><td></td><td>5</td><td>tPROG</td><td>us</td></tr><tr><td>tCBSYW_ECC</td><td>Cache busy time for Cache Program with ECC</td><td></td><td>30</td><td>tPROG_ECC</td><td>us</td></tr><tr><td>tCBSYR</td><td>Cache busy time for Cache Read</td><td></td><td>5</td><td>tRD</td><td>us</td></tr><tr><td>tCBSYR_ECC</td><td>Cache busy time for Cache Read with ECC</td><td></td><td>30</td><td>tRD_ECC</td><td>us</td></tr></table>

Figure18-1. Serial Input Timing  
![](images/881b2dfbbbb8230fb7af423e755404286621abc6443eff5afc5c06cc0c664d47.jpg)

<details>
<summary>text_image</summary>

CS#
tCHSL
tSLCH
SCLK
tDVCH
tCHDX
SI
MSB
LSB
SO
High-Z
tCHSH
tCLCH
tSHCL
tSHSL
</details>

Figure18-2. Output Timing  
![](images/862fdcc50b0a0a0903dfcef387b75249359e0361a7d63a958d4a67596c973807.jpg)

<details>
<summary>text_image</summary>

CS#
SCLK
tCLQV
tCLQX
tCLQV
tCLQX
SO
LSB
tCH
tCL
tSHQZ
SI
Least significant address bit (LIB) in
</details>

Figure18-3. Hold Timing  
![](images/6e6e3f492d6a3bcaf451ad36a791b73d3bd48ab15ff9722b61aa57f64c01c4d3.jpg)

<details>
<summary>text_image</summary>

CS#
SCLK
tCHHL
tHLCH
tHHCH
SO
tHLQZ
tCHHH
tHHQX
HOLD#
</details>

Sl do not care during HOLD operation.

## 19ORDERING INFORMATION

![](images/35356c13b1070de72632d77901f1c5c94ab8bdcb460e745577a05a11ca95ea6b.jpg)  
Note: (1) Industrial+: F grade has implemented additional test flows to ensure higher product quality than I grade.

## 20 PACKAGE INFORMATION

Figure 20-1.WSON8 (8\*6mm)  
![](images/d72dc2e6eb040b370a50a8b5b5b57cf54cc5974bd404967d05fd4adf0cfe3562.jpg)  
Bottom View

![](images/74a98a721fb00f3476cd1d40fc6b762a4fce0c57c2885119aa8012aef7a70f84.jpg)

<details>
<summary>text_image</summary>

C
A1
A
</details>

Side View

Dimensions

<table><tr><td colspan="2">Symbol</td><td rowspan="2">A</td><td rowspan="2">A1</td><td rowspan="2">c</td><td rowspan="2">b</td><td rowspan="2">D</td><td rowspan="2">D2</td><td rowspan="2">E</td><td rowspan="2">E2</td><td rowspan="2">e</td><td rowspan="2">L</td></tr><tr><td colspan="2">Unit</td></tr><tr><td rowspan="3">mm</td><td>Min</td><td>0.70</td><td>0.00</td><td>0.180</td><td>0.35</td><td>7.90</td><td>3.30</td><td>5.90</td><td>4.20</td><td rowspan="3">1.27</td><td>0.45</td></tr><tr><td>Nom</td><td>0.75</td><td>0.02</td><td>0.203</td><td>0.40</td><td>8.00</td><td>3.40</td><td>6.00</td><td>4.30</td><td>0.50</td></tr><tr><td>Max</td><td>0.80</td><td>0.05</td><td>0.250</td><td>0.45</td><td>8.10</td><td>3.50</td><td>6.10</td><td>4.40</td><td>0.55</td></tr><tr><td rowspan="3">Inch</td><td>Min</td><td>0.028</td><td>0</td><td>0.007</td><td>0.014</td><td>0.311</td><td>0.130</td><td>0.232</td><td>0.165</td><td rowspan="3">0.05</td><td>0.018</td></tr><tr><td>Nom</td><td>0.030</td><td>0.001</td><td>0.008</td><td>0.016</td><td>0.315</td><td>0.134</td><td>0.236</td><td>0.169</td><td>0.020</td></tr><tr><td>Max</td><td>0.032</td><td>0.002</td><td>0.010</td><td>0.018</td><td>0.319</td><td>0.138</td><td>0.240</td><td>0.173</td><td>0.022</td></tr></table>

Figure 20-2.TFBGA-24BALL (5\*5-1 ball array)  
![](images/309918a65f99632a28c75a9aeae076c813083d9dfa76271cea0dd3611eea32b9.jpg)  
Dimensions

<table><tr><td colspan="2">Symbol</td><td rowspan="2">A</td><td rowspan="2">A1</td><td rowspan="2">A2</td><td rowspan="2">b</td><td rowspan="2">D</td><td rowspan="2">D1</td><td rowspan="2">E</td><td rowspan="2">E1</td><td rowspan="2">e</td><td rowspan="2">SE</td><td rowspan="2">SD</td></tr><tr><td colspan="2">Unit</td></tr><tr><td rowspan="3">mm</td><td>Min</td><td></td><td>0.25</td><td>0.75</td><td>0.35</td><td>5.90</td><td rowspan="3">4.00 BSC</td><td>7.90</td><td rowspan="3">4.00 BSC</td><td rowspan="3">1.00 BSC</td><td rowspan="3">1.00 TYP</td><td rowspan="3">1.00 TYP</td></tr><tr><td>Nom</td><td></td><td>0.30</td><td>0.80</td><td>0.40</td><td>6.00</td><td>8.00</td></tr><tr><td>Max</td><td>1.20</td><td>0.35</td><td>0.85</td><td>0.45</td><td>6.10</td><td>8.10</td></tr><tr><td rowspan="3">Inch</td><td>Min</td><td></td><td>0.010</td><td>0.030</td><td>0.014</td><td>0.232</td><td rowspan="3">0.157 BSC</td><td>0.311</td><td rowspan="3">0.157 BSC</td><td rowspan="3">0.039 BSC</td><td rowspan="3">0.039 TYP</td><td rowspan="3">0.039 TYP</td></tr><tr><td>Nom</td><td></td><td>0.012</td><td>0.031</td><td>0.016</td><td>0.236</td><td>0.315</td></tr><tr><td>Max</td><td>0.047</td><td>0.014</td><td>0.033</td><td>0.018</td><td>0.240</td><td>0.319</td></tr></table>

Note：Both package length and width do not include mold flash.

Figure20-3. TFBGA-24BALL (4\*6 ball array)  
![](images/08d3fc107d74ce1b70a342f0d55cddefae442ab529e89cfab2eef1f18c12f9d6.jpg)

Dimensions

<table><tr><td colspan="2">Symbol</td><td rowspan="2">A</td><td rowspan="2">A1</td><td rowspan="2">A2</td><td rowspan="2">b</td><td rowspan="2">D</td><td rowspan="2">D1</td><td rowspan="2">E</td><td rowspan="2">E1</td><td rowspan="2">e</td><td rowspan="2">SE</td><td rowspan="2">SD</td></tr><tr><td colspan="2">Unit</td></tr><tr><td rowspan="3">mm</td><td>Min</td><td></td><td>0.25</td><td>0.70</td><td>0.35</td><td>5.90</td><td rowspan="3">3.00 BSC</td><td>7.90</td><td rowspan="3">5.00 BSC</td><td rowspan="3">1.00 BSC</td><td rowspan="3">0.50 TYP</td><td rowspan="3">0.50 TYP</td></tr><tr><td>Nom</td><td></td><td>0.30</td><td>0.80</td><td>0.40</td><td>6.00</td><td>8.00</td></tr><tr><td>Max</td><td>1.20</td><td>0.35</td><td>0.85</td><td>0.45</td><td>6.10</td><td>8.10</td></tr><tr><td rowspan="3">Inch</td><td>Min</td><td></td><td>0.010</td><td>0.028</td><td>0.014</td><td>0.232</td><td rowspan="3">0.118 BSC</td><td>0.311</td><td rowspan="3">0.197 BSC</td><td rowspan="3">0.039 BSC</td><td rowspan="3">0.020 TYP</td><td rowspan="3">0.020 TYP</td></tr><tr><td>Nom</td><td></td><td>0.012</td><td>0.031</td><td>0.016</td><td>0.236</td><td>0.315</td></tr><tr><td>Max</td><td>0.047</td><td>0.014</td><td>0.034</td><td>0.018</td><td>0.240</td><td>0.319</td></tr></table>

Note: Both the package length and width do not include the mold flash.

21 REVISION HISTORY

<table><tr><td>Version No</td><td>Description</td><td>Page Number</td><td>Date</td></tr><tr><td>1.0</td><td>Initial Release</td><td></td><td>2019-08-01</td></tr><tr><td>1.1</td><td>Modify the 03H command description in Figure 8-6.Page Read to Cache Timing Diagram.Add Note in Figure 8-6 Page Read to Cache Timing Diagram about Read From Cache command.Modify the “P_FAIL” “E_FAIL” default value after power up from ‘Page 0’ to ‘0’.</td><td>252551</td><td>2019-08-13</td></tr><tr><td>1.2</td><td>Add Note of EEH DTR command in 8.9 &amp; 17 AC Characteristics..Modify the descriptions of Industrial+ F grade in Ordering information.Modify the descriptions of FFH command.Add the Register bit value after reset command (FFH).Move Table 12.2 Register bit description to 12.1Modify the Figure 3-1 Array Organization.</td><td>29/617/6416/4649/504910</td><td>2019-08-27</td></tr><tr><td>1.3</td><td>Add tCBSYR_ECC and tCBSYW_ECC in 18 Performance and Timing.</td><td>62</td><td>2019-09-11</td></tr><tr><td>1.4</td><td>Update the tSLCH Value from 5ns to 7ns for 1.8V.Update the tVSL Value from 5ms to 1ms.Update the VWI Value from 1.7V to 1.4V.</td><td>615757</td><td>2019-11-15</td></tr><tr><td>1.5</td><td>Update the tRD_ECC Max Value from 50us to 60usAdd Industrial 105° productModify the Storage Temperature to -65°C~150°CUpdate the 8.12 Parameter Page Table Byte137/138 and recalculate the CRC Byte 254/255</td><td>6275835/36</td><td>2020-03-09</td></tr><tr><td>1.6</td><td>Add the description of the OTP Area ECC protected.Modify the description of the initial Bad Block Mark with internal ECC on.Remove the description of the 84h/C4h/34h must be use in internal data move.Modify the error description “Program an invalid address will cause P_Fail”</td><td>525616/43/4451</td><td>2021-11-13</td></tr></table>

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