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同步CubeMX 6.18重生成的HAL/CMSIS/FreeRTOS vendor与工程配置(.ioc/.uvprojx/.mxproject及生成Src/Inc)基线

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This commit is contained in:
Wanderingss
2026-09-21 01:26:09 +08:00
parent 2039ac5621
commit 2ef1e1f0dd
45 changed files with 1781 additions and 1983 deletions
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Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
+15 -15
View File
@@ -139,7 +139,7 @@ extern "C" {
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
#if defined(STM32L0)
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM
input 1 for COMP1, LPTIM input 2 for COMP2 */
#endif
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
@@ -241,9 +241,9 @@ extern "C" {
*/
#if defined(STM32H5) || defined(STM32C0)
#else
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
inter STM32 series compatibility */
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
inter STM32 series compatibility */
#endif
/**
@@ -472,7 +472,7 @@ extern "C" {
#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5)
#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5)
#define PAGESIZE FLASH_PAGE_SIZE
#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */
#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
@@ -1602,35 +1602,35 @@ extern "C" {
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to
the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from
MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus
or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status
of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and
transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input
frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control
de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control
activate threshold */
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
#if defined(STM32F1)
#else
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status
(or time-stamp) */
#endif
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and
status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
@@ -2500,9 +2500,9 @@ extern "C" {
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is
done into HAL_COMP_Init() */
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is
done into HAL_COMP_Init() */
/**
* @}
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h
+9 -9
View File
@@ -2,7 +2,7 @@
******************************************************************************
* @file stm32f4xx_hal.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the HAL
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
@@ -15,7 +15,7 @@
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_H
@@ -34,7 +34,7 @@
/** @addtogroup HAL
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
@@ -60,13 +60,13 @@ typedef enum
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup HAL_Exported_Macros HAL Exported Macros
* @{
*/
/** @brief Freeze/Unfreeze Peripherals in Debug mode
/** @brief Freeze/Unfreeze Peripherals in Debug mode
*/
#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
@@ -151,7 +151,7 @@ typedef enum
#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\
}while(0);
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)
/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
@@ -255,7 +255,7 @@ uint32_t HAL_GetUIDw2(void);
defined(STM32F469xx) || defined(STM32F479xx)
void HAL_EnableMemorySwappingBank(void);
void HAL_DisableMemorySwappingBank(void);
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
/**
* @}
*/
@@ -286,8 +286,8 @@ void HAL_DisableMemorySwappingBank(void);
/**
* @}
*/
*/
#ifdef __cplusplus
}
#endif
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h
+23 -22
View File
@@ -13,7 +13,7 @@
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_CORTEX_H
@@ -32,7 +32,7 @@
/** @addtogroup CORTEX
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Types Cortex Exported Types
* @{
@@ -40,31 +40,31 @@
#if (__MPU_PRESENT == 1U)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @brief MPU Region initialization structure
* @brief MPU Region initialization structure
* @{
*/
typedef struct
{
uint8_t Enable; /*!< Specifies the status of the region.
uint8_t Enable; /*!< Specifies the status of the region.
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
uint8_t Number; /*!< Specifies the number of the region to protect.
uint8_t Number; /*!< Specifies the number of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
uint8_t Size; /*!< Specifies the size of the region to protect.
uint8_t Size; /*!< Specifies the size of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint8_t TypeExtField; /*!< Specifies the TEX field level.
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
uint8_t AccessPermission; /*!< Specifies the region access permission type.
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
uint8_t AccessPermission; /*!< Specifies the region access permission type.
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
uint8_t DisableExec; /*!< Specifies the instruction access status.
uint8_t DisableExec; /*!< Specifies the instruction access status.
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
}MPU_Region_InitTypeDef;
/**
@@ -99,7 +99,7 @@ typedef struct
* @}
*/
/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
* @{
*/
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
@@ -211,8 +211,8 @@ typedef struct
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
@@ -252,7 +252,7 @@ typedef struct
/** @addtogroup CORTEX_Exported_Functions
* @{
*/
/** @addtogroup CORTEX_Exported_Functions_Group1
* @{
*/
@@ -387,22 +387,23 @@ void HAL_CORTEX_ClearEvent(void);
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
#endif /* __MPU_PRESENT */
/**
* @}
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F4xx_HAL_CORTEX_H */
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h
+25 -25
View File
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_def.h
* @author MCD Application Team
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
@@ -32,10 +32,10 @@
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL Status structures definition
*/
typedef enum
/**
* @brief HAL Status structures definition
*/
typedef enum
{
HAL_OK = 0x00U,
HAL_ERROR = 0x01U,
@@ -43,13 +43,13 @@ typedef enum
HAL_TIMEOUT = 0x03U
} HAL_StatusTypeDef;
/**
* @brief HAL Lock structures definition
/**
* @brief HAL Lock structures definition
*/
typedef enum
typedef enum
{
HAL_UNLOCKED = 0x00U,
HAL_LOCKED = 0x01U
HAL_LOCKED = 0x01U
} HAL_LockTypeDef;
/* Exported macro ------------------------------------------------------------*/
@@ -71,11 +71,11 @@ typedef enum
/** @brief Reset the Handle's State field.
* @param __HANDLE__ specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
* @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's "State" field.
* Otherwise, "State" field may have any random value and the first time the function
* Otherwise, "State" field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling
@@ -137,58 +137,58 @@ typedef enum
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler V5*/
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
/**
/**
* @brief __RAM_FUNC definition
*/
*/
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
/* ARM Compiler V4/V5 and V6
--------------------------
RAM functions are defined using the toolchain options.
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
dialog.
dialog.
*/
#define __RAM_FUNC
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
RAM functions are defined using a specific toolchain keyword "__ramfunc".
RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/
#define __RAM_FUNC __ramfunc
#elif defined ( __GNUC__ )
/* GNU Compiler
------------
RAM functions are defined using a specific toolchain attribute
RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
*/
#define __RAM_FUNC __attribute__((section(".RamFunc")))
#endif
/**
/**
* @brief __NOINLINE definition
*/
*/
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
/* ARM V4/V5 and V6 & GNU Compiler
-------------------------------
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h
+96 -96
View File
@@ -14,7 +14,7 @@
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_DMA_H
@@ -33,24 +33,24 @@
/** @addtogroup DMA
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DMA_Exported_Types DMA Exported Types
* @brief DMA Exported Types
* @brief DMA Exported Types
* @{
*/
/**
/**
* @brief DMA Configuration Structure definition
*/
typedef struct
{
uint32_t Channel; /*!< Specifies the channel used for the specified stream.
uint32_t Channel; /*!< Specifies the channel used for the specified stream.
This parameter can be a value of @ref DMA_Channel_selection */
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
from memory to memory or from peripheral to memory.
This parameter can be a value of @ref DMA_Data_transfer_direction */
@@ -76,27 +76,27 @@ typedef struct
uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
This parameter can be a value of @ref DMA_FIFO_direct_mode
@note The Direct mode (FIFO mode disabled) cannot be used if the
@note The Direct mode (FIFO mode disabled) cannot be used if the
memory-to-memory data transfer is configured on the selected stream */
uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
This parameter can be a value of @ref DMA_FIFO_threshold_level */
uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
It specifies the amount of data to be transferred in a single non interruptible
transaction.
This parameter can be a value of @ref DMA_Memory_burst
This parameter can be a value of @ref DMA_Memory_burst
@note The burst mode is possible only if the address Increment mode is enabled. */
uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
It specifies the amount of data to be transferred in a single non interruptible
transaction.
uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
It specifies the amount of data to be transferred in a single non interruptible
transaction.
This parameter can be a value of @ref DMA_Peripheral_burst
@note The burst mode is possible only if the address Increment mode is enabled. */
}DMA_InitTypeDef;
/**
/**
* @brief HAL DMA State structures definition
*/
typedef enum
@@ -109,7 +109,7 @@ typedef enum
HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
}HAL_DMA_StateTypeDef;
/**
/**
* @brief HAL DMA Error Code structure definition
*/
typedef enum
@@ -118,7 +118,7 @@ typedef enum
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
}HAL_DMA_LevelCompleteTypeDef;
/**
/**
* @brief HAL DMA Error Code structure definition
*/
typedef enum
@@ -132,39 +132,39 @@ typedef enum
HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
}HAL_DMA_CallbackIDTypeDef;
/**
/**
* @brief DMA handle Structure definition
*/
typedef struct __DMA_HandleTypeDef
{
DMA_Stream_TypeDef *Instance; /*!< Register base address */
DMA_InitTypeDef Init; /*!< DMA communication parameters */
DMA_InitTypeDef Init; /*!< DMA communication parameters */
HAL_LockTypeDef Lock; /*!< DMA locking object */
HAL_LockTypeDef Lock; /*!< DMA locking object */
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
void *Parent; /*!< Parent object state */
void *Parent; /*!< Parent object state */
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
uint32_t StreamIndex; /*!< DMA Stream Index */
}DMA_HandleTypeDef;
/**
@@ -174,14 +174,14 @@ typedef struct __DMA_HandleTypeDef
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMA_Exported_Constants DMA Exported Constants
* @brief DMA Exported constants
* @brief DMA Exported constants
* @{
*/
/** @defgroup DMA_Error_Code DMA Error Code
* @brief DMA Error Code
* @brief DMA Error Code
* @{
*/
*/
#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
#define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */
@@ -195,9 +195,9 @@ typedef struct __DMA_HandleTypeDef
*/
/** @defgroup DMA_Channel_selection DMA Channel selection
* @brief DMA channel selection
* @brief DMA channel selection
* @{
*/
*/
#define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */
#define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */
#define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */
@@ -221,30 +221,30 @@ typedef struct __DMA_HandleTypeDef
*/
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
* @brief DMA data transfer direction
* @brief DMA data transfer direction
* @{
*/
*/
#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
/**
* @}
*/
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
* @brief DMA peripheral incremented mode
* @brief DMA peripheral incremented mode
* @{
*/
*/
#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */
/**
* @}
*/
*/
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
* @brief DMA memory incremented mode
* @brief DMA memory incremented mode
* @{
*/
*/
#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */
/**
@@ -252,19 +252,19 @@ typedef struct __DMA_HandleTypeDef
*/
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
* @brief DMA peripheral data size
* @brief DMA peripheral data size
* @{
*/
*/
#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
/**
* @}
*/
*/
/** @defgroup DMA_Memory_data_size DMA Memory data size
* @brief DMA memory data size
* @{
* @brief DMA memory data size
* @{
*/
#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
@@ -274,9 +274,9 @@ typedef struct __DMA_HandleTypeDef
*/
/** @defgroup DMA_mode DMA mode
* @brief DMA mode
* @brief DMA mode
* @{
*/
*/
#define DMA_NORMAL 0x00000000U /*!< Normal mode */
#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
@@ -285,7 +285,7 @@ typedef struct __DMA_HandleTypeDef
*/
/** @defgroup DMA_Priority_level DMA Priority level
* @brief DMA priority levels
* @brief DMA priority levels
* @{
*/
#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */
@@ -294,7 +294,7 @@ typedef struct __DMA_HandleTypeDef
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
/**
* @}
*/
*/
/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
* @brief DMA FIFO direct mode
@@ -304,10 +304,10 @@ typedef struct __DMA_HandleTypeDef
#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
/**
* @}
*/
*/
/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
* @brief DMA FIFO level
* @brief DMA FIFO level
* @{
*/
#define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */
@@ -316,24 +316,24 @@ typedef struct __DMA_HandleTypeDef
#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
/**
* @}
*/
*/
/** @defgroup DMA_Memory_burst DMA Memory burst
* @brief DMA memory burst
* @brief DMA memory burst
* @{
*/
*/
#define DMA_MBURST_SINGLE 0x00000000U
#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
/**
* @}
*/
*/
/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
* @brief DMA peripheral burst
* @brief DMA peripheral burst
* @{
*/
*/
#define DMA_PBURST_SINGLE 0x00000000U
#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
@@ -343,7 +343,7 @@ typedef struct __DMA_HandleTypeDef
*/
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
* @brief DMA interrupts definition
* @brief DMA interrupts definition
* @{
*/
#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
@@ -356,9 +356,9 @@ typedef struct __DMA_HandleTypeDef
*/
/** @defgroup DMA_flag_definitions DMA flag definitions
* @brief DMA flag definitions
* @brief DMA flag definitions
* @{
*/
*/
#define DMA_FLAG_FEIF0_4 0x00000001U
#define DMA_FLAG_DMEIF0_4 0x00000004U
#define DMA_FLAG_TEIF0_4 0x00000008U
@@ -386,7 +386,7 @@ typedef struct __DMA_HandleTypeDef
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @brief Reset DMA handle state
@@ -399,7 +399,7 @@ typedef struct __DMA_HandleTypeDef
* @brief Return the current DMA Stream FIFO filled level.
* @param __HANDLE__ DMA handle
* @retval The FIFO filling state.
* - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
* - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
* and not empty.
* - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
* - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
@@ -449,7 +449,7 @@ typedef struct __DMA_HandleTypeDef
* @brief Return the current DMA Stream half transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index.
*/
*/
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
@@ -535,7 +535,7 @@ typedef struct __DMA_HandleTypeDef
* @arg DMA_FLAG_TEIFx: Transfer error flag.
* @arg DMA_FLAG_DMEIFx: Direct mode error flag.
* @arg DMA_FLAG_FEIFx: FIFO error flag.
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
@@ -553,7 +553,7 @@ typedef struct __DMA_HandleTypeDef
* @arg DMA_FLAG_TEIFx: Transfer error flag.
* @arg DMA_FLAG_DMEIFx: Direct mode error flag.
* @arg DMA_FLAG_FEIFx: FIFO error flag.
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
@@ -564,7 +564,7 @@ typedef struct __DMA_HandleTypeDef
/**
* @brief Enable the specified DMA Stream interrupts.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask.
* @arg DMA_IT_HT: Half transfer complete interrupt mask.
@@ -579,7 +579,7 @@ typedef struct __DMA_HandleTypeDef
/**
* @brief Disable the specified DMA Stream interrupts.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask.
* @arg DMA_IT_HT: Half transfer complete interrupt mask.
@@ -610,18 +610,18 @@ typedef struct __DMA_HandleTypeDef
/**
* @brief Writes the number of data units to be transferred on the DMA Stream.
* @param __HANDLE__ DMA handle
* @param __COUNTER__ Number of data units to be transferred (from 0 to 65535)
* @param __COUNTER__ Number of data units to be transferred (from 0 to 65535)
* Number of data items depends only on the Peripheral data format.
*
* @note If Peripheral data format is Bytes: number of data units is equal
*
* @note If Peripheral data format is Bytes: number of data units is equal
* to total number of bytes to be transferred.
*
* @note If Peripheral data format is Half-Word: number of data units is
*
* @note If Peripheral data format is Half-Word: number of data units is
* equal to total number of bytes to be transferred / 2.
*
* @note If Peripheral data format is Word: number of data units is equal
*
* @note If Peripheral data format is Word: number of data units is equal
* to total number of bytes to be transferred / 4.
*
*
* @retval The number of remaining data units in the current DMAy Streamx transfer.
*/
#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
@@ -629,34 +629,34 @@ typedef struct __DMA_HandleTypeDef
/**
* @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
* @param __HANDLE__ DMA handle
*
*
* @retval The number of remaining data units in the current DMA Stream transfer.
*/
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
/* Include DMA HAL Extension module */
#include "stm32f4xx_hal_dma_ex.h"
#include "stm32f4xx_hal_dma_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup DMA_Exported_Functions DMA Exported Functions
* @brief DMA Exported functions
* @brief DMA Exported functions
* @{
*/
/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
* @brief I/O operation functions
* @brief I/O operation functions
* @{
*/
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
@@ -671,32 +671,32 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
/**
* @}
*/
*/
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
* @brief Peripheral State functions
* @brief Peripheral State functions
* @{
*/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
/**
* @}
*/
*/
/**
* @}
*/
*/
/* Private Constants -------------------------------------------------------------*/
/** @defgroup DMA_Private_Constants DMA Private Constants
* @brief DMA private defines and constants
* @brief DMA private defines and constants
* @{
*/
/**
* @}
*/
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMA_Private_Macros DMA Private Macros
* @brief DMA private macros
* @brief DMA private macros
* @{
*/
#if defined (DMA_SxCR_CHSEL_3)
@@ -729,7 +729,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
@@ -749,12 +749,12 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
((MODE) == DMA_CIRCULAR) || \
((MODE) == DMA_PFCTRL))
((MODE) == DMA_PFCTRL))
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
((PRIORITY) == DMA_PRIORITY_HIGH) || \
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
((STATE) == DMA_FIFOMODE_ENABLE))
@@ -775,11 +775,11 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
((BURST) == DMA_PBURST_INC16))
/**
* @}
*/
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DMA_Private_Functions DMA Private Functions
* @brief DMA private functions
* @brief DMA private functions
* @{
*/
/**
@@ -788,7 +788,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
/**
* @}
*/
*/
/**
* @}
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h
+6 -6
View File
@@ -33,17 +33,17 @@
/** @addtogroup DMAEx
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
* @brief DMAEx Exported types
* @{
*/
/**
* @brief HAL DMA Memory definition
*/
/**
* @brief HAL DMA Memory definition
*/
typedef enum
{
MEMORY0 = 0x00U, /*!< Memory 0 */
@@ -76,7 +76,7 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
* @brief DMAEx Private functions
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h
+1 -1
View File
@@ -183,7 +183,7 @@ typedef struct
*/
#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
#define OB_RDP_LEVEL_1 ((uint8_t)0x55)
#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2
#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2
it s no more possible to go back to level 1 or 0 */
/**
* @}
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h
+17 -17
View File
@@ -14,7 +14,7 @@
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_GPIO_H
@@ -33,16 +33,16 @@
/** @addtogroup GPIO
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Types GPIO Exported Types
* @{
*/
/**
* @brief GPIO Init structure definition
*/
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
@@ -57,12 +57,12 @@ typedef struct
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_speed_define */
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.
This parameter can be a value of @ref GPIO_Alternate_function_selection */
}GPIO_InitTypeDef;
/**
* @brief GPIO Bit SET and Bit RESET enumeration
/**
* @brief GPIO Bit SET and Bit RESET enumeration
*/
typedef enum
{
@@ -77,7 +77,7 @@ typedef enum
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
* @{
*/
*/
/** @defgroup GPIO_pins_define GPIO pins define
* @{
@@ -113,7 +113,7 @@ typedef enum
* - Y : Output type (Push Pull or Open Drain) on 1 bit
* - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
* @{
*/
*/
#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
@@ -121,11 +121,11 @@ typedef enum
#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */
@@ -149,14 +149,14 @@ typedef enum
/** @defgroup GPIO_pull_define GPIO pull define
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
*/
#define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */
#define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */
/**
* @}
*/
/**
* @}
*/
@@ -240,11 +240,11 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
/**
* @}
*/
*/
/**
* @}
*/
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
@@ -311,7 +311,7 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
/**
* @}
*/
*/
/**
* @}
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h
+486 -486
View File
File diff suppressed because it is too large Load Diff
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h
+28 -28
View File
@@ -13,7 +13,7 @@
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_PWR_H
@@ -32,14 +32,14 @@
/** @addtogroup PWR
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PWR_Exported_Types PWR Exported Types
* @{
*/
/**
* @brief PWR PVD configuration structure definition
*/
@@ -60,7 +60,7 @@ typedef struct
/** @defgroup PWR_Exported_Constants PWR Exported Constants
* @{
*/
/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
* @{
*/
@@ -71,7 +71,7 @@ typedef struct
/** @defgroup PWR_PVD_detection_level PWR PVD detection level
* @{
*/
*/
#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
@@ -79,12 +79,12 @@ typedef struct
#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage
#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage
(Compare internally to VREFINT) */
/**
* @}
*/
*/
/** @defgroup PWR_PVD_Mode PWR PVD Mode
* @{
*/
@@ -108,7 +108,7 @@ typedef struct
/**
* @}
*/
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
* @{
*/
@@ -144,8 +144,8 @@ typedef struct
/**
* @}
*/
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup PWR_Exported_Macro PWR Exported Macro
* @{
@@ -154,21 +154,21 @@ typedef struct
/** @brief Check PWR flag is set or not.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
* was received from the WKUP pin or from the RTC alarm (Alarm A
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
* was received from the WKUP pin or from the RTC alarm (Alarm A
* or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
* An additional wakeup event is detected if the WKUP pin is enabled
* (by setting the EWUP bit) when the WKUP pin level is already high.
* An additional wakeup event is detected if the WKUP pin is enabled
* (by setting the EWUP bit) when the WKUP pin level is already high.
* @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
* resumed from StandBy mode.
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
* resumed from StandBy mode.
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
* For this reason, this bit is equal to 0 after Standby or reset
* until the PVDE bit is set.
* @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
* when the device wakes up from Standby mode or by a system reset
* or power reset.
* @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
* @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
* when the device wakes up from Standby mode or by a system reset
* or power reset.
* @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
* scaling output selection is ready.
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
@@ -247,7 +247,7 @@ typedef struct
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\
}while(0U)
}while(0U)
/**
* @brief checks whether the specified PVD Exti interrupt flag is set or not.
@@ -278,8 +278,8 @@ typedef struct
/** @addtogroup PWR_Exported_Functions PWR Exported Functions
* @{
*/
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
@@ -290,7 +290,7 @@ void HAL_PWR_DisableBkUpAccess(void);
* @}
*/
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
/* Peripheral Control functions **********************************************/
@@ -422,12 +422,12 @@ void HAL_PWR_DisableSEVOnPend(void);
/**
* @}
*/
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h
+30 -30
View File
@@ -13,7 +13,7 @@
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F4xx_HAL_PWR_EX_H
@@ -32,16 +32,16 @@
/** @addtogroup PWREx
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
* @{
*/
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode
* @{
*/
@@ -49,8 +49,8 @@
#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
/**
* @}
*/
*/
/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag
* @{
*/
@@ -65,7 +65,7 @@
/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
* @{
*/
#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */
#define PWR_REGULATOR_VOLTAGE_SCALE2 0x00000000U /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */
#else
@@ -74,7 +74,7 @@
#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to
168 MHz by activating the over-drive mode. */
#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS_0 /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */
#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
/**
* @}
*/
@@ -85,20 +85,20 @@
*/
#define PWR_WAKEUP_PIN2 0x00000080U
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
#define PWR_WAKEUP_PIN3 0x00000040U
#endif /* STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Zx || STM32F412Vx || \
STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
/**
* @}
*/
*/
#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
STM32F413xx || STM32F423xx */
/**
* @}
*/
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
* @{
@@ -139,7 +139,7 @@
tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
UNUSED(tmpreg); \
} while(0U)
#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
@@ -150,19 +150,19 @@
#define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE)
/** @brief Macros to enable or disable the Over drive switching.
* @note These macros can be used only for STM32F42xx/STM3243xx devices.
* @note These macros can be used only for STM32F42xx/STM3243xx devices.
*/
#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE)
#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE)
/** @brief Macros to enable or disable the Under drive mode.
* @note This mode is enabled only with STOP low power mode.
* In this mode, the 1.2V domain is preserved in reduced leakage mode. This
* mode is only available when the main regulator or the low power regulator
* is in low voltage mode.
* @note If the Under-drive mode was enabled, it is automatically disabled after
* exiting Stop mode.
* When the voltage regulator operates in Under-drive mode, an additional
* In this mode, the 1.2V domain is preserved in reduced leakage mode. This
* mode is only available when the main regulator or the low power regulator
* is in low voltage mode.
* @note If the Under-drive mode was enabled, it is automatically disabled after
* exiting Stop mode.
* When the voltage regulator operates in Under-drive mode, an additional
* startup delay is induced when waking up from Stop mode.
*/
#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN)
@@ -173,9 +173,9 @@
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
* is ready
* is ready
* @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
* switching is ready
* switching is ready
* @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
* is enabled in Stop mode
* @retval The new state of __FLAG__ (TRUE or FALSE).
@@ -196,14 +196,14 @@
/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
* @{
*/
/** @addtogroup PWREx_Exported_Functions_Group1
* @{
*/
void HAL_PWREx_EnableFlashPowerDown(void);
void HAL_PWREx_DisableFlashPowerDown(void);
void HAL_PWREx_DisableFlashPowerDown(void);
HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
uint32_t HAL_PWREx_GetVoltageRange(void);
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
@@ -254,7 +254,7 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t
/* Alias word address of ODSWEN bit */
#define ODSWEN_BIT_NUMBER PWR_CR_ODSWEN_Pos
#define CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U))
/* Alias word address of MRLVDS bit */
#define MRLVDS_BIT_NUMBER PWR_CR_MRLVDS_Pos
#define CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U))
@@ -269,7 +269,7 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t
/** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address
* @{
*/
*/
/* --- CSR Register ---*/
/* Alias word address of BRE bit */
#define BRE_BIT_NUMBER PWR_CSR_BRE_Pos
@@ -304,7 +304,7 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t
#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
#if defined(STM32F446xx)
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2))
@@ -326,12 +326,12 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t
/**
* @}
*/
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h
+1 -1
View File
@@ -5889,7 +5889,7 @@ typedef struct
#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
STM32F412Rx || STM32F412Cx */
#if defined(STM32F446xx)
/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h
+20 -20
View File
@@ -139,10 +139,10 @@ typedef struct
This parameter can be a value of @ref DMA_LL_EC_PRIORITY
This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
This parameter can be a value of @ref DMA_LL_FIFOMODE
@note The Direct mode (FIFO mode disabled) cannot be used if the
@note The Direct mode (FIFO mode disabled) cannot be used if the
memory-to-memory data transfer is configured on the selected stream
This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
@@ -152,19 +152,19 @@ typedef struct
This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
It specifies the amount of data to be transferred in a single non interruptible
transaction.
This parameter can be a value of @ref DMA_LL_EC_MBURST
@note The burst mode is possible only if the address Increment mode is enabled.
This parameter can be a value of @ref DMA_LL_EC_MBURST
@note The burst mode is possible only if the address Increment mode is enabled.
This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
It specifies the amount of data to be transferred in a single non interruptible
transaction.
uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
It specifies the amount of data to be transferred in a single non interruptible
transaction.
This parameter can be a value of @ref DMA_LL_EC_PBURST
@note The burst mode is possible only if the address Increment mode is enabled.
@note The burst mode is possible only if the address Increment mode is enabled.
This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
@@ -327,7 +327,7 @@ typedef struct
/**
* @}
*/
/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
* @{
*/
@@ -335,7 +335,7 @@ typedef struct
#define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */
/**
* @}
*/
*/
/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
* @{
@@ -360,7 +360,7 @@ typedef struct
/**
* @}
*/
/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
* @{
*/
@@ -1149,7 +1149,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t S
/**
* @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
* @rmtoll CR CT LL_DMA_SetCurrentTargetMem
* @rmtoll CR CT LL_DMA_SetCurrentTargetMem
* @param DMAx DMAx Instance
* @param Stream This parameter can be one of the following values:
* @arg @ref LL_DMA_STREAM_0
@@ -1172,7 +1172,7 @@ __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stre
/**
* @brief Get Current target (only in double buffer mode).
* @rmtoll CR CT LL_DMA_GetCurrentTargetMem
* @rmtoll CR CT LL_DMA_GetCurrentTargetMem
* @param DMAx DMAx Instance
* @param Stream This parameter can be one of the following values:
* @arg @ref LL_DMA_STREAM_0
@@ -1214,7 +1214,7 @@ __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t S
/**
* @brief Disable the double buffer mode.
* @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
* @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
* @param DMAx DMAx Instance
* @param Stream This parameter can be one of the following values:
* @arg @ref LL_DMA_STREAM_0
@@ -1280,7 +1280,7 @@ __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
/**
* @brief Enable Fifo mode.
* @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
* @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
* @param DMAx DMAx Instance
* @param Stream This parameter can be one of the following values:
* @arg @ref LL_DMA_STREAM_0
@@ -1379,7 +1379,7 @@ __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint3
/**
* @brief Configure the Source and Destination addresses.
* @note This API must not be called when the DMA stream is enabled.
* @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
* @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
* PAR PA LL_DMA_ConfigAddresses
* @param DMAx DMAx Instance
* @param Stream This parameter can be one of the following values:
@@ -1726,7 +1726,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
{
return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));
}
}
/**
* @brief Get Stream 0 transfer complete flag.
@@ -1814,7 +1814,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
{
return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));
}
}
/**
* @brief Get Stream 0 transfer error flag.
@@ -1902,7 +1902,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
{
return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));
}
}
/**
* @brief Get Stream 0 direct mode error flag.
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h
+6 -6
View File
@@ -268,12 +268,12 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHMemorySTOP(void)
* @brief Enable Under Drive Mode
* @rmtoll CR UDEN LL_PWR_EnableUnderDriveMode
* @note This mode is enabled only with STOP low power mode.
* In this mode, the 1.2V domain is preserved in reduced leakage mode. This
* mode is only available when the main Regulator or the low power Regulator
* is in low voltage mode.
* @note If the Under-drive mode was enabled, it is automatically disabled after
* exiting Stop mode.
* When the voltage Regulator operates in Under-drive mode, an additional
* In this mode, the 1.2V domain is preserved in reduced leakage mode. This
* mode is only available when the main Regulator or the low power Regulator
* is in low voltage mode.
* @note If the Under-drive mode was enabled, it is automatically disabled after
* exiting Stop mode.
* When the voltage Regulator operates in Under-drive mode, an additional
* startup delay is induced when waking up from Stop mode.
* @retval None
*/
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h
+52 -52
View File
@@ -117,7 +117,7 @@ extern "C" {
#endif /* SYSCFG_MEMRMP_UFB_MODE */
/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
* @{
*/
*/
#if defined(SYSCFG_CFGR_FMPI2C1_SCL)
#define LL_SYSCFG_I2C_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL /*!< Enable Fast Mode Plus on FMPI2C_SCL pin */
#define LL_SYSCFG_I2C_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA /*!< Enable Fast Mode Plus on FMPI2C_SDA pin*/
@@ -181,9 +181,9 @@ extern "C" {
* @{
*/
#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP output of CortexM4
#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP output of CortexM4
with Break Input of TIM1/8 */
#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIM1/8 Break Input
#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIM1/8 Break Input
and also the PVDE and PLS bits of the Power Control Interface */
#endif /* SYSCFG_CFGR2_CLL */
/**
@@ -201,7 +201,7 @@ extern "C" {
*/
/** @defgroup SYSTEM_LL_DFSDM_MCHDLYEN SYSCFG MCHDLY MCHDLYEN
* @{
*/
*/
#define LL_SYSCFG_DFSDM1_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY1EN
#define LL_SYSCFG_DFSDM2_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY2EN
/**
@@ -222,7 +222,7 @@ extern "C" {
*/
/** @defgroup SYSTEM_LL_DFSDM_DataIn2_Source SYSCFG MCHDLY DFSDMD2SEL
* @{
*/
*/
#define LL_SYSCFG_DFSDM1_DataIn2 SYSCFG_MCHDLYCR_DFSDM1D2SEL
#define LL_SYSCFG_DFSDM2_DataIn2 SYSCFG_MCHDLYCR_DFSDM2D2SEL
@@ -235,7 +235,7 @@ extern "C" {
*/
/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK02SEL
* @{
*/
*/
#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0 (uint32_t)0x00000000
#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL
/**
@@ -243,7 +243,7 @@ extern "C" {
*/
/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK13SEL
* @{
*/
*/
#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1 (uint32_t)0x00000000
#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL
/**
@@ -259,7 +259,7 @@ extern "C" {
*/
/** @defgroup SYSTEM_LL_DFSDM1_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM1CKOSEL
* @{
*/
*/
#define LL_SYSCFG_DFSDM1_CKOUT (uint32_t)0x00000000
#define LL_SYSCFG_DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL
/**
@@ -268,7 +268,7 @@ extern "C" {
/** @defgroup SYSTEM_LL_DFSDM2_DataIn4_SourceSelection SYSCFG MCHDLY DFSDM2D4SEL
* @{
*/
*/
#define LL_SYSCFG_DFSDM2_DataIn4_PAD (uint32_t)0x00000000
#define LL_SYSCFG_DFSDM2_DataIn4_DM SYSCFG_MCHDLYCR_DFSDM2D4SEL
/**
@@ -276,7 +276,7 @@ extern "C" {
*/
/** @defgroup SYSTEM_LL_DFSDM2_DataIn6_SourceSelection SYSCFG MCHDLY DFSDM2D6SEL
* @{
*/
*/
#define LL_SYSCFG_DFSDM2_DataIn6_PAD (uint32_t)0x00000000
#define LL_SYSCFG_DFSDM2_DataIn6_DM SYSCFG_MCHDLYCR_DFSDM2D6SEL
/**
@@ -284,7 +284,7 @@ extern "C" {
*/
/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC4_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK04SEL
* @{
*/
*/
#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0 (uint32_t)0x00000000
#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL
/**
@@ -292,7 +292,7 @@ extern "C" {
*/
/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC3_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK15SEL
* @{
*/
*/
#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1 (uint32_t)0x00000000
#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL
/**
@@ -300,7 +300,7 @@ extern "C" {
*/
/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK26SEL
* @{
*/
*/
#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2 (uint32_t)0x00000000
#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL
/**
@@ -308,7 +308,7 @@ extern "C" {
*/
/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK37SEL
* @{
*/
*/
#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3 (uint32_t)0x00000000
#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7 SYSCFG_MCHDLYCR_DFSDM2CK37SEL
/**
@@ -316,7 +316,7 @@ extern "C" {
*/
/** @defgroup SYSTEM_LL_DFSDM2_CLKIN_SourceSelection SYSCFG MCHDLY DFSDM2CFG
* @{
*/
*/
#define LL_SYSCFG_DFSDM2_CKIN_PAD (uint32_t)0x00000000
#define LL_SYSCFG_DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG
/**
@@ -324,13 +324,13 @@ extern "C" {
*/
/** @defgroup SYSTEM_LL_DFSDM2_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM2CKOSEL
* @{
*/
*/
#define LL_SYSCFG_DFSDM2_CKOUT (uint32_t)0x00000000
#define LL_SYSCFG_DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL
/**
* @}
*/
#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
*/
#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
* @{
@@ -487,8 +487,8 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
/**
* @brief Enables the FMC Memory Mapping Swapping
* @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_EnableFMCMemorySwapping
* @note SDRAM is accessible at 0x60000000 and NOR/RAM
* is accessible at 0xC0000000
* @note SDRAM is accessible at 0x60000000 and NOR/RAM
* is accessible at 0xC0000000
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void)
@@ -499,7 +499,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void)
/**
* @brief Disables the FMC Memory Mapping Swapping
* @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_DisableFMCMemorySwapping
* @note SDRAM is accessible at 0xC0000000 (default mapping)
* @note SDRAM is accessible at 0xC0000000 (default mapping)
* and NOR/RAM is accessible at 0x60000000 (default mapping)
* @retval None
*/
@@ -545,7 +545,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
#if defined(SYSCFG_PMC_MII_RMII_SEL)
/**
* @brief Select Ethernet PHY interface
* @brief Select Ethernet PHY interface
* @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_SetPHYInterface
* @param Interface This parameter can be one of the following values:
* @arg @ref LL_SYSCFG_PMC_ETHMII
@@ -558,7 +558,7 @@ __STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
}
/**
* @brief Get Ethernet PHY interface
* @brief Get Ethernet PHY interface
* @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_GetPHYInterface
* @retval Returned value can be one of the following values:
* @arg @ref LL_SYSCFG_PMC_ETHMII
@@ -570,7 +570,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL));
}
#endif /* SYSCFG_PMC_MII_RMII_SEL */
#if defined(SYSCFG_MEMRMP_UFB_MODE)
@@ -583,7 +583,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
{
{
MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE, Bank);
}
@@ -736,7 +736,7 @@ __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
* @arg @ref LL_SYSCFG_TIMBREAK_PVD
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
{
{
return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK));
}
#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
@@ -792,7 +792,7 @@ __STATIC_INLINE void LL_SYSCFG_DFSDM_DisableDelayClock(uint32_t MCHDLY)
}
/**
* @brief Select the source for DFSDM1 or DFSDM2 DatIn0
* @brief Select the source for DFSDM1 or DFSDM2 DatIn0
* @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL LL_SYSCFG_DFSDM_SetDataIn0Source
* @param Source This parameter can be one of the following values:
* @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
@@ -823,7 +823,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn0Source(uint32_t Source)
return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
}
/**
* @brief Select the source for DFSDM1 or DFSDM2 DatIn2
* @brief Select the source for DFSDM1 or DFSDM2 DatIn2
* @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL LL_SYSCFG_DFSDM_SetDataIn2Source
* @param Source This parameter can be one of the following values:
* @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
@@ -855,7 +855,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn2Source(uint32_t Source)
}
/**
* @brief Select the distribution of the bitsream lock gated by TIM4 OC2
* @brief Select the distribution of the bitsream lock gated by TIM4 OC2
* @rmtoll SYSCFG_MCHDLYCR DFSDM1CK02SEL LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution
* @param Source This parameter can be one of the following values:
* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
@@ -867,7 +867,7 @@ __STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution(uint32_t S
MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL, Source);
}
/**
* @brief Get the distribution of the bitsream lock gated by TIM4 OC2
* @brief Get the distribution of the bitsream lock gated by TIM4 OC2
* @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution
* @retval Returned value can be one of the following values:
* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
@@ -880,7 +880,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution(void)
}
/**
* @brief Select the distribution of the bitsream lock gated by TIM4 OC1
* @brief Select the distribution of the bitsream lock gated by TIM4 OC1
* @rmtoll SYSCFG_MCHDLYCR DFSDM1CK13SEL LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution
* @param Source This parameter can be one of the following values:
* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
@@ -892,7 +892,7 @@ __STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution(uint32_t S
MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL, Source);
}
/**
* @brief Get the distribution of the bitsream lock gated by TIM4 OC1
* @brief Get the distribution of the bitsream lock gated by TIM4 OC1
* @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution
* @retval Returned value can be one of the following values:
* @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
@@ -905,7 +905,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution(void)
}
/**
* @brief Select the DFSDM1 Clock In
* @brief Select the DFSDM1 Clock In
* @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG LL_SYSCFG_DFSDM1_SetClockInSourceSelection
* @param ClockSource This parameter can be one of the following values:
* @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
@@ -930,7 +930,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockInSourceSelection(void)
}
/**
* @brief Select the DFSDM1 Clock Out
* @brief Select the DFSDM1 Clock Out
* @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL LL_SYSCFG_DFSDM1_SetClockOutSourceSelection
* @param ClockSource This parameter can be one of the following values:
* @arg @ref LL_SYSCFG_DFSDM1_CKOUT
@@ -974,7 +974,7 @@ __STATIC_INLINE void LL_SYSCFG_DFSDM2_DisableDelayClock(void)
CLEAR_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
}
/**
* @brief Select the source for DFSDM2 DatIn0
* @brief Select the source for DFSDM2 DatIn0
* @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL LL_SYSCFG_DFSDM2_SetDataIn0Source
* @param Source This parameter can be one of the following values:
* @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
@@ -999,7 +999,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn0Source(void)
}
/**
* @brief Select the source for DFSDM2 DatIn2
* @brief Select the source for DFSDM2 DatIn2
* @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL LL_SYSCFG_DFSDM2_SetDataIn2Source
* @param Source This parameter can be one of the following values:
* @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
@@ -1024,7 +1024,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn2Source(void)
}
/**
* @brief Select the source for DFSDM2 DatIn4
* @brief Select the source for DFSDM2 DatIn4
* @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL LL_SYSCFG_DFSDM2_SetDataIn4Source
* @param Source This parameter can be one of the following values:
* @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
@@ -1049,7 +1049,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn4Source(void)
}
/**
* @brief Select the source for DFSDM2 DatIn6
* @brief Select the source for DFSDM2 DatIn6
* @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL LL_SYSCFG_DFSDM2_SetDataIn6Source
* @param Source This parameter can be one of the following values:
* @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
@@ -1074,7 +1074,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn6Source(void)
}
/**
* @brief Select the distribution of the bitsream lock gated by TIM3 OC4
* @brief Select the distribution of the bitsream lock gated by TIM3 OC4
* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution
* @param Source This parameter can be one of the following values:
* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
@@ -1086,7 +1086,7 @@ __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution(uint32_t S
MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL, Source);
}
/**
* @brief Get the distribution of the bitsream lock gated by TIM3 OC4
* @brief Get the distribution of the bitsream lock gated by TIM3 OC4
* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution
* @retval Returned value can be one of the following values:
* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
@@ -1099,7 +1099,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution(void)
}
/**
* @brief Select the distribution of the bitsream lock gated by TIM3 OC3
* @brief Select the distribution of the bitsream lock gated by TIM3 OC3
* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK15SEL LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution
* @param Source This parameter can be one of the following values:
* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
@@ -1111,7 +1111,7 @@ __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution(uint32_t S
MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL, Source);
}
/**
* @brief Get the distribution of the bitsream lock gated by TIM3 OC4
* @brief Get the distribution of the bitsream lock gated by TIM3 OC4
* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution
* @retval Returned value can be one of the following values:
* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
@@ -1124,7 +1124,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution(void)
}
/**
* @brief Select the distribution of the bitsream lock gated by TIM3 OC2
* @brief Select the distribution of the bitsream lock gated by TIM3 OC2
* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK26SEL LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution
* @param Source This parameter can be one of the following values:
* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
@@ -1136,7 +1136,7 @@ __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution(uint32_t S
MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL, Source);
}
/**
* @brief Get the distribution of the bitsream lock gated by TIM3 OC2
* @brief Get the distribution of the bitsream lock gated by TIM3 OC2
* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution
* @retval Returned value can be one of the following values:
* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
@@ -1149,7 +1149,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution(void)
}
/**
* @brief Select the distribution of the bitsream lock gated by TIM3 OC1
* @brief Select the distribution of the bitsream lock gated by TIM3 OC1
* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution
* @param Source This parameter can be one of the following values:
* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
@@ -1161,7 +1161,7 @@ __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution(uint32_t S
MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL, Source);
}
/**
* @brief Get the distribution of the bitsream lock gated by TIM3 OC1
* @brief Get the distribution of the bitsream lock gated by TIM3 OC1
* @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution
* @retval Returned value can be one of the following values:
* @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
@@ -1174,7 +1174,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution(void)
}
/**
* @brief Select the DFSDM2 Clock In
* @brief Select the DFSDM2 Clock In
* @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG LL_SYSCFG_DFSDM2_SetClockInSourceSelection
* @param ClockSource This parameter can be one of the following values:
* @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
@@ -1199,7 +1199,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockInSourceSelection(void)
}
/**
* @brief Select the DFSDM2 Clock Out
* @brief Select the DFSDM2 Clock Out
* @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL LL_SYSCFG_DFSDM2_SetClockOutSourceSelection
* @param ClockSource This parameter can be one of the following values:
* @arg @ref LL_SYSCFG_DFSDM2_CKOUT
@@ -1389,7 +1389,7 @@ __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
@@ -1406,7 +1406,7 @@ __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
*
*
* (*) value not defined in all devices.
* @retval None
*/
@@ -1441,7 +1441,7 @@ __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
@@ -1458,7 +1458,7 @@ __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
*
*
* (*) value not defined in all devices.
* @retval None
*/
Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h
+1 -1
View File
@@ -233,7 +233,7 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void)
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 (*)
* @arg @ref LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 (*)
*
*
* (*) value not defined in all devices.
*/
__STATIC_INLINE uint32_t LL_GetPackageType(void)