diff --git a/AGENTS.md b/AGENTS.md new file mode 100644 index 0000000..cc6274f --- /dev/null +++ b/AGENTS.md @@ -0,0 +1,67 @@ +# STM32F4-Base + +## 项目概述 + +STM32F407ZGTx (Cortex-M4 FPU) 基础固件项目，集成 CH395F 以太网控制器 SPI 驱动（CH395F 自带 MAC+PHY 及 TCP/IP 协议栈固件）。 + +## 关键文件 + +| 路径 | 说明 | +|---|---| +| `Src/main.c` | 程序入口，初始化序列及主循环 | +| `Src/ch395f.c` / `Inc/ch395f.h` | CH395F 以太网芯片 SPI 驱动（核心自定义代码） | +| `MDK-ARM/STM32F407-Demo.uvprojx` | Keil MDK 项目文件 | +| `STM32F407-Demo.ioc` | STM32CubeMX 项目源文件 | + +## 构建 + +仅支持 Keil MDK-ARM v5 (ARMCC)。打开 `MDK-ARM/STM32F407-Demo.uvprojx` 编译。 + +- 编译器：ARMCC V5.06 update 7 +- 优化等级：`-O4` (项目级)，`spi.c`/`usart.c` / HAL 源文件使用 `-O0` +- C 标准：C99 +- 全局宏定义：`USE_HAL_DRIVER, STM32F407xx` + +## 硬件配置 + +- **主频：** HSE 25MHz → PLL 168MHz (4/168/2) +- **6 个 LED：** PC4, PC5, PB1, PB2, PF11, PF12（低电平点亮） +- **CH395F：** SPI2 (PB12 CS, PB13 SCK, PB14 SDO, PB15 SDI) +- **USART1：** PA9 TX, PA10 RX (115200bps) + +## 启动顺序 + +``` +HAL_Init() → SystemClock_Config() → MX_GPIO_Init() → MX_USART1_UART_Init() → MX_SPI2_Init() → ch395f_reset() → ch395f_init() +``` + +## 代码规范 + +参考 `嵌入式C语言代码规范（V1.0）.md`，关键要点： + +- 缩进：4 空格，禁止 Tab +- 命名：小写字母+下划线；全局变量 `g_` 前缀，静态 `s_`，指针 `p_`，数组 `a_` +- 函数注释块需包含：函数功能、入口参数、返回值、限定条件、函数说明 +- 大括号：K&R 风格（左大括号不换行） + +## 注意 + +- `Inc/` 和 `Src/` 中 CubeMX 生成的文件（gpio, spi, usart, stm32f4xx_it, main 的骨架）带有 `USER CODE BEGIN`/`END` 标记，自定义代码应写在这些区域之间以免被 CubeMX 重新生成时覆盖 +- `ch395f.c`/`ch395f.h` 为纯手工代码，不受 CubeMX 保护 +- 每次 SPI 事务需调用 `ch395f_spi_begin()` / `ch395f_spi_end()` 包裹 +- CH395F 命令执行时序参考 `ch395f.h` 中命令码注释及 `CH395F.md` + +## 已知问题 + +### CH395F 与 RTL8305NBI 自动协商不兼容 + +CH395F 与 RTL8305NBI-CG 直连（经网络变压器）时，自动协商始终失败（返回 `PHY_DISCONN`），但强制 100M 全双工工作正常。强制 10M 全双工同样失败。 + +**诊断结果：** +- Auto-Neg: `0x01 (DISCONNECTED)` +- Force 100M-FULL: `0x08 (LINK OK)` +- Force 10M-FULL: `0x01 (DISCONNECTED)` + +**解决方案：** 初始化协议栈后调用 `ch395f_set_phy(CH395F_PHY_100M_FULL)` 跳过自动协商。 + +**推测根因：** 不同厂家 PHY 直连时的自动协商实现差异（CH395F WCH 固件 vs RTL8305NBI Realtek 硬件），物理层正常。 diff --git a/Src/ch395f.c b/Drivers/BSP/CH395F/ch395f.c similarity index 99% rename from Src/ch395f.c rename to Drivers/BSP/CH395F/ch395f.c index c0c2487..38f28fa 100644 --- a/Src/ch395f.c +++ b/Drivers/BSP/CH395F/ch395f.c @@ -915,4 +915,4 @@ uint8_t ch395f_get_sock_int_status(uint8_t sock) ch395f_spi_end(); return status; -} \ No newline at end of file +} diff --git a/Inc/ch395f.h b/Drivers/BSP/CH395F/ch395f.h similarity index 99% rename from Inc/ch395f.h rename to Drivers/BSP/CH395F/ch395f.h index 4f1365b..bf008f5 100644 --- a/Inc/ch395f.h +++ b/Drivers/BSP/CH395F/ch395f.h @@ -492,4 +492,4 @@ uint8_t ch395f_get_sock_int_status(uint8_t sock); } #endif -#endif /* __CH395F_H */ \ No newline at end of file +#endif /* __CH395F_H */ diff --git a/Drivers/BSP/GD5F2GQ5UE/fal_cfg.h b/Drivers/BSP/GD5F2GQ5UE/fal_cfg.h new file mode 100644 index 0000000..4b07ac1 --- /dev/null +++ b/Drivers/BSP/GD5F2GQ5UE/fal_cfg.h @@ -0,0 +1,35 @@ +/** + ****************************************************************************** + * @file fal_cfg.h + * @brief FAL 配置：Flash 设备表 + 分区表 + ****************************************************************************** + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#define FAL_DEBUG 0 + +#define FAL_PART_HAS_TABLE_CFG + +/* ===================== Flash 设备表 ===================== */ +extern const struct fal_flash_dev gd5f2gq5ue_flash; + +#define FAL_FLASH_DEV_TABLE \ +{ \ + &gd5f2gq5ue_flash, \ +} + +/* ===================== 分区表 ===================== */ +/* 分区名称 设备名称 偏移 大小 */ +/* KVDB: 64MB @ 0 */ +/* TSDB: 64MB @ 64MB */ +#ifdef FAL_PART_HAS_TABLE_CFG +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "fdb_kvdb1", "gd5f2gq5ue", 0, 64*1024*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "fdb_tsdb1", "gd5f2gq5ue", 64*1024*1024, 64*1024*1024, 0}, \ +} +#endif + +#endif /* _FAL_CFG_H_ */ diff --git a/Drivers/BSP/GD5F2GQ5UE/fal_flash_gd5f2gq5ue.c b/Drivers/BSP/GD5F2GQ5UE/fal_flash_gd5f2gq5ue.c new file mode 100644 index 0000000..ff3ec9e --- /dev/null +++ b/Drivers/BSP/GD5F2GQ5UE/fal_flash_gd5f2gq5ue.c @@ -0,0 +1,47 @@ +/** + ****************************************************************************** + * @file fal_flash_gd5f2gq5ue.c + * @brief FAL 端口：GD5F2GQ5UE SPI NAND Flash 适配层 + ****************************************************************************** + */ + +#include "fal_def.h" +#include "gd5f2gq5ue.h" + +/* ===================== FAL Flash 设备操作函数 ===================== */ + +static int gd5f_fal_init(void) +{ + return gd5f2gq5ue_init(); +} + +static int gd5f_fal_read(long offset, uint8_t *buf, size_t size) +{ + return gd5f2gq5ue_read(offset, buf, size); +} + +static int gd5f_fal_write(long offset, const uint8_t *buf, size_t size) +{ + return gd5f2gq5ue_write(offset, buf, size); +} + +static int gd5f_fal_erase(long offset, size_t size) +{ + return gd5f2gq5ue_erase(offset, size); +} + +/* ===================== FAL Flash 设备定义 ===================== */ + +const struct fal_flash_dev gd5f2gq5ue_flash = { + .name = "gd5f2gq5ue", + .addr = 0, + .len = GD5F_TOTAL_SIZE, /* 256MB */ + .blk_size = GD5F_BLOCK_SIZE, /* 128KB */ + .ops = { + .init = gd5f_fal_init, + .read = gd5f_fal_read, + .write = gd5f_fal_write, + .erase = gd5f_fal_erase, + }, + .write_gran = 8, +}; diff --git a/Drivers/BSP/GD5F2GQ5UE/fdb_cfg.h b/Drivers/BSP/GD5F2GQ5UE/fdb_cfg.h new file mode 100644 index 0000000..3644272 --- /dev/null +++ b/Drivers/BSP/GD5F2GQ5UE/fdb_cfg.h @@ -0,0 +1,32 @@ +/** + ****************************************************************************** + * @file fdb_cfg.h + * @brief FlashDB 配置文件 + ****************************************************************************** + */ + +#ifndef _FDB_CFG_H_ +#define _FDB_CFG_H_ + +/* 启用 KVDB（键值数据库） */ +#define FDB_USING_KVDB + +#ifdef FDB_USING_KVDB +/* 当 KVDB 版本号变化时自动更新到最新默认值 */ +/* #define FDB_KV_AUTO_UPDATE */ +#endif + +/* 启用 TSDB（时序数据库） */ +#define FDB_USING_TSDB + +/* 使用 FAL 存储模式（非文件模式） */ +#define FDB_USING_FAL_MODE + +/* Flash 写入粒度（单位：bit） + * STM32F4 = 8（字节可编程） */ +#define FDB_WRITE_GRAN 8 + +/* 调试输出 */ +#define FDB_DEBUG_ENABLE + +#endif /* _FDB_CFG_H_ */ diff --git a/Drivers/BSP/GD5F2GQ5UE/gd5f2gq5ue.c b/Drivers/BSP/GD5F2GQ5UE/gd5f2gq5ue.c new file mode 100644 index 0000000..9e66c38 --- /dev/null +++ b/Drivers/BSP/GD5F2GQ5UE/gd5f2gq5ue.c @@ -0,0 +1,367 @@ +/** + ****************************************************************************** + * @file gd5f2gq5ue.c + * @brief GD5F2GQ5UE SPI NAND Flash 驱动实现 + ****************************************************************************** + */ + +#include "gd5f2gq5ue.h" +#include + +extern SPI_HandleTypeDef hspi1; + +/* ===================== 内部辅助函数 ===================== */ + +/** + * @brief SPI 发送/接收单字节 + */ +static uint8_t gd5f_spi_xfer(uint8_t tx) +{ + uint8_t rx; + HAL_SPI_TransmitReceive(&hspi1, &tx, &rx, 1, 100); + return rx; +} + +/** + * @brief SPI 发送缓冲区 + */ +static void gd5f_spi_tx(const uint8_t *buf, size_t len) +{ + HAL_SPI_Transmit(&hspi1, (uint8_t *)buf, len, 100); +} + +/** + * @brief SPI 接收缓冲区 + */ +static void gd5f_spi_rx(uint8_t *buf, size_t len) +{ + HAL_SPI_Receive(&hspi1, buf, len, 100); +} + +/** + * @brief 等待操作完成（OIP 位清零） + * @param timeout_ms: 超时时间（毫秒） + * @retval GD5F_OK 成功, GD5F_BUSY_TIMEOUT 超时 + */ +static int gd5f_wait_busy(uint32_t timeout_ms) +{ + uint8_t cmd = GD5F_CMD_GET_FEATURE; + uint8_t addr = GD5F_REG_STATUS; + uint8_t status; + uint32_t tickstart = HAL_GetTick(); + + while (1) { + GD5F_CS_LOW(); + gd5f_spi_tx(&cmd, 1); + gd5f_spi_tx(&addr, 1); + gd5f_spi_rx(&status, 1); + GD5F_CS_HIGH(); + + if ((status & GD5F_STATUS_OIP) == 0) { + return GD5F_OK; + } + + if ((HAL_GetTick() - tickstart) >= timeout_ms) { + return GD5F_BUSY_TIMEOUT; + } + } +} + +/** + * @brief 写使能 + */ +static int gd5f_write_enable(void) +{ + uint8_t cmd = GD5F_CMD_WRITE_ENABLE; + GD5F_CS_LOW(); + gd5f_spi_tx(&cmd, 1); + GD5F_CS_HIGH(); + return GD5F_OK; +} + +/** + * @brief 读取状态寄存器 + */ +static int gd5f_read_status(uint8_t *status) +{ + uint8_t cmd = GD5F_CMD_GET_FEATURE; + uint8_t addr = GD5F_REG_STATUS; + GD5F_CS_LOW(); + gd5f_spi_tx(&cmd, 1); + gd5f_spi_tx(&addr, 1); + gd5f_spi_rx(status, 1); + GD5F_CS_HIGH(); + return GD5F_OK; +} + +/** + * @brief 页读取到缓存（Page Read to Cache） + * @param page_addr: 页地址（行地址，包含 block + page） + */ +static int gd5f_page_read(uint32_t page_addr) +{ + uint8_t cmd[4]; + cmd[0] = GD5F_CMD_PAGE_READ; + cmd[1] = (page_addr >> 16) & 0xFF; + cmd[2] = (page_addr >> 8) & 0xFF; + cmd[3] = page_addr & 0xFF; + + GD5F_CS_LOW(); + gd5f_spi_tx(cmd, 4); + GD5F_CS_HIGH(); + + return gd5f_wait_busy(100); +} + +/** + * @brief 从缓存读取数据（Read from Cache） + * @param column: 列地址（页内偏移） + * @param buf: 数据缓冲区 + * @param size: 读取字节数 + */ +static int gd5f_read_from_cache(uint16_t column, uint8_t *buf, size_t size) +{ + uint8_t cmd[5]; + cmd[0] = GD5F_CMD_READ_FROM_CACHE; + cmd[1] = (column >> 8) & 0xFF; + cmd[2] = column & 0xFF; + cmd[3] = 0x00; /* dummy byte */ + + GD5F_CS_LOW(); + gd5f_spi_tx(cmd, 4); + gd5f_spi_rx(buf, size); + GD5F_CS_HIGH(); + + return GD5F_OK; +} + +/** + * @brief 页编程（从缓存写入阵列） + * @param page_addr: 页地址 + * @param column: 列地址 + * @param buf: 数据缓冲区 + * @param size: 写入字节数 + */ +static int gd5f_page_program(uint32_t page_addr, uint16_t column, const uint8_t *buf, size_t size) +{ + int ret; + uint8_t cmd[4]; + + /* 1. 写使能 */ + gd5f_write_enable(); + + /* 2. 数据加载到缓存 (Program Load) */ + cmd[0] = GD5F_CMD_PROGRAM_LOAD; + cmd[1] = (column >> 8) & 0xFF; + cmd[2] = column & 0xFF; + + GD5F_CS_LOW(); + gd5f_spi_tx(cmd, 3); + gd5f_spi_tx(buf, size); + GD5F_CS_HIGH(); + + /* 3. 编程执行 (Program Execute) */ + cmd[0] = GD5F_CMD_PROGRAM_EXEC; + cmd[1] = (page_addr >> 16) & 0xFF; + cmd[2] = (page_addr >> 8) & 0xFF; + cmd[3] = page_addr & 0xFF; + + GD5F_CS_LOW(); + gd5f_spi_tx(cmd, 4); + GD5F_CS_HIGH(); + + /* 4. 等待完成 */ + ret = gd5f_wait_busy(1000); + if (ret != GD5F_OK) return ret; + + /* 5. 检查编程结果 */ + uint8_t status; + gd5f_read_status(&status); + if (status & GD5F_STATUS_P_FAIL) { + /* 清除 P_FAIL：写使能 + 读状态 */ + gd5f_write_enable(); + return GD5F_PROGRAM_FAIL; + } + + return GD5F_OK; +} + +/** + * @brief 块擦除 + * @param block_addr: 块地址 (0 ~ 2047) + */ +static int gd5f_block_erase(uint32_t block_addr) +{ + int ret; + uint8_t cmd[4]; + + /* 1. 写使能 */ + gd5f_write_enable(); + + /* 2. 块擦除命令 */ + cmd[0] = GD5F_CMD_BLOCK_ERASE; + cmd[1] = (block_addr >> 8) & 0xFF; + cmd[2] = block_addr & 0xFF; + cmd[3] = 0x00; + + GD5F_CS_LOW(); + gd5f_spi_tx(cmd, 4); + GD5F_CS_HIGH(); + + /* 3. 等待完成（擦除较慢） */ + ret = gd5f_wait_busy(5000); + if (ret != GD5F_OK) return ret; + + /* 4. 检查擦除结果 */ + uint8_t status; + gd5f_read_status(&status); + if (status & GD5F_STATUS_E_FAIL) { + gd5f_write_enable(); + return GD5F_ERASE_FAIL; + } + + return GD5F_OK; +} + +/* ===================== 公共接口实现 ===================== */ + +int gd5f2gq5ue_init(void) +{ + int ret; + uint8_t mid, did; + + /* 确保控制引脚处于非激活状态 */ + GD5F_CS_HIGH(); + GD5F_WP_HIGH(); + GD5F_HOLD_HIGH(); + + /* 小延时等待上电稳定 */ + HAL_Delay(10); + + /* 复位芯片 */ + ret = gd5f2gq5ue_reset(); + if (ret != GD5F_OK) return ret; + + HAL_Delay(5); + + /* 读取 ID 验证通信 */ + ret = gd5f2gq5ue_read_id(&mid, &did); + if (ret != GD5F_OK) return ret; + + if (mid != GD5F_MANUFACTURER_ID || did != GD5F_DEVICE_ID) { + return GD5F_ID_MISMATCH; + } + + return GD5F_OK; +} + +int gd5f2gq5ue_read_id(uint8_t *mid, uint8_t *did) +{ + uint8_t cmd = GD5F_CMD_READ_ID; + uint8_t id_buf[3]; + + GD5F_CS_LOW(); + gd5f_spi_tx(&cmd, 1); + gd5f_spi_rx(id_buf, 3); /* dummy + MID + DID */ + GD5F_CS_HIGH(); + + *mid = id_buf[1]; /* id_buf[0] = dummy */ + *did = id_buf[2]; + + return GD5F_OK; +} + +int gd5f2gq5ue_read(long offset, uint8_t *buf, size_t size) +{ + int ret; + + while (size > 0) { + /* 计算页地址和列偏移 */ + uint32_t page_addr = offset / GD5F_PAGE_SIZE; + uint16_t column = offset % GD5F_PAGE_SIZE; + + /* 本次读取字节数（不超过当前页剩余空间） */ + size_t bytes = GD5F_PAGE_SIZE - column; + if (bytes > size) bytes = size; + + /* Page Read to Cache */ + ret = gd5f_page_read(page_addr); + if (ret != GD5F_OK) return ret; + + /* Read from Cache */ + ret = gd5f_read_from_cache(column, buf, bytes); + if (ret != GD5F_OK) return ret; + + offset += bytes; + buf += bytes; + size -= bytes; + } + + return GD5F_OK; +} + +int gd5f2gq5ue_write(long offset, const uint8_t *buf, size_t size) +{ + int ret; + + while (size > 0) { + /* 计算页地址和列偏移 */ + uint32_t page_addr = offset / GD5F_PAGE_SIZE; + uint16_t column = offset % GD5F_PAGE_SIZE; + + /* 本次写入字节数（不超过当前页剩余空间） */ + size_t bytes = GD5F_PAGE_SIZE - column; + if (bytes > size) bytes = size; + + /* 页编程 */ + ret = gd5f_page_program(page_addr, column, buf, bytes); + if (ret != GD5F_OK) return ret; + + offset += bytes; + buf += bytes; + size -= bytes; + } + + return GD5F_OK; +} + +int gd5f2gq5ue_erase(long offset, size_t size) +{ + int ret; + + /* 擦除起始地址必须块对齐 */ + if (offset % GD5F_BLOCK_SIZE != 0) { + return GD5F_ERROR; + } + + /* 擦除大小必须为块大小的整数倍 */ + if (size % GD5F_BLOCK_SIZE != 0) { + return GD5F_ERROR; + } + + /* 逐块擦除 */ + while (size > 0) { + uint32_t block_addr = offset / GD5F_BLOCK_SIZE; + + ret = gd5f_block_erase(block_addr); + if (ret != GD5F_OK) return ret; + + offset += GD5F_BLOCK_SIZE; + size -= GD5F_BLOCK_SIZE; + } + + return GD5F_OK; +} + +int gd5f2gq5ue_reset(void) +{ + uint8_t cmd = GD5F_CMD_RESET; + + GD5F_CS_LOW(); + gd5f_spi_tx(&cmd, 1); + GD5F_CS_HIGH(); + + HAL_Delay(5); + + return GD5F_OK; +} diff --git a/Drivers/BSP/GD5F2GQ5UE/gd5f2gq5ue.h b/Drivers/BSP/GD5F2GQ5UE/gd5f2gq5ue.h new file mode 100644 index 0000000..ba9eb93 --- /dev/null +++ b/Drivers/BSP/GD5F2GQ5UE/gd5f2gq5ue.h @@ -0,0 +1,133 @@ +/** + ****************************************************************************** + * @file gd5f2gq5ue.h + * @brief GD5F2GQ5UE SPI NAND Flash 驱动头文件 + ****************************************************************************** + */ + +#ifndef __GD5F2GQ5UE_H +#define __GD5F2GQ5UE_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "main.h" +#include "spi.h" + +/* ===================== 硬件引脚定义 ===================== */ +#define GD5F_CS_LOW() HAL_GPIO_WritePin(GD_CS_GPIO_Port, GD_CS_Pin, GPIO_PIN_RESET) +#define GD5F_CS_HIGH() HAL_GPIO_WritePin(GD_CS_GPIO_Port, GD_CS_Pin, GPIO_PIN_SET) +#define GD5F_WP_HIGH() HAL_GPIO_WritePin(GD_WP_GPIO_Port, GD_WP_Pin, GPIO_PIN_SET) +#define GD5F_HOLD_HIGH() HAL_GPIO_WritePin(GD_HOLD_GPIO_Port, GD_HOLD_Pin, GPIO_PIN_SET) + +/* ===================== SPI 命令码 ===================== */ +#define GD5F_CMD_WRITE_ENABLE 0x06 +#define GD5F_CMD_WRITE_DISABLE 0x04 +#define GD5F_CMD_GET_FEATURE 0x0F +#define GD5F_CMD_SET_FEATURE 0x1F +#define GD5F_CMD_READ_ID 0x9F +#define GD5F_CMD_PAGE_READ 0x13 +#define GD5F_CMD_READ_FROM_CACHE 0x0B /* Fast Read, 1 dummy byte */ +#define GD5F_CMD_PROGRAM_LOAD 0x02 +#define GD5F_CMD_PROGRAM_EXEC 0x10 +#define GD5F_CMD_BLOCK_ERASE 0xD8 +#define GD5F_CMD_RESET 0xFF + +/* ===================== 寄存器地址 ===================== */ +#define GD5F_REG_STATUS 0xC0 +#define GD5F_REG_PROTECT 0xA0 +#define GD5F_REG_FEATURE 0xB0 +#define GD5F_REG_DRIVER 0xD0 + +/* ===================== 状态位定义 ===================== */ +#define GD5F_STATUS_OIP (1 << 0) /* 操作进行中 */ +#define GD5F_STATUS_WEL (1 << 1) /* 写使能锁存 */ +#define GD5F_STATUS_E_FAIL (1 << 2) /* 擦除失败 */ +#define GD5F_STATUS_P_FAIL (1 << 3) /* 编程失败 */ +#define GD5F_STATUS_BIT4 (1 << 4) +#define GD5F_STATUS_ECCS0 (1 << 5) +#define GD5F_STATUS_ECCS1 (1 << 6) +#define GD5F_STATUS_ECCSE0 (1 << 4) /* ECC 单 bit 错误低位 */ +#define GD5F_STATUS_ECCSE1 (1 << 5) /* ECC 单 bit 错误高位 */ +#define GD5F_STATUS_ECCSE2 (1 << 6) /* ECC 单 bit 错误高位 */ + +/* ===================== Feature 位定义 ===================== */ +#define GD5F_FEATURE_ECC_EN (1 << 4) +#define GD5F_FEATURE_QE (1 << 0) /* Quad Enable, B0[0] */ + +/* ===================== 芯片参数 ===================== */ +#define GD5F_PAGE_SIZE 2048 /* 主数据区字节数 */ +#define GD5F_SPARE_SIZE 64 /* ECC 启用时 spare 区 */ +#define GD5F_TOTAL_PAGE_SIZE 2112 /* 2048 + 64 */ +#define GD5F_PAGES_PER_BLOCK 64 +#define GD5F_BLOCK_SIZE (GD5F_PAGES_PER_BLOCK * GD5F_PAGE_SIZE) /* 128KB */ +#define GD5F_TOTAL_BLOCKS 2048 +#define GD5F_TOTAL_SIZE (GD5F_TOTAL_BLOCKS * GD5F_BLOCK_SIZE) /* 256MB */ + +/* 制造商 ID 和设备 ID */ +#define GD5F_MANUFACTURER_ID 0xC8 +#define GD5F_DEVICE_ID 0x52 + +/* ===================== 返回值定义 ===================== */ +#define GD5F_OK 0 +#define GD5F_ERROR -1 +#define GD5F_BUSY_TIMEOUT -2 +#define GD5F_ECC_ERROR -3 +#define GD5F_PROGRAM_FAIL -4 +#define GD5F_ERASE_FAIL -5 +#define GD5F_ID_MISMATCH -6 + +/* ===================== 公共接口函数 ===================== */ + +/** + * @brief 初始化 GD5F2GQ5UE（SPI + GPIO + 读 ID 验证） + * @retval GD5F_OK 成功, 其他为错误码 + */ +int gd5f2gq5ue_init(void); + +/** + * @brief 读取芯片 ID（MID + DID） + * @param mid: 制造商 ID 输出指针 + * @param did: 设备 ID 输出指针 + * @retval GD5F_OK 成功 + */ +int gd5f2gq5ue_read_id(uint8_t *mid, uint8_t *did); + +/** + * @brief 从 NAND 读取数据（支持跨页） + * @param offset: 起始字节偏移（相对于 Flash 起始地址） + * @param buf: 数据缓冲区 + * @param size: 读取字节数 + * @retval GD5F_OK 成功 + */ +int gd5f2gq5ue_read(long offset, uint8_t *buf, size_t size); + +/** + * @brief 向 NAND 写入数据（支持跨页） + * @param offset: 起始字节偏移 + * @param buf: 数据缓冲区 + * @param size: 写入字节数 + * @retval GD5F_OK 成功 + */ +int gd5f2gq5ue_write(long offset, const uint8_t *buf, size_t size); + +/** + * @brief 擦除块（按块擦除，最小单位 128KB） + * @param offset: 起始字节偏移（必须块对齐） + * @param size: 擦除字节数（必须为块大小的整数倍） + * @retval GD5F_OK 成功 + */ +int gd5f2gq5ue_erase(long offset, size_t size); + +/** + * @brief 复位芯片 + * @retval GD5F_OK 成功 + */ +int gd5f2gq5ue_reset(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __GD5F2GQ5UE_H */ diff --git a/GD5F2GQ5UExxG.md b/GD5F2GQ5UExxG.md new file mode 100644 index 0000000..4196cef --- /dev/null +++ b/GD5F2GQ5UExxG.md @@ -0,0 +1,1843 @@ +## GD5F2GQ5xExxG + +## DATASHEET + +2G-bit 2K+128BPageSize with E Version + +## Contents + +1 FEATURE .... + +2 GENERAL DESCRIPTION ...... + +2.1 PRODUCT LIST ..... + +2.2 CONNECTION DIAGRAM. . 8 + +2.3 PIN DESCRIPTION..... 9 + +2.4 BLOCK DIAGRAM ...... + +3 MEMORY MAPPING... ..10 + +4 ARRAY ORGANIZATION....... 11 + +5 DEVICE OPERATION.... .12 + +5.1 SPI MODES....... ..... 12 + +5.2 HOLD MODE...... ..... 13 + +5.3 WRITE PROTECTION.... .. 13 + +5.4 POWER OFF TIMING ... . 14 + +6 COMMANDS DESCRIPTION ... .15 + +7 WRITE OPERATIONS ..... + +7.1 WRITE ENABLE (WREN) (06H) ..... . 17 + +7.2 WRITE DISABLE (WRDI) (04H)... . 17 + +8 READ OPERATIONS..... ..18 + +8.1 PAGE READ ....... ..... 18 + +8.2 PAGE READ TO CACHE (13H) . . 19 + +8.3 CACHE READ FUNCTION (31H/3FH).. . 20 + +8.4 READ FROM CACHE (03H OR 0BH)...... + +8.5 READ FROM CACHE X2 (3BH) .... .... 26 + +8.6 READ FROM CACHE X4 (6BH) ...... . 27 + +8.7 READ FROM CACHE DUAL IO (BBH) . .. 28 + +8.8 READ FROM CACHE QUAD IO (EBH)..... + +8.9 READ FROM CACHE QUAD I/O DTR (EEH) . .. 30 + +8.10 READ ID (9FH)...... .... 31 + +8.11 READ UID . 32 + +8.12 READ PARAMETER PAGE..... + +## 9 PROGRAM OPERATIONS.... ..38 + +9.1 PAGE PROGRAM ........ .... 38 +9.2 PROGRAM LOAD (PL) (02H)... .. 39 +9.3 PROGRAM LOAD X4 (PL X4) (32H) ...... +9.4 PROGRAM EXECUTE (PE) (10H) . . 41 +9.5 PROGRAM EXECUTE BACKGROUND (10H + ADDRESS + 15H).. ..... 42 +9.6 INTERNAL DATA MOVE .. . 44 +9.7 PROGRAM LOAD RANDOM DATA (84H) ..... ...... 45 +9.8 PROGRAM LOAD RANDOM DATA X4 (C4H/34H)...... ...... 46 + +## 10 ERASE OPERATIONS .. ..47 + +10.1 BLOCK ERASE (D8H) . . 47 + +## 11 RESET OPERATIONS..... + +11.1 SOFT RESET (FFH) . .. 48 +11.2 ENABLE POWER ON RESET (66H) AND POWER ON RESET (99H).. ..... 49 + +## 12 FEATURE OPERATIONS...... .50 + +12.1 GET FEATURES (0FH) AND SET FEATURES (1FH) . . 50 +12.2 STATUS REGISTER AND DRIVER REGISTER.. . 53 +12.3 OTP REGION....... .... 54 +12.4 ASSISTANT BAD BLOCK MANAGEMENT ... .. 55 +12.5 BLOCK PROTECTION.. .. 56 +12.6 INTERNAL ECC.. . 57 + +## 13 POWER ON TIMING..... .59 + +## 14 ABSOLUTE MAXIMUM RATINGS .... + +## 15 CAPACITANCE MEASUREMENT CONDITIONS..... ....61 + +## 16 DC CHARACTERISTIC .... .....62 + +## 17 AC CHARACTERISTICS ....... .....63 + +## 18 PERFORMANCE AND TIMING .... + +## 19 ORDERING INFORMATION... ...66 + +20 PACKAGE INFORMATION..... ....67 +REVISION HISTORY .... ....70 + +## 1 FEATURE + +◆ 2Gb SLC NAND Flash + +◆ Page Size + +\- Internal ECC On (ECC\_EN=1, default): + +Page Size：2048-Byte+64-Byte + +\- Internal ECC Off (ECC\_EN=0): + +Page Size：2048-Byte+128-Byte + +◆ Standard, Dual, Quad SPI,DTR + +\- Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD# + +\- Dual SPI: SCLK, CS#, SIO0, SIO1, WP#, HOLD# + +\- Quad SPI: SCLK, CS#, SIO0, SIO1, SIO2, SIO3 + +\- DTR(Double Transfer Rate) Read : SCLK, CS#, SIO0, SIO1, SIO2, SIO3, DQS + +◆ High Speed Clock Frequency + +\- 3.3V: 104MHz for fast read with 30pF load + +\- 1.8V: 80MHz for fast read with 30pF load + +\- 3.3V: Quad I/O Data transfer up to 416Mbits/s + +\- 1.8V: Quad I/O Data transfer up to 320Mbits/s + +◆ Software/Hardware Write Protection + +\- Write protect all/portion of memory via software + +\- Register protection with WP# Pin + +◆ Single Power Supply Voltage + +\- Full voltage range for 1.8V: 1.7V \~ 2.0V + +\- Full voltage range for 3.3V: 2.7V \~ 3.6V + +◆ Advanced security Features + +\- 8K-Byte OTP Region + +◆ Program/Erase/Read Speed + +\- Page Program time: 300us typical + +\- Block Erase time: 3ms typical + +\- Page read time: 60us maximum + +◆ Low Power Consumption + +\- 30mA maximum active current + +\- 50uA maximum standby current + +◆ Enhanced access performance + +\- 2Kbyte cache for fast random read + +\- Cache read and cache program + +◆ Advanced Feature for NAND + +\- Factory good block0 + +◆ Reliability- Factory good block0 + +\- P/E cycles with ECC: 100K + +\- Data retention: 10 Years + +◆ Internal ECC + +\- 4bits /528Byte + +Note: (1) ECC is on default, which can be disable by user. + +## 2 GENERAL DESCRIPTION + +SPI (Serial Peripheral Interface) NAND Flash provides an ultra-cost effective while high density non-volatile memory storage solution for embedded systems, based on an industry-standard NAND Flash memory core. It is an attractive alternative to SPI-NOR and standard parallel NAND Flash, with advanced features. + +• Total pin count is 8, including VCC and GND +• Density 2Gb +• Superior write performance and cost per bit over SPI-NOR +• Significant low cost than parallel NAND + +This low-pin-count NAND Flash memory follows the industry-standard serial peripheral interface, and always remains the same pin out from one density to another. The command sets resemble common SPI-NOR command sets, modified to handle NAND specific functions and added new features. GigaDevice SPI NAND is an easy-to-integrate NAND Flash memory, with specified designed features to ease host management: + +• User-selectable internal ECC. ECC parity is generated internally during a page program operation. When a page is read to the cache register, the ECC parity is detected and corrects the errors when necessary. The device outputs corrected data and returns an ECC error status. +• Internal data move or copy back with internal ECC. The device can be easily refreshed and manage garbage collection task, without need of shift in and out of data. This command string can only be used on blocks with the same parity attribute. +• Power on Read with internal ECC. The device will automatically read first page of fist block to cache after power on, then host can directly read data from cache for easy boot. Also the data is promised correct by internal ECC when ECC enabled. + +It is programmed and read in page-based operations, and erased in block-based operations. Data is transferred to or from the NAND Flash memory array, page by page, to a data register and a cache register. The cache register is closest to I/O control circuits and acts as a data buffer for the I/O data; the data register is closest to the memory array and acts as a data buffer for the NAND Flash memory array operation. The cache register functions as the buffer memory to enable page and random data READ/WRITE and copy back operations. These devices also use a SPI status register that reports the status of device operation. + +## 2.1 Product List + +Please contact GigaDevice regional sales for the latest product selection and available form factors + +
Product NumberDensityVoltagePackage TypeTemperature
GD5F2GQ5REYIG2Gbit1.7V to 2.0VWSON8(8*6mm)-40°C to 85°C
GD5F2GQ5REBIG2Gbit1.7V to 2.0VTFBGA24(5*5 Ball Array)-40°C to 85°C
GD5F2GQ5REZIG2Gbit1.7V to 2.0VTFBGA24(4*6 Ball Array)-40°C to 85°C
GD5F2GQ5UEYIG2Gbit2.7V to 3.6VWSON8(8*6mm)-40°C to 85°C
GD5F2GQ5UEBIG2Gbit2.7V to 3.6VTFBGA24(5*5 Ball Array)-40°C to 85°C
GD5F2GQ5UEZIG2Gbit2.7V to 3.6VTFBGA24(4*6 Ball Array)-40°C to 85°C
GD5F2GQ5REYFG*2Gbit1.7V to 2.0VWSON8(8*6mm)-40°C to 85°C
GD5F2GQ5REBFG*2Gbit1.7V to 2.0VTFBGA24(5*5 Ball Array)-40°C to 85°C
GD5F2GQ5REZFG*2Gbit1.7V to 2.0VTFBGA24(4*6 Ball Array)-40°C to 85°C
GD5F2GQ5UEYFG*2Gbit2.7V to 3.6VWSON8(8*6mm)-40°C to 85°C
GD5F2GQ5UEBFG*2Gbit2.7V to 3.6VTFBGA24(5*5 Ball Array)-40°C to 85°C
GD5F2GQ5UEZFG*2Gbit2.7V to 3.6VTFBGA24(4*6 Ball Array)-40°C to 85°C
GD5F2GQ5REYJG2Gbit1.7V to 2.0VWSON8(8*6mm)-40°C to 105°C
GD5F2GQ5REBJG2Gbit1.7V to 2.0VTFBGA24(5*5 Ball Array)-40°C to 105°C
GD5F2GQ5REZJG2Gbit1.7V to 2.0VTFBGA24(4*6 Ball Array)-40°C to 105°C
GD5F2GQ5UEYJG2Gbit2.7V to 3.6VWSON8(8*6mm)-40°C to 105°C
GD5F2GQ5UEBJG2Gbit2.7V to 3.6VTFBGA24(5*5 Ball Array)-40°C to 105°C
GD5F2GQ5UEZJG2Gbit2.7V to 3.6VTFBGA24(4*6 Ball Array)-40°C to 105°C
+ +Note: (1) Industrial+: F grade has implemented additional test flows to ensure higher product quality than I grade. + +## 2.2 CONNECTION DIAGRAM + +Figure 2-1.Connect Diagram +![](images/aabcb50ecd150cac1381cae03d26d2043e276d1247bf7ba20937e6ab3390da9f.jpg) + +![](images/b196abbdc8befa63ccd45faeb7c5c8adae6ca3a07fa73a08d3dce0ccd02f3d92.jpg) + +
+text_image + +Top View +A1 A2 A3 A4 +NC NC NC NC +B1 B2 B3 B4 +NC SCLK VSS VCC +C1 C2 C3 C4 +NC CS# DQS WP#(SIO2) +D1 D2 D3 D4 +NC SO(SIO1) SI(SIO0) HOLD# (SIO3) +E1 E2 E3 E4 +NC NC NC NC +F1 F2 F3 F4 +NC NC NC NC +
+ +24-BALL TFBGA (4x6 ball array) + +## 2.3 PIN DESCRIPTION + +
Pin NameI/ODescription
CS#IChip Select input, active low
SO/SIO1I/OSerial Data Output / Serial Data Input Output 1
WP#/SIO2I/OWrite Protect, active low / Serial Data Input Output 2
VSSGroundGround
SI/SIO0I/OSerial Data Input / Serial Data Input Output 0
SCLKISerial Clock input
HOLD#/SIO3I/OHold Input/Serial Data Input Output 3
DQS (only for BGA24)OData Strobe Signal Output
VCCSupplyPower Supply
NCNot Connect, Not internal connection; can be driven or floated.
+ +Note： +1. CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on. +2. If the DQS Function is not used, this pin must be floating. + +## 2.4 BLOCK DIAGRAM + +Figure 2-2.Block Diagram +![](images/ceba4f83b170efebf3759e0c718679d5ae2af33e9bea308e57867c09d42e091a.jpg) + +
+flowchart + +```mermaid +graph TD + A["DQS"] --> B["Serial NAND controller"] + C["SCLK"] --> B + D["SI/SIO0"] --> B + E["SO/SIO1"] --> B + F["CS#"] --> B + G["HOLD#/SIO3"] --> B + H["WP#/SIO2"] --> B + B --> I["Cache memory"] + I --> J["NAND memory core"] + J --> K["Status register"] + L["Vcc"] --> M["Output"] + N["Vss"] --> M +``` +
+ +## 3 MEMORY MAPPING + +For 2G +![](images/f3958476281234049cbc69364b427e40440d9777400cec28188cdaf1e02c88dc.jpg) + +
+flowchart + +```mermaid +graph LR + subgraph Blocks + A["Blocks\nRA<16:6>"] --> B["0"] + A --> C["1"] + A --> D["2"] + D --> E["2047"] + end + + subgraph Pages + F["Pages\nRA<5:0>"] --> G["0"] + F --> H["1"] + H --> I["63"] + end + + subgraph Bytes + J["Bytes\nCA<11:0>"] --> K["0"] + J --> L["1"] + J --> M["2"] + M --> N["2175"] + end +``` +
+ +Note: +1. CA: Column Address. The 12-bit address is capable of addressing from 0 to 4095 bytes; however, only bytes 0 through 2175 are valid. Bytes 2176 through 4095 of each page are “out of bounds,” do not exist in the device, and cannot be addressed. +2. RA: Row Address. RA<5:0>selects a page inside a block, and RA<16:6>selects a block. + +## 4 ARRAY ORGANIZATION + +Table 3-1.Array Organization + +
Each device hasEach block hasEach page has
2Gb
256M+16M128K+8K2K+128bytes
2048 x 6464-pages
2048--blocks
+ +Figure 3-1. Array Organization + +![](images/fc43d0e740b6032fe3d47e5bf3dc4ee18e86164889ab96549816ee6b0dca0319.jpg) + +
+text_image + +Cache Register +2048 128 +Data Register +2048 128 +Per device: +2Gb: 2048 blocks +1 page = (2K + 128) bytes +1 block = (2K + 128) bytes x 64 pages += (128K + 8K) bytes +1 device = (128K + 8K) bytes x 2048 blocks += 2Gb +
+ +Internal ECC = OFF + +![](images/453b6115979aa006cbf329e3cafc825f3357ee26a83e5f45a17271ac0299de19.jpg) + +
+text_image + +Cache Register +2048 64 +Data Register +2048 64 +Per device: +2Gb: 2048 blocks +1 block +SO +SI +1 page = (2K + 64) bytes +1 block = (2K + 64) bytes x 64 pages += (128K + 4K) bytes +1 device = (128K + 4K) bytes x 2048 blocks += 2Gb +
+ +Internal ECC = ON + +## Note: + +1.When Internal ECC is enabled，user can program the first 64 bytes of the entire 128 bytes spare area and the last 64 bytes of the whole spare area cannot be programed，user can read the entire 128 Byte spare area. +2.When Internal ECC is disabled，user can read and program the entire 128 bytes spare area. + +## 5 DEVICE OPERATION + +## 5.1 SPI Modes + +SPI NAND supports two SPI modes: + +• CPOL = 0, CPHA = 0 (Mode 0) +• CPOL = 1, CPHA = 1 (Mode 3) + +Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK for both modes. All timing diagrams shown in this data sheet are mode 0. See Figure5-1 for more details. + +Figure 5-1. SPI Modes Timing Diagram +![](images/5adddb568ef448df4679e84c8dbeb3c7ac66462b4314ad576c31571a21816932.jpg) +Note: While CS# is HIGH, keep SCLK at VCC or GND (determined by mode 0 or mode 3). Do not toggle SCLK until CS# is driven LOW. +We recommend that the user pull CS# to high when user don’t use SPI flash, otherwise the flash is always in the read state, which is not good for flash. +When CS# is high and SCLK at VCC or GND state, the device is in idle state. + +## Standard SPI + +SPI NAND Flash features a standard serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). + +## Dual SPI + +SPI NAND Flash supports Dual SPI operation when using the x2 and dual IO commands. These commands allow data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: SIO0 and SIO1. + +## Quad SPI + +SPI NAND Flash supports Quad SPI operation when using the x4 and Quad IO commands. These commands allow data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become bidirectional I/O pins: SIO0 and SIO1, and WP# and HOLD# pins become SIO2 and SIO3. + +## DTR Quad SPI + +The device supports DTR Quad SPI operation when using the “DTR Quad I/O Fast Read” command. + +These command allow data to be transferred to or from the device at eight times the rate of the standard SPI, and data output will be latched on both rising and falling edges of the serial clock. When using the DTR Quad SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. DTR Quad SPI commands require the Quad Enable bit (QE) in Status Register to be enable. The device has the DQS pin (Only for BGA24 Package). A data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver + +## 5.2 HOLD Mode + +The HOLD# function is only available when QE=0. If QE=1, the HOLD# functions is disabled, the pin acts as dedicated data I/O pin. + +The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of reading, programming, or erasing in progress. + +The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low). + +The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and then CS# must be at low. + +Figure5-2. Hold Condition +![](images/26cc48d89db717a20fc4ba65d779836eafd444f616474db40cd1a1f0f15f8085.jpg) + +
+text_image + +CS# +SCLK +HOLD# +HOLD→ +HOLD→ +
+ +## 5.3 Write Protection + +SPI NAND provides Hardware Protection Mode besides the Software Mode. Write Protect (WP#) prevents the block lock bits (BP0, BP1, BP2 and INV, CMP) from being over written. If the BRWD bit is set to 1 and WP# is LOW, the block protect bits cannot be altered. + +To enable the Write Protection, the Quad Enable bit (QE) of feature (B0[0]) must be set to 0. + +## 5.4 Power Off Timing + +Please do not turn off the power before Write/Erase operation is completed. Avoid using the device when the battery is low. Power shortage and/or power failure before Write/Erase operation is complete will cause loss of data and/or damage to data. + +## 6 COMMANDS DESCRIPTION + +Table 6-1. Commands Set + +
Command NameByte1Byte2Byte3Byte4Byte5Byte6Byte 7
Write Enable06H
Write Disable04H
Get Features0FHA7-A0D7-D0 $Wrap^{(7)}$
Set Feature1FHA7-A0D7-D0
Page Read (to cache)13HA23-A16A15-A8A7-A0
Next Page Read (to cache)31H
Next Page Cache Read Random13HA23-A16A15-A8A7-A031H
Last Page Read (to cache)3FH
Read From Cache03H/0BHA15-A8 $A7-A0^{(2)}$ $Dummy^{(1)}$ D7-D0
Read From Cache x 23BHA15-A8 $A7-A0^{(2)}$ $Dummy^{(1)}$ D7-D0
Read From Cache x 46BHA15-A8 $A7-A0^{(2)}$ $Dummy^{(1)}$ D7-D0
Read From Cache Dual IOBBHA15-A8 $A7-A0^{(2)}$ $Dummyx2^{(1)}$ D7-D0
Read From Cache Quad IOEBHA15-A8 $A7-A0^{(2)}$ $Dummyx4^{(1)}$ D7-D0
Read From Cache Quad I/O DTREEHA31-A24A23-A16A15-A8 $A7-A0^{(2)}$ Dummy $x8^{(1)}$ D7-D0
$Read ID^{(4)}$ 9FHDummyMIDDID
Read parameter page13H00H00H04H
Read UID13H00H00H06H
Program Load02HA15-A8 $A7-A0^{(3)}$ D7-D0Next byte
Program Load x432HA15-A8 $A7-A0^{(3)}$ D7-D0Next byte
Program Execute10HA23-A16A15-A8A7-A0
Program Execute Background10HA23-A16A15-A8A7-A015H
Program Load Random Data84HA15-A8 $A7-A0^{(3)}$ D7-D0Next byte
Program Load Random Data x4C4H/34HA15-A8 $A7-A0^{(3)}$ D7-D0Next byte
Block Erase(128K)D8HA23-A16A15-A8A7-A0
$Reset^{(5)}$ FFH
Enable Power on Reset66h
$Power on Reset^{(6)}$ 99h
+ +## Note: + +1. The dummy has 8 clock. +03H/0BH/3BH/6BH has 1 byte dummy. BBH has 2 bytes dummy. +EBH has 4 bytes dummy. EEH has 8 bytes dummy. + +2. The A15-A0 (03H/0BH/3BH/6BH) has 16 clock, include 4 clock dummy. + +The A15-A0 (BBH) has 8 clock, include 2 clock dummy. + +The A15-A0 (EBH) has 4 clock, include 1 clock dummy. + +The A31-A0 (EEH) has 4 clock, include 2.5 clock dummy. + +3. The A15-A0 has 16 clock, include 4 clock dummy. +4. MID is Manufacture ID (C8h for GigaDevice), DID is Device ID. +5. Reset command: + +• Reset will reset PAGE READ/PROGRAM/ERASE operation. +• Reset will reset status register bits P\_FAIL/E\_FAIL/WEL/OIP/CBSY/ECCS/ECCSE. +6. Power on reset: + +Retrieve status register and data in cache to power on status. + +7. The output would be updated by real-time, until CS# is driven high. + +## 7 WRITE OPERATIONS + +## 7.1 Write Enable (WREN) (06H) + +The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to following operations that change the contents of the memory array: + +• Page program +• OTP program/OTP protection +• Block erase + +The WEL bit can be cleared after a reset command. + +Figure 7-1.Write Enable Timing Diagram +![](images/343f7b3c31c7222d5f6f45041cdcd903fbb8b6f15ea145f0a79be413b11bbf7b.jpg) + +
+text_image + +CS# +0 1 2 3 4 5 6 7 +SCLK +Command +SI +06H +High-Z +SO +
+ +## 7.2 Write Disable (WRDI) (04H) + +The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The WEL bit is reset by following condition: + +• Page program +• OTP program/OTP protection +• Block erase + +Figure 7-2.Write Disable Timing Diagram +![](images/7441b7c3bb1b3d617b08706cc77d8099c3e619b8f2ad82d6751a3fd0bf589a1c.jpg) + +
+text_image + +CS# +0 1 2 3 4 5 6 7 +SCLK +Command +SI +04H +High-Z +SO +
+ +## 8 READ OPERATIONS + +## 8.1 Page Read + +The PAGE READ (13H) command transfers the data from the NAND Flash array to the cache register. The command sequence is as follows: + +• 13H (PAGE READ to cache) +• 0FH (GET FEATURES command to read the status) +• 03H or 0BH (Read from cache)/3BH (Read from cache x2)/6BH (Read from cache x4)/BBH/EBH/EEH (Read from cache DTR x4) + +The PAGE READ command requires a 24-bit address. After the block/page addresses are registered, the device starts the transfer from the main array to the cache register, and is busy for tRD time. During this time, the GET FEATURE (0FH) command can be issued to monitor the status. Followed the page read operation, the RANDOM DATA READ (03H/0BH/3BH/6BH/EEH) command must be issued in order to read out the data from cache. The output data starts at the initial address specified in the command, once it reaches the ending boundary of whole page section, the output will wrap around from the beginning boundary until CS# is pulled high to terminate this operation. Refer waveforms to view the entire READ operation. + +Note:(1) The command 6BH (Read from cache x4)/EBH (Read from cache Quad IO)/EEH (Read from cache Quad IO DTR) is only available with the QE enable. +(2) When user read to the end of 64-Byte spare area, it won’t wrap around from the beginning boundary and an additional 64Byte ECC code will be read. (Internal ECC enabled) + +## 8.2 Page Read to Cache (13H) + +The command page read to cache is read the data from flash array to cache register. + +Figure 8-1.Page Read to cache Timing Diagram +![](images/4af5305727b1bb17fb0a9669a56b6401806a645327f604a28dc2c9743ba940ea.jpg) + +## 8.3 Cache Read Function (31H/3FH) + +A “Cache Read” function has been implemented in SPI series to improve the overall read throughput. It is possible to transfer the data from array to the Data Register simultaneously while a Read Data command is being performed to read out data from the Cache Register. + +When multiple pages of data is to be read out sequentially, the host should issue a “Page Read to Cache (13h)” command followed by a Page Address which specifies the starting page of the data(1). Once the command is accepted, the host should use “Get Feature (0Fh)” to check the OIP bit value to determine if the internal operation has completed or not. + +Prior to issuing a Read Data command (i.e. 03h/0Bh/3Bh/6Bh/BBh/EBh) to read out the data in the Cache Register, the host can issue a “Next Page Cache Read (31h)” command to initiate the Cache Read operation. There is not necessary to provide any Page Address since the device will automatically increment the Page Address specified earlier by “Page Read to Cache (13h)” instruction. After the “Next Page Cache Read” (31h) command issued, the device starts to transfer data from data register to cache register for tCBSYR. And CBSY bit (through GET FEATURE command to check this status bit) goes to 1 from 0. + +While the device is transferring the next page array data to the Data Register, the host can now use Read From Cache command to shift out the current page data inside the Cache Register. Once CBSY bit becomes 0, the host can issue a Read Data command to shift out the Cache Register data, then issue “Next Page Cache Read (31h)” again to read the next page in the array. + +If the current page address is the last page of a block or the last page of the data being read out, the host should issue “Last Page Cache Read (3Fh)” instead of “Next Page Cache Read (31h)”, and proceed with the last Read from cache command. If the data being read out is more than one block, another “Page Read to Cache (13h)” command is needed to specify the first page of the next block and initiate the “Cache Read” operation again in the next block. + +Table 8-1.Cache Read instruction description + +
InstructionCommand CodeDescription
Next Page Cache Read31hIssue prior to current page “Read From Cache” and read next page data into Data Register.
Next Page Cache Read Random13h+addr+31hIssue prior to current page “Read From Cache” and read special page data into Data Register.
Last Page Cache Read3FhIssue prior to last page “Read From Cache” at the end of a block or the end of the data being read.
+ +## Notes: + +1. Upon powered up, SPI NAND will automatically load Block-0/Page-0 data into the Cache Register. If this is the starting page of the data that is to be read out, it is not necessary to issue a “Page Read to Cache (13h)” command to initiate the “Cache Read” operation. +2. Before issuing 31h/3Fh, CBSY bit must be checked to make sure CBSY=0, device is not performing any internal operations. + +The command sequence is as follows: + +• 13H (PAGE READ to cache) +• 0FH (GET FEATURES command to read the status until OIP status bit is changed from 1 to 0) +• 31H (NEXT PAGE CACHE READ command to transfer data from data register to cache register and kick off the next page transfer from array to data register) +• 0FH (GET FEATURES command to read the status until CBSY=0) +• 03H or 0BH (Read from cache)/3BH (Read from cache x2)/6BH (Read from cache x4)/BBH/EBH/EEH (Read from cache DTR x4) +• 3FH (LAST PAGE CACHE READ command to end the read page cache sequence and copy a last page from the data register to cache register) +• 0FH (GET FEATURES command to read the status until CBSY=0) +• 03H or 0BH (Read from cache)/3BH (Read from cache x2)/6BH (Read from cache x4)/BBH/EBH/EEH (Read from cache DTR x4) + +Figure 8-2.Cache Read operation flow chart +![](images/e3503671df72f45ed106fb3d776cc9470593584d6bad0a8b281258044b32c694.jpg) + +
+flowchart + +```mermaid +graph TD + Start["Start Cache Read"] --> PageRead["Page Read\n(Page N)"] + PageRead --> CheckIOIP{"OIP=0?"} + CheckIOIP -->|N| NextPageRead["Next Page Read\n(Page n+1)"] + CheckIOIP -->|Y| NextPageRead + NextPageRead --> CheckCBSY{"CBSY=0?"} + CheckCBSY -->|N| NextPageRead + CheckCBSY -->|Y| ReadData["Read Data\n(Page N)"] + ReadData --> N+1["N=N+1"] + N1["N+1"] --> CheckEOB{"N=EOB or EOD?"} + CheckEOB -->|N| NextPageRead + CheckEOB -->|Y| ReadData + ReadData --> Done["Done"] + NextPageRead --> CheckCBSY{"CBSY=0?"} + CheckCBSY -->|N| LastPageRead["Last Page Read\n(Page M)"] + LastPageRead --> CheckCBSY + CheckCBSY -->|Y| ReadData + ReadData --> Done + CheckCBSY -->|N| LastPageRead + CheckCBSY -->|Y| ReadData +``` +
+ +Figure 8-3.Page Read to Cache Timing Diagram +![](images/ea8cff647c04b2e0ac8d1a3060e1bd9d9c4f50cbd06ce45c8542cc1559200a18.jpg) + +
+text_image + +CS# +0 1 2 3 4 5 6 7 +SCLK +Command +SI +31H +SO +High-Z +CS# +0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +SLK +tCS +Get Feature +1 byte address +SI +0FH +7 6 5 4 3 2 1 0 +SO +High-Z +MSB +CS# +16 17 18 19 20 21 22 23 24 +SCLK +SI +Data byte +SO +7 6 5 4 3 2 1 0 7 +MSB +
+ +Figure 8-4.Page Read to Cache Timing Diagram + +![](images/ea764a257b8125933e6403664d7a9d31cec67e8730b18b3daeafca6a3145a3f4.jpg) + +
+text_image + +CS# +0 1 2 3 4 5 6 7 8 9 10 +SCLK +Command +24-bit address +SI +13H +23 22 21 +3 2 1 0 +31H +SO +High-Z +CS# +0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +SLK +tCS +Get Feature +1 byte address +SI +0FH +7 6 5 4 3 2 1 0 +SO +High-Z +MSB +CS# +16 17 18 19 20 21 22 23 24 +SCLK +SI +Data byte +SO +7 6 5 4 3 2 1 0 7 +MSB +
+ +Figure 8-5.Page Read to Cache Timing Diagram +![](images/31c34d53aa5fbde9fac6df83c5c12c8dbd4bfd5158ed1898f585f3103e18bb97.jpg) + +
+text_image + +CS# +0 1 2 3 4 5 6 7 +SCLK +Command +SI +3FH +SO +High-Z +CS# +0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +SLK +tCS +Get Feature +1 byte address +SI +0FH +7 6 5 4 3 2 1 0 +SO +High-Z +MSB +CS# +16 17 18 19 20 21 22 23 24 +SCLK +SI +Data byte +SO +7 6 5 4 3 2 1 0 7 +MSB +
+ +Figure 8-6.Page Read to Cache Timing Diagram +![](images/339900a74423153c5c2f48ae3b9f82a7f463ca764e808410d077aa8b6ca0c835.jpg) + +
+text_image + +CS# +0 1 2 3 4 5 6 7 8 9 10 +SCLK +Page Read +24-bit address +tRD +Cache Read +0 1 2 3 4 5 6 7 +SI +13H +MSB +3 2 1 0 +SO +High-Z +CS# +0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +SCLK +tCBSYR +Read From Cache +Dummy<3:0> +A11-A0 +Dummy byte +Data byte 0 +SI +03H +0 0 0 0 11 10 +SO +High-Z +MSB +CS# +0 1 2 3 4 5 6 7 +SCLK +0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +SI +31H +tCBSYR +Read From Cache +Dummy<3:0> +A11-A0 +Dummy byte +Data byte 0 +SO +High-Z +CS# +32 33 34 35 36 37 38 39 +SCLK +Data byte 0 +SI +3FH +Last Page Read +tCBSYR +Read From Cache +03H +SO +7 6 5 4 3 2 1 0 +MSB +CS# +8 9 10 11 12 13 14 +SCLK +Dummy<3:0> +A11-A0 +Dummy byte +Data byte 0 +Data byte 1 +Data byte N +SI +0 0 0 0 11 10 +3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 +
+ +## Note： + +1. Command 03h/0Bh/3Bh/6Bh/BBh/EBh is available to read out the data in the Cache Register. +2. For high speed performance, we recommend to use EBh to read out the data in the Cache Register. (Please refer to 8.8 Read From Cache Quad IO) +3. We recommend to use GET FEATURES command (0Fh) to read the status until CBSY=0. + +## 8.4 Read From Cache (03H or 0BH) + +The command sequence is shown below. + +Figure 8-7.Read From Cache Timing Diagram +![](images/09c5172dc7c3328e5e10b532a26a7e97ffd02c5da26241e7ee3520222914159f.jpg) + +
+text_image + +CS# +SCLK +Command +Dummy<3:0> +A11-A0 +SI +03H or 0BH +0 0 0 0 11 10 +3 2 1 0 +SO +High-Z +CS# +SCLK +Dummy byte +SI +7 6 5 4 3 2 1 0 +Data byte 0 +SO +7 6 5 4 3 2 1 0 +Data byte 1 +MSB +MSB +
+ +## 8.5 Read From Cache x2 (3BH) + +The command sequence is shown below. + +Figure 8-8.Read From Cache x2 Timing Diagram +![](images/c935e090628694cb5b7c2d5b5e5cdd970504fbe6ce4b4164ea41e6d1a37437bf.jpg) + +
+text_image + +CS# +SCLK +Command +Dummy<3:0> +A11-A0 +SI/SIO0 +3BH +0 0 0 0 11 10 +3 2 1 0 +SO/SIO1 +High-Z +CS# +SCLK +Dummy byte +SI/SIO0 +7 6 5 4 3 2 1 0 +6 4 2 0 +6 4 2 0 +6 4 2 +SO/SIO1 +Data byte 0 +Data byte 1 +MSB +MSB +7 5 3 1 +7 5 3 1 +7 5 3 +
+ +## 8.6 Read From Cache x4 (6BH) + +The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read from cache x4 command. The command sequence is shown below. + +Figure 8-9.Read From Cache x4 Timing Diagram +![](images/4654ffcb1c75a72cebdd19cdd5562ac345b2d2f84f37efb7cce5ac83a3043823.jpg) + +
+text_image + +CS# +0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 22 23 +SCLK +Command Dummy<3:0> A11-A0 +SI(SIO0) 6BH 0 0 0 0 11 10 3 2 1 0 +SO(SIO1) High-Z +WP#(SIO2) High-Z +HOLD#(SIO3) High-Z +CS# +24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 +SCLK Dummy byte +SI(SIO0) 7 6 5 4 3 2 1 0 4 0 4 0 4 0 4 0 4 +SO(SIO1) 5 1 5 1 5 1 5 1 5 +WP#(SIO2) 6 2 6 2 6 2 6 2 6 +HOLD#(SIO3) 7 3 7 3 7 3 7 3 7 +Byte0 Byte1 Byte2 Byte3 +
+ +## 8.7 Read From Cache Dual IO (BBH) + +The Read from Cache Dual I/O command (BBH) is similar to the Read form Cache x2 command (3BH) but with the capability to input the 4 Dummy bits, followed by a 12-bit column address for the starting byte address and dummy bytes by SIO0 and SIO1, each bit being latched in during the rising edge of SCLK, then the cache contents are shifted out 2-bit per clock cycle from SIO0 and SIO1. The first address byte can be at any location. The address increments automatically to the next higher address after each byte of data shifted out. The command sequence is shown below. + +Figure 8-10.Read From Cache Dual IO Timing Diagram +![](images/e2e726866d1895649ec7e388b5035a8500e43a91b7baa3d45c2c7f0637baad86.jpg) + +
+text_image + +CS# +SCLK +Command +Dummy +<3:0> +A11-A0 +BBH +Dummy +SI(SIO0) +SO(SIO1) +CS# +SCLK +SI(SIO0) +SO(SIO1) +Data +byte 0 +Data +byte 1 +Data +byte 2 +Data +byte 3 +Data +byte 0 +Data +byte 1 +Data +byte 2 +Data +byte 3 +
+ +## 8.8 Read From Cache Quad IO (EBH) + +The Read from Cache Quad IO command is similar to the Read from Cache x4 command but with the capability to input the 4 dummy bits, followed a 12-bit column address for the starting byte address and dummy bytes by SIO0, SIO1, SIO3, SIO4, each bit being latched in during the rising edge of SCLK, then the cache contents are shifted out 4-bit per clock cycle from SIO0, SIO1, SIO2, SIO3. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read from cache quad IO command. The command sequence is shown below. + +Figure 8-11.Read From Cache Quad IO Timing Diagram +![](images/b4f48eb41fe925af5d8eefab289e736bdec20ce1083c66cc7aabc2b65ef62d11.jpg) + +
+text_image + +CS# +SCLK +Command Dummy +3:0 +SI(SIO0) EBH +SO(SIO1) +WP#(SIO2) +HOLD#(SIO3) +A11 - A0 Dummy Byte0 Byte1 +
+ +## 8.9 Read From Cache Quad I/O DTR (EEH) + +The DTR QIO command enables Double Transfer Rate throughput on quad I/O of Serial Flash in read mode. A Quad Enable (QE) bit of status Register must be set to “1” before sending the DTR QIO command. The address (interleave on 4 I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on 4 I/O pins) shift out on both rising and falling edge of SCLK. The 8-bit address can be latched-in at one clock, and 8-bit data can be read out at one clock, which means four bits at rising edge of clock, the other four bits at falling edge of clock. + +The first address Byte can be at any location. The address is automatically increased to the next higher address after each Byte data is shifted out, so the whole page can be read out at a single DTR QIO command. The address counter rolls over to 0 when the highest address has been reached. + +Figure 8-12.Read From Cache Quad I/O DTR Timing Diagram +![](images/65b603938a3331f3f449c2c6ed5cd6aa5126d90244b8116c97c76afa4d3407f1.jpg) + +
+text_image + +CS# +SCLK +Command +EEH +SI(IO0) +Dummy +<19:0> +Dummy +4 0 4 0 +SO(IO1) +0 0 0 0 0 9 5 1 +5 1 5 1 +DQS +IO2 +0 0 0 0 0 10 6 2 +6 2 6 2 +IO3 +0 0 0 0 0 11 7 3 +A11-A0 +Byte 0Byte 1 +19 20 +
+ +## Note: + +Please contact GigaDevice when there is a need to use the EEh command for DTR. + +The max clock rate for DTR depends on the tCLQV (clock to data output valid). Per datasheet, with output load capacitance of 30pf, the tCLQV is about 11ns. This will limit the max rate to 45Mhz. + +However, in general, most of PCB designs have output loading much less than 30pf. Lower output loading will in turn shorten the tCLQV and result in higher max clock rate. + +GigaDevice recommend customers measure the tCLQV and then set the clock rate to match the SPI host data sampling data setup time and hold time. + +## 8.10 Read ID (9FH) + +The READ ID command is used to identify the NAND Flash device. + +• With address 00H, the READ ID command outputs the Manufacturer ID and the device ID. See Table 8-2 for details. + +Figure 8-13.Read ID Timing Diagram +![](images/4fdbdfd9298bda9175599f45dc0d85b9a37c97dcb8ce4fdf5f0e2037c6691d9f.jpg) + +
+text_image + +CS# +0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +SCLK +Command +Dummy +SI +9FH +7 6 5 4 3 2 1 0 +SO +High-Z +CS# +16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 +SCLK +SI +Manufacturer ID +Device ID +SO +7 6 5 4 3 2 1 0 +MSB +MSB +
+ +Table 8-2. READ ID Table + +
Part NoMIDDID1
GD5F2GQ5UExxGC8H52H
GD5F2GQ5RExxGC8H42H
+ +## 8.11 Read UID + +The Read Unique ID function is used to retrieve the 16 bytes unique ID (UID) for the device. The unique ID when combined with the device manufacturer shall be unique. + +The UID data may be stored within the Flash array. To allow the host to determine if the UID is without bit errors, the UID is returned with its complement. If the XOR of the UID and its bit-wise complement is all ones, then the UID is valid. To accommodate robust retrieval of the UID in the case of bit errors, sixteen copies of the UID and the corresponding complement are stored by the target. For example, reading byte 32-63 returns to the host another copies of the UID and its complement. + +
BytesValue
0-15UID
16-31UID complement (bit-wise)
+ +## Sequence is as follows: + +1. Use Set Feature command to set B0 register, to enable OTP\_EN. +2. Use Get Feature command to get data from B0 register and check if the OTP\_EN is enable. +3. Use Page Read to Cache (13h) command with address 24’h000006h, read data from array to cache. +4. Use 0FH (GET FEATURES command) read the status. +5. User can use Read from cache command (03H/0BH), read 16 bytes UID from cache. + +Figure 8-14. Read UID to cache and Get Feature command Timing Diagram +![](images/64d79f7353b7ae65411a1c43d8d7b3d0a12c6e96df699da85b21a00f2133abad.jpg) + +
+text_image + +CS# +0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 +SCLK +SI +Command +24-bit address +13H +000006H +SO +High-Z +CS# +0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +SLK +tCS +Get Feature +1 byte address +SI +0FH +7 6 5 4 3 2 1 0 +SO +High-Z +MSB +CS# +16 17 18 19 20 21 22 23 24 +SCLK +SI +Data byte +SO +7 6 5 4 3 2 1 0 7 +MSB +
+ +## 8.12 Read Parameter Page + +The Read Parameter Page function retrieves the data structure that describes the chip’s organization, features, timing and other behavioral parameters. This data structure enables the host processor to automatically recognize the SPI-NAND Flash configuration of a device. A minimum of three copies of the parameter page are stored in the device. The Read from Cache command can be used to change the location of data output. + +Sequences as follows: + +1. Use Set Feature command to set B0 register, to enable OTP\_EN. +2. Use Get Feature command to get data from B0 register and check if the OTP\_EN is enable. +3. Use Page Read to Cache (13h) command with address 24’h000004. Load parameter page from array to cache. +4. Use 0Fh (GET FEATURES command) read the status +5. User can use Read from cache command (03h/0Bh), read parameter page from cache. + +Figure 8-15. Read parameter page to cache and Get Feature command Timing Diagram +![](images/09ca7246ee158e984bf4611476216ff1782ecd917d21b0a0ccc3d34b29398ee8.jpg) + +Parameter page table as follow + +
ByteO/MDescription3.3V/1.8V
0-3MParameter page signature4FH
Byte 0: 4FH, “O”4EH
Byte 1: 4EH, “N”46H
Byte 2: 46H, “F”49H
Byte 3: 49H, “I”
4-5MRevision number00H
0-15 Reserved (0)00H
6-7MFeatures supported00H
0-15 Reserved (0)00H
8-9MReserved (0)00H
00H
10-31Reserved (0)00H
...
00H
Manufacturer Information block
32-43MDevice manufacturer (12 ASCII characters)“GIGADEVICE ”47H
49H
47H
41H
44H
45H
56H
49H
43H
45H
20H
20H
44-63MDevice model (20 ASCII characters)47H
Device ModelORGANIZATIONVCC RANGE44H
“GD5F2GQ5U”X42.7v ~ 3.6v35H
“GD5F2GQ5R”X41.7v ~ 2.0v46H
32H
47H
51H
35H
55H/52H
20H
20H
20H
20H
20H
+ +
20H20H20H20H20H
64MJEDEC manufacturer ID“C8”C8H
65-66ODate code00H00H
67-79Reserved00H00H00H
Memory organization block
80-83MNumber of data bytes per page00H08H00H00H
84-85MNumber of spare bytes per page80H00H
86-89MNumber of data bytes per partial page00H02H00H00H
90-91MNumber of spare bytes per partial page20H00H
92-95MNumber of pages per block40H00H00H00H
96-99MNumber of blocks per logical unit00H08H00H00H
100MNumber of logical units01H
101MReserved00H
102MNumber of bits per cell01H
103-104MBad blocks maximum per logical unit28H00H
105-106MBlock endurance01H05H
107MGuaranteed valid blocks at beginning of target01H
108-109MBlock endurance for guaranteed valid blocks00H00H
110MNumber of programs per page04H
111MPartial programming attributes5-7 Reserved4 1 = partial page layout is partial page data followed by partial page spare1-3 Reserved0 1 = partial page programming has constraints00H
112MNumber of bits ECC correctability00H
113MNumber of interleaved address bits4-7 Reserved (0)0-3 Number of interleaved address bits00H
114OInterleaved operation attributes4-7 Reserved (0)3 Address restrictions for program cache2 1 = program cache supported1 1 = no block address restrictions0 Overlapped / concurrent interleaving support00H
115-127Reserved00H...00H
Electrical parameters block
128MI/O capacitance06H
129-130MIO clock support3-1 5 Reserved (0)2 1 = supports 80MHz1 1 = supports 104MHz0 1 = supports 120MHz02H/04H00H
131-132OReserved (0)00H00H
133-134MtPROG Maximum page program time (us)58H02H
135-136MtBERS Maximum block erase time (us)88H13H
137-138MtR Maximum page read time (us)3CH00H
139-140MReserved00H00H
141-163Reserved00H
Vendor block
164-165MVendor specific Revision number00H
166-253Vendor specific00H
254-255MIntegrity CRCSet on test
Redundant parameter pages
256-511MValue of bytes 0-255
512-767MValue of bytes 0-255
768+OAdditional redundant parameter pages
+ +## Notes: + +1. “O” Stands for Optional, “M” for Mandatory +2. The Integrity CRC (Cycling Redundancy Check) field is used to verify that the contents of the parameters page were transferred correctly to the host. Please refer to ONFI 1.0 specifications for details. The CRC shall be calculated using the following 16-bit generator polynomial: $\mathsf { G } ( \mathsf { X } ) = \mathsf { X } ^ { 1 6 } + \mathsf { X } ^ { 1 5 } + \mathsf { X } ^ { 2 } + 1$ ，This polynomial in hex may be represented as 8005h. +3．The CRC value shall be initialized with a value of 4F4Eh before the calculation begins. There is no XOR applied to the final CRC value after it is calculated. There is no reversal of the data bytes or the CRC calculated value. + +
Device ModelORGANIZATIONVCC RANGECRC value B254/B255
“GD5F2GQ5UxxxG”X42.7v ~ 3.6v5BH/05H
“GD5F2GQ5RxxxG”X41.7v ~ 2.0v96H/48H
+ +## 9 PROGRAM OPERATIONS + +## 9.1 Page Program + +The PAGE PROGRAM operation sequence programs 1 byte to whole page bytes of data within a page. The page program sequence is as follows: + +• 02H (PROGRAM LOAD)/32H (PROGRAM LOAD x4) +• 06H (WRITE ENABLE) +• 10H (PROGRAM EXECUTE) +• 0FH (GET FEATURE command to read the status) + +Firstly, a PROGRAM LOAD (02H/32H) command is issued. PROGRAM LOAD consists of an 8-bit Op code, followed by 4 dummy bits and a 12-bit column address, then the data bytes to be programmed. The Program address should be in sequential order in a block. The data bytes are loaded into a cache register that is whole page long. If more than one page data are loaded, then those additional bytes are ignored by the cache register. The command sequence ends when CS# goes from LOW to HIGH. Figure 9-1 shows the PROGRAM LOAD operation. Secondly, prior to performing the PROGRAM EXECUTE operation, a WRITE ENABLE (06H) command must be issued. As with any command that changes the memory contents, the WRITE ENABLE must be executed in order to set the WEL bit. If this command is not issued, then the rest of the program sequence is ignored. + +## Note: + +1. The contents of Cache Register don’t reset when Program Random Load (84h) command and RESET (FFh) command. +2. When Program Execute (10h) command was issued just after Program Load (02h) command, the 0xFF is output to the address that data was not loaded by Program Load (02h) command. +3. When Program Execute (10h) command was issued just after Program Load Random Data (84h) command, the contents of Cache Register are output to the NAND array. +4. The Program address should be in sequential order in a block. +5. Program Load x4 is only available with the QE enable. + +## 9.2 Program Load (PL) (02H) + +The command sequence is shown below. + +Figure 9-1. Program Load Timing Diagram +![](images/96a851b255ea13b19d69011401becadc5fda55a205daa3061da824f5d39269bb.jpg) + +
+text_image + +CS# +SCLK +SI +Command +Dummy<3:0> +A11-A0 +02H +0 0 0 0 1 10 +3 2 1 0 +CS# +SCLK +SI +24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 +Data byte 0 +Data byte 1 +Data byte N +MSB +
+ +Note: When internal ECC disabled the Data Byte is 2176, when internal ECC enabled the Data Byte is 2112. + +## 9.3 Program Load x4 (PL x4) (32H) + +The Program Load x4 command (32H) is similar to the Program Load command (02H) but with the capability to input the data bytes by four pins: SIO0, SIO1, SIO2, and SIO3. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the program load x4 command. The command sequence is shown below. + +Figure 9-2. Program Load x4 Timing Diagram +![](images/b660c2be6cd0f35871a725005cd39d61d55e0712c188b10f3060221330d68b26.jpg) +Note: When internal ECC disabled the Data Byte is 2176, when internal ECC enabled the Data Byte is 2112. + +## 9.4 Program Execute (PE) (10H) + +After the data is loaded, a PROGRAM EXECUTE (10H) command must be issued to initiate the transfer of data from the cache registers to the main array. PROGRAM EXECUTE consists of an 8-bit Op code, followed by a 24-bit address. After the page/block address is registered, the memory device starts the transfer from the cache register to the main array, and is busy for tPROG time. This operation shown in Figure 9-3. During this busy time, the status register can be polled to monitor the status of the operation (refer to Status Register). When the operation completes successfully, the next series of data can be loaded with the PROGRAM LOAD command. + +Figure 9-3. Program Execute Timing Diagram +![](images/23355b92f7c8598e09f40a15770d923a15aee870f89915343a1335487c3e83b6.jpg) + +## 9.5 Program Execute Background (10h + address + 15h) + +A “Cache Program” function has been implemented in SPI series to improve the overall program throughput. It is possible to program the data from Data Register to array the simultaneously while a Load Data command is being performed to write data to the Cache Register. + +When multiple pages of data is to be program sequentially, the host should issue a “Program Load (02h)” command followed by a Column Address and data written. When the command is accepted, the host should use Program Execute Background（10h+address+15h）to initial the internal program operation, then the CBSY becomes 1. + +Once the CBSY becomes 0, user can issue again the “Program Load (02h)” command followed by a Page Address and data written. Then user can send Program Execute Background command to continue the cache program. + +When the last page of one block to be program and the OIP bit is 0, the program execute command (10h+address) should be used to finish the last program operation. + +The program execute command (10h+address+15h) is allowed to cross blocks before reaching the last block. + +Figure 9-4. Program Execute Background Operation Flow Chart +![](images/305761c95e760f28ce942527a3b942b95011ae4b7b7fb6b139818940ca41ae56.jpg) + +
+flowchart + +```mermaid +graph TD + Start(["Start cache Program"]) --> PageN["Page N"] + PageN --> PageLoad["Page Load\n(Page N)"] + PageLoad --> Background["Program execute background"] + Background --> CBSY{"CBSY = 0 ? (tCBSYW)"} + CBSY -->|N| Background + CBSY -->|Y| PageN1["Page N+1"] + PageN1 --> LastPage{"Last Page"} + LastPage -->|N| PageLoad + LastPage -->|Y| PageLoad + PageLoad --> OIP{"OIP = 0 ?"} + OIP -->|N| PageLoad + OIP -->|Y| ProgramExecute["Program Execute"] + ProgramExecute --> Done["Done"] +``` +
+ +Figure 9-5. Program Execute Background Timing +![](images/58ae5c4adb2ba5406689db21c0730acd47b49e05982433f44acabd1fbf1353e2.jpg) + +
+text_image + +CS# +SCLK +SI +02H +22 23 +Command +Dummy<3:0>,A11-A0 +Data 0 +Data N +SO +High-Z +CS# +SCLK +SI +10H +23 22 +30 31 32 33 38 39 +Command +24-bit address +Page addr M +Command +tCBSYW +Command +15H +02H +SO +High-Z +CS# +SCLK +SI +8 9 +22 23 +Dummy<3:0>,A11-A0 +Data 0 +Data N +Wait OIP Ready +0 1 4 5 6 +24-bit address +Page addr N +tPROG +SO +High-Z +CS# +SCLK +SI +10H +23 22 +30 31 +Command +1 0 +1 0 +SO +High-Z +
+ +## 9.6 Internal Data Move + +The INTERNAL DATA MOVE command sequence programs or replaces data in a page with existing data. The INTERNAL DATA MOVE command sequence is as follows: + +• 13H (PAGE READ to cache) +• Optional 84H/C4H/34H (PROGRAM LOAD RANDOM DATA) +• 06H (WRITE ENABLE) +• 10H (PROGRAM EXECUTE) +• 0FH (GET FEATURE command to read the status) + +Prior to performing an internal data move operation, the target page content must be read out into the cache register by issuing a PAGE READ (13H) command. The PROGRAM LOAD RANDOM DATA (84H/C4H) command can be issued, if user wants to update bytes of data in the page. New data is loaded in the 12-bit column address. If the random data is not sequential, another PROGRAM LOAD RANDOM DATA (84H/C4H) command must be issued with the new column address. After the data is loaded, the WRITE ENABLE command must be issued, and then PROGRAMEXECUTE (10H) command can be issued to start the programming operation. Only the block with the same parity attribute can use the command. + +## 9.7 Program Load Random Data (84H) + +The Program Load Random Data command programs or replaces data in a page with existing data. This command consists of an 8-bit Op code, followed by 4 dummy bits, and a 12-bit column address. New data is loaded in the column address provided with the 12 bits. If the random data is not sequential, then another PROGRAM LOAD RANDOM DATA (84H) command must be issued with a new column address, see Figure 9-6 for details. + +Figure 9-6. Program Load Random Data Timing Diagram +![](images/3a5cd052e863303d1a72acb4cfc8001882b3bba1c697960e9933f0d3ced6b269.jpg) + +
+text_image + +CS# +0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 22 23 +SCLK +Command Dummy<3:0> A11 - A0 +SI 84H 0 0 0 0 1 1 10 3 2 1 0 +CS# +24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 +SCLK +Data byte 0 Data byte 1 Data byte N +SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 +MSB +
+ +## 9.8 Program Load Random Data x4 (C4H/34H) + +The Program Load Random Data x4 command (C4H/34H) is similar to the Program Load Random Data command (84H) but with the capability to input the data bytes by four pins: SIO0, SIO1, SIO2, and SIO3. The command sequence is shown below. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable for the program load random data x4 command. See Figure 9-7 for details. + +Figure 9-7. Program Load Random Data x4 Timing Diagram +![](images/d2689b1999b01197d306d53971378631bbe3472f017cbb2affe7c340e362d484.jpg) + +
+text_image + +CS# +SCLK +Command Dummy<3:0> A11 - A0 Byte 0 Byte 1 +SI(SIO0) C4H/34H 0 0 0 0 11 1 0 4 0 4 0 4 0 4 0 +SO(SIO1) +WP#(SIO2) +HOLD#(SIO3) +CS# +SCLK +32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 +SI(SIO0) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 +SO(SIO1) 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 +WP#(SIO2) 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 +HOLD#(SIO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 +
+ +## 10ERASE OPERATIONS + +## 10.1 Block Erase (D8H) + +The BLOCK ERASE (D8H) command is used to erase at the block level. The BLOCK ERASE command (D8H) operates on one block at a time. The command sequence for the BLOCK ERASE operation is as follows: + +• 06H (WRITE ENBALE command) +• D8H (BLOCK ERASE command) +• 0FH (GET FEATURES command to read the status register) + +Prior to performing the BLOCK ERASE operation, the WRITE ENABLE (06H) command must be issued. As with any command that changes the memory contents, the WRITE ENABLE command must be executed in order to set the WEL bit. If the WRITE ENABLE command is not issued, then the rest of the erase sequence is ignored. The WRITE ENABLE command must be followed by the BLOCK ERASE (D8H) command. This command requires a 24-bit address. After the row address is registered, the control logic automatically controls timing and erase-verify operations. The device is busy for tBERS time during the BLOCK ERASE operation. The GET FEATURES (0FH) command can be used to monitor the status of the operation. + +Figure10-1. Block Erase Timing Diagram +![](images/f921480c0cb742615c5a7244738d62e37798d90a0da0dbed5107f7f047e9df06.jpg) + +## 11 RESET OPERATIONS + +## 11.1 Soft Reset (FFH) + +The RESET (FFH) command stops all operations and the status. For example, in case of a program or erase or read operation, the reset command can make the device enter the idle state. + +During a cache program or cache read, a reset can also stops the previous operation and the pending operation. + +Figure11-1. Reset Timing Diagram +![](images/15f15746a12a6271d2735432e42186d37c619e700e811c711153eda6a69acecc.jpg) + +
+text_image + +CS# +SCLK +SI +FFH +SO +High-Z +CS# +0 1 2 3 4 5 6 7 +SLK +tCS +get feature +Status register address +SI +0FH +7 6 5 4 3 2 1 0 +SO +High-Z +MSB +CS# +16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 +SCLK +SI +Status register data out +Status register data out +SO +7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 +MSB +MSB +
+ +Note: The Register bit value after soft reset refers to Table 12-2. Register bit Descriptions. + +## 11.2 Enable Power on Reset (66H) and Power on Reset (99H) + +If the Power on Reset command is accepted, any on-going internal operation will be terminated and the device will return to its default power-on state and lose all the current feature settings. + +The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in SPI mode. The “Reset (99H)” command sequence as follow: CS# goes low -> Sending Enable Reset command ->CS# goes high ->CS# goes low.->Sending Reset command ->CS# goes high. Once the Reset command is accepted by the device, the device will take approximately tVSL to reset. During this period, no command will be accepted. It is recommended to check the OIP bit in Status Register before issuing any other command sequence. The contents of the memory location being programmed or the block being erased are no longer valid. + +Figure11-2. Reset Timing Diagram +![](images/b5cf335087123fa59f61f0fcb0621602888481ae28eab8e186d1d981f87357aa.jpg) + +
+text_image + +CS# +0 1 2 3 4 5 6 7 +SCLK +Command +SI +66H +Command +99H +SO +High-Z +High-Z +
+ +## 12FEATURE OPERATIONS + +## 12.1 Get Features (0FH) and Set Features (1FH) + +The GET FEATURES (0FH) and SET FEATURES (1FH) commands are used to monitor the device status and alter the device behavior. These commands use a 1-byte feature address to determine which feature is to be read or modified. Feature such as OTP can be enabled or disabled by setting specific feature bits (shown in the below table).The status registers (C0H/F0H) is mostly read, except WEL, which is a writable bit with the WRITE ENABLE (06H) command. + +When a feature (A0H/B0H/D0H) is set, it remains active until the device is power cycled or the feature is written to. Unless otherwise specified in the following table, once the device is set, it remains set, even if a RESET (FFH) command is issued. + +Table 12-1. Features Settings + +
RegisterAddr.76543210
ProtectionA0HBRWDReservedBP2BP1BP0INVCMPReserved
FeatureB0HOTP_PRTOTP_ENReservedECC_ENReservedReservedReservedQE
StatusC0HReservedReservedECCS1ECCS0P_FAILE_FAILWELOIP
FeatureD0HReservedDS_IO[1]DS_IO[0]ReservedReservedReservedReservedReserved
StatusF0HReservedReservedECCSE1ECCSE0BPSReservedReservedCBSY
+ +Note: 1. If BRWD is enabled and WP# is LOW, then the block lock register cannot be changed. +2. If QE is enabled, the quad IO operations can be executed. +3. All the reserved bits must be held low when the feature is set. +4. These registers A0H/B0H/D0H are write/read type, and Registers C0H/F0H are read only. +5. The OTP\_PRT is non-volatile, others bits are volatile. +6. The Register Bit default value after power-up refers to Table 12-2. Register Bit Descriptions. + +Table 12-2. Register Bit Descriptions + +
BitBit NameAfter Power up or Power on Reset(66H-99H)After Reset command (FFH)Description
BRWDBlock register write disable0No ChangeWhich is used combined with WP#, If BRWD is high enabled and WP# is LOW, then the Protection register cannot be changed
BP2Block1No ChangeUsed combination, refer to chapter Block Protection
BP11
BP0Protection1
INVbits0
CMP0
OTP_PRTOTP0No ChangeUsed combination, refer to chapter OTP Region
OTP_ENRegion0
bitsBefore OTP Set
ECC_ENECC1No ChangeThe device offers data corruption protection by offering optional internal ECC. READs and PROGRAMs with internal ECC can be enabled or disabled by setting feature bit ECC_EN. ECC is enabled by default when device powered on, so the default READ and PROGRAM commands operate with internal ECC in the “active” state when ECC enable.
Enable
Latch
QEThe Quad0No ChangeThis bit indicates that whether the quad IO operations can be executed. If QE is set to 1, the quad IO operations can be executed.
Enable bit
ECCS0ECC StatusPage 0 Status0ECCS provides ECC status as the following table. ECCS and ECCSE are set to 00b either following a RESET, or at the beginning of the READ. They are then updated after the device completes a valid READ operation. ECCS and ECCSE are invalid if internal ECC is disabled (via a SET FEATURES command to reset ECC_EN to 0). After power-on RESET, ECC status is set to reflect the contents of block 0, page 0.
ECCS10
ECCSE00
ECCSE10
P_FAILProgram Fail00This bit indicates that a program failure has occurred (P_FAIL =1). It will also be set if the user attempts to program a protected region, including the OTP area. This bit is cleared during the PROGRAM EXECUTE command sequence or a RESET command (P_FAIL = 0).
E_FAILErase Fail00This bit indicates that an erase failure has occurred (E_FAIL = 1). It will also be set if the user attempts to erase a locked region. This bit is cleared (E_FAIL = 0) at the start of the BLOCK ERASE command sequence or the RESET command.
WELWrite Enable Latch00This bit indicates the current status of the write enable latch (WEL) and must be set (WEL = 1), prior to issuing a PROGRAM EXECUTE or BLOCK ERASE command. It is set by issuing the WRITE ENABLE command. WEL can also be disabled (WEL = 0), by issuing the WRITE DISABLE command.
OIPOperation In Progress00This bit is set (OIP = 1) when a PROGRAM EXECUTE, PAGE READ, BLOCK ERASE, or RESET command is executing, indicating the device is busy. When the bit is 0, the interface is in the ready state.
DS_IO[0] DS_IO[1]Driven Strength register00No ChangeIO driver strength setting. Default is 00b.
BPSBlock Protection Status1No ChangeBlock protection statusBPS is 1, selected block is protectedBPS is 0, selected block is unprotected.
CBSYCache Busy status bit00CBSY is to indicate whether cache is busy, non-available for data read or data load. This bit is the status, which indicates if the cache is busy or ready, 1 is busy, 0 is ready.
+ +Figure12-1. Get Features Timing Diagram +![](images/755b7da828ecf51f8b7bb32f3e782c4fe37dd23584f907ad1032a5bba08b0251.jpg) + +
+text_image + +CS# +0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 +SCLK +SI +Command +1 byte address +0FH +MSB +Data byte +SO +High-Z +MSB +7 6 5 4 3 2 1 0 +MSB +
+ +Figure12-2. Set Features Timing Diagram +![](images/84a2b2bbda5fd48f94be290045d18e4ed46209ceb284bdc5da7ff6d48b8195a8.jpg) + +
+text_image + +CS# +0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 +SCLK +SI +Command +1 byte address +Data byte +1FH +MSB +MSB +High-Z +SO +
+ +## 12.2 Status Register and Driver Register + +The NAND Flash device has the status registers (C0H/F0H) that software can read during the device operation for operation state query. The status register can be read by issuing the GET FEATURES (0FH) command, followed by the feature address C0H or F0H (see FEATURE OPERATION). The Output Driver Register can be set and read by issuing the SET FEATURE (0FH) and GET FEATURE command followed by the feature address D0H (see FEATURE OPERATION). + +Table 12-3.ECC Error Bits Descriptions + +
ECCS1ECCS0ECCSE1ECCSE0Description
00xxNo bit errors were detected during the previous read algorithm
0100Bit errors(=1) were detected and corrected
0101Bit errors (=2) were detected and corrected.
0110Bit errors (=3) were detected and corrected.
0111Bit errors (=4) were detected and corrected.
11xxReserved
10xxBit errors greater than ECC capability(4 bits) and not corrected
+ +12-4. Driver Register Bits Descriptions + +
DS_IO[1]DS_IO[0]Driver Strength
00100%
0175%
1050%
1125%
+ +## 12.3 OTP Region + +The serial device offers a protected, One-Time Programmable NAND Flash memory area. 4 full pages are available on the device. Customers can use the OTP area as they prefer, like programming serial numbers, or other data, for permanent storage. When delivered from factory, feature bit OTP\_PRT is 0. To access the OTP feature, the user must set feature bits OTP\_EN/OTP\_PRT by SET FEATURES command. When the OTP is ready for access, only pages 00h–03H can be programmed in sequential order by PROGRAM LOAD (02H) and PROGRAM EXECUTE (10H) commands (when not yet protected), and read out by PAGE READ (13H) command and output data by READ from CACHE(03H/0BH/3BH/6BH). When ECC is enabled, data written in the OTP area is ECC protected. + +Table 12-5.OTP States + +
OTP_PRTOTP_ENState
x0Normal Operation
01Access OTP region, read and program data
111. When the device power on state OTP_PRT is 0, user can set feature bit OTP_PRT and OTP_EN to 1, then issue PROGRAM EXECUTE (10H) to lock OTP, and after that OTP_PRT will permanently remain 1.2. When the device power on state OTP_PRT is 1, user can only read the OTP region data
+ +Note: The OTP space cannot be erased and after it has been protected, it cannot be programmed again, please use this function carefully. + +Access to OTP data + +• Issue the SET FEATURES command (1FH) +• Set feature bit OTP\_EN +• Issue the PAGE PROGRAM (only when OTP\_PRT is 0) or PAGE READ command + +Protect OTP region + +Only when the following steps are completed, the OTP\_PRT will be set and users can get this feature out with 0FH command. + +• Issue the SET FEATURES command (1FH) +• Set feature bit OTP\_EN and OTP\_PRT +• 06H (WRITE ENABLE) +• Issue the PROGRAM EXECUTE (10H) command. + +## 12.4 Assistant Bad Block Management + +As a NAND Flash, the device may have blocks that are invalid when shipped from the factory, and a minimum number of valid blocks (NVB) of the total available blocks are specified. An invalid block is one that contains at least one page that has more bad bits than can be corrected by the minimum required ECC. Additional bad blocks may develop with use. However, the total number of available blocks will not fall below NVB during the endurance life of the product. + +Although NAND Flash memory devices may contain bad blocks, they can be used reliably in systems that provide badblock management and error-correction algorithms, which ensure data integrity. Internal circuitry isolates each block from other blocks, so the presence of a bad block does not affect the operation of the rest of the NAND Flash array. + +NAND Flash devices are shipped from the factory erased. The factory identifies invalid blocks before shipping by programming the Bad Block Mark (00h) to the first spare area location in each bad block. This method is compliant with ONFI Factory Defect Mapping requirements. See the following table for the bad-block mark. + +System software should initially check the first spare area location for non-FFH data on the first page of each block prior to performing any program or erase operations on the NAND Flash device. A bad-block table can then be created, enabling system software to map around these areas. Factory testing is performed under worst-case conditions. Because invalid blocks may be marginal, it may not be possible to recover the bad-block marking if the block is erased. + +To simplify the system requirement and guard the data integration, GigaDevice SPI NAND provides assistant Management options as below. + +Table 12-6. Bad Block Mark information (2Gb) + +
DescriptionRequirement
Minimum number of valid blocks (NVB)2008
Total available blocks per die2048
First spare area locationByte 2048
Bad-block mark00h(use non FFH to check)
+ +## 12.5 Block Protection + +The block lock feature provides the ability to protect the entire device, or ranges of blocks, from the PROGRAM and ERASE operations. After power-up, the device is in the “locked” state, i.e., feature bits BP0, BP1and BP2 are set to 1, INV, CMP and BRWD are set to 0. To unlock all the blocks, or a range of blocks, the SET FEATURES command must be issued to alter the state of protection feature bits. When BRWD is set and WP# is LOW, none of the writable protection feature bits can be set. Also, when a PROGRAM/ERASE command is issued to a locked block, status bit OIP remains 0. When an ERASE command is issued to a locked block, the erase failure, status bit E\_FAIL set to 1. When a PROGRAM command is issued to a locked block, program failure, status bit P\_FAIL set to 1. + +To enable the Write Protection (WP#), the Quad Enable bit (QE) of feature (B0[0]) must be set to 0. + +Table 12-7. Block Lock Register Block Protect Bits (2Gb) + +
CMPINVBP2BP1BP0Protect Row AddressProtect Rows
2Gb
xx000NONENone—all unlocked
000011F800h ~ 1FFFFhUpper 1/64 locked
000101F000h ~ 1FFFFhUpper 1/32 locked
000111E000h ~ 1FFFFhUpper 1/16 locked
001001C000h ~ 1FFFFhUpper 1/8 locked
0010118000h ~ 1FFFFhUpper 1/4 locked
0011010000h ~ 1FFFFhUpper 1/2 locked
xx1110000h ~ 1FFFFhAll locked (default)
010010000h ~7FFhLower 1/64 locked
010100000h ~FFFhLower 1/32 locked
010110000h ~ 1FFFhLower 1/16 locked
011000000h ~ 3FFFhLower 1/8 locked
011010000h ~ 7FFFhLower 1/4 locked
011100000h ~ FFFFhLower 1/2 locked
100010000h ~ 1F7FFhLower 63/64 locked
100100000h ~ 1FFFFhLower31/32 locked
100110000h ~ 1DFFFhLower 15/16 locked
101000000h ~ 1BFFFhLower7/8 locked
101010000h ~ 17FFFhLower3/4 locked
101100000h ~ 003FhBlock0
110010800h ~ 1FFFFhUpper 63/64 locked
110101000h ~ 1FFFFhUpper31/32 locked
110112000h ~ 1FFFFhUpper 15/16 locked
111004000h ~ 1FFFFhUpper7/8 locked
111018000h ~ 1FFFFhUpper3/4 locked
111100000h ~ 003FhBlock0
+ +When WP# is not LOW, user can issue bellows commands to alter the protection states as want. +• Issue SET FEATURES register write (1FH) +• Issue the feature bit address (A0h) and the feature bits combination as the table + +## 12.6 Internal ECC + +The device offers data corruption protection by offering optional internal ECC. READs and PROGRAMs with internal ECC can be enabled or disabled by setting feature bit ECC\_EN. ECC is enabled by default when device powered on, so the default READ and PROGRAM commands operate with internal ECC in the “active” state when ECC enable. + +To enable/disable ECC, perform the following command sequence: + +• Issue the SET FEATURES command (1FH) to set the feature bit ECC\_EN: + +1. To enable ECC, Set ECC\_EN to 1. +2. To disable ECC, Clear ECC\_EN to 0. + +During a PROGRAM operation, the device calculates an ECC code on the 2k page in the cache register, before the page is written to the NAND Flash array. + +During a READ operation, the page data is read from the array to the cache register, where the ECC code is calculated and compared with the ECC code value read from the array. If error bits are detected (error bits≤4 bits), the error is corrected in the cache register. Only corrected data is output on the I/O bus. The ECC status bit indicates whether or not the error correction was successful. The ECC Protection table below shows the ECC protection scheme used throughout a page. + +The ECC protection format as follow: + +• User meta data I is not protected by internal ECC and User meta data II is protected by internal ECC. + +Any data wrote to the ECC parity data area are ignored when ECC enabled. + +Table 12-8. The Distribution of ECC Segment and Spare Area in a Page + +
Main Area(2KB)Spare Area(128B)
User dataUser meta data(I+II)ECC Parity Data
Main0Main1Main2Main3Spare0Spare1Spare2Spare3Spare0Spare1Spare2Spare3
(512B)(512B)(512B)(512B)(4B+12B)(4B+12B)(4B+12B)(4B+12B)(16B)(16B)(16B)(16B)
+ +Table 12-9. ECC Protection and Spare Area + +
Min Byte AddressMax Byte AddressECC ProtectedAreaDescription
000H1FFHYesMain 0User data 0
200H3FFHYesMain 1User data 1
400H5FFHYesMain 2User data 2
600H7FFHYesMain 3User data 3
800H803HNoSpare 0User meta 0 data I
804H80FHYesSpare 0User meta 0 data II
810H813HNoSpare 1User meta 1 data I
814H81FHYesSpare 1User meta 1 data II
820H823HNoSpare 2User meta 2 data I
824H82FHYesSpare 2User meta 2 data II
830H833HNoSpare 3User meta 3 data I
834H83FHYesSpare 3User meta 3 data II
840H84FHYesSpare 0ECC Parity Data
850H85FHYesSpare 1ECC Parity Data
860H86FHYesSpare 2ECC Parity Data
870H87FHYesSpare 3ECC Parity Data
+ +## Note + +1. 800H is reserved for initial bad block mark. +2. When Internal ECC is enabled, user cannot program the Address 840H\~87FH, but user can read the Address 840H\~87FH. +When Internal ECC is disabled, the whole page area is open for user. And we recommend the user to provide external ECC protection. + +## 13POWER ON TIMING + +Figure13-1. Power on Timing Sequence +![](images/fc2ca4121a17b855a4c8a71f284d70319d2bc8b9fca9d2b20f302b19c512cd19.jpg) + +
+line + +| Metric | Description | +| --- | --- | +| Vcc(max) | Maximum voltage threshold | +| Vcc(min) | Minimum voltage threshold | +| VWI | Minimum voltage threshold | +| tVSL | Time-voltage duration between Vcc(min) and Vcc(max) | +| Device is fully accessible | Accessible device status | +
+ +Table 13-1. Power-On Timing and Write Inhibit Threshold for 1.8V/3.3V + +
SymbolParameterMinMaxUnit
tVSLVCC(min) To CS# Low1ms
VWIWrite Inhibit Voltage1.8V1.4V
3.3V2.5
+ +## 14ABSOLUTE MAXIMUM RATINGS + +Table 14-1.Absolute Maximum Ratings + +
ParameterValueUnit
Ambient Operating Temperature-40 to 105°C
Storage Temperature-65 to 150°C
Applied Input / Output Voltage-0.6 to VCC+0.4V
VCC(3.3V)-0.6 to 4.0V
VCC(1.8V)-0.6 to 2.5V
+ +Figure14-1. Input Test Waveform and Measurement Level + +Maximum Negative Overshoot Waveform +![](images/5ab9164ef39545ab8995032a9593308a8e83278273c448fa9d38eccfff56b99c.jpg) + +
+text_image + +Vss +20ns +20ns +Vss-2.0V +20ns +
+ +Maximum Positive Overshoot Waveform +![](images/36919d0fe4bdd81447f6d77ddf3e347ad916ab43a2f5d3ba7c47afd64a7e6893.jpg) + +
+text_image + +Vcc + 2.0V +20ns +20ns +20ns +
+ +## 15CAPACITANCE MEASUREMENT CONDITIONS + +
SymbolParameterMinTypMaxUnitConditions
CINInput Capacitance6pFVIN=0V
COUTOutput Capacitance8pFVOUT=0V
CLLoad Capacitance30pF
Input Rise And Fall time5ns
Input Pulse Voltage0.1VCC to 0.8VCCV
Input Timing Reference Voltage0.2VCC to 0.7VCCV
Output Timing Reference Voltage0.5VCCV
+ +Figure15-1. Input Test Waveform and Measurement Level +![](images/e9b06380ede32fb2048221570af522de84505438d4d429602d78b8d5248f9ea0.jpg) + +
+text_image + +0.8VCC +0.7VCC +0.2VCC +0.1VCC +AC Measurement Level +Output timing reference level +0.5VCC +
+ +Note: Input pulse rise and fall time are<5ns + +## 16DC CHARACTERISTIC + +(T= -40℃\~85℃/-40℃\~105℃, VCC=2.7\~3.6V) + +
SymbolParameterTest ConditionMin.Typ.Max.Unit.
$I_{LI}$ Input Leakage Current±2μA
$I_{LO}$ Output Leakage Current±2μA
$I_{CC1}$ Standby CurrentCS#=VCC, $V_{IN}$ =VCC or VSS50μA
$I_{CC2}$ Operating Current (Read)CLK=0.1VCC / 0.9VCCat 104MHz,Q=Open(*1,*2,*4 I/O)30mA
$I_{CC3}$ Operating Current (Program)30mA
$I_{CC4}$ Operating Current (Erase)30mA
$V_{IL}$ Input Low Voltage-0.50.2VCCV
$V_{IH}$ Input High Voltage0.8VCCVCC+0.4V
$V_{OL}$ Output Low Voltage $I_{OL}$ =1.6mA0.4V
$V_{OH}$ Output High Voltage $I_{OH}$ =-100μAVCC-0.2V
+ +(T= -40℃\~85℃/-40℃\~105℃, VCC=1.7\~2.0V) + +
SymbolParameterTest ConditionMin.Typ.Max.Unit.
$I_{LI}$ Input Leakage Current±2μA
$I_{LO}$ Output Leakage Current±2μA
$I_{CC1}$ Standby CurrentCS#=VCC, $V_{IN}$ =VCC or VSS50μA
$I_{CC2}$ Operating Current (Read)CLK=0.1VCC / 0.9VCCat 80MHz,Q=Open(*1,*2,*4 I/O)30mA
$I_{CC3}$ Operating Current (Program)30mA
$I_{CC4}$ Operating Current (Erase)30mA
$V_{IL}$ Input Low Voltage-0.50.2VCCV
$V_{IH}$ Input High Voltage0.8VCCVCC+0.4V
$V_{OL}$ Output Low Voltage $I_{OL}$ =1.6mA0.4V
$V_{OH}$ Output High Voltage $I_{OH}$ =-100μAVCC-0.2V
+ +Note: Value guaranteed by design and/or characterization, not 100% tested in production + +## 17AC CHARACTERISTICS + +(T= -40℃\~85℃/-40℃\~105℃, VCC=1.7\~2.0V/2.7\~3.6V, CL=30pF) + +
SymbolParameter1.8V3.3VUnit.
Min.Max.Min.Max.
FC1Serial Clock Frequency80104MHz
FC2*Serial Clock Frequency for DTR4545MHZ
tCHSerial Clock High Time44ns
tCLSerial Clock Low Time44ns
tCLCHSerial Clock Rise Time (Slew Rate)0.20.2V/ns
tCHCLSerial Clock Fall Time (Slew Rate)0.20.2V/ns
tCHSHCS# Active Hold Time55ns
tSHCHCS# Not Active Setup Time55ns
tSLCHCS# Active Setup Time75ns
tCHSLCS# Not Active Hold Time55ns
tSHSL/tCSCS# High Time2020ns
tSHQZOutput Disable Time2020ns
tCLQXOutput Hold Time22ns
tDVCHData In Setup Time22ns
tCHDXData In Hold Time22ns
tHLCHHold# Low Setup Time (relative to Clock)55ns
tHHCHHold# High Setup Time (relative to Clock)55ns
tCHHLHold# High Hold Time (relative to Clock)55ns
tCHHHHold# Low Hold Time (relative to Clock)55ns
tHLQZHold# Low To High-Z Output1515ns
tHHQXHold# High To Low-Z Output1515ns
tCLQVClock Low To Output Valid119ns
tWHSLWP# Setup Time Before CS# Low2020ns
tSHWLWP# Hold Time After CS# High100100ns
+ +## Note: + +1. Value guaranteed by design and/or characterization, not 100% tested in production +2. Please contact GigaDevice when there is a need to use the EEh command for DTR. + +The max clock rate for DTR depends on the tCLQV (clock to data output valid). Per datasheet, with output load capacitance of 30pf, the tCLQV is about 11ns. This will limit the max rate to 45Mhz. + +However, in general, most of PCB designs have output loading much less than 30pf. Lower output loading will in turn shorten the tCLQV and result in higher max clock rate. + +GigaDevice recommend customers measure the tCLQV and then set the clock rate to match the SPI host data sampling data setup time and hold time. + +## 18PERFORMANCE AND TIMING + +
SymbolParameterMin.Typ.Max.Unit.
tRSTCS# High To Next Command After Reset(FFh)500us
tRDRead From Array25us
tRD_ECCRead From Array with ECC4560us
tPROGPage Programming Time300600us
tPROG_ECCPage Programming Time with ECC400600us
tBERSBlock Erase Time35ms
tCBSYWCache busy time for Cache Program5tPROGus
tCBSYW_ECCCache busy time for Cache Program with ECC30tPROG_ECCus
tCBSYRCache busy time for Cache Read5tRDus
tCBSYR_ECCCache busy time for Cache Read with ECC30tRD_ECCus
+ +Figure18-1. Serial Input Timing +![](images/881b2dfbbbb8230fb7af423e755404286621abc6443eff5afc5c06cc0c664d47.jpg) + +
+text_image + +CS# +tCHSL +tSLCH +SCLK +tDVCH +tCHDX +SI +MSB +LSB +SO +High-Z +tCHSH +tCLCH +tSHCL +tSHSL +
+ +Figure18-2. Output Timing +![](images/862fdcc50b0a0a0903dfcef387b75249359e0361a7d63a958d4a67596c973807.jpg) + +
+text_image + +CS# +SCLK +tCLQV +tCLQX +tCLQV +tCLQX +SO +LSB +tCH +tCL +tSHQZ +SI +Least significant address bit (LIB) in +
+ +Figure18-3. Hold Timing +![](images/6e6e3f492d6a3bcaf451ad36a791b73d3bd48ab15ff9722b61aa57f64c01c4d3.jpg) + +
+text_image + +CS# +SCLK +tCHHL +tHLCH +tHHCH +SO +tHLQZ +tCHHH +tHHQX +HOLD# +
+ +Sl do not care during HOLD operation. + +## 19ORDERING INFORMATION + +![](images/35356c13b1070de72632d77901f1c5c94ab8bdcb460e745577a05a11ca95ea6b.jpg) +Note: (1) Industrial+: F grade has implemented additional test flows to ensure higher product quality than I grade. + +## 20 PACKAGE INFORMATION + +Figure 20-1.WSON8 (8\*6mm) +![](images/d72dc2e6eb040b370a50a8b5b5b57cf54cc5974bd404967d05fd4adf0cfe3562.jpg) +Bottom View + +![](images/74a98a721fb00f3476cd1d40fc6b762a4fce0c57c2885119aa8012aef7a70f84.jpg) + +
+text_image + +C +A1 +A +
+ +Side View + +Dimensions + +
SymbolAA1cbDD2EE2eL
Unit
mmMin0.700.000.1800.357.903.305.904.201.270.45
Nom0.750.020.2030.408.003.406.004.300.50
Max0.800.050.2500.458.103.506.104.400.55
InchMin0.02800.0070.0140.3110.1300.2320.1650.050.018
Nom0.0300.0010.0080.0160.3150.1340.2360.1690.020
Max0.0320.0020.0100.0180.3190.1380.2400.1730.022
+ +Figure 20-2.TFBGA-24BALL (5\*5-1 ball array) +![](images/309918a65f99632a28c75a9aeae076c813083d9dfa76271cea0dd3611eea32b9.jpg) +Dimensions + +
SymbolAA1A2bDD1EE1eSESD
Unit
mmMin0.250.750.355.904.00 BSC7.904.00 BSC1.00 BSC1.00 TYP1.00 TYP
Nom0.300.800.406.008.00
Max1.200.350.850.456.108.10
InchMin0.0100.0300.0140.2320.157 BSC0.3110.157 BSC0.039 BSC0.039 TYP0.039 TYP
Nom0.0120.0310.0160.2360.315
Max0.0470.0140.0330.0180.2400.319
+ +Note：Both package length and width do not include mold flash. + +Figure20-3. TFBGA-24BALL (4\*6 ball array) +![](images/08d3fc107d74ce1b70a342f0d55cddefae442ab529e89cfab2eef1f18c12f9d6.jpg) + +Dimensions + +
SymbolAA1A2bDD1EE1eSESD
Unit
mmMin0.250.700.355.903.00 BSC7.905.00 BSC1.00 BSC0.50 TYP0.50 TYP
Nom0.300.800.406.008.00
Max1.200.350.850.456.108.10
InchMin0.0100.0280.0140.2320.118 BSC0.3110.197 BSC0.039 BSC0.020 TYP0.020 TYP
Nom0.0120.0310.0160.2360.315
Max0.0470.0140.0340.0180.2400.319
+ +Note: Both the package length and width do not include the mold flash. + +21 REVISION HISTORY + +
Version NoDescriptionPage NumberDate
1.0Initial Release2019-08-01
1.1Modify the 03H command description in Figure 8-6.Page Read to Cache Timing Diagram.Add Note in Figure 8-6 Page Read to Cache Timing Diagram about Read From Cache command.Modify the “P_FAIL” “E_FAIL” default value after power up from ‘Page 0’ to ‘0’.2525512019-08-13
1.2Add Note of EEH DTR command in 8.9 & 17 AC Characteristics..Modify the descriptions of Industrial+ F grade in Ordering information.Modify the descriptions of FFH command.Add the Register bit value after reset command (FFH).Move Table 12.2 Register bit description to 12.1Modify the Figure 3-1 Array Organization.29/617/6416/4649/5049102019-08-27
1.3Add tCBSYR_ECC and tCBSYW_ECC in 18 Performance and Timing.622019-09-11
1.4Update the tSLCH Value from 5ns to 7ns for 1.8V.Update the tVSL Value from 5ms to 1ms.Update the VWI Value from 1.7V to 1.4V.6157572019-11-15
1.5Update the tRD_ECC Max Value from 50us to 60usAdd Industrial 105° productModify the Storage Temperature to -65°C~150°CUpdate the 8.12 Parameter Page Table Byte137/138 and recalculate the CRC Byte 254/2556275835/362020-03-09
1.6Add the description of the OTP Area ECC protected.Modify the description of the initial Bad Block Mark with internal ECC on.Remove the description of the 84h/C4h/34h must be use in internal data move.Modify the error description “Program an invalid address will cause P_Fail”525616/43/44512021-11-13
+ +## Important Notice + +This document is the property of GigaDevice Semiconductor (Beijing) Inc. and its subsidiaries (the "Company"). This document, including any product of the Company described in this document (the “Product”), is owned by the Company under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide. The Company reserves all rights under such laws and treaties and does not grant any license under its patents, copyrights, trademarks, or other intellectual property rights. The names and brands of third party referred thereto (if any) are the property of their respective owner and referred to for identification purposes only. + +The Company makes no warranty of any kind, express or implied, with regard to this document or any Product, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. The Company does not assume any liability arising out of the application or use of any Product described in this document. Any information provided in this document is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Except for customized products which has been expressly identified in the applicable agreement, the Products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only. The Products are not designed, intended, or authorized for use as components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, atomic energy control instruments, combustion control instruments, airplane or spaceship instruments, traffic signal instruments, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or Product could cause personal injury, death, property or environmental damage ("Unintended Uses"). Customers shall take any and all actions to ensure using and selling the Products in accordance with the applicable laws and regulations. The Company is not liable, in whole or in part, and customers shall and hereby do release the Company as well as it’s suppliers and/or distributors from any claim, damage, or other liability arising from or related to all Unintended Uses of the Products. Customers shall indemnify and hold the Company as well as it’s suppliers and/or distributors harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of the Products. Customers shall discard the device according to the local environmental law. + +Information in this document is provided solely in connection with the Products. The Company reserves the right to make changes, corrections, modifications or improvements to this document and the Products and services described herein at any time, without notice. \ No newline at end of file diff --git a/Inc/main.h b/Inc/main.h index 3f9708f..24b1dbf 100644 --- a/Inc/main.h +++ b/Inc/main.h @@ -81,6 +81,18 @@ void Error_Handler(void); #define ST_TX0_GPIO_Port GPIOA #define ST_RX0_Pin GPIO_PIN_10 #define ST_RX0_GPIO_Port GPIOA +#define GD_SCLK_Pin GPIO_PIN_3 +#define GD_SCLK_GPIO_Port GPIOB +#define GD_SO_Pin GPIO_PIN_4 +#define GD_SO_GPIO_Port GPIOB +#define GD_SI_Pin GPIO_PIN_5 +#define GD_SI_GPIO_Port GPIOB +#define GD_WP_Pin GPIO_PIN_8 +#define GD_WP_GPIO_Port GPIOB +#define GD_CS_Pin GPIO_PIN_0 +#define GD_CS_GPIO_Port GPIOE +#define GD_HOLD_Pin GPIO_PIN_1 +#define GD_HOLD_GPIO_Port GPIOE /* USER CODE BEGIN Private defines */ diff --git a/Inc/spi.h b/Inc/spi.h index e95ad04..030130a 100644 --- a/Inc/spi.h +++ b/Inc/spi.h @@ -32,12 +32,15 @@ extern "C" { /* USER CODE END Includes */ +extern SPI_HandleTypeDef hspi1; + extern SPI_HandleTypeDef hspi2; /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ +void MX_SPI1_Init(void); void MX_SPI2_Init(void); /* USER CODE BEGIN Prototypes */ diff --git a/Lib/FlashDB b/Lib/FlashDB new file mode 160000 index 0000000..8236571 --- /dev/null +++ b/Lib/FlashDB @@ -0,0 +1 @@ +Subproject commit 8236571f6e29273a16bba62061bf0405e4186878 diff --git a/Lib/fal b/Lib/fal new file mode 160000 index 0000000..aa02112 --- /dev/null +++ b/Lib/fal @@ -0,0 +1 @@ +Subproject commit aa0211218634a613d3638425a830854bd07a0b76 diff --git a/MDK-ARM/STM32F407-Demo.uvprojx b/MDK-ARM/STM32F407-Demo.uvprojx index aa5b6b0..58efc69 100644 --- a/MDK-ARM/STM32F407-Demo.uvprojx +++ b/MDK-ARM/STM32F407-Demo.uvprojx @@ -340,7 +340,7 @@ USE_HAL_DRIVER,STM32F407xx - ../Inc;../Drivers/STM32F4xx_HAL_Driver/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F4xx/Include;../Drivers/CMSIS/Include + ../Inc;../Drivers/STM32F4xx_HAL_Driver/Inc;../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F4xx/Include;../Drivers/CMSIS/Include;../Drivers/BSP/CH395F;../Drivers/BSP/GD5F2GQ5UE;../Lib/FlashDB/port/fal/inc;../Lib/FlashDB/inc @@ -516,11 +516,6 @@ - - ch395f.c - 1 - ../Src/ch395f.c - stm32f4xx_it.c 1 @@ -725,6 +720,66 @@ + + Drivers/BSP + + + ch395f.c + 1 + ..\Drivers\BSP\CH395F\ch395f.c + + + fal_flash_gd5f2gq5ue.c + 1 + ..\Drivers\BSP\GD5F2GQ5UE\fal_flash_gd5f2gq5ue.c + + + gd5f2gq5ue.c + 1 + ..\Drivers\BSP\GD5F2GQ5UE\gd5f2gq5ue.c + + + + + lib/FlashDB + + + fdb.c + 1 + ..\Lib\FlashDB\src\fdb.c + + + fdb_kvdb.c + 1 + ..\Lib\FlashDB\src\fdb_kvdb.c + + + fdb_tsdb.c + 1 + ..\Lib\FlashDB\src\fdb_tsdb.c + + + fdb_utils.c + 1 + ..\Lib\FlashDB\src\fdb_utils.c + + + fal.c + 1 + ..\Lib\FlashDB\port\fal\src\fal.c + + + fal_flash.c + 1 + ..\Lib\FlashDB\port\fal\src\fal_flash.c + + + fal_partition.c + 1 + ..\Lib\FlashDB\port\fal\src\fal_partition.c + + + ::CMSIS @@ -745,4 +800,13 @@ + + + + STM32F407-Demo + 1 + + + + diff --git a/RTL8305NBI-CG.md b/RTL8305NBI-CG.md new file mode 100644 index 0000000..6e7d0b2 --- /dev/null +++ b/RTL8305NBI-CG.md @@ -0,0 +1,1549 @@ +## NOT FOR PUBLIC RELEASE + +## RTL8305NBI-CG + +## DRAFT + +# SINGLE-CHIP 5-PORT 10/100M ETHERNET SWITCH CONTROLLER + +## DATASHEET + +(CONFIDENTIAL: Development Partners Only) + +Rev. 1.0 + +30 May 2015 + +Track ID: JATR-8275-15 + +## COPYRIGHT + +©2015 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. + +## DISCLAIMER + +Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. + +## TRADEMARKS + +Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. + +## USING THIS DOCUMENT + +This document is intended for the software engineer's reference and provides detailed programming information. + +Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. + +REVISION HISTORY + +
RevisionRelease DateSummary
1.02015/05/30First release.
+ +## Table of Contents + +1. GENERAL DESCRIPTION....1 +2. FEATURES....2 +3. SYSTEM APPLICATIONS....3 +4. BLOCK DIAGRAM....4 +5. PIN ASSIGNMENTS ....5 + +5.1. PIN ASSIGNMENTS DIAGRAM....5 +5.2. PACKAGE IDENTIFICATION....5 +5.3. PIN ASSIGNMENTS TABLE....6 + +6. PIN DESCRIPTIONS....7 + +6.1. PIN ASSIGNMENT CODES 7 +6.2. MEDIA CONNECTION PINS 7 +6.3. MISCELLANEOUS PINS 8 +6.4. PORT LED PINS 8 +6.5. STRAPPING PINS....9 +6.6. REGULATOR PINS....9 +6.7. POWER AND GND PINS....9 + +7. BASIC FUNCTION DESCRIPTIONS....10 + +7.1. SWITCH CORE FUNCTION OVERVIEW....10 + +7.1.1. Flow Control....10 + +7.1.1.1 IEEE 802.3x Full Duplex Flow Control....10 +7.1.1.2 Half Duplex Back Pressure....10 + +7.1.2. Address Search, Learning, and Aging....11 +7.1.3. Half Duplex Operation....11 +7.1.4. InterFrame Gap....11 +7.1.5. Illegal Frame....11 + +7.2. PHYSICAL LAYER FUNCTIONAL OVERVIEW 12 + +7.2.1. Auto-Negotiation....12 +7.2.2. 10Base-T Transmit Function....12 +7.2.3. 10Base-T Receive Function....12 +7.2.4. Link Monitor....12 +7.2.5. 100Base-TX Transmit Function....12 +7.2.6. 100Base-TX Receive Function....12 +7.2.7. Power-Down Mode....13 +7.2.8. Crossover Detection and Auto Correction....13 +7.2.9. Polarity Detection and Correction....13 + +7.3. GENERAL FUNCTION OVERVIEW....14 + +7.3.1. Power-On Sequence 14 +7.3.2. Setup and Configuration....15 +7.3.3. Serial EEPROM Example....16 + +7.3.3.1 EEPROM Device Operation....16 +7.3.3.2 EEPROM Size Selection....18 + +7.3.4. SMI....18 +7.3.5. Head-Of-Line Blocking 18 +7.3.6. Filtering/Forwarding Reserved Control Frame....19 +7.3.7. Loop Detection....19 +7.3.8. Reg.0.14 PHY Digital Loopback Return to Internal....21 +7.3.9. LDO for 1.0V Power Generation 22 +7.3.10. Crystal/Oscillator 22 + +## 8. ADVANCED FUNCTION DESCRIPTIONS ....23 + +8.1. VLAN FUNCTION ....23 + +8.1.1. VLAN Description ....23 +8.1.2. Port-Based VLAN....24 +8.1.3. IEEE 802.1Q Tagged-VID Based VLAN 24 +8.1.4. Insert/Remove/Replace Tag....24 +8.1.5. Ingress and Egress Rules....25 + +8.2. IEEE 802.1P REMARKING FUNCTION....25 + +8.3. QoS FUNCTION....26 + +8.3.1. Bandwidth Control 26 + +8.3.1.1 Output (TX) Bandwidth Control....26 +8.3.1.2 Input (RX) Bandwidth Control 27 + +8.3.2. Priority Assignment....27 + +8.3.2.1 Queue Number Selection....27 +8.3.2.2 Port-Based Priority Assignment....27 +8.3.2.3 IEEE 802.1p/Q-Based Priority Assignment....28 +8.3.2.4 DSCP-Based Priority Assignment 28 +8.3.2.5 IP Address-Based Priority....28 +8.3.2.6 Reassigned Priority....28 +8.3.2.7 RLDP-Based Priority....28 +8.3.2.8 Packet Priority Selection....29 + +8.4. LOOKUP TABLE FUNCTION ....30 + +8.4.1. Function Description....30 +8.4.2. Address Search, Learning, and Aging....30 +8.4.3. Lookup Table Definition....31 + +8.5. STORM FILTER FUNCTION....32 +8.6. INPUT AND OUTPUT DROP FUNCTION 32 +8.7. LED FUNCTION....33 +8.8. ENERGY-EFFICIENT ETHERNET (EEE)....34 +8.9. CABLE DIAGNOSIS 34 + +## 9. CHARACTERISTICS....35 + +9.1. ELECTRICAL CHARACTERISTICS/MAXIMUM RATINGS ....35 +9.2. OPERATING RANGE....35 +9.3. DC CHARACTERISTICS....35 +9.4. THERMAL CHARACTERISTICS....36 + +9.4.1. Simulation Conditions 36 +9.4.2. Thermal Characteristics Results ....36 + +9.5. DIGITAL TIMING CHARACTERISTICS ....37 + +9.5.1. LED Timing....37 +9.5.2. Reception/Transmission Data Timing of SMI Interface 37 +9.5.3. EEPROM Auto-Load Timing....38 + +## 10. MECHANICAL DIMENSIONS....39 + +10.1. MECHANICAL DIMENSIONS NOTES ....40 + +## 11. ORDERING INFORMATION....41 + +## List of Tables + +TABLE 1. PIN ASSIGNMENTS TABLE ....6 + +TABLE 2. MEDIA CONNECTION PINS....7 + +TABLE 3. MISCELLANEOUS PINS ....8 + +TABLE 4. PORT LED PINS....8 + +TABLE 5. STRAPPING PINS....9 + +TABLE 6. REGULATOR PINS....9 + +TABLE 7. POWER AND GND PINS ....9 + +TABLE 8. BASIC SMI READ/WRITE CYCLES....18 + +TABLE 9. EXTENDED SMI MANAGEMENT FRAME FORMAT ..... 18 + +TABLE 10. RESERVED ETHERNET MULTICAST ADDRESSES....19 + +TABLE 11. LOOP FRAME FORMAT ....20 + +TABLE 12. CRYSTAL AND OSCILLATOR REQUIREMENTS....22 + +TABLE 13. VLAN TABLE....23 + +TABLE 14. VLAN ENTRY ....23 + +TABLE 15. L2 TABLE 4-WAY HASH INDEX METHOD ....31 + +TABLE 16. ELECTRICAL CHARACTERISTICS/MAXIMUM RATINGS .....35 + +TABLE 17. OPERATING RANGE....35 + +TABLE 18. DC CHARACTERISTICS....35 + +TABLE 19. PCB DESCRIPTIONS ......36 + +TABLE 20. CONDITION DESCRIPTIONS ....36 + +TABLE 21. THERMAL CHARACTERISTICS RESULTS ....36 + +TABLE 22. LED TIMING....37 + +TABLE 23. SMI TIMING....37 + +TABLE 24. EEPROM AUTO-LOAD TIMING CHARACTERISTICS ....38 + +TABLE 25. ORDERING INFORMATION ....41 + +## List of Figures + +FIGURE 1. BLOCK DIAGRAM....4 +FIGURE 2. PIN ASSIGNMENTS ....5 +FIGURE 3. COLLISION-BASED BACKPRESSURE SIGNAL TIMING....10 +FIGURE 4. POWER-ON SEQUENCE....14 +FIGURE 5. RESET 15 +FIGURE 6. START AND STOP DEFINITION....17 +FIGURE 7. OUTPUT ACKNOWLEDGE ....17 +FIGURE 8. RANDOM READ....17 +FIGURE 9. SEQUENTIAL READ ....17 +FIGURE 10. LOOP EXAMPLE ....19 +FIGURE 11. LED AND BUZZER CONTROL SIGNAL FOR LOOP DETECTION ....20 +FIGURE 12. LOOP EXAMPLE 2 ....21 +FIGURE 13. REG. 0.14 LOOPBACK ....21 +FIGURE 14. PACKET-SCHEDULING DIAGRAM....26 +FIGURE 15. RTL8305NBI PRIORITY ASSIGNMENT DIAGRAM....27 +FIGURE 16. BROADCAST INPUT DROP VS. OUTPUT DROP....32 +FIGURE 17. MULTICAST INPUT DROP VS. OUTPUT DROP....32 +FIGURE 18. FLOATING AND PULL-HIGH OF LED PINS FOR LED ....33 +FIGURE 19. RECEPTION DATA TIMING OF SMI INTERFACE....37 +FIGURE 20. TRANSMISSION DATA TIMING OF SMI INTERFACE....37 +FIGURE 21. EEPROM AUTO-LOAD TIMING....38 + +## 1. General Description + +The RTL8305NBI is a 5-port 10/100M Ethernet switch controller that integrates memory, five MACs, and five physical layer transceivers for 10Base-T and 100Base-TX operation into a single chip. + +In order to accomplish diagnostics in complex network systems, the RTL8305NBI provides a loopback feature in each port. + +The RTL8305NBI supports several advanced QoS functions with four-level priority queues to improve multimedia or real-time networking applications, including: + +• Multi-priority assignment +- Differential queue weight +• Port-based rate limitation +- Queue-based rate limitation + +## DRAFT + +The RTL8305NBI supports 16 VLAN groups. These can be configured as port-based VLANs and/or 802.1Q tag-based VLANs. The RTL8305NBI also supports VLAN learning, with four Independent VLAN Learning (IVL) filtering databases. + +The RTL8305NBI contains a 2K-entry address lookup table. A 4-way associative hash algorithm avoids hash collisions and maintains forwarding performance. + +Maximum packet length can be 2048 bytes. Three types of independent storm filter are provided to filter packet storms, and an intelligent switch engine prevents Head-of-Line blocking problems. + +The RTL8305NBI supports Energy-Efficient Ethernet mode (EEE; defined in IEEE 802.3az) to minimize system power consumption. Energy-Efficient Ethernet (EEE) supports Low Power Idle Mode. When Low Power Idle Mode is enabled, systems on both sides of the link can disable portions of the functionality and save power during periods of low link utilization. + +To simplify the peripheral power circuit, the RTL8305NBI integrates one LDO regulator to generate 1.0V from a 3.3V input power, and needs only one external diode. + +## 2. Features + +## Basic Switching Functions + +## DRAFT + +■ 5-port switch controller with memory and transceiver for 10Base-T and 100Base-TX +■ Non-blocking wire-speed reception and transmission and non-head-of-line-blocking forwarding +■ Complies with IEEE 802.3/802.3u auto-negotiation +■ Built-in high efficiency SRAM for packet buffer, with 2K-entry lookup table and two 4-way associative hash algorithms +■ 2048 byte maximum packet length +■ Flow control fully supported +◆ Half duplex: Back pressure flow control +◆ Full duplex: IEEE 802.3x flow control + +## Service Quality + +■ Supports high performance QoS function on each port +◆ Supports 4-level priority queues +◆ Weighted round robin service +◆ Supports strict priority +◆ Input/Output port bandwidth control +◆ Queue-based bandwidth control +◆ 1Q-based, Port-based, DSCP-based, IP address-based, and other types of priority assignments +■ Supports IEEE 802.1p Traffic Remarking + +## DRAFT + +## Security and Management + +■ Supports reserved control frame filtering +■ Supports advanced storm filtering +■ Optional EEPROM interface for configuration + +## VLAN Functions + +■ Supports up to 16 VLAN groups +■ Flexible 802.1Q port/tag-based VLAN +■ Supports four IVLs +■ Leaky VLAN for unicast/multicast/broadcast/ARP packets + +## Power Saving Functions + +■ Supports Energy-Efficient Ethernet (EEE) function (IEEE 802.3az) +■ Link Down Power Saving Mode + +## Diagnostic Functions + +■ Supports hardware loop detection function with LEDs and buzzer to indicate the existence of a loop +■ Supports cable diagnosis (RTCT function) +■ Flexible LED indicators +◆ RTCT status indication +◆ Loop status indication +◆ LEDs blink upon reset for LED diagnostics + +## Other Features + +■ Optional MDI/MDIX auto crossover for plug-and-play + +■ Physical layer port Polarity Detection and Correction function +■ Robust baseline wander correction for improved 100Base-TX performance +■ 25MHz crystal or 3.3V OSC input + +## DRAFT + +■ Single 3.3V power input can be transformed by integrating an LDO regulator to generate 1.0V from 3.3V via a low-cost external diode +■ Low power, 1.0/3.3V, 55nm CMOS technology +■ 48-pin QFN ‘Green’ package + +## 3. System Applications + +■ 5-port switch (10Base-T & 100Base-TX) + +## 4. Block Diagram + +![](images/198313fafc0c4560187d639b30e333064548c707efff34e8d11cd020dfecd291.jpg) + +
+flowchart + +This diagram illustrates the architecture and data flow of a system architecture, showing interactions between components like a Lookup Table, Packet Buffer, MII_REG/AUTOLOAD, Global Function, LED Control, LDO Regulator, Waveform Shaping, and LED_BLNK_TIME. +
+ +Figure 1. Block Diagram + +## 5. Pin Assignments + +## 5.1. Pin Assignments Diagram + +![](images/bd801eb45eda6fbd1ccdb70573cb87911847e19b5dc867acebccf0258d140cba.jpg) + +
+text_image + +V10OUT +DVDDL +P4LED +P3LED +P2LED/DIS_RST_BLNK +DVDDH +P1LED +P0LED/DIS_EEE +LDIND/DIS_LD +RESETB +SDA/MDIO +SCL/MDC +36 +35 +34 +33 +32 +31 +30 +29 +28 +27 +26 +25 +V 33 IN +37 +AVDDHPLL +38 +XO +39 +XI +40 +AVDDLPLL +41 +IBREF +42 +AVDDL +43 +RXIP 0 +44 +RXIN 0 +45 +TXON 0 +46 +TXOP 0 +47 +AVDDH +48 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +24 +DVDDL +AVDDL +RXIP4 +RXIN4 +TXON4 +TXOP4 +AVDDH +TXOP3 +TXON3 +RXIN3 +RXIP3 +AVDDL +AVDDL +
+ +Figure 2. Pin Assignments + +## 5.2. Package Identification + +Green package is indicated by the ‘G’ in GXXXX in Figure 2. + +## 5.3. Pin Assignments Table + +‘Type’ codes used in the following table: A=Analog, D=Digital, I=Input, O=Output, I/O=Input/Output, I $_{PU}$ =Input Pin with Pull-Up Resistor, I $_{PD}$ =Input Pin with Pull-Down Resistor, G=Ground. + +Table 1. Pin Assignments Table + +
NamePin No.Type
AVDDL1AP
RXIP12AI/O
RXIN13AI/O
TXON14AI/O
TXOP15AI/O
AVDDH6AP
DVDDL7P
AVDDH8P
TXOP29AI/O
TXON210AI/O
RXIN211AI/O
RXIP212AI/O
AVDDL13AP
RXIP314AI/O
RXIN315AI/O
TXON316AI/O
TXOP317AI/O
AVDDH18AP
TXOP419AI/O
TXON420AI/O
RXIN421AI/O
RXIP422AI/O
AVDDL23AP
DVDDL24P
SCL/MDC25I/ $O_{PU}$
+ +
NamePin No.Type
SDA/MDIO26 $I/O_{PU}$
RESETB27 $I_{PU}$
LDIND/DIS_LD28 $I/O_{PU}$
P0LED/DIS_EEE29 $I/O_{PD}$
P1LED30 $I/O_{PD}$
DVDDH31P
P2LED/DIS_RST_BLNK32 $I/O_{PD}$
P3LED33 $I/O_{PD}$
P4LED34 $I/O_{PD}$
DVDDL35P
V10OUT36AO
V33IN37AP
AVDDHPLL38AP
XO39AO
XI40AI
AVDDLPLL41AP
IBREF42AO
AVDDL43AP
RXIP044AI/O
RXIN045AI/O
TXON046AI/O
TXOP047AI/O
AVDDH48AP
E-PADE-PADG
+ +## 6. Pin Descriptions + +## 6.1. Pin Assignment Codes + +I: Input Pin + +O: Output Pin + +I/O: Bi-Directional Input/Output Pin + +P: Digital Power Pin + +G: Digital Ground Pin + +$I_{PU}$ : Input Pin With Pull-Up Resistor; +(Typical Value is about 75KΩ) + +$I_{PD}$ : Input Pin With Pull-Down Resistor; +(Typical Value is about 75KΩ) + +$I/O_{PU}$ : $I_{PU}$ and $O_{PU}$ + +AI: Analog Input Pin + +AO: Analog Output Pin + +AI/O: Analog Bi-Directional Input/Output Pin + +AP: Analog Power Pin + +AG: Analog Ground Pin + +$O_{PU}$ : Output Pin With Pull-Up Resistor; +(Typical Value is about 75KΩ) + +$O_{PD}$ : Output Pin With Pull-Down Resistor; +(Typical Value is about 75KΩ) + +$I/O_{PD}: I_{PD}$ and $O_{PD}$ + +## 6.2. Media Connection Pins + +Table 2. Media Connection Pins + +
Pin NamePin No.TypeDrive (mA)Description
RXIP4/RXIN422, 21AI/O-Differential Receive Data Input.
RXIP3/RXIN314, 15Port0~4 support 10Base-T, 100Base-TX.
RXIP2/RXIN212, 11
RXIP1/RXIN12, 3
RXIP0/RXIN044, 45
TXOP4/TXON419, 20AI/O-Differential Transmit Data Output.
TXOP3/TXON317, 16Port0~4 support 10Base-T, 100Base-TX.
TXOP2/TXON29, 10
TXOP1/TXON15, 4
TXOP0/TXON047, 46
+ +## 6.3. Miscellaneous Pins + +As the output of the RTL8305NBI is 3.3V, the serial EEPROM and external device must be 3.3V compatible. + +Table 3. Miscellaneous Pins + +
Pin NamePin No.TypeDrive (mA)Description
LDIND/DIS_LD28I/ $O_{PU}$ 10Loop Indication Used by LED and Buzzer.
SCL/MDC25I/ $O_{PU}$ 4I2C Interface Clock for EEPROM Auto Load when Power On.After power on, this pin is MDC/MDIO Interface Clock for access registers.
SDA/MDIO26I/ $O_{PU}$ 4I2C Interface Data Input/Output for EEPROM Auto Load when Power On.After power on, this pin is MDC/MDIO Interface Data Input/Output for access registers.
RESETB27 $I_{PU}$ -System Pin Reset Input.
XI40AI-25MHz Crystal Clock Input.The clock tolerance is ±50ppm.
XO39AO-25MHz Crystal Clock Output Pin.When the pin of XI is using an oscillator this pin should be floating.
IBREF42AO-Reference Resistor for PHY Bandgap.A 2.49KΩ (1%) resistor should be connected between IBREF and GND.
+ +## 6.4. Port LED Pins + +All LED statuses are represented as active-low or high depending on input strapping. + +Those pins that are dual-function pins are output for LED, or input for strapping. Below are LED descriptions only. + +Table 4. Port LED Pins + +
Pin NamePin No.TypeDrive (mA)Description
P0LED/DIS_EEE29I/ $O_{PD}$ 10LED for Port0 Status Indication.
P1LED30I/ $O_{PD}$ 10LED for Port1 Status Indication.
P2LED/DIS_RST_BLNK32I/ $O_{PD}$ 10LED for Port2 Status Indication.
P3LED33I/ $O_{PD}$ 10LED for Port3 Status Indication.
P4LED34I/ $O_{PD}$ 10LED for Port4 Status Indication.
+ +## 6.5. Strapping Pins + +Pins that are dual function pins are outputs for LED or inputs for strapping. Below are strapping descriptions only. + +Table 5. Strapping Pins + +
Pin NamePin No.TypeDefaultDescription
DIS_LD/LDIND28I/ $O_{PU}$ -Disable Loop Detection Function.0: Enable1: Disable (default)
DIS_EEE/P0LED29I/ $O_{PD}$ -Disable EEE Function.0: Enable EEE function (default)1: Disable EEE function
DIS_RST_BLNK/P2LED32I/ $O_{PD}$ -Disable LED Power on Blinking.0: Enable (default)1: Disable
+ +## 6.6. Regulator Pins + +Table 6. Regulator Pins + +
Pin NamePin No.TypeDrive (mA)Description
V10OUT36AO-Switch Regulator 1.0V Output.
V33IN37AP-Switch Regulator 3.3V Input.
+ +## 6.7. Power and GND Pins + +Table 7. Power and GND Pins + +
Pin NamePin No.TypeDescription
AVDDH6, 8, 18, 48APAnalog Power 3.3V.
AVDDL1, 13, 23, 43APAnalog Power 1.0V.
AVDDHPLL38APPower 3.3V for PLL.
AVDDLPLL41APPower 1.0V for PLL.
DVDDH31PDigital Power 3.3V for IO Pin.
DVDDL7, 24, 35PDigital Power 1.0V for Core Voltage.
GNDE-PADGGround for Whole Chip.
+ +## 7. Basic Function Descriptions + +## 7.1. Switch Core Function Overview + +## 7.1.1. Flow Control + +The RTL8305NBI supports IEEE 802.3x full duplex flow control, force mode full duplex flow control, and optional half duplex backpressure. + +## 7.1.1.1 IEEE 802.3x Full Duplex Flow Control + +For UTP with auto-negotiation ability, the pause ability of full duplex flow control is enabled by internal registers via SMI on a per-port basis after reset. IEEE 802.3x flow control's ability is auto-negotiated between the remote device and the RTL8305NBI. If the auto-negotiation result of the IEEE 802.3x pause ability is ‘Enabled’, the full duplex 802.3x flow control function is enabled. Otherwise, full duplex IEEE 802.3x flow control function is disabled. + +## 7.1.1.2 Half Duplex Back Pressure + +There are two mechanisms for half duplex backpressure; collision-based or carrier-based. + +## Collision-Based Backpressure (Jam Mode) + +If the buffer is ready to overflow, this mechanism will force a collision. When the link partner detects this collision, the transmission is rescheduled. + +The Reschedule procedure is: + +- The RTL8305NBI will drive TXEN to high and send the preamble; SFD and a 4-byte Jam signal (pattern is 0xAA). The RTL8305NBI will then drive TXEN to low +- When the link partner receives the Jam signal, it will feedback a 4-byte signal (pattern is CRC^0x01), it will then drive RXDV to low +- The link partner waits for a random back-off time then re-sends the packet. The timing is shown in Figure 3 + +![](images/645c55aea70b2e7ea978cce17c9de05b162cc555c8c34ff94a7ab9144348c03d.jpg) + +
+flowchart + +```mermaid +graph LR + subgraph CongestionState + A["Congestion State\n0b'1: Congestion\n0b'0: No Congestion"] + end + + subgraph RXD + B["Preamble+SFD+packet"] + C["CRC^0x01"] + end + + subgraph RXDV + D["JAM"] + end + + subgraph TXEN + E["JAM"] + end + + subgraph TXD + F["12bytes"] + end + + A --> B + B -->|Jamming\n4bytes| C + C -->|Backoff time| D + D -->|96 bit times Interframe gap| E + E --> F + F -->|Preamble+SFD+4bytes '0xAA'| B +``` +
+ +Figure 3. Collision-Based Backpressure Signal Timing + +## Carrier-Based Backpressure (Defer Mode) + +If the buffer is about to overflow, this mechanism will send an 0xAA pattern to defer the other station's transmission. The RTL8305NBI will continuously send the defer signal until the buffer overflow is resolved. + +## 7.1.2. Address Search, Learning, and Aging + +When a packet is received, the RTL8305NBI will use the destination MAC address and FID to index the 2048-entry lookup table. If the indexed entry is valid, the received packet will be forwarded to the corresponding destination port. Otherwise, the RTL8305NBI will broadcast the packet. This is the 'Address Search'. + +The RTL8305NBI then combines the source MAC address and the FID to index the 2048-entry lookup table. If the entry is not in the table it will record the source MAC address and add switching information. If this is an occupied entry, it will update the entry with new information when LRU is enabled. This is called ‘Learning’. + +Address aging is used to keep the contents of the address table correct in a dynamic network topology. The lookup engine will update the time stamp information of an entry whenever the corresponding source MAC address appears. An entry will be invalid (aged-out) if its time stamp information is not refreshed by the address learning process during the aging time period. The aging time of the RTL8305NBI is between 200 and 400 seconds. + +## 7.1.3. Half Duplex Operation + +In half duplex mode, the CSMA/CD media access method is the means by which two or more stations share a common transmission medium. To transmit, a station waits (defers) for a quiet period on the medium (that is, no other station is transmitting) and then sends the intended message in bit-serial form. If the message collides with that of another station, then each transmitting station intentionally transmits for an additional predefined period to ensure propagation of the collision throughout the system. The station remains silent for a random amount of time (backoff) before attempting to transmit again. + +When a transmission attempt has terminated due to a collision, it is retried until it is successful. A controlled randomization process called ‘truncated binary exponential backoff’ determines the scheduling of the retransmissions. At the end of enforcing a collision (jamming), the switch delays before attempting to retransmit the frame. The delay is an integer multiple of slot time (512 bit times). The number of slot times to delay before the n $^{th}$ retransmission attempt is chosen as a uniformly distributed random integer ‘r’ in the range: + +$$ +0 \leq \mathrm{r} < 2 ^ {\mathrm{k}} +$$ + +where: + +k = min (n, backoffLimit). IEEE 802.3 defines the backoffLimit as 10. + +## 7.1.4. InterFrame Gap + +The InterFrame Gap is 9.6μs for 10Mbps Ethernet and 960ns for 100Mbps Fast Ethernet. + +## 7.1.5. Illegal Frame + +Illegal frames such as CRC error packets, runt packets (length < 64 bytes), and oversize packets (length > maximum length), will be discarded. + +## 7.2. Physical Layer Functional Overview + +## 7.2.1. Auto-Negotiation + +The RTL8305NBI obtains the states of duplex, speed, and flow control ability for each port through the auto-negotiation mechanism defined in the IEEE 802.3 specifications. During auto-negotiation, each port advertises its ability to its link partner and compares its ability with advertisements received from its link partner. By default, the RTL8305NBI advertises full capabilities (100Full, 100Half, 10Full, 10Half) together with flow control ability. The RTL8305NBI also advertises the Energy Efficient Ethernet (EEE) capability to the link partner. + +## 7.2.2. 10Base-T Transmit Function + +The output 10Base-T waveform is Manchester-encoded before it is driven onto the network media. The internal filter shapes the driven signals to reduce EMI emissions, eliminating the need for an external filter. + +## 7.2.3. 10Base-T Receive Function + +The Manchester decoder converts the incoming serial stream to NRZ data when the squelch circuit detects the signal level is above squelch level. + +## 7.2.4. Link Monitor + +The 10Base-T link pulse detection circuit continually monitors the RXIP/RXIN pins for the presence of valid link pulses. Auto-polarity is implemented to correct the detected reverse polarity of RXIP/RXIN signal pairs. + +## 7.2.5. 100Base-TX Transmit Function + +The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ/NRZI conversion, and MLT-3 encoding. The 5-bit serial data stream after 4B/5B coding is then scrambled as defined by the TP-PMD Stream Cipher function to flatten the power spectrum energy such that EMI effects are significantly reduced. + +The scrambled seed is based on PHY addresses and is unique for each port. After scrambling, the bit stream is driven into the network media in the form of MLT-3 signaling. The MLT-3 multi-level signaling technology moves the power spectrum energy from high frequency to low frequency, which further reduces EMI emissions. + +## 7.2.6. 100Base-TX Receive Function + +The receive path includes a receiver composed of an adaptive equalizer and DC restoration circuits (to compensate for an incoming distorted MLT-3 signal), an MLT-3 to NRZI and NRZI to NRZ converter to convert analog signals to digital bit-stream, and a PLL circuit to clock data bits with minimum bit error rate. A De-scrambler, 5B/4B decoder, and serial-to-parallel conversion circuits are followed by the PLL circuit. Finally, the converted parallel data is fed into the MAC. + +## 7.2.7. Power-Down Mode + +The RTL8305NBI implements power-down mode on a per-port basis. Setting MII Reg.0.11 forces the corresponding port of the RTL8305NBI to enter power-down mode. This disables all transmit/receive functions, except SMI (Serial Management Interface: MDC/MDIO, also known as MII Management Interface). + +## 7.2.8. Crossover Detection and Auto Correction + +During the link setup phase, the RTL8305NBI checks whether it receives active signals on every port in order to determine if a connection can be established. In cases where the receiver data pin pair is connected to the transmitter data pin pair of the peer device and vice versa, the RTL8305NBI automatically changes its configuration and swaps receiver/transmitter data pins as required. If a port is connected to a PC or NIC with MDI-X interface with a crossover cable, the RTL8305NBI will reconfigure the port to ensure proper connection. This replaces the DIP switch commonly used for reconfiguring a port on a hub or switch. + +Note: IEEE 802.3 compliant forced mode 100M ports with Autoxover have link problems with NWay (Auto-Negotiation) ports. It is recommended to not use Autoxover for forced 100M. + +## 7.2.9. Polarity Detection and Correction + +For better noise immunity and lower interference to ambient devices, the Ethernet electrical signal on a twisted-pair cable is transmitted in differential form. That is, the signal is transmitted on two wires in each direction with inverse polarities (+/-). If wiring on the connector is faulty, or a faulty transformer is used, the two inputs to a transceiver may carry signals with opposite but incorrect polarities. As a direct consequence, the transceiver will not work properly. + +When the RTL8305NBI operates in 10Base-T mode, it automatically reverses the polarity of its two receiver input pins if it detects that the polarities of the incoming signals on the pins is incorrect. However, this feature is unnecessary when the RTL8305NBI is operating in 100Base-TX mode. + +## 7.3. General Function Overview + +## 7.3.1. Power-On Sequence + +Two power voltage types are required for RTL8305NBI normal operation; 3.3V and 1.0V. The 1.0V is converted from 3.3V via the LDO of the RTL8305NBI. + +- Ta is the moment when 3.3V power is higher than 2.6V (±5%). 3.3V power never falls lower than 2.6V (±5%) after Ta +- Tb is the moment when 1.0V power is higher than 0.71V (±10%). 1.0V power never falls lower than 0.71V (±10%) after Tb +- Tc is the moment when both 3.3V and 1.0V power are stable (the voltage is always in the legal operating range) +- Td is the moment that the pin reset signal is de-asserted +- Te is the moment that the RTL8305NBI device is ready to be accessed by an external CPU + +![](images/c61a49ca2a243089749f3dccd0833f0a71f3aede6b8a7e61b4ad73951ddb7f65.jpg) + +
+line + +| Time | Pin Reset (V) | 3.3V Power (V) | 1.0V Power (V) | +| --- | --- | --- | --- | +| 0 | 0 | 0 | 0 | +| Ta | 1.0 | 3.3 | 0 | +| Tb | 1.0 | 3.3 | 1.0 | +| Tc | 1.0 | 3.3 | 1.0 | +| Td | 1.0 | 3.3 | 1.0 | +| Te | 3.3 | 3.3 | 1.0 | +
+ +Figure 4. Power-On Sequence + +## The requirements are: + +- The time of Ta should be between $500\mu \mathrm{s}$ and $20\mathrm{ms}$ +- The sequence of Ta is always less than Tb for the LDO of the RTL8305NBI. In principle, the sequence of Td and Ta/Tb/Tc is also not required. The sequence of Td > 5ms is recommended +- The time from Te to the later of Ta/Tb/Td is the sum of the time of the EEPROM loading + 30ms. The EEPROM loading time varies according to the autoloaded data bytes in the serial EEPROM +- Reset + +Depending on the type of reset, the whole or just part of the RTL8305NBI is initialized. There are several ways to reset the RTL8305NBI. + +- Hardware reset for the whole chip via pin RESET# or power-on +- Soft reset for packet buffer, queue, and MIB counter via register SoftReset +• PHY software reset for each PHY by register reset + +Hardware Reset: Power-on, or pull the RESET# pin low for at least 1μs. The RTL8305NBI resets the whole chip and after all power is ready and the RESET# pin is de-asserted, it gets initial values from pins and serial EEPROM. + +Soft Reset: The RTL8305NBI does not reset the LUT, LED circuit, and all registers, and does not load data from serial EEPROM and pins to registers. The packet buffer, queue, and MIB counter will be reset. After changing the queue number via SMI (Serial Management Interface), the external device must perform a soft reset in order to update the configuration. + +PHY Software Reset: Write bit15 of Reg0 of a PHY as 1. The RTL8305NBI will then reset this PHY. + +![](images/4e7f1972851669ee7813932cc0ad1873e0e5703e864a4861aede3708b17ab9f8.jpg) +Figure 5. Reset + +Some setting values for operation modes are latched from those corresponding mode pins upon hardware reset. ‘Upon reset’ is defined as a short time after the end of a hardware reset. Other advanced configuration parameters may be latched from serial EEPROM. + +## 7.3.2. Setup and Configuration + +The RTL8305NBI can be configured easily and flexibly by: + +• Hardware pins upon reset +- Optional serial EEPROM upon reset (contact Realtek for detailed EEPROM configuration settings) +- Internal registers (including PHY registers for each port and global MAC registers) accessed via SMI (Serial Management Interface: MDC/MDIO, also known as MII Management Interface) + +There are three methods of configuration: + +- Only hardware pins for normal switch applications +• Hardware pins and serial EEPROM for advanced switch applications +- Hardware pins and internal registers via SMI for applications with processor + +Two types of pins, each with internal pull-high or pull-low resistors, are used for configuration: + +- Input/Output pins used for strapping upon reset and used as output pins after reset +- Input/Output pins used for strapping upon reset and used as LED indicator pins after reset. The LED statuses are represented as active-low or high depending on input strapping + +Pins with default value=0 are internal pull-low and use I/O pads. They can be left floating to set the input value as low, but should not be connected to VDD without a pull-high resistor. + +The serial EEPROM shares two pins, SCL/MDC and SDA/MDIO, with SMI, and is optional for advanced configuration. SCL/MDC and SDA/MDIO are tri-state during hardware reset (pin RESET#=0). The RTL8305NBI will try to automatically find the serial EEPROM upon reset. + +Internal registers can still be accessed after reset via SMI (pin SCL/MDC and SDA/MDIO). Serial EEPROM signals and SMI signals must not exist at the same time. + +## 7.3.3. Serial EEPROM Example + +Both the 24LC01/02/04/08/16 and 24C01/02/04/08/16 can be used with the RTL8305NBI. The interface is a 2-wire serial EEPROM interface providing 1K/2K/4K/8K/16K bits of storage space. The EEPROM must be 3.3V compatible. + +## 7.3.3.1 EEPROM Device Operation + +Clock and Data Transitions: The SDA pin is normally pulled high with an external resistor. Data on the SDA pin may change only during SCL low time periods. Data changes during SCL high periods will indicate a start or stop condition as defined below. The SCL frequency is 200kHz. + +## Start Condition + +A high-to-low transition of SDA with SCL high is the start condition and must precede any other command. + +## Stop Condition + +A low-to-high transition of SDA with SCL high is a stop condition. + +## Acknowledge + +All addresses and data are transmitted serially to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. + +## Random Read + +A random read requires a ‘dummy’ byte write sequence to load in the data word address. + +## Sequential Read + +For the RTL8305NBI, the sequential reads are initiated by a random address read. After the EEPROM receives a data word, it responds with an acknowledgement. As long as the EEPROM receives an acknowledgement, it will continue to increment the data word address and clock out sequential data words in series. + +![](images/49a918a670aa35035f6309dd20e125137a749897c90d9e4d522f99072068924f.jpg) + +
+flowchart + +```mermaid +graph LR + SDA["SDA"] --> START["START"] + SDA --> STOP["STOP"] + SCL["SCL"] --> START + SCL --> STOP +``` +
+ +Figure 6. Start and Stop Definition + +![](images/5099fe8479487d47f0920c348773ec1a8a10fcf7f3c216e5368948d904f9e870.jpg) + +
+flowchart + +This diagram illustrates the signal processing logic for a digital communication system, showing the relationship between SCL, DATA IN, and DATA OUT signals across a sequence of events. +
+ +Figure 7. Output Acknowledge + +![](images/7e0b5ec52961bb1b0f7b5951ba753a1ad55cb3a81db33f9060a2603822fca44a.jpg) + +
+flowchart + +```mermaid +graph LR + Start --> DeviceAddress["Device Address"] + DeviceAddress --> Write["Write"] + Write --> WordAddress["Word Address n"] + WordAddress --> Start + Start --> DeviceAddress["Device Address"] + DeviceAddress --> Read["Read"] + Read --> Stop + Stop --> Stop + Stop --> Data_n["Data n"] + DataN["Data n"] --> ACK["ACK"] + DataN --> NOACK["NO ACK"] + DataN --> R/WACK["R/W ACK"] + RWack["R/WACK"] --> SDA + SDA --> DummyWrite["Dummy Write"] +``` +
+ +Figure 8. Random Read + +![](images/eb9ba53c18aa9fa48d946018bc43f108cb8756b4610466743ddb7662d3a48e08.jpg) + +
+flowchart + +```mermaid +graph LR + A["Device Address"] --> B["Read"] + B --> C["ACK"] + C --> D["ACK"] + D --> E["ACK"] + E --> F["Stop"] + F --> G["NO ACK"] +``` +
+ +Figure 9. Sequential Read + +## 7.3.3.2 EEPROM Size Selection + +The RTL8305NBI supports five serial EEPROM sizes —1k bits, 2k bits, 4k bits, 8k bits and 16k bits. Via the auto-download operation, the RTL8305NBI decides the size of the data downloaded to the RTL8305NBI from the EEPROM according to the value of the $2^{nd}$ byte data in the serial EEPROM. + +If the $2^{nd}$ byte data = 0x01, 0x02, 0x04, 0x08 or 0x16, it means the data size is 1k bits, 2k bits, 4k bits, 8k bits or 16k bits respectively. The value of the $2^{nd}$ byte should accord with the actual EEPROM data size. For example, the value of the $2^{nd}$ byte cannot be ‘0x02’ when the 24(L)C02 is used. + +## 7.3.4. SMI + +The SMI (Serial Management Interface) is also known as the MII Management Interface, and consists of two signals (MDIO and MDC). It allows external devices with SMI master mode (MDC is output) to control the state of the PHY and internal registers (SMI slave mode: MDC is input). MDC is an input clock for the RTL8305NBI to latch MDIO on its rising edge. The clock can run from DC to 2.5MHz. MDIO is a bi-directional connection used to write data to, or read data from the RTL8305NBI. The PHY address is from 0 to 4. + +Table 8. Basic SMI Read/Write Cycles + +
Preamble (32 bits)Start (2 bits)OP Code (2 bits)PHYAD (5 bits)REGAD (5 bits)Turn Around (2 bits)Data (16 bits)Idle
Read1......10110 $A_4A_3A_2A_1A_0$ $R_4R_3R_2R_1R_0$ Z0 $D_{15}......D_0$ Z*
Write1......10101 $A_4A_3A_2A_1A_0$ $R_4R_3R_2R_1R_0$ 10 $D_{15}......D_0$ Z*
+ +\*: High-impedance. During idle time MDIO state is determined by an external 1.5KΩ pull-up resistor. + +For MDIO Manageable Device (MMD) access, the RTL8305NBI supports the extended SMI format. + +Table 9. Extended SMI Management Frame Format + +
FramePRESTOPPHYADDEVADTADATAIDLE
Address1...10000AAAAAEEEE10AAAAAAAAAAAAAAAAAAZ
Write1...10001AAAAAEEEE10DDDDDDDDDDDDDDDZ
Read1...10011AAAAAEEEEZ0DDDDDDDDDDDDDDDZ
Post-Read-Increment-Address1...10010AAAAAEEEEZ0DDDDDDDDDDDDDDDZ
+ +To guarantee the first successful SMI transaction after power-on reset, the external device should delay a few moments before issuing the first SMI Read/Write Cycle relative to the rising edge of reset. + +## 7.3.5. Head-Of-Line Blocking + +The RTL8305NBI incorporates a mechanism to prevent Head-Of-Line blocking problems when flow control is disabled. When the flow control function is disabled, the RTL8305NBI first checks the destination address of the incoming packet. If the destination port is congested, the RTL8305NBI will discard this packet to avoid blocking the next packet, which is going to a non-congested port. + +## 7.3.6. Filtering/Forwarding Reserved Control Frame + +The RTL8305NBI supports the ability to forward or drop the frames of the IEEE 802.1 specified reserved Ethernet multicast addresses. + +Table 10. Reserved Ethernet Multicast Addresses +B: Broadcast (Search the Look-Up Table) D: Drop + +
AssignmentValueAvailable Action
Bridge Group Address01-80-C2-00-00-00D, B (Default)
IEEE Std 802.3, 1988 Edition, Full Duplex PAUSE Operation01-80-C2-00-00-01D (Default), B
IEEE 802.3ad Slow_Protocols-Multicast Address01-80-C2-00-00-02D (Default), B
IEEE 802.1X PAE Address01-80-C2-00-00-03D, B (Default)
Reserved for Future Standards01-80-C2-00-00-04~01-80-C2-00-00-0D, 01-80-C2-00-00-0FD (Default), B
LLDP IEEE Std 802.1AB Link Layer Discovery Protocol Multicast Address01-80-C2-00-00-0ED, B (Default)
All LANs Bridge Management Group Address01-80-C2-00-00-10D (Default), B
Reserved for 01-80-C2-00-00-1x01-80-C2-00-00-11~01-80-C2-00-00-1FD, B (Default)
GMRP Address01-80-C2-00-00-20D (Default), B
GVRP Address01-80-C2-00-00-21D, B (Default)
Reserved for use by Multiple Registration Protocol (MRP) Applications01-80-C2-00-00-22~01-80-C2-00-00-2FD (Default), B
802.1ag PDU CCM/LTM01-80-C2-00-00-31~01-80-C2-00-00-3FD, B (Default)
+ +## 7.3.7. Loop Detection + +Loops should be avoided between switch applications. The simplest loop as shown below results in: +1) Unicast frame duplication; 2) Broadcast frame multiplication; 3) Address table non-convergence. +Frames are transmitted from Switch1 to Switch2 via Link1, and then returned to Switch1 via Link 2. + +![](images/a91efa1ba7aa08580b2c946cf0970104371fbf2044f56a0ee244b9ea97e9af13.jpg) + +
+text_image + +Switch1 +Switch2 +Link1 +Link2 +
+ +Figure 10. Loop Example + +The loop detect function can be enabled/disabled via strapping pin or registers. When the loop detection function is enabled, the RTL8305NBI sends out a broadcast 64-byte loop frame (the frequency is configured by register) and sniffs for the sent loop frame on each port to detect whether there is a network loop (or bridge loop). If a loop is detected, the RTL8305NBI will drive the external LEDs and buzzer alarm. + +• The LED driven by the LDIND pin will blink +- The LEDs driven by port LED pins (see Table 4, page 8) of the ports on which the network loop is detected will all blink simultaneously +- The buzzer driven by the LDIND pin will buzz at the same frequency as the LED blinking + +Both passive and active buzzers can be supported. The resonant frequency for the passive buzzer is approximately 2kHz. The buzzer and all LEDs will turn on/off simultaneously. In Figure 11, T1 is the turned-off period and T2 is the turned-on period. T1 and T2 are equal and can be configured to 400ms or 800ms. + +![](images/6124cfe6c8b70c02b7c7fa66a9a697e10decded4f8828c08287acdbdafd71dbe.jpg) +Figure 11. LED and Buzzer Control Signal for Loop Detection + +Loop status, LED, and buzzer indications can be cleared when one of the following conditions occurs. + +- Loop frame is not detected in the next loop detection period +• The loop port links down + +The Loop frame length is 64 bytes. Its format is shown below. + +Table 11. Loop Frame Format + +
48-bit48-bit16-bit16-bit12-bit4-bit352-bit16-bit
FFFF FFFF FFFFSID88992300000TTL0000CRC
+ +In order to achieve loop detection, each switch device needs a unique SID (the source MAC address). If an EEPROM is not used, a unique SID should be assigned via SMI after reset. The TTL (Time-To-Live) field is used to avoid a storm triggered by the loop frame. The TTL field in the loop frame will decrease by 1 when it passes through an RTL8305NBI whose MAC address is not equal to the SID of the loop frame. The RTL8305NBI will drop a loop frame in which the TTL is the minimum value (0001 is the minimum value. 0000, meaning 16, is the maximum value). The initial value of the TTL field can be configured via SMI or EEPROM. + +In Figure 12, device A, B, and C are in a loop. Device D connects to device B. Device D generates a loop frame with an initial TTL value 3 then sends to device B. When the loop frame arrives at device C, the TTL value decreases to 2. It turns to 1 when the loop frame is transmitted to device A, and then the loop frame is dropped by the device A. If device D generates loop frames without the TTL mechanism, the loop frames will cause a storm in the loop of devices A, B, and C. The RTL8305NBI provides an option to assign high priority to loop frames to reduce the possibility of erroneous loop frame dropping, and thereby enhance loop detection. + +![](images/1b805c43a02b8e0db8ce9ac7c76cbbed14cca9418e9bc1da130cbf2334237c0c.jpg) + +
+flowchart + +```mermaid +graph TD + A["RTL8305NBI\nD"] --> B["RTL8305NB\nB"] + B --> C["RTL8305NBI\nC"] + C --> D["Dropped"] + D --> A + A --> E["Loop Frame\nTTL=3"] + E --> B + B --> F["Loop Frame\nTTL=2"] +``` +
+ +Figure 12. Loop Example 2 + +## 7.3.8. Reg.0.14 PHY Digital Loopback Return to Internal + +The digital loopback mode of the PHY (return to internal MAC) may be enabled on a per-port basis by setting MII Reg.0.14 to 1. In digital loopback mode, the TXD of the PHY is transferred directly to the RXD of the PHY, with TXEN changed to CRS\_DV, and returns to the MAC via an internal MII. The data stream coming from the MAC will not egress to the physical medium, and an incoming data stream from the network medium will be blocked in this mode. The packets will be looped back in 10Mbps full duplex or 100Mbps full duplex mode. This function is especially useful for diagnostic purposes. For example, a NIC can be used to send broadcast frames into Port 0 of the RTL8305NBI and set Port 1 to Reg0.14 Loopback. The frame will be looped back to Port 0, so the received packet count can be checked to verify that the switch device is good. In this example, Port 0 can be 10M or 100M, and full or half duplex. + +![](images/ff397eedfa5fc265a971e70c369614c56cad1f5059d5ef1e0eed003169e1ae98.jpg) + +
+flowchart + +```mermaid +graph LR + A["MAC"] -->|"Internal MII"| B["PHY"] + B -->|"Output"| A +``` +
+ +Figure 13. Reg. 0.14 Loopback + +As the RTL8305NBI only supports digital loopback in full duplex mode, PHY Reg.0.8 for each port will always be kept on 1 when digital loopback is enabled. The digital loopback only functions on broadcast packets (DA=FF-FF-FF-FF-FF-FF). In loopback mode, the link LED of the loopback port should always be ON, and the Speed and Duplex LED combined to reflect the link status (100full/10full) correctly, regardless of what the previous status of this loopback port was. + +## 7.3.9. LDO for 1.0V Power Generation + +The RTL8305NBI can use an internal LDO to generate 1.0V from a 3.3V power supply. This 1.0V is used for the digital core and analog receiver circuits. Do not use the LDO for other chips, even if the rating is enough. + +Do not connect an inductor (bead) directly between the V10OUT pin and AVDDLPLL pin. This will adversely affect the stability of the 1.0V power to a significant degree. Refer to the reference design for details. + +## 7.3.10. Crystal/Oscillator + +When using a crystal, the RTL8305NBI should connect a loading capacitor from each pin of XI and XO to ground. Whether using an oscillator or driving an external 25MHz clock from another device, the external clock should be fed into the XI pin. The following table shows the requirements of the crystal and oscillator. + +Table 12. Crystal and Oscillator Requirements + +
Nominal Frequency25.000 MHz
Frequency Tolerance±50ppm Max.
Temperature Characteristics±50ppm in Operating Temperature Range
Equivalent Series Resistance of Crystal50 Ohm Max.
XTALI/OSC Input Clock Jitter Tolerance (in 5KHz to 2.5MHz Range)250ps Max.
Duty Cycle40%~60%
+ +## 8. Advanced Function Descriptions + +## 8.1. VLAN Function + +## 8.1.1. VLAN Description + +The RTL8305NBI supports 16 VLAN groups via the 16-entry VLAN table (see Table 13 and Table 14). These can be configured as port-based VLANs and/or IEEE 802.1Q tag-based VLANs. The RTL8305NBI supports four IVLs, with the mapping information in the VLAN table. The contents of the VLAN table can be configured via SMI or EEPROM. Multiple ingress filtering and egress filtering options provide various VLAN admit rules for the RTL8305NBI. The RTL8305NBI also provides a flexible VLAN tag insert/remove function based on port and VID. + +Table 13. VLAN Table + +
Entry IndexVLAN IDMembershipUNTAG_MSKFID
VLAN Entry 0VLAN ID A[11:0]VLAN ID A membership [4:0]VLAN ID A UNTAG_MSK [4:0]FID[1:0]
VLAN Entry 1VLAN ID B [11:0]VLAN ID B membership [4:0]VLAN ID B UNTAG_MSK [4:0]FID[1:0]
..............................
VLAN Entry 15VLAN ID P [11:0]VLAN ID P membership [4:0]VLAN ID P UNTAG_MSK [4:0]FID[1:0]
+ +Table 14. VLAN Entry + +
FieldDescriptionBits
VIDThe VLAN ID for Search. +The VID of the ingress packet will be compared with this field.12
MBRVLAN Member Port Set. +If the bit in this field is ‘1’, the corresponding port is a member port of the VLAN specified by the VID field.6
UNTAG SETVLAN Untag Set. +If the bit in this field is ‘1’, egress packets from the corresponding port will be VLAN-untagged.6
PRIORITYVID-Based Priority. +The priority assigned to all ingress packets of the VLAN specified by the VID field.2
FIDThe FID is Used by Lookup Table for IVL Application.12
+ +The main VLAN features of the RTL8305NBI are as follows: + +• Supports up to 16 VLAN groups +• Flexible IEEE 802.1Q port/tag-based VLAN +- Four IVLs +- Leaky VLAN for ARP broadcast/unicast/multicast packets +- Leaky inter-VLAN mirror function +- VLAN tag Insert/Remove function + +## 8.1.2. Port-Based VLAN + +The 16 VLAN membership registers designed into the RTL8305NBI provide full flexibility for users to configure the member ports to associate with different VLAN groups in the VLAN table. Each port can join more than one VLAN group. + +Port-based VLAN mapping is the simplest implicit mapping rule. Each ingress packet is assigned to a VLAN group based on the input port. It is not necessary to parse and inspect frames in real-time to determine their VLAN association. All the packets received on a given input port will be forwarded to this port's VLAN members. The RTL8305NBI supports VLAN indexes for each port to individually index this port to one of the 16 VLAN membership registers. A port that is not included in a VLAN's member set cannot transmit packets to this VLAN. + +For non-VLAN tagged frames, the RTL8305NBI performs port-based VLAN. The VLAN ID associated with the port-based VLAN index setting is the Port VID (PVID) of this port. The VLAN tag with the ingress port's PVID can be inserted (or replace the VID with a PVID for VLAN-tagged packets) into the packet on egress. The RTL8305NBI also provides an option to admit VLAN tagged packets with a specific PVID only. When IEEE 802.1Q tag-aware VLAN is enabled, the VLAN tag admit control and non-PVID discard are enabled at the same time. Non-tagged packets and packets with an incorrect PVID will be RTL8305NBI. + +The RTL8305NBI supports Port VID (PVID) for each port and can insert a PVID in the VLAN tag on egress. The PVID in the inserted (or replaced) VLAN tag on egress can indicate the source port of the packet. Using this function, VID information carried in the VLAN tag will be changed to PVID. The RTL8305NBI also provides an option to admit VLAN tagged packets with a specific PVID only. If this function is enabled, it will drop non-tagged packets and packets with an incorrect PVID. + +## 8.1.3. IEEE 802.1Q Tagged-VID Based VLAN + +The RTL8305NBI supports 16 VLAN entries to perform IEEE 802.1Q-tagged VID-based VLAN mapping. The RTL8305NBI uses a 12-bit explicit identifier in the VLAN tag to associate received packets with a VLAN. If the VID of a VLAN-tagged frame does not match any of the 16 VLAN entries, the RTL8305NBI will drop the frame. Otherwise, the RTL8305NBI compares the explicit identifier in the VLAN tag with the 16 VLAN IDs to determine the VLAN association of this packet, and then forwards this packet to the member set of this VLAN. + +Two VIDs are reserved for special purposes; one of them is all 1's, which is reserved and currently unused. The other is all 0's, which indicates a priority tag. A priority-tagged frame should be treated as an untagged frame. + +When ‘802.1Q tag aware VLAN’ is enabled, the RTL8305NBI performs 802.1Q tag-based VLAN mapping for tagged frames, but still performs port-based VLAN mapping for untagged frames. If ‘802.1Q tag aware VLAN’ is disabled, the RTL8305NBI performs only port-based VLAN mapping both on non-tagged and tagged frames. + +## 8.1.4. Insert/Remove/Replace Tag + +The RTL8305NBI supports the VLAN Insertion/Removal/replacing action for each port. The 802.1Q VLAN tags can be inserted, removed, or replaced based on the port's setting. + +## 8.1.5. Ingress and Egress Rules + +The RTL8305NBI provides flexible VLAN ingress and egress rules to permit comprehensive traffic control. The RTL8305NBI can filter packets on ingress according to the tag condition of the packet. For a normalized VLAN application and VLAN translation application, each of the RTL8305NBI ports can be independently configured to: + +- ‘admit all frames’ +- ‘admit only tagged frames’ +- ‘admit only untagged frames’ + +Note: The priority tagged frame (VID=0) will be treated as an untagged frame. + +The RTL8305NBI can optionally discard a frame associated with a VLAN of which the ingress port is not in the member set. + +For the egress filter, the RTL8305NBI drops the frame if this frame belongs to a VLAN but its egress port is not one of the VLAN's member ports. However, there are 5 leaky options to provide exceptions for special applications. + +- ‘Unicast leaky VLAN’ enables inter-VLAN unicast packet forwarding. That is, if the layer 2 lookup table search has a hit, then the unicast packet will be forwarded to the egress port, ignoring the egress rule +- ‘Multicast leaky VLAN’ enables inter-VLAN multicast packet forwarding. Packets may be flooded to all the multicast address group member sets, ignoring the VLAN member set domain limitation +- ‘Broadcast leaky VLAN’ enables inter-VLAN broadcast packet forwarding. Packets may be flooded to all the other ports, ignoring the VLAN member set domain limitation +- ‘ARP leaky VLAN’ enables broadcasting of ARP packets to all other ports, ignoring the egress rule +- ‘Inter-VLAN mirror function’ enables the inter-VLAN mirror function, ignoring the VLAN member set domain limitation. The default value is ‘Enable the inter-VLAN mirror’ + +## 8.2. IEEE 802.1p Remarking Function + +The RTL8305NBI provides IEEE 802.1p Remarking ability. Each port can enable or disable IEEE 802.1p Remarking ability. + +In addition, there is a RTL8305NBI global IEEE 802.1p Remarking Table. When one port enables 802.1p Remarking ability, 2-bit priority (not QID) determined by the RTL8305NBI is mapped to 3-bit priority according to the 1p Remarking Table. + +If the port's 1p remarking function is enabled, transmitting VLAN tagged packets will have the 1Q VLAN tag's Priority field replaced with the 3-bit 1p remarking Priority. + +When the VLAN tags are inserted to non-tagged packets, the inserted tag's priority will accord with the 1p remarking table, even if the port's 1p remarking function is disabled. When the VLAN tag is replaced on tagged packets and the 1p remarking function is disabled, the VLAN tag's VID will be replaced but the priority will not change. For a VLAN-tagged packet, the VID and 3-bit priority can be replaced by the RTL8305NBI independently. + +## 8.3. QoS Function + +## 8.3.1. Bandwidth Control + +## 8.3.1.1 Output (TX) Bandwidth Control + +The RTL8305NBI supports MIN-MAX packet scheduling. + +Packet scheduling offers three modes: + +- Type I leaky bucket, which specifies the average rate of one queue (see Figure 14; only Q2 and Q3 have leaky bucket, Q0 and Q1 do not). The queue rate can be configured from 0kbps to the line rate in steps of 64kbps +- Weighted Round Robin (WRR), which decides which queue is selected in one slot time to guarantee the minimal packet rate of one queue +- Port bandwidth control (type II leaky bucket) to control the bandwidth of the whole port. The port rate can be configured from 0kbps to the line rate in steps of 64kbps + +In addition, the RTL8305NBI can select one of the two sets of packet-scheduling configurations according to the packet-scheduling mode. Figure 14 shows the RTL8305NBI packet-scheduling diagram. + +![](images/749dec27c23c03f95da26e19f9cc62be88663349725479a4468173e933279e14.jpg) + +
+flowchart + +```mermaid +graph LR + Q0["Input Token"] --> Center(("Central Node")) + Q1["Input Token"] --> Center + Q2["Input Token"] --> Center + Q3["Input Token"] --> Center + Center --> Output(("Port Bandwidth Control")) +``` +
+ +Figure 14. Packet-Scheduling Diagram + +## Weighted Round Robin (WRR) + +WRR adds weighting on the basis of Round Robin; for example, assume Q3:Q2:Q1:Q0: 4:3:2:1, then the transmit order will be: + +```txt +Q0-> +Q1->Q1-> +Q2->Q2->Q2-> +Q3->Q3->Q3->Q3-> +``` + +WRR guarantees a minimal packet rate for one queue only. + +If there is strict priority (only in Q2 and Q3) and WRR at the same time, the queue with strict priority has higher priority than WRR. When the scheduler scans queues, queues with strict priority are scanned first, and then the other queues are scanned according to WRR. If there is more than one queue with strict priority, the queue with the bigger QID has higher priority. + +## 8.3.1.2 Input (RX) Bandwidth Control + +Input bandwidth control limits the input bandwidth. When input traffic is more than the RX Bandwidth parameter, this port will either send out a ‘pause ON’ frame, or drop the input packet depending on flow control status. The input bandwidth can also be configured from 0kbps to the line rate in steps of 64kbps. + +## 8.3.2. Priority Assignment + +Priority assignment specifies the priority of a received packet according to various rules. The RTL8305NBI can recognize the QoS priority information of incoming packets to give a different egress service priority. + +The RTL8305NBI identifies the priority of packets based on several types of QoS priority information: + +• Port-based priority +• IEEE 802.1p/Q VLAN Priority Tag +- DSCP Priority field +- IP Address +• Reassigned priority +- RLDP priority + +Below is a block diagram of the priority assignment. + +![](images/b6fe08b94dfd4b27cb615e32019d57e24f462b5012f407caac11f5a8c89cda41.jpg) + +
+flowchart + +```mermaid +graph LR + A["Frame"] --> B["1Q-Based Priority Assignment"] + A --> C["Port-Based Priority Assignment"] + A --> D["DSCP-Based Priority Assignment"] + B -->|"3-bit priority"| E["Priority Mapping"] + C -->|"2-bit priority"| F["Traffic Priority Selection"] + D -->|"2-bit priority/NULL"| F + E --> F + F --> G["IP priority"] + F --> H["IP priority enabled and IP address matched"] + G --> I["Reassigned priority"] + H --> I + I --> J["Reassignment enabled"] + J --> K["RLDP priority"] + K --> L["Loop Frame Priority Enable"] + L --> M["Priority To QID"] + M --> N["QID"] +``` +
+ +Figure 15. RTL8305NBI Priority Assignment Diagram + +## 8.3.2.1 Queue Number Selection + +In the RTL8305NBI, the output queue number can be set. All ports follow a global configuration. The maximum number of output queues per port is 4. After changing the queue number via SMI (Serial Management Interface), the external device must perform a soft reset in order to update the configuration. + +## 8.3.2.2 Port-Based Priority Assignment + +Each physical port is assigned a 2-bit priority level. Packets received from a high-priority port are sent to the high-priority queue of the destination port. Port-based priority can be disabled by register setting. + +## 8.3.2.3 IEEE 802.1p/Q-Based Priority Assignment + +In IEEE 802.1Q-based priority assignment, when a packet is VLAN-tagged or priority-tagged, the 3-bit priority is specified by tag. When a packet is untagged, the 802.1Q-based priority is assigned to the default 2-bit priority information of a physical port. So, each port must provide a default 2-bit priority (every received packet must be assigned a 2-bit 1Q-Based Priority). When the priority comes from a packet, the 1Q-based priority is acquired by mapping 3-bit tag priority to 2-bit priority though an RTL8305NBI 1Q-based Priority Mapping Table. The 1Q-based priority can be disabled. + +## 8.3.2.4 DSCP-Based Priority Assignment + +DSCP (Differentiated Services Code Point)-based priority assignment maps the DSCP of an IP packet to 2-bit priority information through a DSCP to priority table, as DSCP is only in the IP packet. A non-IP packet (such as a Layer 2 frame, ARP, etc) will get a NULL instead of a 2-bit priority. For an IPv6 IP header, DSCP-based priority assignment acquires the DSCP value according to the class of IPv6 header. + +In the RTL8305NBI, DSCP-based priority assignment provides a DSCP to Priority Table of all DSCP value. If the DSCP of a packet is not matched in the table, the DSCP-based priority is 2'b00, The DSCP-based priority can be disabled by register. + +## 8.3.2.5 IP Address-Based Priority + +When IP-based priority is enabled, any incoming packets with source or destination IP address equal to the configuration in register IP Priority Address [A] and IP Priority Mask [A], or IP Priority Address [B] and IP Priority Mask [B] will be set to a 2-bit priority. + +IP priority [A] and IP priority [B] may be enabled or disabled independently. IP address-based priority can be enabled or disabled by the control register. + +## 8.3.2.6 Reassigned Priority + +RTL8305NBI can reassign the priority mainly according to the packets' DMAC information. This function is used to differentiate the priority of the Layer 2 control packet, broadcast packet, multicast packet, unicast packet, and so on. + +## 8.3.2.7 RLDP-Based Priority + +To support the loop detection effectively, the RTL8305NBI provides the RLDP-based priority assignment. When it is enabled, the pre-defined priority will be assigned to all RLDP packets. + +## 8.3.2.8 Packet Priority Selection + +As one received packet may simultaneously support several priority assignment mechanisms, e.g., Port-Based Priority, 1Q-Based Priority, DSCP-Based Priority, it may get several different priority values. + +- RLDP-based priority has the highest priority +- If RLDP-based priority is disabled, the final priority is equal to the reassigned priority +- If RLDP-based priority and reassigned priority is disabled, the final priority is equal to the IP address priority +- If RLDP-based priority, reassigned priority and IP address priority are disabled, the following rules are used to decide a final priority for the other five types of priority + +There is a 2-bit register for each of the three types of priority that represent the weight of the priority. The higher value in the register indicates a higher weight for the priority. If more than one of the three types of priority is the same, the final priority will be the one of the three types, whose priority value is greatest. + +## Queue Priority Mapping + +The 2-bit priority has four numbers; however, every port has at most four output queues, so every port needs a User Priority to Traffic Class Mapping Table to map the priority to QID. A set of Traffic Class Mapping Tables is provided for each port independently. There is a mechanism to prevent a problem caused by mapping the traffic to an unused queue. For example, when a port's queue number is 2, the queue 2 and queue 3 are not used and mapping the traffic to queue 2 or queue 3 will cause the system to crash. In the mechanism, traffic mapped to the unused queue will be forced to the highest used queue (queue 2 in a 3-queue case, queue 1 in a 2-queue case, queue 0 in a 1-queue case). In the example, the traffic mapped to a port's queue 2 or queue 3 will be forwarded to queue 1. + +## 8.4. Lookup Table Function + +## 8.4.1. Function Description + +• 2048-entry Lookup Table (LUT) +• 4-way entry for each entry index +- Supports LRU (Least Recently Used) function for lookup table learning + +## 8.4.2. Address Search, Learning, and Aging + +Received packets are forwarded according to the information learned or written into the LUT. When a packet is received, the RTL8305NBI tries to retrieve learned information and assign a forwarding destination port to the packet. + +The 48-bit destination MAC address (DA) of the received packet and the 2-bit FID are used to calculate a 9-bit index value. The hash algorithm uses all 48 bits of the MAC address and 2 bits of the FID. The hash algorithm is shown below. + +```txt +Index 0 = MAC4 ^ MAC11 ^ MAC18 ^ MAC25 ^ MAC32 +Index1 = MAC3 ^ MAC10 ^ MAC17 ^ MAC24 ^ MAC47 +Index2 = MAC2 ^ MAC9 ^ MAC16 ^ MAC39 ^ MAC46 +Index3 = MAC1 ^ MAC8 ^ MAC31 ^ MAC38 ^ MAC45 +Index4 = FID1 ^ MAC0 ^ MAC23 ^ MAC30 ^ MAC37 ^ MAC44 +Index5 = FID0 ^ MAC15 ^ MAC22 ^ MAC29 ^ MAC36 ^ MAC43 +Index6 = MAC7 ^ MAC14 ^ MAC21 ^ MAC28 ^ MAC35 ^ MAC42 +Index7 = MAC6 ^ MAC13 ^ MAC20 ^ MAC27 ^ MAC34 ^ MAC41 +Index8 = MAC5 ^ MAC12 ^ MAC19 ^ MAC26 ^ MAC33 ^ MAC40 +``` + +As the 9-bit MAC addresses, MAC[13:15] and MAC[0:5], are not stored in the LUT entries, these MAC address bits should be calculated from the index information via the following method when the hash algorithm is selected. + +```txt +MAC0 = Index4 ^ FID1 ^ MAC23 ^ MAC30 ^ MAC37 ^ MAC44 +MAC1 = Index3 ^ MAC8 ^ MAC31 ^ MAC38 ^ MAC45 +MAC2 = Index2 ^ MAC9 ^ MAC16 ^ MAC39 ^ MAC46 +MAC3 = Index1 ^ MAC10 ^ MAC17 ^ MAC24 ^ MAC47 +MAC4 = Index0 ^ MAC11 ^ MAC18 ^ MAC25 ^ MAC32 +MAC5 = Index8 ^ MAC12 ^ MAC19 ^ MAC26 ^ MAC33 ^ MAC40 +MAC13 = Index7 ^ MAC6 ^ MAC20 ^ MAC27 ^ MAC34 ^ MAC41 +MAC14 = Index6 ^ MAC7 ^ MAC21 ^ MAC28 ^ MAC35 ^ MAC42 +MAC15 = Index5 ^ FID0 ^ MAC22 ^ MAC29 ^ MAC36 ^ MAC43 +``` + +The hashed index key is used to locate a matching LUT entry. There are 4 entries sharing one index key (Table 15). This is called a 4-way hash. It is helpful to minimize address collisions in the address learning process. The address search engine compares the DA packet with the data in 4 entries, from entry 3 to entry 0. The final forwarding destination is abstracted from the first matching entry. If the address search fails to return a matching LUT entry, the packet will be flooded to appropriate ports. + +Table 15. L2 Table 4-Way Hash Index Method + +
IndexEntry 0Entry 1Entry 2Entry 3
0x00MAC Addr 0MAC Addr 1MAC Addr 2MAC Addr 3
0x01MAC Addr 4MAC Addr 5MAC Addr 6MAC Addr 7
0x02MAC Addr 8MAC Addr 9MAC Addr 10MAC Addr 11
...............
0x1FEMAC Addr 2040MAC Addr 2041MAC Addr 2042MAC Addr 2043
0x1FFMAC Addr 2044MAC Addr 2045MAC Addr2046MAC Addr 2047
+ +Address learning is the gathering process and storing of information from received packets for the future purpose of forwarding frames addressed to the receiving port. The information includes the source MAC address (SA) and the receiving port. As with the hash algorithm, an address search is used in address learning. The SA of the received packet is used to calculate the entry index. The receiving port information and the aging timer of the first matching entry will be updated when an address is learned. If there is no matching entry, the packet's information will be ‘learned’ into the first empty entry. The SA will not be learned when all of the 4 entries are occupied. The address learning process can be disabled on a per-port basis via register setting. + +For unicast packet learning & search, and multicast packet search, the RTL8305NBI applies the same 4-way hash algorithm. + +Address aging is used to keep the contents of the learned address table updated in a dynamic network topology. The look-up engine will update the aging timer of an entry whenever the corresponding SA appears. An entry will be invalid (aged out) if its aging timer is not refreshed by the address learning process during the aging time period. The aging time of the RTL8305NBI is between 200 and 400 seconds. The RTL8305NBI also supports a fast aging function that is used to age all dynamic entries within 1ms. + +## 8.4.3. Lookup Table Definition + +In traditional switch learning, if a MAC address hash collision occurs then the later MAC address in the collision will not be learned into the lookup table. The LRU function attempts to resolve this problem. + +When Enable LRU = 0b1, then the LRU function is enabled. If the Source MAC address of the incoming packet encounters a hash collision during the learning process and when the 4-way entries are all occupied, then the switch will learn the address in one of the 4-way entries using the LRU aging timer. The criteria for selecting the entry to over-write is comparing via the aging timer and choosing the oldest entry. If the aging timer of the 4 entries are the same, then the entry with the highest Entry\_Address[1:0] value is selected to be over-written. + +## 8.5. Storm Filter Function + +The RTL8305NBI can effectively control four-types of broadcast storms; those caused by broadcast packets, multicast packets, unknown multicast packets, and unknown DA unicast packets. + +Note: Broadcast packets discussed here are packets whose DA is ff-ff-ff-ff-ff-ff. + +Multicast packets include all multicast packets and only unknown multicast packets, which are those whose DA is a multicast address, but excluding 01-80-C2-00-00-xx. + +An unknown DA unicast packet is a packet whose DA is a unicast address and is not found in the lookup table of the switch. + +The RTL8305NBI can configure a storm filter rate for these four packet types, and the rate unit can be configured as packet-based or byte-based via registers. The storm filter rate limits the packet forwarding rate to less than the rate threshold. + +## 8.6. Input and Output Drop Function + +If some destination ports are blocking, or the buffer is full, the frames to these ports will be dropped. + +There are two types of drop: + +- Input Drop: Drop the frame directly. Do not forward to any port +- Output Drop: Forward only to non-blocking ports + +For the RTL8305NBI, the dropping of broadcast, multicast, and unknown DA frames can be controlled independently. + +1. Broadcast packet from Port 0. +2. Buffer of Port 4 is full, others are not full. + +![](images/4fe8f9acb653060f87c94c3c6953b00ba53ca74abddd65eb47add29d9aaa4aea.jpg) + +
+flowchart + +```mermaid +graph LR + Input["Input Signal"] --> Port1["Port 1"] + Port1 --> Port2["Port 2"] + Port2 --> Port3["Port 3"] + Port3 --> Port4["Port 4"] + Port4 --> Output["Full Output"] +``` +
+ +![](images/b59e70a3c9bf0c9ae04938f84f7483a5988f92f9ac0b568e65ea9e3414f1955d.jpg) + +
+flowchart + +```mermaid +graph LR + A["RX: Port 0"] --> B["1"] + B --> C["2"] + C --> D["3"] + D --> E["4"] + E --> F["Full"] + F --> G["Output Drop"] +``` +
+ +Figure 16. Broadcast Input Drop vs. Output Drop + +1. Multicast packet from Port 0. +2. Buffer of Port 4 is full, Port 1 is not full. + +![](images/3135275e347bf51648ad50ff6efa0c45e2cd3bc7d7c5339fd025eefb82ae4f75.jpg) + +
+flowchart + +```mermaid +graph LR + A["Input Drop"] --> B["RX: Port 0"] + B --> C["1"] + C --> D["2"] + D --> E["3"] + E --> F["4"] + F --> G["Full"] +``` +
+ +![](images/3b3056034742118b08abf87ff01edcafeed8cb793c0634c93168a3b075bf9978.jpg) + +
+flowchart + +```mermaid +graph LR + A["RX: Port 0"] -->|1| B["Output Drop"] + B -->|2| C["Output Drop"] + C -->|3| D["Output Drop"] + D -->|4| E["Full Output"] +``` +
+ +Figure 17. Multicast Input Drop vs. Output Drop + +## 8.7. LED Function + +The RTL8305NBI provides flexible LED functions for diagnostics. The LEDs can be configured to indicate the link information (link, activity, speed, duplex), and collision & loop detection information. + +The parallel LED for each port indicates the port's link information when loop-detection is disabled or no loop condition occurs. If the loop is detected on a port, the parallel LED will blink. + +All LED statuses are represented as active-low or high depending on input strapping. + +LED\_BLINK\_TIME determines the LED blinking period for activity and collision via register (0: 32ms and 1: 128ms). + +Some LED pins are dual function pins: input operation for configuration upon reset, and output operation for LED after reset. If the pin input is floating upon reset, the pin output is active high after reset. Otherwise, if the pin input is pulled high upon reset, the pin output is active low after reset. + +Figure 18 shows example circuits for LEDs. Typical values for pull-down resistors are 10KΩ. + +![](images/0adbe7f62e1c38cd50ea0890e6ebd215d7c8805643091907bd9562688f173534.jpg) +Figure 18. Floating and Pull-High of LED Pins for LED + +## 8.8. Energy-Efficient Ethernet (EEE) + +The RTL8305NBI supports Energy-Efficient Ethernet (EEE) function as defined in IEEE 802.3az. The EEE function implements the Low Power Idle (LPI) mode at 100Mbps operation to save power during periods of low link utilization. In Low Power Idle mode, devices on both sides of the link disable portions of the functionality to lower the power consumption. + +At the transmitter side, the RTL8305NBI port 0\~4 can automatically enter or quit LPI mode based on their transmission loading. When a port's EEE function is enabled, the transmission loading is monitored in real time. If the transmission loading is lower than a preset threshold, this port's transmission circuit will enter LPI mode during the idle period. When there are packets to be transmitted, this port wakes up and quits LPI mode. + +There are two types of wake-up: + +- Packets in a high priority queue or a control packet (e.g., a PAUSE frame). These can wake up the port immediately +- Packet in a low priority queue that reach a preset number. A port in LPI mode can be woken up by low priority packets when the number of the cumulated low priority packets exceeds the preset threshold or a delay timer expires + +At the receiver side, each embedded PHY of the RTL8305NBI will automatically respond to the request from the link partner to enter or quit the LPI mode. + +The EEE ability for 100Base-TX on each side of a link should be exchanged via auto-negotiation. Auto-negotiation is mandatory when EEE is enabled. The MDIO Manageable Device (MMD), defined in IEEE 802.3, Clause 45, should also be supported, as the EEE register is located in the MMD of each PHY. + +The RTL8305NBI also supports EEE at 10Mbps operation by reducing the transmit amplitude (10Base-Te). 10Base-Te is fully interoperable with 10Base-T PHYs over 100m of Category 5 or better cable. + +The EEE function for each port is enabled by default and can be disabled independently via strapping pin, registers, or EEPROM configurations. + +## 8.9. Cable Diagnosis + +The RTL8305NBI physical layer transceivers use DSP technology to implement the Realtek Cable Tester (RTCT) feature for cable diagnosis. The RTCT feature can detect short, open, or normal in both differential pair signal runs. + +## 9. Characteristics + +## 9.1. Electrical Characteristics/Maximum Ratings + +WARNING: Maximum ratings are limits beyond which permanent damage may be caused to the device or which may affect device reliability. All voltages are specified reference to GND unless otherwise specified. + +Table 16. Electrical Characteristics/Maximum Ratings + +
ParameterMinMaxUnits
DVDDH, AVDDH, AVDDHPLL Supply Referenced to GNDGND-0.3+3.63V
DVDDL, AVDDL, AVDDLPLL Supply Referenced to GNDGND-0.3+1.10V
+ +## 9.2. Operating Range + +Table 17. Operating Range + +
ParameterMinMaxUnits
Storage Temperature-55+150°C
Ambient Operating Temperature (Ta)-40+85°C
3.3V Vcc Supply Voltage Range (DVDDH, AVDDH, AVDDHPLL)3.133.47V
1.0V Vcc Supply Voltage Range (DVDDL, AVDDL, AVDDLPLL)0.951.05V
+ +## 9.3. DC Characteristics + +Table 18. DC Characteristics + +
ParameterSYMConditionMinTypicalMaxUnits
TTL Input High Voltage $V_{ih}$ -2.0--V
TTL Input Low Voltage $V_{il}$ ---0.8V
TTL Input Current $I_{in}$ --10-10μA
TTL Input Capacitance $C_{in}$ --3-pF
Output High Voltage $V_{oh}$ -2.25--V
Output Low Voltage $V_{ol}$ ---0.4V
Output Three State Leakage Current $|I_{OZ}|$ ---10μA
Power Supply Current for 1.0VIcc10Base-T, idle-31-mA
10Base-T, Peak continuous 100% utilization-32-
100Base-TX, idle-81-
100Base-TX, Peak continuous 100% utilization-81-
Link down-30-
Power Supply Current for 3.3VIcc10Base-T, idle-18-mA
10Base-T, Peak continuous 100% utilization-81-
100Base-TX, idle-95-
100Base-TX, Peak continuous 100% utilization-95-
Link down-18-
Total Power Consumption for All PortsPS10Base-T, idle-89.4-mW
10Base-T, Peak continuous 100% utilization-301.6-
100Base-TX, idle-391.5-
100Base-TX, Peak continuous 100% utilization-393.5-
Link down-89.4-
+ +Note: All power supply currents are measured under the following conditions: +1. DVDDL=AVDDL=AVDDHPLL=1.0V; DVDDH=AVDDH=AVDDHPLL=3.3V. +2. Room temperature. +3. The EEE and Green features are disabled. +4. All LEDs are in low-active mode. +5. LDO power is not included. + +## 9.4. Thermal Characteristics + +## 9.4.1. Simulation Conditions + +Table 19. PCB Descriptions + +
PCBPCB Dimension (L x W)79.7 x 50.8mm
PCB Thickness1.6mm
PCB Top GND Plane Size75%
Number of Cu Layer-PCB1-Layer
+ +Table 20. Condition Descriptions + +
Input Power0.6 W
Test Board (PCB)1 Layer
Control ConditionAir Flow= 0, 1, 2, 3ms
+ +## 9.4.2. Thermal Characteristics Results + +Table 21. Thermal Characteristics Results + +
Air Flow (ms)0123
θJA (°C/W)51.645.643.441.7
ψJT (°C/W)0.8---
ψJB (°C/W)24.6---
Max. Junction Temperature125°C
+ +## 9.5. Digital Timing Characteristics + +## 9.5.1. LED Timing + +Table 22. LED Timing + +
ParameterSYMConditionMinTypicalMaxUnits
LED On TimetLEDonLED Blinking to Indicate Link Information32-128ms
LED Off TimetLEDoffLED Blinking to Indicate Link Information32-128ms
+ +## 9.5.2. Reception/Transmission Data Timing of SMI Interface + +![](images/7d971618b48b9647493fb7939595c2c8a2f31c4e06308131dc583addd2400177.jpg) + +
+text_image + +MDC +TIS +TIH +MDIO +
+ +Figure 19. Reception Data Timing of SMI Interface + +![](images/b95afb7d11a0eb43124d7c3287be746dd592e42aa3991a53342b1b722202b104.jpg) + +
+text_image + +MDC +Tcyc +MDIO +TD +
+ +Figure 20. Transmission Data Timing of SMI Interface + +Table 23. SMI Timing + +
ParameterSYMDescriptionI/OMinTypeMaxUnits
MDC $T_{cyc}$ MDC Clock CycleI400--ns
MDIO Input Setup Time $T_{IS}$ MDIO to MDC Rising Edge Setup TimeI50--ns
MDIO Input Hold Time $T_{IH}$ MDIO to MDC Rising Edge Hold TimeI10--ns
MDIO Output Delay Time $T_{D}$ MDIO to MDC Rising Edge Output DelayO2-10ns
+ +## 9.5.3. EEPROM Auto-Load Timing + +![](images/b813a873447159e8f9aacb5135706460e80e1c779e67ac3ea33c692d197c3df9.jpg) + +
+text_image + +SCK +t3 t4 +t7 +t1 t2 +t5 t6 +t8 +SDA +Data Output Data Output Data Input Data Input +
+ +Figure 21. EEPROM Auto-Load Timing + +Table 24. EEPROM Auto-Load Timing Characteristics + +
SymbolDescriptionMinTypicalMaxUnits
t1SCL High Time-2.52-μs
t2SCL Low Time-2.52-μs
t3START Condition Setup Time-2.52-μs
t4START Condition Hold Time-2.52-μs
t5Data In Hold Time0--ns
t6Data In Setup Time100--ns
t7Data Output Hold Time-1.28-μs
t8STOP Condition Setup Time-2.52-μs
+ +## 10. Mechanical Dimensions + +![](images/f292d0b643217da7989de2986c95f0561d2d48ed985fd11b0d171eac4d8d757a.jpg) + +10.1. Mechanical Dimensions Notes + +
SymbolDimension in mmDimension in inch
MinNomMaxMinNomMax
A0.750.851.000.0300.0340.039
A10.000.020.050.0000.0010.002
A30.20 REF0.008 REF
b0.150.200.250.0060.0080.010
D/E6.00BSC0.236BSC
D2/E24.154.44.650.1630.1730.183
e0.40BSC0.016BSC
L0.300.400.500.0120.0160.020
+ +Note 1: CONTROLLING DIMENSION: MILLIMETER (mm). +Note 2: REFERENCE DOCUMENT: JEDEC MO-220. + +## 11. Ordering Information + +Table 25. Ordering Information + +
Part NumberPackageStatus
RTL8305NBI-CG48-Pin QFN in ‘Green’ Package (RoHS Compliant)MP
+ +Note: See page 5 for package identification. + +Realtek Semiconductor Corp. + +Headquarters + +No. 2, Innovation Road II + +Hsinchu Science Park, Hsinchu 300, Taiwan + +Tel.: +886-3-578-0211. Fax: +886-3-577-6047 + +www.realtek.com \ No newline at end of file diff --git a/STM32F407-Demo.ioc b/STM32F407-Demo.ioc index 3fae45d..dff3b07 100644 --- a/STM32F407-Demo.ioc +++ b/STM32F407-Demo.ioc @@ -9,10 +9,11 @@ Mcu.CPN=STM32F407ZGT6 Mcu.Family=STM32F4 Mcu.IP0=NVIC Mcu.IP1=RCC -Mcu.IP2=SPI2 -Mcu.IP3=SYS -Mcu.IP4=USART1 -Mcu.IPNb=5 +Mcu.IP2=SPI1 +Mcu.IP3=SPI2 +Mcu.IP4=SYS +Mcu.IP5=USART1 +Mcu.IPNb=6 Mcu.Name=STM32F407Z(E-G)Tx Mcu.Package=LQFP144 Mcu.Pin0=PH0-OSC_IN @@ -23,8 +24,14 @@ Mcu.Pin12=PA9 Mcu.Pin13=PA10 Mcu.Pin14=PA13 Mcu.Pin15=PA14 -Mcu.Pin16=VP_SYS_VS_Systick +Mcu.Pin16=PB3 +Mcu.Pin17=PB4 +Mcu.Pin18=PB5 +Mcu.Pin19=PB8 Mcu.Pin2=PC4 +Mcu.Pin20=PE0 +Mcu.Pin21=PE1 +Mcu.Pin22=VP_SYS_VS_Systick Mcu.Pin3=PC5 Mcu.Pin4=PB1 Mcu.Pin5=PB2 @@ -32,7 +39,7 @@ Mcu.Pin6=PF11 Mcu.Pin7=PF12 Mcu.Pin8=PB12 Mcu.Pin9=PB13 -Mcu.PinsNb=17 +Mcu.PinsNb=23 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F407ZGTx @@ -99,6 +106,31 @@ PB2.GPIO_Speed=GPIO_SPEED_FREQ_HIGH PB2.Locked=true PB2.PinState=GPIO_PIN_SET PB2.Signal=GPIO_Output +PB3.GPIOParameters=GPIO_PuPd,GPIO_Label +PB3.GPIO_Label=GD_SCLK +PB3.GPIO_PuPd=GPIO_PULLUP +PB3.Locked=true +PB3.Mode=Full_Duplex_Master +PB3.Signal=SPI1_SCK +PB4.GPIOParameters=GPIO_PuPd,GPIO_Label +PB4.GPIO_Label=GD_SO +PB4.GPIO_PuPd=GPIO_PULLUP +PB4.Locked=true +PB4.Mode=Full_Duplex_Master +PB4.Signal=SPI1_MISO +PB5.GPIOParameters=GPIO_PuPd,GPIO_Label +PB5.GPIO_Label=GD_SI +PB5.GPIO_PuPd=GPIO_PULLUP +PB5.Locked=true +PB5.Mode=Full_Duplex_Master +PB5.Signal=SPI1_MOSI +PB8.GPIOParameters=GPIO_Speed,PinState,GPIO_PuPd,GPIO_Label +PB8.GPIO_Label=GD_WP +PB8.GPIO_PuPd=GPIO_PULLUP +PB8.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PB8.Locked=true +PB8.PinState=GPIO_PIN_SET +PB8.Signal=GPIO_Output PC4.GPIOParameters=GPIO_Speed,PinState,GPIO_PuPd,GPIO_Label PC4.GPIO_Label=LED1 PC4.GPIO_PuPd=GPIO_PULLUP @@ -121,6 +153,20 @@ PCC.PartNumber=STM32F407ZGTx PCC.Series=STM32F4 PCC.Temperature=25 PCC.Vdd=3.3 +PE0.GPIOParameters=GPIO_Speed,PinState,GPIO_PuPd,GPIO_Label +PE0.GPIO_Label=GD_CS +PE0.GPIO_PuPd=GPIO_PULLUP +PE0.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PE0.Locked=true +PE0.PinState=GPIO_PIN_SET +PE0.Signal=GPIO_Output +PE1.GPIOParameters=GPIO_Speed,PinState,GPIO_PuPd,GPIO_Label +PE1.GPIO_Label=GD_HOLD +PE1.GPIO_PuPd=GPIO_PULLUP +PE1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH +PE1.Locked=true +PE1.PinState=GPIO_PIN_SET +PE1.Signal=GPIO_Output PF11.GPIOParameters=GPIO_Speed,PinState,GPIO_PuPd,GPIO_Label PF11.GPIO_Label=LED5 PF11.GPIO_PuPd=GPIO_PULLUP @@ -172,7 +218,7 @@ ProjectManager.ToolChainLocation= ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI2_Init-SPI2-false-HAL-true +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI2_Init-SPI2-false-HAL-true,5-MX_SPI1_Init-SPI1-false-HAL-true RCC.48MHZClocksFreq_Value=84000000 RCC.AHBFreq_Value=168000000 RCC.APB1CLKDivider=RCC_HCLK_DIV4 @@ -206,6 +252,11 @@ RCC.VCOI2SOutputFreq_Value=384000000 RCC.VCOInputFreq_Value=2000000 RCC.VCOOutputFreq_Value=336000000 RCC.VcooutputI2S=192000000 +SPI1.CalculateBaudRate=42.0 MBits/s +SPI1.Direction=SPI_DIRECTION_2LINES +SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate +SPI1.Mode=SPI_MODE_MASTER +SPI1.VirtualType=VM_MASTER SPI2.CalculateBaudRate=21.0 MBits/s SPI2.Direction=SPI_DIRECTION_2LINES SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate diff --git a/Src/gpio.c b/Src/gpio.c index 4dd5233..d443ff3 100644 --- a/Src/gpio.c +++ b/Src/gpio.c @@ -50,16 +50,20 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOF_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOC, LED1_Pin|LED2_Pin, GPIO_PIN_SET); /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOB, LED3_Pin|LED4_Pin|CH395_SCS_Pin, GPIO_PIN_SET); + HAL_GPIO_WritePin(GPIOB, LED3_Pin|LED4_Pin|CH395_SCS_Pin|GD_WP_Pin, GPIO_PIN_SET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOF, LED5_Pin|LED6_Pin, GPIO_PIN_SET); + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOE, GD_CS_Pin|GD_HOLD_Pin, GPIO_PIN_SET); + /*Configure GPIO pins : LED1_Pin LED2_Pin */ GPIO_InitStruct.Pin = LED1_Pin|LED2_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; @@ -88,6 +92,20 @@ void MX_GPIO_Init(void) GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; HAL_GPIO_Init(CH395_SCS_GPIO_Port, &GPIO_InitStruct); + /*Configure GPIO pin : GD_WP_Pin */ + GPIO_InitStruct.Pin = GD_WP_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + HAL_GPIO_Init(GD_WP_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : GD_CS_Pin GD_HOLD_Pin */ + GPIO_InitStruct.Pin = GD_CS_Pin|GD_HOLD_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + } /* USER CODE BEGIN 2 */ diff --git a/Src/main.c b/Src/main.c index b78eb9e..7d36aea 100644 --- a/Src/main.c +++ b/Src/main.c @@ -27,6 +27,8 @@ #include #include #include "ch395f.h" +#include "gd5f2gq5ue.h" +#include "flashdb.h" /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ @@ -92,10 +94,93 @@ int main(void) MX_GPIO_Init(); MX_USART1_UART_Init(); MX_SPI2_Init(); + MX_SPI1_Init(); /* USER CODE BEGIN 2 */ - /* CH395F 初始化 */ - ch395f_reset(); - ch395f_init(); + char dbg[64]; + uint8_t mac[6]; + + ch395f_reset(); + + /* [1/5] SPI 通信检测 */ + sprintf(dbg, "[1/5] CH395F %s\r\n", + (ch395f_check_exist() == CH395F_STATUS_OK) ? "detected" : "ERROR: not detected"); + HAL_UART_Transmit(&huart1, (uint8_t*)dbg, strlen(dbg), 1000); + + /* [2/5] 芯片版本 */ + sprintf(dbg, "[2/5] CH395F version: 0x%02X\r\n", ch395f_get_version()); + HAL_UART_Transmit(&huart1, (uint8_t*)dbg, strlen(dbg), 1000); + + /* 配置 IP/网关/掩码 */ + { + uint8_t ip[4] = {192, 168, 1, 100}; + uint8_t gw[4] = {192, 168, 1, 1}; + uint8_t mask[4] = {255, 255, 255, 0}; + ch395f_set_ip_addr(ip); + ch395f_set_gwip_addr(gw); + ch395f_set_mask_addr(mask); + } + + /* [3/5] 协议栈初始化 */ + sprintf(dbg, "[3/5] Protocol stack init %s\r\n", + (ch395f_init() == CH395F_STATUS_OK) ? "OK" : "ERROR"); + HAL_UART_Transmit(&huart1, (uint8_t*)dbg, strlen(dbg), 1000); + + /* [4/5] MAC 地址 */ + ch395f_get_mac_addr(mac); + sprintf(dbg, "[4/5] MAC: %02X:%02X:%02X:%02X:%02X:%02X\r\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + HAL_UART_Transmit(&huart1, (uint8_t*)dbg, strlen(dbg), 1000); + + /* [5/5] 强制 100M 全双工后检测 PHY */ + ch395f_set_phy(CH395F_PHY_100M_FULL); + HAL_Delay(3000); + { + uint8_t s = ch395f_get_phy_status(); + const char *desc = (s == CH395F_PHY_DISCONN) ? "DISCONNECTED" : + (s == CH395F_PHY_100M_FULL) ? "100M FULL" : + (s == CH395F_PHY_100M_HALF) ? "100M HALF" : + (s == CH395F_PHY_10M_FULL) ? "10M FULL" : + (s == CH395F_PHY_10M_HALF) ? "10M HALF" : "RESERVED"; + sprintf(dbg, "[5/5] PHY: 0x%02X (%s)\r\n", s, desc); + HAL_UART_Transmit(&huart1, (uint8_t*)dbg, strlen(dbg), 1000); + } + + /* ===================== FlashDB KVDB 测试 ===================== */ + { + uint8_t gd_mid, gd_did; + int ret; + + /* 检测 GD5F2GQ5UE */ + ret = gd5f2gq5ue_read_id(&gd_mid, &gd_did); + sprintf(dbg, "[GD5F] ID: MID=0x%02X DID=0x%02X %s\r\n", + gd_mid, gd_did, + (ret == GD5F_OK && gd_mid == 0xC8 && gd_did == 0x52) ? "OK" : "FAIL"); + HAL_UART_Transmit(&huart1, (uint8_t*)dbg, strlen(dbg), 1000); + + /* 初始化 FlashDB KVDB */ + { + static struct fdb_kvdb kvdb; + ret = fdb_kvdb_init(&kvdb, "db", "fdb_kvdb1", NULL, NULL); + sprintf(dbg, "[FlashDB] KVDB init: %s\r\n", + (ret == FDB_NO_ERR) ? "OK" : "FAIL"); + HAL_UART_Transmit(&huart1, (uint8_t*)dbg, strlen(dbg), 1000); + + if (ret == FDB_NO_ERR) { + /* 写入测试 KV */ + fdb_kv_set(&kvdb, "test_key", "hello_flashdb"); + HAL_UART_Transmit(&huart1, (uint8_t*)"[FlashDB] KV set OK\r\n", 21, 1000); + + /* 读取测试 KV */ + char *val = fdb_kv_get(&kvdb, "test_key"); + if (val) { + sprintf(dbg, "[FlashDB] KV get: %s\r\n", val); + } else { + sprintf(dbg, "[FlashDB] KV get: NULL\r\n"); + } + HAL_UART_Transmit(&huart1, (uint8_t*)dbg, strlen(dbg), 1000); + } + } + } /* USER CODE END 2 */ /* Infinite loop */ @@ -111,7 +196,7 @@ int main(void) HAL_GPIO_TogglePin(LED4_GPIO_Port, LED4_Pin); HAL_GPIO_TogglePin(LED5_GPIO_Port, LED5_Pin); HAL_GPIO_TogglePin(LED6_GPIO_Port, LED6_Pin); - HAL_UART_Transmit(&huart1, str, strlen((char*)str), 1000); + //HAL_UART_Transmit(&huart1, str, strlen((char*)str), 1000); HAL_Delay(500); } /* USER CODE END 3 */ @@ -195,4 +280,4 @@ void assert_failed(uint8_t *file, uint32_t line) ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ /* USER CODE END 6 */ } -#endif /* USE_FULL_ASSERT */ \ No newline at end of file +#endif /* USE_FULL_ASSERT */ diff --git a/Src/spi.c b/Src/spi.c index 67090af..ded36d7 100644 --- a/Src/spi.c +++ b/Src/spi.c @@ -24,8 +24,41 @@ /* USER CODE END 0 */ +SPI_HandleTypeDef hspi1; SPI_HandleTypeDef hspi2; +/* SPI1 init function */ +void MX_SPI1_Init(void) +{ + + /* USER CODE BEGIN SPI1_Init 0 */ + + /* USER CODE END SPI1_Init 0 */ + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + hspi1.Instance = SPI1; + hspi1.Init.Mode = SPI_MODE_MASTER; + hspi1.Init.Direction = SPI_DIRECTION_2LINES; + hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi1.Init.NSS = SPI_NSS_SOFT; + hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi1.Init.CRCPolynomial = 10; + if (HAL_SPI_Init(&hspi1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} /* SPI2 init function */ void MX_SPI2_Init(void) { @@ -41,10 +74,10 @@ void MX_SPI2_Init(void) hspi2.Init.Mode = SPI_MODE_MASTER; hspi2.Init.Direction = SPI_DIRECTION_2LINES; hspi2.Init.DataSize = SPI_DATASIZE_8BIT; - hspi2.Init.CLKPolarity = SPI_POLARITY_HIGH; - hspi2.Init.CLKPhase = SPI_PHASE_2EDGE; + hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; hspi2.Init.NSS = SPI_NSS_SOFT; - hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256; + hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; hspi2.Init.TIMode = SPI_TIMODE_DISABLE; hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; @@ -63,7 +96,32 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle) { GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(spiHandle->Instance==SPI2) + if(spiHandle->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspInit 0 */ + + /* USER CODE END SPI1_MspInit 0 */ + /* SPI1 clock enable */ + __HAL_RCC_SPI1_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**SPI1 GPIO Configuration + PB3 ------> SPI1_SCK + PB4 ------> SPI1_MISO + PB5 ------> SPI1_MOSI + */ + GPIO_InitStruct.Pin = GD_SCLK_Pin|GD_SO_Pin|GD_SI_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI1_MspInit 1 */ + + /* USER CODE END SPI1_MspInit 1 */ + } + else if(spiHandle->Instance==SPI2) { /* USER CODE BEGIN SPI2_MspInit 0 */ @@ -100,7 +158,26 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle) void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle) { - if(spiHandle->Instance==SPI2) + if(spiHandle->Instance==SPI1) + { + /* USER CODE BEGIN SPI1_MspDeInit 0 */ + + /* USER CODE END SPI1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI1_CLK_DISABLE(); + + /**SPI1 GPIO Configuration + PB3 ------> SPI1_SCK + PB4 ------> SPI1_MISO + PB5 ------> SPI1_MOSI + */ + HAL_GPIO_DeInit(GPIOB, GD_SCLK_Pin|GD_SO_Pin|GD_SI_Pin); + + /* USER CODE BEGIN SPI1_MspDeInit 1 */ + + /* USER CODE END SPI1_MspDeInit 1 */ + } + else if(spiHandle->Instance==SPI2) { /* USER CODE BEGIN SPI2_MspDeInit 0 */