芯片手册图片补充

docs/UI 设计/菜单页面设计.md

@@ -890,7 +890,7 @@ bool ui_content_page_is_open(void);                /* 查询是否有内容页
 | 2026-09-04 | 修正 §四"进入/返回示例"：返回行节点顺序原与进入行相反（参数在左）致 `←` 被读成"前进"方向；改为与进入行**同序**（主界面 L0 在左…参数 L3 在右）+ `←`，并补"怎么读"注（`→`/`←` = 进/退动作方向；返回 = 从最右 参数(L3) 沿 `←` 一级级退回最左 主界面(L0)） |
 | 2026-09-04 | **子页面显示模型定稿（横向级联子框）**：§四 新增 ⑧"显示模型"——横向树，每级一框在上一级**右侧**、顶边对齐上级"选中行"行顶；水平**右锚定**(最深框钉右缘、父框超宽滚出左、行按屏上/外建毁)+ 框宽文字自适应 + **无动画**；垂直每框独立(顶边=上级选中行行顶、框高按内容、**仅底边>160 才上移**贴屏底、比整屏高则 `↑`/`↓` 滚)；焦点=最右框(`↑`/`↓` 移选/滚、`→`/`ENTER` 进、`←`/`ESC` 关最右框)。§七 同步：行对象按层 `s_row[d][i]` 仅屏上框建、去掉逐框页头(`s_header`/`s_back_btn`/`s_title`)、新增每框滚动 `s_scroll[]`(8 B)、"存 vs 算"增 滚动=存/位置=算、持久态 9→17 B、内存预算(静态 ~0.75→~1.3 KB、LVGL 池=屏上 2~3 框)、对照表更新 |
 | 2026-09-04 | **§四⑧ 按参考图 02~07 像素实测校准**（设备 px，误差 ≤3px）：层级树/命名/箭头/选中态全部与图一致 ✓；显示模型两处修正——水平由"右锚定(钉屏幕右缘)"改为"**子框左缘=父框右缘**(共享边框列、零间隙)+ 宽自适应"(实测各子框均贴父框右缘 x≈67/106，最深框止于 x≈113~127 而非屏右缘)；垂直溢出由"上移使底边贴屏底"改为"**上移使子框底边对齐父选中行行底**"(实测三遥 top=26/装置维护 top=54/通讯参数 top=82/记录查询 top=12 均吻合，且可叠到屏顶状态行区、顶部不钳制)。本菜单最深路径 ≈155<160 不会溢出；>160 行为与"根页框宽 99 vs 68"列为待确认。§7.2/§7.3/§7.4 "右锚定"表述同步 |
-| 2026-09-04 | **实现落地，本文档与代码同步**：三层拆分实现（`ui_menu_tab` 生成物 + 新增 `ui_menu_view` 显示层、`ui_menu` 瘦身为纯状态机，§8.1）；§四⑦/§6.4/§6.5/§6.6/§6.7 函数与 API 名同步为实际 `ui_menu_tab_*`/`ui_menu_view_*`/`menu_open|menu_back|menu_key_handle`；§五"待实现"→"已实现"；§七 修正为实际字段（容器从不切 HIDDEN、`s_style_frame`、新增框几何缓存 `s_frame[]`，§7.2 G）；§四⑧ 实测值区分"参考图/实现"两套（实现：根框 66、子框 42/46/54/6，顶 28/58/88/13，偏差入 §8.8 注 5），>160 溢出"待确认"落定为实现行为"屏缘裁切"；新增 **§八 实现架构与关键实施细节**（布局常量/几何公式/对象模型/键路径/初始化时序/分级验证/6 条陷阱与保真度说明）；验证：模拟器 7 状态对照参考图 01~07 + `@build` 0 错 0 警 |
+| 2026-09-04 | **实现落地，本文档与代码同步**：三层拆分实现（`ui_menu_tab` 生成物 + 新增 `ui_menu_view` 显示层、`ui_menu` 瘦身为纯状态机，§8.1）；§四⑦/§6.4/§6.5/§6.6/§6.7 函数与 API 名同步为实际 `ui_menu_tab_*`/`ui_menu_view_*`/`menu_open\|menu_back\|menu_key_handle`；§五"待实现"→"已实现"；§七 修正为实际字段（容器从不切 HIDDEN、`s_style_frame`、新增框几何缓存 `s_frame[]`，§7.2 G）；§四⑧ 实测值区分"参考图/实现"两套（实现：根框 66、子框 42/46/54/6，顶 28/58/88/13，偏差入 §8.8 注 5），>160 溢出"待确认"落定为实现行为"屏缘裁切"；新增 **§八 实现架构与关键实施细节**（布局常量/几何公式/对象模型/键路径/初始化时序/分级验证/6 条陷阱与保真度说明）；验证：模拟器 7 状态对照参考图 01~07 + `@build` 0 错 0 警 |
 | 2026-09-07 | **全文结构重排（理清三层架构与协作）**：旧版三层描述分散在 §六(数据结构)/§七(运行时数据)/§八(实现架构) 三处、§四 又混装导航逻辑与显示模型，读者难以看清各层职责与层间配合；重排为十章——**一 架构总览**（1.1 为什么拆三层 / 1.2 职责速览+依赖图 / 1.3 调用矩阵 / 1.4 一次按键的旅程 / 1.5 初始化时序 / 1.6 层间不变量）→ **二 菜单内容** → **三 数据层**（含 3.7 改菜单流程）→ **四 显示规范**（自 §四⑧ 抽出，含 4.5 参考图偏差）→ **五 显示层**（5.1 职责边界 / 5.5 公开 API 8 接口表）→ **六 逻辑层**（6.2 17 B 状态 / 6.3 导航规则含完整走查 / 6.4 键语义与分发）→ **七 层间配合细节**（7.1 逐键分层动作 / 7.2 框生命周期 / 7.3 存vs算 / 7.4 读写矩阵 / 7.5 内存预算带层归属）→ **八 验证与陷阱** → **九 迁移历史**（结构/运行时/内容三表收拢）→ **十 变更记录**；**修正归属错误**：`s_scroll[]` 实为**逻辑层** `ui_menu.c` 字段（17 B 导航状态之一，见 ui_menu.c），旧 §7.2 误划给显示层，新文 §6.2/§7.5 已归正；全部交叉引用同步到新章号；技术内容零删减 |
 | 2026-09-07 | §1.2/§1.4/§1.5 三幅架构图由 ASCII 转 Mermaid（1 张 flowchart + 2 张 sequenceDiagram，初始化时序含表自检 alt/else 分支）；键源措辞统一为“远端键”（与 `UI_设计架构.md`“远端客户端”一致：MCU 端按键经 TCP 7003 远端客户端 → ui_net_sink → keypad）；职责表/调用矩阵/“两个要点”文字保留 |
 | 2026-09-07 | 正文现状化：删除正文过渡性历史叙述（“设计阶段拟名…/实现采用…/见变更记录”等，旧文见 git 历史），各节改写为现状描述；移除 §九“迁移历史”整章（旧→新对照保留于本变更记录），变更记录重编号为 §九；§8 去日期注记，陷阱 3/4 改写为现状约束 |

docs/代码规范/cppcheck使用说明.md

@@ -83,7 +83,7 @@ cppcheck 是开源 C/C++ 静态分析工具，**不运行代码**，通过语法
 
 | 规则 | 检查什么 |
 |---|---|
-| `clarifyCalculation` | 位运算与逻辑运算易混（`|` vs `\|\|`、`&` vs `&&`）|
+| `clarifyCalculation` | 位运算与逻辑运算易混（`\|` vs `\|\|`、`&` vs `&&`）|
 | `clarifyCondition` / `assignmentInCondition` | 条件里出现赋值（疑似 `=` 误写 `==`）、链式比较 |
 | `bitwiseOnBoolean` | 对布尔量做位运算 |
 | `selfAssignment` | 自赋值 `x = x` |

docs/测试说明/链路延迟测试说明.md

@@ -544,25 +544,6 @@ peer 侧 = `m3_data/m3_dev_*_r200.json`。旧 run15 摘录（`m2_serial_excerpt_
 
 ## 8. 缺陷与修复状态
 
-### 8.1 缺陷总表（编号 = 台架发现顺序；D10~D20/E-02 为测试发现，与 §10.1 的静态分析编号 D1~D10 不同体系）
-
-| 编号 | 缺陷 | 状态 | 机理 | 修复 | 实测证据（前 → 后） |
-|---|---|---|---|---|---|
-| **D10** | 断线重监听 `osDelay(500)` 忙等冻结 netTask | **已修复** | Trap 09 沉降窗口内 `open` 必失败 → 旧代码在 netTask 里 `osDelay(500)` 阻塞重试，期间全网冻结 | 单次尝试 + netTask 每轮延迟重试（`net_relisten_try`/`net_relisten_retry_tick`，间隔 30ms、上限 2s，防饥饿 + 防 fd 残留） | relisten **588ms → 89ms** 且不阻塞；`[LAT]` FAIL → OK |
-| **D11** | 芯片 TCP RX 饱和下重复投递（+138%）并过度 ACK → 对端 RST | **芯片行为，应用侧规避** | RX 缓冲打满（窗口=0）后芯片把已收数据整段重投（发 5000B 实收 11884B） | 灌入限速 20×100B@50ms（1KB/s）+ MCU 冗余字节守卫（超阈值即 abort）+ L10 后 DONTWAIT 抽干 | L3 flood 7.5~8.7ms/chunk 全 OK |
-| **D12** | net 层 `xTaskNotifyWait` 清除掩码 0 = 不清值 → 陈旧结果被重读 | **已修复** | `xTaskNotifyWait(0,0,...)` 掩码 0 根本不清值 → 上次结果残留，零等待重读成"本次结果" → 结果错位/永久等待 | `net_wait_result()` 两段式 + **清除掩码全 1（读取即消费）** + **以返回值 `pdTRUE/pdFALSE` 判定落地** | 三次独立 PASS（run12/13/15） |
-| **D12-a** | 位域切分与 `v!=0` 判定两个同类陷阱（设计约束） | **已避开** | ① 序列号压通知值高 16 位 → 单次结果上限 32767（`TEST_BUF_SIZE=32768` 溢出成负）；② `v!=0` 判落地 → 合法 0 结果（recv=对端关闭）误判 → 永久挂死 | 不切位域（32 位整体仍是结果）；只用返回值判定。**改这条路径前必须复核** | code review |
-| **D12-b** | net 热路径逐调用日志 → 观测改变被测对象 | **已修复**（规则：热路径禁止日志） | 探针两行日志把串口流量抬 26×（40KB→1.04MB）→ 冲掉 `[LAT]` 证据行、`queue_rt_send` 抬高 7.8× | 删除热路径日志，诊断改在 `[LAT]` 段报告侧聚合 | run14 对照（不作基线） |
-| **D13** | 芯片空闲超时 RST（MCU 未就绪时握手已在芯片侧完成） | **芯片行为，客户端容忍** | 连接后 15~30s 无流量 → 芯片 RST（WinError 10054） | peer 3 次重试包装（`--wait` 重试是正常路径）；生产端 E-02 修复消除了"冻结→RST→重连风暴"链条 | 每轮首连失败、+2s 重连成功 |
-| **D14** | 芯片静默回收 Socket（无 DISCONNECT 中断）→ MCU 状态滞留 | **已修复** | 芯片在 peer FIN 后静默回收回监听但不通知 MCU → `state` 滞留 ESTABLISHED，新连接字节被吞 | `net_sock_state()`（只读）+ `net_resync_listen()`（仅修 MCU 态，不发芯片命令）+ `net_relisten()`（芯片侧重监听，含 Trap 09 重试）；abort 后按状态分派 + 10s 周期自愈（干净完成后停止） | run8/9 实证 + 三次 PASS |
-| **D15** | 测试 L7 帧与生产 RemoDispBus 格式不一致 + peer 超读 | **已修复** | 响应 LEN 应为 3204（非 3200）、缺 4B 偏移字段、CRC 只覆盖数据段；peer `recv(4096)` 超读吃掉下一操作字节 | MCU 建帧/校验与 peer 请求/校验全部对齐生产语义（`remo_send`/`remo_handle`）；peer 改 `recv(min(4096, 剩余))` 有界读 | L7 10/0 CRC fail |
-| **D16** | Phase 13 状态机 L7 → 回跳 L3 无限循环 | **已修复** | 重排会话顺序前的旧迁移目标遗留 → 永不下发 `0xFF`，peer 空等 300s | L7 → `P13_ST_DONE`；该处加注释锁定顺序 L5→L3→L10→L6→L7→DONE | run11 → 三次 PASS |
-| **D17** | INIT 应答把 `帧字节数u32` 截成 6B → 字段恒 0 | **已修复** | `remo_send_init` 只发 8B 数据段的前 6B（u32 截半），客户端读到的帧字节数恒 0 | `len=6` 改 `len=8`（字段定义本就是 `[W u16][H u16][FB u32]`）；协议文档同步勘误 | `framebytes` 0 → **3200** |
-| **D18** | 多打点站点共用全局探针窗口 → 跨段污染（测试工装） | **已修复** | 探针窗口串行全局，prod/relisten 段读出 ui_loop 的 ~11ms 值 | `lat_probe_add_seg()` 按段名过滤 | run17 对照 |
-| **D19** | Phase 14 漏调 `lat_time_init()` → DWT 恒 0 假绿（测试工装） | **已修复** | 时基未使能 → 三段全 0 却 `verdict=OK` | 补初始化 + `med==0` 判无效 | run16 对照 |
-| **D20** | FTP 开机首个会话的第 2 个数据连接失败（425） | **已定位未修**（暂缓） | 延迟 DISCONNECT 事件与首次 `net_accept` 的先后竞态（详见 §8.2） | 未实施；保留安全硬化（陈旧 DISCONNECT 甄别 + 2 字节状态缓冲越界修复）；两次不稳定修法已回退 | 复现脚本 `test/ftp_regression.py` |
-| **E-02** | 空闲 FTP 控制连接头阻塞冻结 netTask（= §10.1 的 D3） | **已修复** | `lftpd` 控制行 `read_line` 走阻塞 `net_recv(0)`，netTask 是全部 socket 操作的唯一执行者 → 单会话可冻结全网最长 30s+ | 控制行/数据读改**分片有界读**（`net_recv_to` 5ms 片 + 每片 `vTaskDelay(1)` 让出，总预算仍 30s） | 受压帧 **17.7s → med 65.0ms / max 133.5ms，零尖峰**（2026-09-22 P0-a/P0-b 代码下复验） |
-
 ### 8.2 D20 详情（已定位，未修复）
 
 **复现条件（精确）**：**每次开机后的第一个 FTP 会话**在其第 2 个数据连接失败

docs/芯片手册/RTL8305NBI-CG.md

@@ -37,6 +37,7 @@ Though every effort has been made to ensure that this document is current and ac
 ## REVISION HISTORY
 
 | **Revision** | **Release Date** | **Summary** |
+| --- | --- | --- |
 | 1.0 | 2015/05/30 | First release. |
 
 ## Table of Contents
@@ -448,6 +449,7 @@ Green package is indicated by the ‘G’ in GXXXX in Figure 2.
 **Table 1. Pin Assignments Table**
 
 | **Name** | **Pin No.** | **Type** |
+| --- | --- | --- |
 | AVDDL | 1 | AP |
 | RXIP1 | 2 | AI/O |
 | RXIN1 | 3 | AI/O |
@@ -475,6 +477,7 @@ Green package is indicated by the ‘G’ in GXXXX in Figure 2.
 | SCL/MDC | 25 | I/ $O_{PU}$ |
 
 | **Name** | **Pin No.** | **Type** |
+| --- | --- | --- |
 | SDA/MDIO | 26 | $I/O_{PU}$ |
 | RESETB | 27 | $I_{PU}$ |
 | LDIND/DIS_LD | 28 | $I/O_{PU}$ |
@@ -541,6 +544,7 @@ $I/O_{PD}: I_{PD}$ and $O_{PD}$
 **Table 2. Media Connection Pins**
 
 | **Pin Name** | **Pin No.** | **Type** | **Drive (mA)** | **Description** |
+| --- | --- | --- | --- | --- |
 | RXIP4/RXIN4 | 22, 21 | AI/O | - | Differential Receive Data Input. |
 | RXIP3/RXIN3 | 14, 15 |  |  | Port0~4 support 10Base-T, 100Base-TX. |
 | RXIP2/RXIN2 | 12, 11 |  |  |  |
@@ -559,6 +563,7 @@ As the output of the RTL8305NBI is 3.3V, the serial EEPROM and external device m
 **Table 3. Miscellaneous Pins**
 
 | **Pin Name** | **Pin No.** | **Type** | **Drive (mA)** | **Description** |
+| --- | --- | --- | --- | --- |
 | LDIND/DIS_LD | 28 | I/ $O_{PU}$ | 10 | Loop Indication Used by LED and Buzzer. |
 | SCL/MDC | 25 | I/ $O_{PU}$ | 4 | I2C Interface Clock for EEPROM Auto Load when Power On.After power on, this pin is MDC/MDIO Interface Clock for access registers. |
 | SDA/MDIO | 26 | I/ $O_{PU}$ | 4 | I2C Interface Data Input/Output for EEPROM Auto Load when Power On.After power on, this pin is MDC/MDIO Interface Data Input/Output for access registers. |
@@ -576,6 +581,7 @@ Those pins that are dual-function pins are output for LED, or input for strappin
 **Table 4. Port LED Pins**
 
 | **Pin Name** | **Pin No.** | **Type** | **Drive (mA)** | **Description** |
+| --- | --- | --- | --- | --- |
 | P0LED/DIS_EEE | 29 | I/ $O_{PD}$ | 10 | LED for Port0 Status Indication. |
 | P1LED | 30 | I/ $O_{PD}$ | 10 | LED for Port1 Status Indication. |
 | P2LED/DIS_RST_BLNK | 32 | I/ $O_{PD}$ | 10 | LED for Port2 Status Indication. |
@@ -589,6 +595,7 @@ Pins that are dual function pins are outputs for LED or inputs for strapping. Be
 **Table 5. Strapping Pins**
 
 | **Pin Name** | **Pin No.** | **Type** | **Default** | **Description** |
+| --- | --- | --- | --- | --- |
 | DIS_LD/LDIND | 28 | I/ $O_{PU}$ | - | Disable Loop Detection Function.0: Enable1: Disable (default) |
 | DIS_EEE/P0LED | 29 | I/ $O_{PD}$ | - | Disable EEE Function.0: Enable EEE function (default)1: Disable EEE function |
 | DIS_RST_BLNK/P2LED | 32 | I/ $O_{PD}$ | - | Disable LED Power on Blinking.0: Enable (default)1: Disable |
@@ -598,6 +605,7 @@ Pins that are dual function pins are outputs for LED or inputs for strapping. Be
 **Table 6. Regulator Pins**
 
 | **Pin Name** | **Pin No.** | **Type** | **Drive (mA)** | **Description** |
+| --- | --- | --- | --- | --- |
 | V10OUT | 36 | AO | - | Switch Regulator 1.0V Output. |
 | V33IN | 37 | AP | - | Switch Regulator 3.3V Input. |
 
@@ -606,6 +614,7 @@ Pins that are dual function pins are outputs for LED or inputs for strapping. Be
 **Table 7. Power and GND Pins**
 
 | **Pin Name** | **Pin No.** | **Type** | **Description** |
+| --- | --- | --- | --- |
 | AVDDH | 6, 8, 18, 48 | AP | Analog Power 3.3V. |
 | AVDDL | 1, 13, 23, 43 | AP | Analog Power 1.0V. |
 | AVDDHPLL | 38 | AP | Power 3.3V for PLL. |
@@ -946,6 +955,7 @@ The SMI (Serial Management Interface) is also known as the MII Management Interf
 **Table 8. Basic SMI Read/Write Cycles**
 
 |  | **Preamble (32 bits)** | **Start (2 bits)** | **OP Code (2 bits)** | **PHYAD (5 bits)** | **REGAD (5 bits)** | **Turn Around (2 bits)** | **Data (16 bits)** | **Idle** |
+| --- | --- | --- | --- | --- | --- | --- | --- | --- |
 | Read | 1......1 | 01 | 10 | $A_4A_3A_2A_1A_0$ | $R_4R_3R_2R_1R_0$ | Z0 | $D_{15}......D_0$ | Z* |
 | Write | 1......1 | 01 | 01 | $A_4A_3A_2A_1A_0$ | $R_4R_3R_2R_1R_0$ | 10 | $D_{15}......D_0$ | Z* |
 
@@ -956,6 +966,7 @@ For MDIO Manageable Device (MMD) access, the RTL8305NBI supports the extended SM
 **Table 9. Extended SMI Management Frame Format**
 
 | **Frame** | **PRE** | **ST** | **OP** | **PHYAD** | **DEVAD** | **TA** | **DATA** | **IDLE** |
+| --- | --- | --- | --- | --- | --- | --- | --- | --- |
 | Address | 1...1 | 00 | 00 | AAAAA | EEEE | 10 | AAAAAAAAAAAAAAAAAA | Z |
 | Write | 1...1 | 00 | 01 | AAAAA | EEEE | 10 | DDDDDDDDDDDDDDD | Z |
 | Read | 1...1 | 00 | 11 | AAAAA | EEEE | Z0 | DDDDDDDDDDDDDDD | Z |
@@ -975,6 +986,7 @@ The RTL8305NBI supports the ability to forward or drop the frames of the IEEE 80
 B: Broadcast (Search the Look-Up Table) D: Drop
 
 | **Assignment** | **Value** | **Available Action** |
+| --- | --- | --- |
 | Bridge Group Address | 01-80-C2-00-00-00 | D, B (Default) |
 | IEEE Std 802.3, 1988 Edition, Full Duplex PAUSE Operation | 01-80-C2-00-00-01 | D (Default), B |
 | IEEE 802.3ad Slow_Protocols-Multicast Address | 01-80-C2-00-00-02 | D (Default), B |
@@ -1028,6 +1040,7 @@ The Loop frame length is 64 bytes. Its format is shown below.
 **Table 11. Loop Frame Format**
 
 | **48-bit** | **48-bit** | **16-bit** | **16-bit** | **12-bit** | **4-bit** | **352-bit** | **16-bit** |
+| --- | --- | --- | --- | --- | --- | --- | --- |
 | FFFF FFFF FFFF | SID | 8899 | 2300 | 000 | TTL | 0000 | CRC |
 
 In order to achieve loop detection, each switch device needs a unique SID (the source MAC address). If an EEPROM is not used, a unique SID should be assigned via SMI after reset. The TTL (Time-To-Live) field is used to avoid a storm triggered by the loop frame. The TTL field in the loop frame will decrease by 1 when it passes through an RTL8305NBI whose MAC address is not equal to the SID of the loop frame. The RTL8305NBI will drop a loop frame in which the TTL is the minimum value (0001 is the minimum value. 0000, meaning 16, is the maximum value). The initial value of the TTL field can be configured via SMI or EEPROM.
@@ -1086,6 +1099,7 @@ When using a crystal, the RTL8305NBI should connect a loading capacitor from eac
 **Table 12. Crystal and Oscillator Requirements**
 
 | **Nominal Frequency** | **25.000 MHz** |
+| --- | --- |
 | Frequency Tolerance | ±50ppm Max. |
 | Temperature Characteristics | ±50ppm in Operating Temperature Range |
 | Equivalent Series Resistance of Crystal | 50 Ohm Max. |
@@ -1103,6 +1117,7 @@ The RTL8305NBI supports 16 VLAN groups via the 16-entry VLAN table (see Table 13
 **Table 13. VLAN Table**
 
 | **Entry Index** | **VLAN ID** | **Membership** | **UNTAG_MSK** | **FID** |
+| --- | --- | --- | --- | --- |
 | VLAN Entry 0 | VLAN ID A[11:0] | VLAN ID A membership [4:0] | VLAN ID A UNTAG_MSK [4:0] | FID[1:0] |
 | VLAN Entry 1 | VLAN ID B [11:0] | VLAN ID B membership [4:0] | VLAN ID B UNTAG_MSK [4:0] | FID[1:0] |
 | ...... | ...... | ...... | ...... | ...... |
@@ -1111,6 +1126,7 @@ The RTL8305NBI supports 16 VLAN groups via the 16-entry VLAN table (see Table 13
 **Table 14. VLAN Entry**
 
 | **Field** | **Description** | **Bits** |
+| --- | --- | --- |
 | VID | The VLAN ID for Search. The VID of the ingress packet will be compared with this field. | 12 |
 | MBR | VLAN Member Port Set. If the bit in this field is ‘1’, the corresponding port is a member port of the VLAN specified by the VID field. | 6 |
 | UNTAG SET | VLAN Untag Set. If the bit in this field is ‘1’, egress packets from the corresponding port will be VLAN-untagged. | 6 |
@@ -1365,6 +1381,7 @@ The hashed index key is used to locate a matching LUT entry. There are 4 entries
 **Table 15. L2 Table 4-Way Hash Index Method**
 
 | **Index** | **Entry 0** | **Entry 1** | **Entry 2** | **Entry 3** |
+| --- | --- | --- | --- | --- |
 | 0x00 | MAC Addr 0 | MAC Addr 1 | MAC Addr 2 | MAC Addr 3 |
 | 0x01 | MAC Addr 4 | MAC Addr 5 | MAC Addr 6 | MAC Addr 7 |
 | 0x02 | MAC Addr 8 | MAC Addr 9 | MAC Addr 10 | MAC Addr 11 |
@@ -1527,6 +1544,7 @@ WARNING: Maximum ratings are limits beyond which permanent damage may be caused
 **Table 16. Electrical Characteristics/Maximum Ratings**
 
 | **Parameter** | **Min** | **Max** | **Units** |
+| --- | --- | --- | --- |
 | DVDDH, AVDDH, AVDDHPLL Supply Referenced to GND | GND-0.3 | +3.63 | V |
 | DVDDL, AVDDL, AVDDLPLL Supply Referenced to GND | GND-0.3 | +1.10 | V |
 
@@ -1535,6 +1553,7 @@ WARNING: Maximum ratings are limits beyond which permanent damage may be caused
 **Table 17. Operating Range**
 
 | **Parameter** | **Min** | **Max** | **Units** |
+| --- | --- | --- | --- |
 | Storage Temperature | -55 | +150 | °C |
 | Ambient Operating Temperature (Ta) | -40 | +85 | °C |
 | 3.3V Vcc Supply Voltage Range (DVDDH, AVDDH, AVDDHPLL) | 3.13 | 3.47 | V |
@@ -1545,6 +1564,7 @@ WARNING: Maximum ratings are limits beyond which permanent damage may be caused
 **Table 18. DC Characteristics**
 
 | **Parameter** | **SYM** | **Condition** | **Min** | **Typical** | **Max** | **Units** |
+| --- | --- | --- | --- | --- | --- | --- |
 | TTL Input High Voltage | $V_{ih}$ | - | 2.0 | - | - | V |
 | TTL Input Low Voltage | $V_{il}$ | - | - | - | 0.8 | V |
 | TTL Input Current | $I_{in}$ | - | -10 | - | 10 | μA |
@@ -1582,6 +1602,7 @@ Note: All power supply currents are measured under the following conditions:
 **Table 19. PCB Descriptions**
 
 | **PCB** | **PCB Dimension (L x W)** | **79.7 x 50.8mm** |
+| --- | --- | --- |
 |  | PCB Thickness | 1.6mm |
 |  | PCB Top GND Plane Size | 75% |
 |  | Number of Cu Layer-PCB | 1-Layer |
@@ -1589,6 +1610,7 @@ Note: All power supply currents are measured under the following conditions:
 **Table 20. Condition Descriptions**
 
 | **Input Power** | **0.6 W** |
+| --- | --- |
 | Test Board (PCB) | 1 Layer |
 | Control Condition | Air Flow= 0, 1, 2, 3ms |
 
@@ -1597,6 +1619,7 @@ Note: All power supply currents are measured under the following conditions:
 **Table 21. Thermal Characteristics Results**
 
 | **Air Flow (ms)** | **0** | **1** | **2** | **3** |
+| --- | --- | --- | --- | --- |
 | θJA (°C/W) | 51.6 | 45.6 | 43.4 | 41.7 |
 | ψJT (°C/W) | 0.8 | - | - | - |
 | ψJB (°C/W) | 24.6 | - | - | - |
@@ -1609,6 +1632,7 @@ Note: All power supply currents are measured under the following conditions:
 **Table 22. LED Timing**
 
 | **Parameter** | **SYM** | **Condition** | **Min** | **Typical** | **Max** | **Units** |
+| --- | --- | --- | --- | --- | --- | --- |
 | LED On Time | tLEDon | LED Blinking to Indicate Link Information | 32 | - | 128 | ms |
 | LED Off Time | tLEDoff | LED Blinking to Indicate Link Information | 32 | - | 128 | ms |
 
@@ -1643,6 +1667,7 @@ TD
 **Table 23. SMI Timing**
 
 | **Parameter** | **SYM** | **Description** | **I/O** | **Min** | **Type** | **Max** | **Units** |
+| --- | --- | --- | --- | --- | --- | --- | --- |
 | MDC | $T_{cyc}$ | MDC Clock Cycle | I | 400 | - | - | ns |
 | MDIO Input Setup Time | $T_{IS}$ | MDIO to MDC Rising Edge Setup Time | I | 50 | - | - | ns |
 | MDIO Input Hold Time | $T_{IH}$ | MDIO to MDC Rising Edge Hold Time | I | 10 | - | - | ns |
@@ -1670,6 +1695,7 @@ Data Output Data Output Data Input Data Input
 **Table 24. EEPROM Auto-Load Timing Characteristics**
 
 | **Symbol** | **Description** | **Min** | **Typical** | **Max** | **Units** |
+| --- | --- | --- | --- | --- | --- |
 | t1 | SCL High Time | - | 2.52 | - | μs |
 | t2 | SCL Low Time | - | 2.52 | - | μs |
 | t3 | START Condition Setup Time | - | 2.52 | - | μs |
@@ -1686,6 +1712,7 @@ Data Output Data Output Data Input Data Input
 ### 10.1. Mechanical Dimensions Notes
 
 | **Symbol** | **Dimension in mm** |  |  | **Dimension in inch** |  |  |
+| --- | --- | --- | --- | --- | --- | --- |
 |  | Min | Nom | Max | Min | Nom | Max |
 | A | 0.75 | 0.85 | 1.00 | 0.030 | 0.034 | 0.039 |
 | A1 | 0.00 | 0.02 | 0.05 | 0.000 | 0.001 | 0.002 |
@@ -1704,6 +1731,7 @@ Note 2: REFERENCE DOCUMENT: JEDEC MO-220.
 **Table 25. Ordering Information**
 
 | **Part Number** | **Package** | **Status** |
+| --- | --- | --- |
 | RTL8305NBI-CG | 48-Pin QFN in ‘Green’ Package (RoHS Compliant) | MP |
 
 Note: See page 5 for package identification.