diff --git a/.gitignore b/.gitignore index 716da59a..64445203 100644 --- a/.gitignore +++ b/.gitignore @@ -81,4 +81,4 @@ simulator/SDL2/ # Binary / large files *.bin -*.pyc \ No newline at end of file +*.pyc diff --git a/.mxproject b/.mxproject index 305a7d0b..20e7f986 100644 --- a/.mxproject +++ b/.mxproject @@ -11,4 +11,3 @@ HeaderPath=..\Inc HeaderFiles=gpio.h;FreeRTOSConfig.h;dma.h;i2c.h;spi.h;usart.h;stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h; SourcePath=..\Src SourceFiles=gpio.c;freertos.c;dma.c;i2c.c;spi.c;usart.c;stm32f4xx_it.c;stm32f4xx_hal_msp.c;stm32f4xx_hal_timebase_tim.c;main.c; - diff --git a/App/task/net_task.c b/App/task/net_task.c index 79452011..aa39ba4f 100644 --- a/App/task/net_task.c +++ b/App/task/net_task.c @@ -113,7 +113,7 @@ void net_task_func(void const *arg) osDelay(1000); } } - + /* 广播"网络就绪"，唤醒等待它的 ftpTask / start_test_task / timeSyncTask 等 */ if (sys_evtHandle != NULL) { osEventFlagsSet(sys_evtHandle, SYS_EVT_NET_READY); diff --git a/Drivers/BSP/GD5F2GQ5UE/gd5f2gq5ue.c b/Drivers/BSP/GD5F2GQ5UE/gd5f2gq5ue.c index 13c68aa5..6d0f8617 100644 --- a/Drivers/BSP/GD5F2GQ5UE/gd5f2gq5ue.c +++ b/Drivers/BSP/GD5F2GQ5UE/gd5f2gq5ue.c @@ -959,4 +959,3 @@ int32_t gd5f_bbt_wipe_pool(void) { int32_t gd5f_bbt_reload(void) { return gd5f_bbt_load(); } - diff --git a/Drivers/BSP/NET/net_socket.c b/Drivers/BSP/NET/net_socket.c index c88994c2..d8cd1192 100644 --- a/Drivers/BSP/NET/net_socket.c +++ b/Drivers/BSP/NET/net_socket.c @@ -1058,7 +1058,7 @@ static int net_close_locked(net_sock_t *p_sock) { /* 排空上一条连接残留的 DISCONNECT 中断（单连接模式仅有 Socket 0， * 复用同一 Socket 时，旧连接的 DISCONNECT 在 FIN/ACK 完成后才上报， * 若不清除会被下一连接误判为"刚建立就断开"）。等待芯片回到 CLOSED - * 并清掉 Socket/全局中断状态，避免事件串扰。 + * 并清掉 Socket/全局中断状态，避免事件串扰。 */ do { uint8_t st = 0; diff --git a/Drivers/BSP/SD2506/sd2506.c b/Drivers/BSP/SD2506/sd2506.c index e86eace8..32a734cc 100644 --- a/Drivers/BSP/SD2506/sd2506.c +++ b/Drivers/BSP/SD2506/sd2506.c @@ -494,4 +494,3 @@ int sd2506_read_ctr1(uint8_t *p_val) { return sd2506_read_reg(SD2506_REG_CTR1, p_val); } - diff --git a/Drivers/BSP/UI/ui_font_cn_12.c b/Drivers/BSP/UI/ui_font_cn_12.c index 4cf3d6ae..99f0f290 100644 --- a/Drivers/BSP/UI/ui_font_cn_12.c +++ b/Drivers/BSP/UI/ui_font_cn_12.c @@ -987,4 +987,3 @@ lv_font_t ui_font_cn_12 = { #endif /*#if UI_FONT_CN_12*/ - diff --git a/Drivers/BSP/dbg_cfg.h b/Drivers/BSP/dbg_cfg.h index eb76e648..f3ea1c6f 100644 --- a/Drivers/BSP/dbg_cfg.h +++ b/Drivers/BSP/dbg_cfg.h @@ -25,7 +25,7 @@ extern "C" { /* * 总开关：取消注释启用所有调试输出 */ -#define DBG_ENABLE +#define DBG_ENABLE /* * 调试级别开关：取消注释额外输出 DBG_DEBUG 级别 diff --git a/Drivers/CMSIS/Device/ST/STM32F4xx/LICENSE.txt b/Drivers/CMSIS/Device/ST/STM32F4xx/LICENSE.txt index 872e82b4..93f94ed6 100644 --- a/Drivers/CMSIS/Device/ST/STM32F4xx/LICENSE.txt +++ b/Drivers/CMSIS/Device/ST/STM32F4xx/LICENSE.txt @@ -1,6 +1,6 @@ This software component is provided to you as part of a software package and applicable license terms are in the Package_license file. If you received this software component outside of a package or without applicable license terms, -the terms of the Apache-2.0 license shall apply. +the terms of the Apache-2.0 license shall apply. You may obtain a copy of the Apache-2.0 at: https://opensource.org/licenses/Apache-2.0 diff --git a/Drivers/CMSIS/Include/cmsis_compiler.h b/Drivers/CMSIS/Include/cmsis_compiler.h index adbf296f..ff806745 100644 --- a/Drivers/CMSIS/Include/cmsis_compiler.h +++ b/Drivers/CMSIS/Include/cmsis_compiler.h @@ -280,4 +280,3 @@ #endif /* __CMSIS_COMPILER_H */ - diff --git a/Drivers/CMSIS/Include/core_armv8mbl.h b/Drivers/CMSIS/Include/core_armv8mbl.h index 932d3d18..e9c9b5bf 100644 --- a/Drivers/CMSIS/Include/core_armv8mbl.h +++ b/Drivers/CMSIS/Include/core_armv8mbl.h @@ -2043,7 +2043,7 @@ __STATIC_INLINE void TZ_SAU_Disable(void) @{ */ - + /** \brief Set Debug Authentication Control Register \details writes to Debug Authentication Control register. @@ -2110,7 +2110,7 @@ __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) @{ */ - + /** \brief Get Debug Authentication Status Register \details Reads Debug Authentication Status register. diff --git a/Drivers/CMSIS/Include/core_cm0.h b/Drivers/CMSIS/Include/core_cm0.h index 6441ff34..0a0ba223 100644 --- a/Drivers/CMSIS/Include/core_cm0.h +++ b/Drivers/CMSIS/Include/core_cm0.h @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS CM0 definitions */ #define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ diff --git a/Drivers/CMSIS/Include/core_cm0plus.h b/Drivers/CMSIS/Include/core_cm0plus.h index 4e7179a6..879a3841 100644 --- a/Drivers/CMSIS/Include/core_cm0plus.h +++ b/Drivers/CMSIS/Include/core_cm0plus.h @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS CM0+ definitions */ #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ diff --git a/Drivers/CMSIS/Include/core_cm1.h b/Drivers/CMSIS/Include/core_cm1.h index 76b45697..83b8fc6a 100644 --- a/Drivers/CMSIS/Include/core_cm1.h +++ b/Drivers/CMSIS/Include/core_cm1.h @@ -61,7 +61,7 @@ */ #include "cmsis_version.h" - + /* CMSIS CM1 definitions */ #define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ #define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ diff --git a/Drivers/CMSIS/Include/core_cm23.h b/Drivers/CMSIS/Include/core_cm23.h index 55fff995..f2cf49fb 100644 --- a/Drivers/CMSIS/Include/core_cm23.h +++ b/Drivers/CMSIS/Include/core_cm23.h @@ -1486,7 +1486,7 @@ typedef struct /* Special LR values for Secure/Non-Secure call handling and exception handling */ -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ @@ -2118,7 +2118,7 @@ __STATIC_INLINE void TZ_SAU_Disable(void) @{ */ - + /** \brief Set Debug Authentication Control Register \details writes to Debug Authentication Control register. @@ -2185,7 +2185,7 @@ __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) @{ */ - + /** \brief Get Debug Authentication Status Register \details Reads Debug Authentication Status register. diff --git a/Drivers/CMSIS/Include/core_sc000.h b/Drivers/CMSIS/Include/core_sc000.h index dbc755ff..e252068c 100644 --- a/Drivers/CMSIS/Include/core_sc000.h +++ b/Drivers/CMSIS/Include/core_sc000.h @@ -146,7 +146,7 @@ #define __VTOR_PRESENT 0U #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif - + #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" diff --git a/Drivers/CMSIS/Include/core_starmc1.h b/Drivers/CMSIS/Include/core_starmc1.h index d86c8d38..a09fb524 100644 --- a/Drivers/CMSIS/Include/core_starmc1.h +++ b/Drivers/CMSIS/Include/core_starmc1.h @@ -5,8 +5,8 @@ * @date 07. April 2022 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. - * Copyright (c) 2018-2022 Arm China. + * Copyright (c) 2009-2018 Arm Limited. + * Copyright (c) 2018-2022 Arm China. * All rights reserved. * SPDX-License-Identifier: Apache-2.0 * @@ -535,7 +535,7 @@ typedef struct __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED_ADD1[21U]; + uint32_t RESERVED_ADD1[21U]; __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ uint32_t RESERVED3[69U]; @@ -561,7 +561,7 @@ typedef struct { __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ }EMSS_Type; /* SCB CPUID Register Definitions */ @@ -2130,7 +2130,7 @@ typedef struct #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ #define EMSS_BASE (0xE001E000UL) /*!AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ - SCB_AIRCR_SYSRESETREQ_Msk ); + SCB_AIRCR_SYSRESETREQ_Msk ); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ @@ -3349,10 +3349,10 @@ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { + if ( dsize > 0 ) { int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - + __DSB(); do { @@ -3379,10 +3379,10 @@ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsiz __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { + if ( dsize > 0 ) { int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - + __DSB(); do { @@ -3409,10 +3409,10 @@ __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) { #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { + if ( dsize > 0 ) { int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - + __DSB(); do { diff --git a/Drivers/CMSIS/Include/mpu_armv7.h b/Drivers/CMSIS/Include/mpu_armv7.h index d9eedf81..9909f839 100644 --- a/Drivers/CMSIS/Include/mpu_armv7.h +++ b/Drivers/CMSIS/Include/mpu_armv7.h @@ -21,13 +21,13 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif - + #ifndef ARM_MPU_ARMV7_H #define ARM_MPU_ARMV7_H @@ -79,12 +79,12 @@ /** * MPU Memory Access Attributes -* +* * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. * \param IsShareable Region is shareable between multiple bus masters. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -*/ +*/ #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ @@ -93,7 +93,7 @@ /** * MPU Region Attribute and Size Register Value -* +* * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. @@ -110,7 +110,7 @@ /** * MPU Region Attribute and Size Register Value -* +* * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. @@ -119,7 +119,7 @@ * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. * \param SubRegionDisable Sub-region disable field. * \param Size Region size of the region to be configured, for example 4K, 8K. -*/ +*/ #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) @@ -129,7 +129,7 @@ * - Shareable * - Non-cacheable * - Non-bufferable -*/ +*/ #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) /** @@ -140,7 +140,7 @@ * - Bufferable (if shareable) or non-bufferable (if non-shareable) * * \param IsShareable Configures the device memory as shareable or non-shareable. -*/ +*/ #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) /** @@ -153,7 +153,7 @@ * \param OuterCp Configures the outer cache policy. * \param InnerCp Configures the inner cache policy. * \param IsShareable Configures the memory as shareable or non-shareable. -*/ +*/ #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) /** @@ -184,7 +184,7 @@ typedef struct { uint32_t RBAR; //!< The region base address register value (RBAR) uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR } ARM_MPU_Region_t; - + /** Enable the MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ @@ -224,7 +224,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) /** Configure an MPU region. * \param rbar Value for RBAR register. * \param rasr Value for RASR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) { MPU->RBAR = rbar; @@ -235,7 +235,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rasr Value for RASR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) { MPU->RNR = rnr; @@ -251,7 +251,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t r __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; - for (i = 0U; i < len; ++i) + for (i = 0U; i < len; ++i) { dst[i] = src[i]; } @@ -261,7 +261,7 @@ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_ * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; while (cnt > MPU_TYPE_RALIASES) { diff --git a/Drivers/CMSIS/Include/mpu_armv8.h b/Drivers/CMSIS/Include/mpu_armv8.h index 3de16efc..e6cd1a84 100644 --- a/Drivers/CMSIS/Include/mpu_armv8.h +++ b/Drivers/CMSIS/Include/mpu_armv8.h @@ -102,7 +102,7 @@ (MPU_RLAR_EN_Msk)) #if defined(MPU_RLAR_PXN_Pos) - + /** \brief Region Limit Address Register with PXN value * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. * \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. @@ -113,7 +113,7 @@ (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ (MPU_RLAR_EN_Msk)) - + #endif /** @@ -123,7 +123,7 @@ typedef struct { uint32_t RBAR; /*!< Region Base Address Register value */ uint32_t RLAR; /*!< Region Limit Address Register value */ } ARM_MPU_Region_t; - + /** Enable the MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ @@ -190,11 +190,11 @@ __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t at const uint8_t reg = idx / 4U; const uint32_t pos = ((idx % 4U) * 8U); const uint32_t mask = 0xFFU << pos; - + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { return; // invalid index } - + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); } @@ -241,7 +241,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) * \param rnr Region number to be cleared. */ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) -{ +{ ARM_MPU_ClrRegionEx(MPU_NS, rnr); } #endif @@ -251,7 +251,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) { mpu->RNR = rnr; @@ -263,7 +263,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t r * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) { ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); @@ -274,10 +274,10 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rla * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rlar Value for RLAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) { - ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); } #endif @@ -289,7 +289,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; - for (i = 0U; i < len; ++i) + for (i = 0U; i < len; ++i) { dst[i] = src[i]; } @@ -301,7 +301,7 @@ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_ * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; if (cnt == 1U) { @@ -310,7 +310,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ } else { uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; - + mpu->RNR = rnrBase; while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { uint32_t c = MPU_TYPE_RALIASES - rnrOffset; @@ -321,7 +321,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ rnrBase += MPU_TYPE_RALIASES; mpu->RNR = rnrBase; } - + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); } } @@ -331,7 +331,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { ARM_MPU_LoadEx(MPU, rnr, table, cnt); } @@ -342,11 +342,10 @@ __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, u * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); } #endif #endif - diff --git a/Drivers/CMSIS/Include/pmu_armv8.h b/Drivers/CMSIS/Include/pmu_armv8.h index f8f3d893..aa53bb47 100644 --- a/Drivers/CMSIS/Include/pmu_armv8.h +++ b/Drivers/CMSIS/Include/pmu_armv8.h @@ -192,23 +192,23 @@ __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); __STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); -/** +/** \brief Enable the PMU */ -__STATIC_INLINE void ARM_PMU_Enable(void) +__STATIC_INLINE void ARM_PMU_Enable(void) { PMU->CTRL |= PMU_CTRL_ENABLE_Msk; } -/** +/** \brief Disable the PMU */ -__STATIC_INLINE void ARM_PMU_Disable(void) +__STATIC_INLINE void ARM_PMU_Disable(void) { PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; } -/** +/** \brief Set event to count for PMU eventer counter \param [in] num Event counter (0-30) to configure \param [in] type Event to count @@ -218,7 +218,7 @@ __STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) PMU->EVTYPER[num] = type; } -/** +/** \brief Reset cycle counter */ __STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) @@ -226,7 +226,7 @@ __STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; } -/** +/** \brief Reset all event counters */ __STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) @@ -234,8 +234,8 @@ __STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; } -/** - \brief Enable counters +/** + \brief Enable counters \param [in] mask Counters to enable \note Enables one or more of the following: - event counters (0-30) @@ -246,7 +246,7 @@ __STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) PMU->CNTENSET = mask; } -/** +/** \brief Disable counters \param [in] mask Counters to enable \note Disables one or more of the following: @@ -258,7 +258,7 @@ __STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) PMU->CNTENCLR = mask; } -/** +/** \brief Read cycle counter \return Cycle count */ @@ -267,7 +267,7 @@ __STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) return PMU->CCNTR; } -/** +/** \brief Read event counter \param [in] num Event counter (0-30) to read \return Event count @@ -277,7 +277,7 @@ __STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; } -/** +/** \brief Read counter overflow status \return Counter overflow status bits for the following: - event counters (0-30) @@ -285,10 +285,10 @@ __STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) */ __STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) { - return PMU->OVSSET; + return PMU->OVSSET; } -/** +/** \brief Clear counter overflow status \param [in] mask Counter overflow status bits to clear \note Clears overflow status bits for one or more of the following: @@ -300,8 +300,8 @@ __STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) PMU->OVSCLR = mask; } -/** - \brief Enable counter overflow interrupt request +/** + \brief Enable counter overflow interrupt request \param [in] mask Counter overflow interrupt request bits to set \note Sets overflow interrupt request bits for one or more of the following: - event counters (0-30) @@ -312,8 +312,8 @@ __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) PMU->INTENSET = mask; } -/** - \brief Disable counter overflow interrupt request +/** + \brief Disable counter overflow interrupt request \param [in] mask Counter overflow interrupt request bits to clear \note Clears overflow interrupt request bits for one or more of the following: - event counters (0-30) @@ -324,8 +324,8 @@ __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) PMU->INTENCLR = mask; } -/** - \brief Software increment event counter +/** + \brief Software increment event counter \param [in] mask Counters to increment \note Software increment bits for one or more event counters (0-30) */ diff --git a/Drivers/CMSIS/Include/tz_context.h b/Drivers/CMSIS/Include/tz_context.h index 0d09749f..facc2c9a 100644 --- a/Drivers/CMSIS/Include/tz_context.h +++ b/Drivers/CMSIS/Include/tz_context.h @@ -30,41 +30,41 @@ #ifndef TZ_CONTEXT_H #define TZ_CONTEXT_H - + #include - + #ifndef TZ_MODULEID_T #define TZ_MODULEID_T /// \details Data type that identifies secure software modules called by a process. typedef uint32_t TZ_ModuleId_t; #endif - + /// \details TZ Memory ID identifies an allocated memory slot. typedef uint32_t TZ_MemoryId_t; - + /// Initialize secure context memory system /// \return execution status (1: success, 0: error) uint32_t TZ_InitContextSystem_S (void); - + /// Allocate context memory for calling secure software modules in TrustZone /// \param[in] module identifies software modules called from non-secure mode /// \return value != 0 id TrustZone memory slot identifier /// \return value 0 no memory available or internal error TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); - + /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); - + /// Load secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); - + /// Store secure context (called on RTOS thread context switch) /// \param[in] id TrustZone memory slot identifier /// \return execution status (1: success, 0: error) uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); - + #endif // TZ_CONTEXT_H diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index c3b84738..51d5c3bf 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -139,7 +139,7 @@ extern "C" { #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 #if defined(STM32L0) -#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ #endif #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR @@ -241,9 +241,9 @@ extern "C" { */ #if defined(STM32H5) || defined(STM32C0) #else -#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ -#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ #endif /** @@ -472,7 +472,7 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD -#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) #define PAGESIZE FLASH_PAGE_SIZE #endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE @@ -1602,35 +1602,35 @@ extern "C" { #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ #if defined(STM32F1) #else #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ #endif -#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ @@ -2500,9 +2500,9 @@ extern "C" { /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose * @{ */ -#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ /** * @} @@ -4418,5 +4418,3 @@ extern "C" { #endif #endif /* STM32_HAL_LEGACY */ - - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h index f7eb847b..a259f74b 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32f4xx_hal.h * @author MCD Application Team - * @brief This file contains all the functions prototypes for the HAL + * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** * @attention @@ -15,7 +15,7 @@ * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_H @@ -34,7 +34,7 @@ /** @addtogroup HAL * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ @@ -60,13 +60,13 @@ typedef enum /** * @} */ - + /* Exported macro ------------------------------------------------------------*/ /** @defgroup HAL_Exported_Macros HAL Exported Macros * @{ */ -/** @brief Freeze/Unfreeze Peripherals in Debug mode +/** @brief Freeze/Unfreeze Peripherals in Debug mode */ #define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) #define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) @@ -151,7 +151,7 @@ typedef enum #define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\ }while(0); -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx) /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable @@ -255,7 +255,7 @@ uint32_t HAL_GetUIDw2(void); defined(STM32F469xx) || defined(STM32F479xx) void HAL_EnableMemorySwappingBank(void); void HAL_DisableMemorySwappingBank(void); -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ /** * @} */ @@ -286,12 +286,10 @@ void HAL_DisableMemorySwappingBank(void); /** * @} - */ - + */ + #ifdef __cplusplus } #endif #endif /* __STM32F4xx_HAL_H */ - - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h index 76909305..9366553b 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h @@ -13,7 +13,7 @@ * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_CORTEX_H @@ -32,7 +32,7 @@ /** @addtogroup CORTEX * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Types Cortex Exported Types * @{ @@ -40,31 +40,31 @@ #if (__MPU_PRESENT == 1U) /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition - * @brief MPU Region initialization structure + * @brief MPU Region initialization structure * @{ */ typedef struct { - uint8_t Enable; /*!< Specifies the status of the region. + uint8_t Enable; /*!< Specifies the status of the region. This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ - uint8_t Number; /*!< Specifies the number of the region to protect. + uint8_t Number; /*!< Specifies the number of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Number */ uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ - uint8_t Size; /*!< Specifies the size of the region to protect. + uint8_t Size; /*!< Specifies the size of the region to protect. This parameter can be a value of @ref CORTEX_MPU_Region_Size */ - uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ uint8_t TypeExtField; /*!< Specifies the TEX field level. - This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ - uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ - uint8_t DisableExec; /*!< Specifies the instruction access status. + uint8_t DisableExec; /*!< Specifies the instruction access status. This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ - uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ - uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ - uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ }MPU_Region_InitTypeDef; /** @@ -99,7 +99,7 @@ typedef struct * @} */ -/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source +/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source * @{ */ #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U @@ -211,8 +211,8 @@ typedef struct /** * @} */ - -/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) @@ -252,7 +252,7 @@ typedef struct /** @addtogroup CORTEX_Exported_Functions * @{ */ - + /** @addtogroup CORTEX_Exported_Functions_Group1 * @{ */ @@ -387,24 +387,22 @@ void HAL_CORTEX_ClearEvent(void); #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) #endif /* __MPU_PRESENT */ -/** - * @} +/** + * @} */ /* Private functions ---------------------------------------------------------*/ /** * @} - */ + */ /** * @} */ - + #ifdef __cplusplus } #endif #endif /* __STM32F4xx_HAL_CORTEX_H */ - - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h index 1df0d7d0..17bc901c 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_def.h * @author MCD Application Team - * @brief This file contains HAL common defines, enumeration, macros and - * structures definitions. + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. ****************************************************************************** * @attention * @@ -32,10 +32,10 @@ /* Exported types ------------------------------------------------------------*/ -/** - * @brief HAL Status structures definition - */ -typedef enum +/** + * @brief HAL Status structures definition + */ +typedef enum { HAL_OK = 0x00U, HAL_ERROR = 0x01U, @@ -43,13 +43,13 @@ typedef enum HAL_TIMEOUT = 0x03U } HAL_StatusTypeDef; -/** - * @brief HAL Lock structures definition +/** + * @brief HAL Lock structures definition */ -typedef enum +typedef enum { HAL_UNLOCKED = 0x00U, - HAL_LOCKED = 0x01U + HAL_LOCKED = 0x01U } HAL_LockTypeDef; /* Exported macro ------------------------------------------------------------*/ @@ -71,11 +71,11 @@ typedef enum /** @brief Reset the Handle's State field. * @param __HANDLE__ specifies the Peripheral Handle. - * @note This macro can be used for the following purpose: + * @note This macro can be used for the following purpose: * - When the Handle is declared as local variable; before passing it as parameter - * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro * to set to 0 the Handle's "State" field. - * Otherwise, "State" field may have any random value and the first time the function + * Otherwise, "State" field may have any random value and the first time the function * HAL_PPP_Init() is called, the low level hardware initialization will be missed * (i.e. HAL_PPP_MspInit() will not be executed). * - When there is a need to reconfigure the low level hardware: instead of calling @@ -137,58 +137,58 @@ typedef enum #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4))) #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN + #ifndef __ALIGN_BEGIN #define __ALIGN_BEGIN #endif /* __ALIGN_BEGIN */ #else #ifndef __ALIGN_END #define __ALIGN_END #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN + #ifndef __ALIGN_BEGIN #if defined (__CC_ARM) /* ARM Compiler V5*/ #define __ALIGN_BEGIN __align(4) #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN + #define __ALIGN_BEGIN #endif /* __CC_ARM */ #endif /* __ALIGN_BEGIN */ #endif /* __GNUC__ */ -/** +/** * @brief __RAM_FUNC definition - */ + */ #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) /* ARM Compiler V4/V5 and V6 -------------------------- - RAM functions are defined using the toolchain options. + RAM functions are defined using the toolchain options. Functions that are executed in RAM should reside in a separate source module. - Using the 'Options for File' dialog you can simply change the 'Code / Const' + Using the 'Options for File' dialog you can simply change the 'Code / Const' area of a module to a memory space in physical RAM. Available memory areas are declared in the 'Target' tab of the 'Options for Target' - dialog. + dialog. */ #define __RAM_FUNC #elif defined ( __ICCARM__ ) /* ICCARM Compiler --------------- - RAM functions are defined using a specific toolchain keyword "__ramfunc". + RAM functions are defined using a specific toolchain keyword "__ramfunc". */ #define __RAM_FUNC __ramfunc #elif defined ( __GNUC__ ) /* GNU Compiler ------------ - RAM functions are defined using a specific toolchain attribute + RAM functions are defined using a specific toolchain attribute "__attribute__((section(".RamFunc")))". */ #define __RAM_FUNC __attribute__((section(".RamFunc"))) #endif -/** +/** * @brief __NOINLINE definition - */ + */ #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) /* ARM V4/V5 and V6 & GNU Compiler ------------------------------- @@ -208,5 +208,3 @@ typedef enum #endif #endif /* ___STM32F4xx_HAL_DEF */ - - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h index 7ff3836b..ec6e422c 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h @@ -14,7 +14,7 @@ * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_DMA_H @@ -33,24 +33,24 @@ /** @addtogroup DMA * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup DMA_Exported_Types DMA Exported Types - * @brief DMA Exported Types + * @brief DMA Exported Types * @{ */ - -/** + +/** * @brief DMA Configuration Structure definition */ typedef struct { - uint32_t Channel; /*!< Specifies the channel used for the specified stream. + uint32_t Channel; /*!< Specifies the channel used for the specified stream. This parameter can be a value of @ref DMA_Channel_selection */ - uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of @ref DMA_Data_transfer_direction */ @@ -76,27 +76,27 @@ typedef struct uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. This parameter can be a value of @ref DMA_FIFO_direct_mode - @note The Direct mode (FIFO mode disabled) cannot be used if the + @note The Direct mode (FIFO mode disabled) cannot be used if the memory-to-memory data transfer is configured on the selected stream */ uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. This parameter can be a value of @ref DMA_FIFO_threshold_level */ - uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. + uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. It specifies the amount of data to be transferred in a single non interruptible transaction. - This parameter can be a value of @ref DMA_Memory_burst + This parameter can be a value of @ref DMA_Memory_burst @note The burst mode is possible only if the address Increment mode is enabled. */ - uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. - It specifies the amount of data to be transferred in a single non interruptible - transaction. + uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. This parameter can be a value of @ref DMA_Peripheral_burst @note The burst mode is possible only if the address Increment mode is enabled. */ }DMA_InitTypeDef; -/** +/** * @brief HAL DMA State structures definition */ typedef enum @@ -109,7 +109,7 @@ typedef enum HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ }HAL_DMA_StateTypeDef; -/** +/** * @brief HAL DMA Error Code structure definition */ typedef enum @@ -118,7 +118,7 @@ typedef enum HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ }HAL_DMA_LevelCompleteTypeDef; -/** +/** * @brief HAL DMA Error Code structure definition */ typedef enum @@ -132,39 +132,39 @@ typedef enum HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ }HAL_DMA_CallbackIDTypeDef; -/** +/** * @brief DMA handle Structure definition */ typedef struct __DMA_HandleTypeDef { DMA_Stream_TypeDef *Instance; /*!< Register base address */ - DMA_InitTypeDef Init; /*!< DMA communication parameters */ + DMA_InitTypeDef Init; /*!< DMA communication parameters */ - HAL_LockTypeDef Lock; /*!< DMA locking object */ + HAL_LockTypeDef Lock; /*!< DMA locking object */ __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ - void *Parent; /*!< Parent object state */ + void *Parent; /*!< Parent object state */ void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ - + void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ - + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ - - void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ + + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ __IO uint32_t ErrorCode; /*!< DMA Error code */ - + uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ uint32_t StreamIndex; /*!< DMA Stream Index */ - + }DMA_HandleTypeDef; /** @@ -174,14 +174,14 @@ typedef struct __DMA_HandleTypeDef /* Exported constants --------------------------------------------------------*/ /** @defgroup DMA_Exported_Constants DMA Exported Constants - * @brief DMA Exported constants + * @brief DMA Exported constants * @{ */ /** @defgroup DMA_Error_Code DMA Error Code - * @brief DMA Error Code + * @brief DMA Error Code * @{ - */ + */ #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ #define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */ @@ -195,9 +195,9 @@ typedef struct __DMA_HandleTypeDef */ /** @defgroup DMA_Channel_selection DMA Channel selection - * @brief DMA channel selection + * @brief DMA channel selection * @{ - */ + */ #define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */ #define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */ #define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */ @@ -221,30 +221,30 @@ typedef struct __DMA_HandleTypeDef */ /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction - * @brief DMA data transfer direction + * @brief DMA data transfer direction * @{ - */ + */ #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ /** * @} */ - + /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode - * @brief DMA peripheral incremented mode + * @brief DMA peripheral incremented mode * @{ - */ + */ #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */ /** * @} - */ + */ /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode - * @brief DMA memory incremented mode + * @brief DMA memory incremented mode * @{ - */ + */ #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */ /** @@ -252,19 +252,19 @@ typedef struct __DMA_HandleTypeDef */ /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size - * @brief DMA peripheral data size + * @brief DMA peripheral data size * @{ - */ + */ #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ /** * @} - */ + */ /** @defgroup DMA_Memory_data_size DMA Memory data size - * @brief DMA memory data size - * @{ + * @brief DMA memory data size + * @{ */ #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ @@ -274,9 +274,9 @@ typedef struct __DMA_HandleTypeDef */ /** @defgroup DMA_mode DMA mode - * @brief DMA mode + * @brief DMA mode * @{ - */ + */ #define DMA_NORMAL 0x00000000U /*!< Normal mode */ #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ @@ -285,7 +285,7 @@ typedef struct __DMA_HandleTypeDef */ /** @defgroup DMA_Priority_level DMA Priority level - * @brief DMA priority levels + * @brief DMA priority levels * @{ */ #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */ @@ -294,7 +294,7 @@ typedef struct __DMA_HandleTypeDef #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ /** * @} - */ + */ /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode * @brief DMA FIFO direct mode @@ -304,10 +304,10 @@ typedef struct __DMA_HandleTypeDef #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ /** * @} - */ + */ /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level - * @brief DMA FIFO level + * @brief DMA FIFO level * @{ */ #define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */ @@ -316,24 +316,24 @@ typedef struct __DMA_HandleTypeDef #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ /** * @} - */ + */ /** @defgroup DMA_Memory_burst DMA Memory burst - * @brief DMA memory burst + * @brief DMA memory burst * @{ - */ + */ #define DMA_MBURST_SINGLE 0x00000000U -#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) -#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) -#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) +#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) +#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) +#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) /** * @} - */ + */ /** @defgroup DMA_Peripheral_burst DMA Peripheral burst - * @brief DMA peripheral burst + * @brief DMA peripheral burst * @{ - */ + */ #define DMA_PBURST_SINGLE 0x00000000U #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) @@ -343,7 +343,7 @@ typedef struct __DMA_HandleTypeDef */ /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions - * @brief DMA interrupts definition + * @brief DMA interrupts definition * @{ */ #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) @@ -356,9 +356,9 @@ typedef struct __DMA_HandleTypeDef */ /** @defgroup DMA_flag_definitions DMA flag definitions - * @brief DMA flag definitions + * @brief DMA flag definitions * @{ - */ + */ #define DMA_FLAG_FEIF0_4 0x00000001U #define DMA_FLAG_DMEIF0_4 0x00000004U #define DMA_FLAG_TEIF0_4 0x00000008U @@ -386,7 +386,7 @@ typedef struct __DMA_HandleTypeDef /** * @} */ - + /* Exported macro ------------------------------------------------------------*/ /** @brief Reset DMA handle state @@ -399,7 +399,7 @@ typedef struct __DMA_HandleTypeDef * @brief Return the current DMA Stream FIFO filled level. * @param __HANDLE__ DMA handle * @retval The FIFO filling state. - * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full + * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full * and not empty. * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. @@ -449,7 +449,7 @@ typedef struct __DMA_HandleTypeDef * @brief Return the current DMA Stream half transfer complete flag. * @param __HANDLE__ DMA handle * @retval The specified half transfer complete flag index. - */ + */ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ @@ -535,7 +535,7 @@ typedef struct __DMA_HandleTypeDef * @arg DMA_FLAG_TEIFx: Transfer error flag. * @arg DMA_FLAG_DMEIFx: Direct mode error flag. * @arg DMA_FLAG_FEIFx: FIFO error flag. - * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. * @retval The state of FLAG (SET or RESET). */ #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ @@ -553,7 +553,7 @@ typedef struct __DMA_HandleTypeDef * @arg DMA_FLAG_TEIFx: Transfer error flag. * @arg DMA_FLAG_DMEIFx: Direct mode error flag. * @arg DMA_FLAG_FEIFx: FIFO error flag. - * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. * @retval None */ #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ @@ -564,7 +564,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Enable the specified DMA Stream interrupts. * @param __HANDLE__ DMA handle - * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask. * @arg DMA_IT_HT: Half transfer complete interrupt mask. @@ -579,7 +579,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Disable the specified DMA Stream interrupts. * @param __HANDLE__ DMA handle - * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask. * @arg DMA_IT_HT: Half transfer complete interrupt mask. @@ -610,18 +610,18 @@ typedef struct __DMA_HandleTypeDef /** * @brief Writes the number of data units to be transferred on the DMA Stream. * @param __HANDLE__ DMA handle - * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535) + * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535) * Number of data items depends only on the Peripheral data format. - * - * @note If Peripheral data format is Bytes: number of data units is equal + * + * @note If Peripheral data format is Bytes: number of data units is equal * to total number of bytes to be transferred. - * - * @note If Peripheral data format is Half-Word: number of data units is + * + * @note If Peripheral data format is Half-Word: number of data units is * equal to total number of bytes to be transferred / 2. - * - * @note If Peripheral data format is Word: number of data units is equal + * + * @note If Peripheral data format is Word: number of data units is equal * to total number of bytes to be transferred / 4. - * + * * @retval The number of remaining data units in the current DMAy Streamx transfer. */ #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) @@ -629,34 +629,34 @@ typedef struct __DMA_HandleTypeDef /** * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. * @param __HANDLE__ DMA handle - * + * * @retval The number of remaining data units in the current DMA Stream transfer. */ #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) /* Include DMA HAL Extension module */ -#include "stm32f4xx_hal_dma_ex.h" +#include "stm32f4xx_hal_dma_ex.h" /* Exported functions --------------------------------------------------------*/ /** @defgroup DMA_Exported_Functions DMA Exported Functions - * @brief DMA Exported functions + * @brief DMA Exported functions * @{ */ /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions + * @brief Initialization and de-initialization functions * @{ */ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); /** * @} */ /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions - * @brief I/O operation functions + * @brief I/O operation functions * @{ */ HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); @@ -671,32 +671,32 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca /** * @} - */ + */ /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions + * @brief Peripheral State functions * @{ */ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); /** * @} - */ + */ /** * @} - */ + */ /* Private Constants -------------------------------------------------------------*/ /** @defgroup DMA_Private_Constants DMA Private Constants - * @brief DMA private defines and constants + * @brief DMA private defines and constants * @{ */ /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup DMA_Private_Macros DMA Private Macros - * @brief DMA private macros + * @brief DMA private macros * @{ */ #if defined (DMA_SxCR_CHSEL_3) @@ -729,7 +729,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ - ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) @@ -749,12 +749,12 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ ((MODE) == DMA_CIRCULAR) || \ - ((MODE) == DMA_PFCTRL)) + ((MODE) == DMA_PFCTRL)) #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ ((PRIORITY) == DMA_PRIORITY_HIGH) || \ - ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ ((STATE) == DMA_FIFOMODE_ENABLE)) @@ -775,11 +775,11 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); ((BURST) == DMA_PBURST_INC16)) /** * @} - */ + */ /* Private functions ---------------------------------------------------------*/ /** @defgroup DMA_Private_Functions DMA Private Functions - * @brief DMA private functions + * @brief DMA private functions * @{ */ /** @@ -788,7 +788,7 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); /** * @} - */ + */ /** * @} @@ -799,4 +799,3 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); #endif #endif /* __STM32F4xx_HAL_DMA_H */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h index 9858c741..ed41a28a 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h @@ -33,17 +33,17 @@ /** @addtogroup DMAEx * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup DMAEx_Exported_Types DMAEx Exported Types * @brief DMAEx Exported types * @{ */ - -/** - * @brief HAL DMA Memory definition - */ + +/** + * @brief HAL DMA Memory definition + */ typedef enum { MEMORY0 = 0x00U, /*!< Memory 0 */ @@ -76,7 +76,7 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre /** * @} */ - + /* Private functions ---------------------------------------------------------*/ /** @defgroup DMAEx_Private_Functions DMAEx Private Functions * @brief DMAEx Private functions @@ -99,4 +99,3 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre #endif #endif /*__STM32F4xx_HAL_DMA_EX_H*/ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h index b18a2287..0c96b07b 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h @@ -363,4 +363,3 @@ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); #endif #endif /* STM32f4xx_HAL_EXTI_H */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h index 41f77d28..7f529667 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h @@ -422,4 +422,3 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #endif #endif /* __STM32F4xx_HAL_FLASH_H */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h index 5fa89db5..b9d5bfe8 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h @@ -183,7 +183,7 @@ typedef struct */ #define OB_RDP_LEVEL_0 ((uint8_t)0xAA) #define OB_RDP_LEVEL_1 ((uint8_t)0x55) -#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2 +#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2 it s no more possible to go back to level 1 or 0 */ /** * @} @@ -1060,4 +1060,3 @@ void FLASH_FlushCaches(void); #endif #endif /* __STM32F4xx_HAL_FLASH_EX_H */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h index 2112e747..066eb048 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h @@ -73,4 +73,3 @@ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void); #endif /* __STM32F4xx_FLASH_RAMFUNC_H */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h index 5f3d749e..c68ccb9a 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h @@ -14,7 +14,7 @@ * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_GPIO_H @@ -33,16 +33,16 @@ /** @addtogroup GPIO * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup GPIO_Exported_Types GPIO Exported Types * @{ */ -/** - * @brief GPIO Init structure definition - */ +/** + * @brief GPIO Init structure definition + */ typedef struct { uint32_t Pin; /*!< Specifies the GPIO pins to be configured. @@ -57,12 +57,12 @@ typedef struct uint32_t Speed; /*!< Specifies the speed for the selected pins. This parameter can be a value of @ref GPIO_speed_define */ - uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. This parameter can be a value of @ref GPIO_Alternate_function_selection */ }GPIO_InitTypeDef; -/** - * @brief GPIO Bit SET and Bit RESET enumeration +/** + * @brief GPIO Bit SET and Bit RESET enumeration */ typedef enum { @@ -77,7 +77,7 @@ typedef enum /** @defgroup GPIO_Exported_Constants GPIO Exported Constants * @{ - */ + */ /** @defgroup GPIO_pins_define GPIO pins define * @{ @@ -113,7 +113,7 @@ typedef enum * - Y : Output type (Push Pull or Open Drain) on 1 bit * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits * @{ - */ + */ #define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ #define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ #define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ @@ -121,11 +121,11 @@ typedef enum #define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ #define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ - + #define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ #define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ #define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ - + #define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ #define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ #define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ @@ -149,14 +149,14 @@ typedef enum /** @defgroup GPIO_pull_define GPIO pull define * @brief GPIO Pull-Up or Pull-Down Activation * @{ - */ + */ #define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */ #define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */ #define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */ /** * @} */ - + /** * @} */ @@ -240,11 +240,11 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); /** * @} - */ + */ /** * @} - */ + */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ @@ -311,7 +311,7 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); /** * @} - */ + */ /** * @} @@ -322,4 +322,3 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); #endif #endif /* __STM32F4xx_HAL_GPIO_H */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h index 5e0b7cc6..2a422eee 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h @@ -14,7 +14,7 @@ * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_GPIO_EX_H @@ -33,60 +33,60 @@ /** @defgroup GPIOEx GPIOEx * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants * @{ */ - + /** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection * @{ */ /*------------------------------------------ STM32F429xx/STM32F439xx ---------*/ #if defined(STM32F429xx) || defined(STM32F439xx) -/** - * @brief AF 0 selection - */ +/** + * @brief AF 0 selection + */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ -/** - * @brief AF 1 selection - */ +/** + * @brief AF 1 selection + */ #define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ #define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -/** - * @brief AF 2 selection - */ +/** + * @brief AF 2 selection + */ #define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ #define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ #define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ -/** - * @brief AF 3 selection - */ +/** + * @brief AF 3 selection + */ #define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ #define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ #define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ #define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ -/** - * @brief AF 4 selection - */ +/** + * @brief AF 4 selection + */ #define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ #define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -/** - * @brief AF 5 selection - */ +/** + * @brief AF 5 selection + */ #define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ @@ -95,33 +95,33 @@ #define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ #define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ -/** - * @brief AF 6 selection - */ +/** + * @brief AF 6 selection + */ #define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ #define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ -/** - * @brief AF 7 selection - */ +/** + * @brief AF 7 selection + */ #define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ #define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ #define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ -/** - * @brief AF 8 selection - */ +/** + * @brief AF 8 selection + */ #define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ #define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ #define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ #define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ #define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ -/** - * @brief AF 9 selection - */ +/** + * @brief AF 9 selection + */ #define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ #define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ #define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ @@ -129,499 +129,499 @@ #define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ #define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */ -/** - * @brief AF 10 selection - */ +/** + * @brief AF 10 selection + */ #define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ #define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ -/** - * @brief AF 11 selection - */ +/** + * @brief AF 11 selection + */ #define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ -/** - * @brief AF 12 selection - */ +/** + * @brief AF 12 selection + */ #define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ #define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ #define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ -/** - * @brief AF 13 selection - */ +/** + * @brief AF 13 selection + */ #define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ -/** - * @brief AF 14 selection +/** + * @brief AF 14 selection */ #define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */ -/** - * @brief AF 15 selection - */ +/** + * @brief AF 15 selection + */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ #endif /* STM32F429xx || STM32F439xx */ /*----------------------------------------------------------------------------*/ /*---------------------------------- STM32F427xx/STM32F437xx------------------*/ #if defined(STM32F427xx) || defined(STM32F437xx) -/** - * @brief AF 0 selection - */ +/** + * @brief AF 0 selection + */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ -/** - * @brief AF 1 selection - */ +/** + * @brief AF 1 selection + */ #define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ #define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -/** - * @brief AF 2 selection - */ +/** + * @brief AF 2 selection + */ #define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ #define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ #define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ -/** - * @brief AF 3 selection - */ +/** + * @brief AF 3 selection + */ #define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ #define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ #define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ #define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ -/** - * @brief AF 4 selection - */ +/** + * @brief AF 4 selection + */ #define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ #define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -/** - * @brief AF 5 selection - */ +/** + * @brief AF 5 selection + */ #define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ #define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ #define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ -/** @brief GPIO_Legacy +/** @brief GPIO_Legacy */ #define GPIO_AF5_I2S3ext GPIO_AF5_SPI3 /* I2S3ext_SD Alternate Function mapping */ -/** - * @brief AF 6 selection - */ +/** + * @brief AF 6 selection + */ #define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ #define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ -/** - * @brief AF 7 selection - */ +/** + * @brief AF 7 selection + */ #define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ #define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ #define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ -/** - * @brief AF 8 selection - */ +/** + * @brief AF 8 selection + */ #define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ #define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ #define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ #define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ #define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ -/** - * @brief AF 9 selection - */ +/** + * @brief AF 9 selection + */ #define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ #define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ #define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ #define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ #define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ -/** - * @brief AF 10 selection - */ +/** + * @brief AF 10 selection + */ #define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ #define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ -/** - * @brief AF 11 selection - */ +/** + * @brief AF 11 selection + */ #define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ -/** - * @brief AF 12 selection - */ +/** + * @brief AF 12 selection + */ #define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ #define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ #define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ -/** - * @brief AF 13 selection - */ +/** + * @brief AF 13 selection + */ #define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ -/** - * @brief AF 15 selection - */ +/** + * @brief AF 15 selection + */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ #endif /* STM32F427xx || STM32F437xx */ /*----------------------------------------------------------------------------*/ /*---------------------------------- STM32F407xx/STM32F417xx------------------*/ #if defined(STM32F407xx) || defined(STM32F417xx) -/** - * @brief AF 0 selection - */ +/** + * @brief AF 0 selection + */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ -/** - * @brief AF 1 selection - */ +/** + * @brief AF 1 selection + */ #define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ #define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -/** - * @brief AF 2 selection - */ +/** + * @brief AF 2 selection + */ #define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ #define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ #define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ -/** - * @brief AF 3 selection - */ +/** + * @brief AF 3 selection + */ #define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ #define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ #define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ #define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ -/** - * @brief AF 4 selection - */ +/** + * @brief AF 4 selection + */ #define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ #define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -/** - * @brief AF 5 selection - */ +/** + * @brief AF 5 selection + */ #define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ -/** - * @brief AF 6 selection - */ +/** + * @brief AF 6 selection + */ #define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ -/** - * @brief AF 7 selection - */ +/** + * @brief AF 7 selection + */ #define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ #define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ #define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ -/** - * @brief AF 8 selection - */ +/** + * @brief AF 8 selection + */ #define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ #define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ #define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ -/** - * @brief AF 9 selection - */ +/** + * @brief AF 9 selection + */ #define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ #define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ #define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ #define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ #define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ -/** - * @brief AF 10 selection - */ +/** + * @brief AF 10 selection + */ #define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ #define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ -/** - * @brief AF 11 selection - */ +/** + * @brief AF 11 selection + */ #define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ -/** - * @brief AF 12 selection - */ +/** + * @brief AF 12 selection + */ #define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FSMC Alternate Function mapping */ #define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ #define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ -/** - * @brief AF 13 selection - */ +/** + * @brief AF 13 selection + */ #define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ -/** - * @brief AF 15 selection - */ +/** + * @brief AF 15 selection + */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ #endif /* STM32F407xx || STM32F417xx */ /*----------------------------------------------------------------------------*/ /*---------------------------------- STM32F405xx/STM32F415xx------------------*/ #if defined(STM32F405xx) || defined(STM32F415xx) -/** - * @brief AF 0 selection - */ +/** + * @brief AF 0 selection + */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ -/** - * @brief AF 1 selection - */ +/** + * @brief AF 1 selection + */ #define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ #define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -/** - * @brief AF 2 selection - */ +/** + * @brief AF 2 selection + */ #define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ #define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ #define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ -/** - * @brief AF 3 selection - */ +/** + * @brief AF 3 selection + */ #define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ #define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ #define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ #define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ -/** - * @brief AF 4 selection - */ +/** + * @brief AF 4 selection + */ #define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ #define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -/** - * @brief AF 5 selection - */ +/** + * @brief AF 5 selection + */ #define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ -/** - * @brief AF 6 selection - */ +/** + * @brief AF 6 selection + */ #define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ -/** - * @brief AF 7 selection - */ +/** + * @brief AF 7 selection + */ #define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ #define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ #define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ -/** - * @brief AF 8 selection - */ +/** + * @brief AF 8 selection + */ #define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ #define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ #define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ -/** - * @brief AF 9 selection - */ +/** + * @brief AF 9 selection + */ #define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ #define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ #define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ #define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ #define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ -/** - * @brief AF 10 selection - */ +/** + * @brief AF 10 selection + */ #define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ #define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ -/** - * @brief AF 12 selection - */ +/** + * @brief AF 12 selection + */ #define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FSMC Alternate Function mapping */ #define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ #define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ -/** - * @brief AF 15 selection - */ +/** + * @brief AF 15 selection + */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ #endif /* STM32F405xx || STM32F415xx */ /*----------------------------------------------------------------------------*/ /*---------------------------------------- STM32F401xx------------------------*/ -#if defined(STM32F401xC) || defined(STM32F401xE) -/** - * @brief AF 0 selection - */ +#if defined(STM32F401xC) || defined(STM32F401xE) +/** + * @brief AF 0 selection + */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ -/** - * @brief AF 1 selection - */ +/** + * @brief AF 1 selection + */ #define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ #define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -/** - * @brief AF 2 selection - */ +/** + * @brief AF 2 selection + */ #define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ #define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ #define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ -/** - * @brief AF 3 selection - */ +/** + * @brief AF 3 selection + */ #define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ #define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ #define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ -/** - * @brief AF 4 selection - */ +/** + * @brief AF 4 selection + */ #define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ #define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -/** - * @brief AF 5 selection - */ +/** + * @brief AF 5 selection + */ #define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */ #define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ #define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ -/** - * @brief AF 6 selection - */ +/** + * @brief AF 6 selection + */ #define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ -/** - * @brief AF 7 selection - */ +/** + * @brief AF 7 selection + */ #define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ #define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ -/** - * @brief AF 8 selection - */ +/** + * @brief AF 8 selection + */ #define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ -/** - * @brief AF 9 selection - */ +/** + * @brief AF 9 selection + */ #define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ #define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ -/** - * @brief AF 10 selection - */ +/** + * @brief AF 10 selection + */ #define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ -/** - * @brief AF 12 selection - */ +/** + * @brief AF 12 selection + */ #define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ -/** - * @brief AF 15 selection - */ +/** + * @brief AF 15 selection + */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ #endif /* STM32F401xC || STM32F401xE */ /*----------------------------------------------------------------------------*/ /*--------------- STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-------------*/ -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) -/** - * @brief AF 0 selection - */ +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) +/** + * @brief AF 0 selection + */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ -/** - * @brief AF 1 selection - */ +/** + * @brief AF 1 selection + */ #define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ #define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -/** - * @brief AF 2 selection - */ +/** + * @brief AF 2 selection + */ #define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ #define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ #define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ -/** - * @brief AF 3 selection - */ +/** + * @brief AF 3 selection + */ #define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ #define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ #define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ #define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ -/** - * @brief AF 4 selection - */ +/** + * @brief AF 4 selection + */ #define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ #define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ #define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */ -/** - * @brief AF 5 selection - */ +/** + * @brief AF 5 selection + */ #define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */ #define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ -/** - * @brief AF 6 selection +/** + * @brief AF 6 selection */ #define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ #define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ @@ -629,143 +629,25 @@ #define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ #define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ #define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */ -/** - * @brief AF 7 selection - */ +/** + * @brief AF 7 selection + */ #define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ #define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ #define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ -/** - * @brief AF 8 selection - */ +/** + * @brief AF 8 selection + */ #define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ #define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */ #define GPIO_AF8_DFSDM1 ((uint8_t)0x08) /* DFSDM1 Alternate Function mapping */ #define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */ -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ -#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ -#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ -#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ -#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ -#define GPIO_AF9_FMPI2C1 ((uint8_t)0x09) /* FMPI2C1 Alternate Function mapping */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF10_DFSDM1 ((uint8_t)0x0A) /* DFSDM1 Alternate Function mapping */ -#define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */ -#define GPIO_AF10_FMC ((uint8_t)0x0A) /* FMC Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ -#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ -#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ - -/*----------------------------------------------------------------------------*/ - -/*--------------- STM32F413xx/STM32F423xx-------------------------------------*/ -#if defined(STM32F413xx) || defined(STM32F423xx) -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ -#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ -#define GPIO_AF3_DFSDM2 ((uint8_t)0x03) /* DFSDM2 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */ -#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4/I2S4 Alternate Function mapping */ -#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ -#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ -#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */ -#define GPIO_AF6_DFSDM2 ((uint8_t)0x06) /* DFSDM2 Alternate Function mapping */ -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF7_SAI1 ((uint8_t)0x07) /* SAI1 Alternate Function mapping */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ -#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ -#define GPIO_AF7_DFSDM2 ((uint8_t)0x07) /* DFSDM2 Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ -#define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */ -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ -#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ -#define GPIO_AF8_DFSDM1 ((uint8_t)0x08) /* DFSDM1 Alternate Function mapping */ -#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */ - -/** - * @brief AF 9 selection +/** + * @brief AF 9 selection */ #define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ #define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ @@ -777,8 +659,126 @@ #define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ #define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */ -/** - * @brief AF 10 selection +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_DFSDM1 ((uint8_t)0x0A) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */ +#define GPIO_AF10_FMC ((uint8_t)0x0A) /* FMC Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ +#define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ + +/*----------------------------------------------------------------------------*/ + +/*--------------- STM32F413xx/STM32F423xx-------------------------------------*/ +#if defined(STM32F413xx) || defined(STM32F423xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ +#define GPIO_AF3_DFSDM2 ((uint8_t)0x03) /* DFSDM2 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ +#define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */ +#define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4/I2S4 Alternate Function mapping */ +#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ +#define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ +#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF6_DFSDM2 ((uint8_t)0x06) /* DFSDM2 Alternate Function mapping */ +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF7_SAI1 ((uint8_t)0x07) /* SAI1 Alternate Function mapping */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ +#define GPIO_AF7_DFSDM2 ((uint8_t)0x07) /* DFSDM2 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ +#define GPIO_AF8_DFSDM1 ((uint8_t)0x08) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ +#define GPIO_AF9_FMPI2C1 ((uint8_t)0x09) /* FMPI2C1 Alternate Function mapping */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */ + +/** + * @brief AF 10 selection */ #define GPIO_AF10_SAI1 ((uint8_t)0x0A) /* SAI1 Alternate Function mapping */ #define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ @@ -787,81 +787,81 @@ #define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */ #define GPIO_AF10_FSMC ((uint8_t)0x0A) /* FSMC Alternate Function mapping */ -/** - * @brief AF 11 selection +/** + * @brief AF 11 selection */ #define GPIO_AF11_UART4 ((uint8_t)0x0B) /* UART4 Alternate Function mapping */ #define GPIO_AF11_UART5 ((uint8_t)0x0B) /* UART5 Alternate Function mapping */ #define GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */ #define GPIO_AF11_UART10 ((uint8_t)0x0B) /* UART10 Alternate Function mapping */ #define GPIO_AF11_CAN3 ((uint8_t)0x0B) /* CAN3 Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ + +/** + * @brief AF 12 selection + */ #define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ #define GPIO_AF12_FSMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ -/** - * @brief AF 14 selection - */ +/** + * @brief AF 14 selection + */ #define GPIO_AF14_RNG ((uint8_t)0x0E) /* RNG Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ + +/** + * @brief AF 15 selection + */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ #endif /* STM32F413xx || STM32F423xx */ /*---------------------------------------- STM32F411xx------------------------*/ -#if defined(STM32F411xE) -/** - * @brief AF 0 selection - */ +#if defined(STM32F411xE) +/** + * @brief AF 0 selection + */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ -/** - * @brief AF 1 selection - */ +/** + * @brief AF 1 selection + */ #define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ #define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -/** - * @brief AF 2 selection - */ +/** + * @brief AF 2 selection + */ #define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ #define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ #define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ -/** - * @brief AF 3 selection - */ +/** + * @brief AF 3 selection + */ #define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ #define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ #define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ -/** - * @brief AF 4 selection - */ +/** + * @brief AF 4 selection + */ #define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ #define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -/** - * @brief AF 5 selection - */ +/** + * @brief AF 5 selection + */ #define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ #define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ -/** - * @brief AF 6 selection +/** + * @brief AF 6 selection */ #define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ #define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ @@ -869,177 +869,177 @@ #define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ #define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ -/** - * @brief AF 7 selection - */ +/** + * @brief AF 7 selection + */ #define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ #define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ -/** - * @brief AF 8 selection - */ +/** + * @brief AF 8 selection + */ #define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ -/** - * @brief AF 9 selection - */ +/** + * @brief AF 9 selection + */ #define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ #define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ #define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ -/** - * @brief AF 10 selection - */ +/** + * @brief AF 10 selection + */ #define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ -/** - * @brief AF 12 selection - */ +/** + * @brief AF 12 selection + */ #define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ -/** - * @brief AF 15 selection - */ +/** + * @brief AF 15 selection + */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ #endif /* STM32F411xE */ /*---------------------------------------- STM32F410xx------------------------*/ #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) -/** - * @brief AF 0 selection - */ +/** + * @brief AF 0 selection + */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ -/** - * @brief AF 1 selection - */ +/** + * @brief AF 1 selection + */ #define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ #define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ -/** - * @brief AF 2 selection - */ +/** + * @brief AF 2 selection + */ #define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ -/** - * @brief AF 3 selection - */ +/** + * @brief AF 3 selection + */ #define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ #define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ -/** - * @brief AF 4 selection - */ +/** + * @brief AF 4 selection + */ #define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ #define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */ -/** - * @brief AF 5 selection - */ +/** + * @brief AF 5 selection + */ #define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ -#if defined(STM32F410Cx) || defined(STM32F410Rx) +#if defined(STM32F410Cx) || defined(STM32F410Rx) #define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ -#endif /* STM32F410Cx || STM32F410Rx */ +#endif /* STM32F410Cx || STM32F410Rx */ -/** - * @brief AF 6 selection +/** + * @brief AF 6 selection */ #define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping */ -#if defined(STM32F410Cx) || defined(STM32F410Rx) +#if defined(STM32F410Cx) || defined(STM32F410Rx) #define GPIO_AF6_SPI2 ((uint8_t)0x06) /* I2S2 Alternate Function mapping */ -#endif /* STM32F410Cx || STM32F410Rx */ +#endif /* STM32F410Cx || STM32F410Rx */ #define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5/I2S5 Alternate Function mapping */ -/** - * @brief AF 7 selection - */ +/** + * @brief AF 7 selection + */ #define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -/** - * @brief AF 8 selection - */ +/** + * @brief AF 8 selection + */ #define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ -/** - * @brief AF 9 selection - */ +/** + * @brief AF 9 selection + */ #define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ #define GPIO_AF9_FMPI2C1 ((uint8_t)0x09) /* FMPI2C1 Alternate Function mapping */ -/** - * @brief AF 15 selection - */ +/** + * @brief AF 15 selection + */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ /*---------------------------------------- STM32F446xx -----------------------*/ #if defined(STM32F446xx) /** - * @brief AF 0 selection - */ + * @brief AF 0 selection + */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ -/** - * @brief AF 1 selection - */ +/** + * @brief AF 1 selection + */ #define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ #define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -/** - * @brief AF 2 selection - */ +/** + * @brief AF 2 selection + */ #define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ #define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ #define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ -/** - * @brief AF 3 selection - */ +/** + * @brief AF 3 selection + */ #define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ #define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ #define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ #define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ #define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */ -/** - * @brief AF 4 selection - */ +/** + * @brief AF 4 selection + */ #define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ #define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ #define GPIO_AF4_FMPI2C1 ((uint8_t)0x04) /* FMPI2C1 Alternate Function mapping */ #define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */ -/** - * @brief AF 5 selection - */ +/** + * @brief AF 5 selection + */ #define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ -/** - * @brief AF 6 selection - */ +/** + * @brief AF 6 selection + */ #define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping */ #define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ -/** - * @brief AF 7 selection - */ +/** + * @brief AF 7 selection + */ #define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ #define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ @@ -1048,18 +1048,18 @@ #define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF7_SPDIFRX ((uint8_t)0x07) /* SPDIFRX Alternate Function mapping */ -/** - * @brief AF 8 selection - */ +/** + * @brief AF 8 selection + */ #define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ #define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ #define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ #define GPIO_AF8_SPDIFRX ((uint8_t)0x08) /* SPDIFRX Alternate Function mapping */ #define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */ -/** - * @brief AF 9 selection - */ +/** + * @brief AF 9 selection + */ #define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ #define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ #define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ @@ -1067,34 +1067,34 @@ #define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ #define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */ -/** - * @brief AF 10 selection - */ +/** + * @brief AF 10 selection + */ #define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ #define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ #define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */ #define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */ -/** - * @brief AF 11 selection - */ +/** + * @brief AF 11 selection + */ #define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ -/** - * @brief AF 12 selection - */ +/** + * @brief AF 12 selection + */ #define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ #define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ #define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ -/** - * @brief AF 13 selection - */ +/** + * @brief AF 13 selection + */ #define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ -/** - * @brief AF 15 selection - */ +/** + * @brief AF 15 selection + */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ #endif /* STM32F446xx */ @@ -1102,46 +1102,46 @@ /*-------------------------------- STM32F469xx/STM32F479xx--------------------*/ #if defined(STM32F469xx) || defined(STM32F479xx) -/** - * @brief AF 0 selection - */ +/** + * @brief AF 0 selection + */ #define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF0_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ -/** - * @brief AF 1 selection - */ +/** + * @brief AF 1 selection + */ #define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ #define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -/** - * @brief AF 2 selection - */ +/** + * @brief AF 2 selection + */ #define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ #define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ #define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ -/** - * @brief AF 3 selection - */ +/** + * @brief AF 3 selection + */ #define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ #define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ #define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ #define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ -/** - * @brief AF 4 selection - */ +/** + * @brief AF 4 selection + */ #define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ #define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -/** - * @brief AF 5 selection - */ +/** + * @brief AF 5 selection + */ #define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */ @@ -1150,33 +1150,33 @@ #define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ #define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ -/** - * @brief AF 6 selection - */ +/** + * @brief AF 6 selection + */ #define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF6_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping */ #define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ -/** - * @brief AF 7 selection - */ +/** + * @brief AF 7 selection + */ #define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ #define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ #define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ #define GPIO_AF7_I2S3ext ((uint8_t)0x07) /* I2S3ext_SD Alternate Function mapping */ -/** - * @brief AF 8 selection - */ +/** + * @brief AF 8 selection + */ #define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ #define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ #define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ #define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ #define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ -/** - * @brief AF 9 selection - */ +/** + * @brief AF 9 selection + */ #define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ #define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ #define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ @@ -1185,46 +1185,46 @@ #define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */ #define GPIO_AF9_QSPI ((uint8_t)0x09) /* QSPI Alternate Function mapping */ -/** - * @brief AF 10 selection - */ +/** + * @brief AF 10 selection + */ #define GPIO_AF10_OTG_FS ((uint8_t)0x0A) /* OTG_FS Alternate Function mapping */ #define GPIO_AF10_OTG_HS ((uint8_t)0x0A) /* OTG_HS Alternate Function mapping */ #define GPIO_AF10_QSPI ((uint8_t)0x0A) /* QSPI Alternate Function mapping */ -/** - * @brief AF 11 selection - */ +/** + * @brief AF 11 selection + */ #define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ -/** - * @brief AF 12 selection - */ +/** + * @brief AF 12 selection + */ #define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ #define GPIO_AF12_OTG_HS_FS ((uint8_t)0x0C) /* OTG HS configured in FS, Alternate Function mapping */ #define GPIO_AF12_SDIO ((uint8_t)0x0C) /* SDIO Alternate Function mapping */ -/** - * @brief AF 13 selection - */ +/** + * @brief AF 13 selection + */ #define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ #define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */ -/** - * @brief AF 14 selection +/** + * @brief AF 14 selection */ #define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */ -/** - * @brief AF 15 selection - */ +/** + * @brief AF 15 selection + */ #define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ #endif /* STM32F469xx || STM32F479xx */ /*----------------------------------------------------------------------------*/ /** * @} - */ + */ /** * @} @@ -1288,13 +1288,13 @@ ((__GPIOx__) == (GPIOJ))? 9U : 10U) #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) #define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ ((__GPIOx__) == (GPIOB))? 1U :\ ((__GPIOx__) == (GPIOC))? 2U : 7U) #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ -#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) #define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ ((__GPIOx__) == (GPIOB))? 1U :\ ((__GPIOx__) == (GPIOC))? 2U :\ @@ -1302,7 +1302,7 @@ ((__GPIOx__) == (GPIOE))? 4U : 7U) #endif /* STM32F401xC || STM32F401xE || STM32F411xE */ -#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) +#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) #define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ ((__GPIOx__) == (GPIOB))? 1U :\ ((__GPIOx__) == (GPIOC))? 2U :\ @@ -1336,7 +1336,7 @@ /** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function * @{ - */ + */ /*------------------------- STM32F429xx/STM32F439xx---------------------------*/ #if defined(STM32F429xx) || defined(STM32F439xx) #define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ @@ -1459,12 +1459,12 @@ #endif /* STM32F401xC || STM32F401xE */ /*----------------------------------------------------------------------------*/ /*---------------------------------------- STM32F410xx------------------------*/ -#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) #define IS_GPIO_AF(AF) (((AF) < 10U) || ((AF) == 15U)) #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ /*---------------------------------------- STM32F411xx------------------------*/ -#if defined(STM32F411xE) +#if defined(STM32F411xE) #define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ @@ -1485,7 +1485,7 @@ /*----------------------------------------------------------------------------*/ /*----------------------------------------------- STM32F446xx ----------------*/ -#if defined(STM32F446xx) +#if defined(STM32F446xx) #define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ @@ -1517,7 +1517,7 @@ /*----------------------------------------------------------------------------*/ /*------------------------------------------- STM32F469xx/STM32F479xx --------*/ -#if defined(STM32F469xx) || defined(STM32F479xx) +#if defined(STM32F469xx) || defined(STM32F479xx) #define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF9_TIM14) || \ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF0_TAMPER) || \ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ @@ -1546,20 +1546,20 @@ /*----------------------------------------------------------------------------*/ /*------------------STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-----------*/ -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) +#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) #define IS_GPIO_AF(AF) (((AF) < 16U) && ((AF) != 11U) && ((AF) != 14U) && ((AF) != 13U)) #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ /*----------------------------------------------------------------------------*/ /*------------------STM32F413xx/STM32F423xx-----------------------------------*/ -#if defined(STM32F413xx) || defined(STM32F423xx) +#if defined(STM32F413xx) || defined(STM32F423xx) #define IS_GPIO_AF(AF) (((AF) < 16U) && ((AF) != 13U)) #endif /* STM32F413xx || STM32F423xx */ /*----------------------------------------------------------------------------*/ /** * @} - */ + */ /** * @} @@ -1576,15 +1576,14 @@ /** * @} - */ + */ /** * @} - */ - + */ + #ifdef __cplusplus } #endif #endif /* __STM32F4xx_HAL_GPIO_EX_H */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h index 9a7a67ef..1d100266 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h @@ -738,4 +738,3 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #endif /* __STM32F4xx_HAL_I2C_H */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h index 31ad99c3..e43e7480 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h @@ -111,5 +111,3 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ #endif #endif /* __STM32F4xx_HAL_I2C_EX_H */ - - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h index a7273d5e..c391153b 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h @@ -13,7 +13,7 @@ * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_PWR_H @@ -32,14 +32,14 @@ /** @addtogroup PWR * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup PWR_Exported_Types PWR Exported Types * @{ */ - + /** * @brief PWR PVD configuration structure definition */ @@ -60,7 +60,7 @@ typedef struct /** @defgroup PWR_Exported_Constants PWR Exported Constants * @{ */ - + /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins * @{ */ @@ -71,7 +71,7 @@ typedef struct /** @defgroup PWR_PVD_detection_level PWR PVD detection level * @{ - */ + */ #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 @@ -79,12 +79,12 @@ typedef struct #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 -#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage +#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage (Compare internally to VREFINT) */ /** * @} - */ - + */ + /** @defgroup PWR_PVD_Mode PWR PVD Mode * @{ */ @@ -108,7 +108,7 @@ typedef struct /** * @} */ - + /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry * @{ */ @@ -144,8 +144,8 @@ typedef struct /** * @} - */ - + */ + /* Exported macro ------------------------------------------------------------*/ /** @defgroup PWR_Exported_Macro PWR Exported Macro * @{ @@ -154,21 +154,21 @@ typedef struct /** @brief Check PWR flag is set or not. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event - * was received from the WKUP pin or from the RTC alarm (Alarm A + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event + * was received from the WKUP pin or from the RTC alarm (Alarm A * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. - * An additional wakeup event is detected if the WKUP pin is enabled - * (by setting the EWUP bit) when the WKUP pin level is already high. + * An additional wakeup event is detected if the WKUP pin is enabled + * (by setting the EWUP bit) when the WKUP pin level is already high. * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was - * resumed from StandBy mode. - * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled - * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode + * resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled + * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode * For this reason, this bit is equal to 0 after Standby or reset * until the PVDE bit is set. - * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset - * when the device wakes up from Standby mode or by a system reset - * or power reset. - * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage + * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset + * when the device wakes up from Standby mode or by a system reset + * or power reset. + * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage * scaling output selection is ready. * @retval The new state of __FLAG__ (TRUE or FALSE). */ @@ -247,7 +247,7 @@ typedef struct */ #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\ __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\ - }while(0U) + }while(0U) /** * @brief checks whether the specified PVD Exti interrupt flag is set or not. @@ -278,8 +278,8 @@ typedef struct /** @addtogroup PWR_Exported_Functions PWR Exported Functions * @{ */ - -/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ /* Initialization and de-initialization functions *****************************/ @@ -290,7 +290,7 @@ void HAL_PWR_DisableBkUpAccess(void); * @} */ -/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions * @{ */ /* Peripheral Control functions **********************************************/ @@ -422,12 +422,12 @@ void HAL_PWR_DisableSEVOnPend(void); /** * @} - */ + */ /** * @} */ - + #ifdef __cplusplus } #endif diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h index 57fd4d93..68d49b50 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h @@ -13,7 +13,7 @@ * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_PWR_EX_H @@ -32,16 +32,16 @@ /** @addtogroup PWREx * @{ - */ + */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup PWREx_Exported_Constants PWREx Exported Constants * @{ */ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - + /** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode * @{ */ @@ -49,8 +49,8 @@ #define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS)) /** * @} - */ - + */ + /** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag * @{ */ @@ -65,7 +65,7 @@ /** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale * @{ */ -#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) +#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */ #define PWR_REGULATOR_VOLTAGE_SCALE2 0x00000000U /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */ #else @@ -74,7 +74,7 @@ #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to 168 MHz by activating the over-drive mode. */ #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS_0 /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */ -#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ +#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ /** * @} */ @@ -85,20 +85,20 @@ */ #define PWR_WAKEUP_PIN2 0x00000080U #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ - defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) + defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) #define PWR_WAKEUP_PIN3 0x00000040U #endif /* STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Zx || STM32F412Vx || \ STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ /** * @} - */ + */ #endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ /** * @} - */ - + */ + /* Exported macro ------------------------------------------------------------*/ /** @defgroup PWREx_Exported_Constants PWREx Exported Constants * @{ @@ -139,7 +139,7 @@ tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \ UNUSED(tmpreg); \ } while(0U) -#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ +#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) @@ -150,19 +150,19 @@ #define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE) /** @brief Macros to enable or disable the Over drive switching. - * @note These macros can be used only for STM32F42xx/STM3243xx devices. + * @note These macros can be used only for STM32F42xx/STM3243xx devices. */ #define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE) #define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE) /** @brief Macros to enable or disable the Under drive mode. * @note This mode is enabled only with STOP low power mode. - * In this mode, the 1.2V domain is preserved in reduced leakage mode. This - * mode is only available when the main regulator or the low power regulator - * is in low voltage mode. - * @note If the Under-drive mode was enabled, it is automatically disabled after - * exiting Stop mode. - * When the voltage regulator operates in Under-drive mode, an additional + * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + * mode is only available when the main regulator or the low power regulator + * is in low voltage mode. + * @note If the Under-drive mode was enabled, it is automatically disabled after + * exiting Stop mode. + * When the voltage regulator operates in Under-drive mode, an additional * startup delay is induced when waking up from Stop mode. */ #define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN) @@ -173,9 +173,9 @@ * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode - * is ready + * is ready * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode - * switching is ready + * switching is ready * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode * is enabled in Stop mode * @retval The new state of __FLAG__ (TRUE or FALSE). @@ -196,14 +196,14 @@ /** @addtogroup PWREx_Exported_Functions PWREx Exported Functions * @{ */ - + /** @addtogroup PWREx_Exported_Functions_Group1 * @{ */ void HAL_PWREx_EnableFlashPowerDown(void); -void HAL_PWREx_DisableFlashPowerDown(void); +void HAL_PWREx_DisableFlashPowerDown(void); HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void); -HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); uint32_t HAL_PWREx_GetVoltageRange(void); HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); @@ -254,7 +254,7 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t /* Alias word address of ODSWEN bit */ #define ODSWEN_BIT_NUMBER PWR_CR_ODSWEN_Pos #define CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U)) - + /* Alias word address of MRLVDS bit */ #define MRLVDS_BIT_NUMBER PWR_CR_MRLVDS_Pos #define CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U)) @@ -269,7 +269,7 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t /** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address * @{ - */ + */ /* --- CSR Register ---*/ /* Alias word address of BRE bit */ #define BRE_BIT_NUMBER PWR_CSR_BRE_Pos @@ -304,7 +304,7 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t #define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) -#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ +#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ #if defined(STM32F446xx) #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2)) @@ -326,12 +326,12 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t /** * @} - */ + */ /** * @} */ - + #ifdef __cplusplus } #endif diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h index 2e3909ad..15aa0640 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h @@ -1455,4 +1455,3 @@ void HAL_RCC_CSSCallback(void); #endif #endif /* __STM32F4xx_HAL_RCC_H */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h index 3b621340..0ba93afd 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h @@ -5889,7 +5889,7 @@ typedef struct #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || - STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || + STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ #if defined(STM32F446xx) /** @brief Macro to configure the PLLI2S clock multiplication and division factors . @@ -7187,4 +7187,3 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); #endif #endif /* __STM32F4xx_HAL_RCC_EX_H */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h index 84d1b515..e56ff8a3 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h @@ -730,4 +730,3 @@ uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); #endif #endif /* STM32F4xx_HAL_SPI_H */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h index e6ce82fc..64e978bd 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h @@ -906,4 +906,3 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa #endif #endif /* __STM32F4xx_HAL_UART_H */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h index ce19d4d9..15c86288 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h @@ -2102,4 +2102,3 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs) #endif #endif /* __STM32F4xx_LL_BUS_H */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h index 9a183ea7..21a643cd 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h @@ -644,4 +644,3 @@ __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) #endif #endif /* __STM32F4xx_LL_CORTEX_H */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h index 055ba5f2..4a5e3750 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h @@ -139,10 +139,10 @@ typedef struct This parameter can be a value of @ref DMA_LL_EC_PRIORITY This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */ - + uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. This parameter can be a value of @ref DMA_LL_FIFOMODE - @note The Direct mode (FIFO mode disabled) cannot be used if the + @note The Direct mode (FIFO mode disabled) cannot be used if the memory-to-memory data transfer is configured on the selected stream This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */ @@ -152,19 +152,19 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */ - uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. + uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. It specifies the amount of data to be transferred in a single non interruptible transaction. - This parameter can be a value of @ref DMA_LL_EC_MBURST - @note The burst mode is possible only if the address Increment mode is enabled. + This parameter can be a value of @ref DMA_LL_EC_MBURST + @note The burst mode is possible only if the address Increment mode is enabled. This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */ - uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. - It specifies the amount of data to be transferred in a single non interruptible - transaction. + uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. This parameter can be a value of @ref DMA_LL_EC_PBURST - @note The burst mode is possible only if the address Increment mode is enabled. + @note The burst mode is possible only if the address Increment mode is enabled. This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */ @@ -327,7 +327,7 @@ typedef struct /** * @} */ - + /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE * @{ */ @@ -335,7 +335,7 @@ typedef struct #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ /** * @} - */ + */ /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 * @{ @@ -360,7 +360,7 @@ typedef struct /** * @} */ - + /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM * @{ */ @@ -1149,7 +1149,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t S /** * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. - * @rmtoll CR CT LL_DMA_SetCurrentTargetMem + * @rmtoll CR CT LL_DMA_SetCurrentTargetMem * @param DMAx DMAx Instance * @param Stream This parameter can be one of the following values: * @arg @ref LL_DMA_STREAM_0 @@ -1172,7 +1172,7 @@ __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stre /** * @brief Get Current target (only in double buffer mode). - * @rmtoll CR CT LL_DMA_GetCurrentTargetMem + * @rmtoll CR CT LL_DMA_GetCurrentTargetMem * @param DMAx DMAx Instance * @param Stream This parameter can be one of the following values: * @arg @ref LL_DMA_STREAM_0 @@ -1214,7 +1214,7 @@ __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t S /** * @brief Disable the double buffer mode. - * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode + * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode * @param DMAx DMAx Instance * @param Stream This parameter can be one of the following values: * @arg @ref LL_DMA_STREAM_0 @@ -1280,7 +1280,7 @@ __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) /** * @brief Enable Fifo mode. - * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode + * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode * @param DMAx DMAx Instance * @param Stream This parameter can be one of the following values: * @arg @ref LL_DMA_STREAM_0 @@ -1379,7 +1379,7 @@ __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint3 /** * @brief Configure the Source and Destination addresses. * @note This API must not be called when the DMA stream is enabled. - * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n + * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n * PAR PA LL_DMA_ConfigAddresses * @param DMAx DMAx Instance * @param Stream This parameter can be one of the following values: @@ -1726,7 +1726,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7)); -} +} /** * @brief Get Stream 0 transfer complete flag. @@ -1814,7 +1814,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7)); -} +} /** * @brief Get Stream 0 transfer error flag. @@ -1902,7 +1902,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) { return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7)); -} +} /** * @brief Get Stream 0 direct mode error flag. @@ -2865,4 +2865,3 @@ void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); #endif #endif /* __STM32F4xx_LL_DMA_H */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h index 65ab6918..e90e6d10 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h @@ -951,4 +951,3 @@ void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); #endif #endif /* __STM32F4xx_LL_EXTI_H */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h index 6bee7fd1..84f6db30 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h @@ -978,4 +978,3 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); #endif #endif /* __STM32F4xx_LL_GPIO_H */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h index 92d4a74a..f6f9719d 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_i2c.h @@ -1887,4 +1887,3 @@ void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); #endif #endif /* __STM32F4xx_LL_I2C_H */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h index ea23dc52..ae415e9e 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h @@ -268,12 +268,12 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHMemorySTOP(void) * @brief Enable Under Drive Mode * @rmtoll CR UDEN LL_PWR_EnableUnderDriveMode * @note This mode is enabled only with STOP low power mode. - * In this mode, the 1.2V domain is preserved in reduced leakage mode. This - * mode is only available when the main Regulator or the low power Regulator - * is in low voltage mode. - * @note If the Under-drive mode was enabled, it is automatically disabled after - * exiting Stop mode. - * When the voltage Regulator operates in Under-drive mode, an additional + * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + * mode is only available when the main Regulator or the low power Regulator + * is in low voltage mode. + * @note If the Under-drive mode was enabled, it is automatically disabled after + * exiting Stop mode. + * When the voltage Regulator operates in Under-drive mode, an additional * startup delay is induced when waking up from Stop mode. * @retval None */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h index 0a6a5b92..42259fcd 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h @@ -7098,4 +7098,3 @@ uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); #endif #endif /* __STM32F4xx_LL_RCC_H */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_spi.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_spi.h index 164cbb94..b2bdff21 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_spi.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_spi.h @@ -2039,4 +2039,3 @@ ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_ #endif #endif /* STM32F4xx_LL_SPI_H */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h index 84ea5c4d..0f67e3e6 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h @@ -117,7 +117,7 @@ extern "C" { #endif /* SYSCFG_MEMRMP_UFB_MODE */ /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS * @{ - */ + */ #if defined(SYSCFG_CFGR_FMPI2C1_SCL) #define LL_SYSCFG_I2C_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL /*!< Enable Fast Mode Plus on FMPI2C_SCL pin */ #define LL_SYSCFG_I2C_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA /*!< Enable Fast Mode Plus on FMPI2C_SDA pin*/ @@ -181,9 +181,9 @@ extern "C" { * @{ */ #if defined(SYSCFG_CFGR2_LOCKUP_LOCK) -#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP output of CortexM4 +#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8 */ -#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIM1/8 Break Input +#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIM1/8 Break Input and also the PVDE and PLS bits of the Power Control Interface */ #endif /* SYSCFG_CFGR2_CLL */ /** @@ -201,7 +201,7 @@ extern "C" { */ /** @defgroup SYSTEM_LL_DFSDM_MCHDLYEN SYSCFG MCHDLY MCHDLYEN * @{ - */ + */ #define LL_SYSCFG_DFSDM1_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY1EN #define LL_SYSCFG_DFSDM2_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY2EN /** @@ -222,7 +222,7 @@ extern "C" { */ /** @defgroup SYSTEM_LL_DFSDM_DataIn2_Source SYSCFG MCHDLY DFSDMD2SEL * @{ - */ + */ #define LL_SYSCFG_DFSDM1_DataIn2 SYSCFG_MCHDLYCR_DFSDM1D2SEL #define LL_SYSCFG_DFSDM2_DataIn2 SYSCFG_MCHDLYCR_DFSDM2D2SEL @@ -235,7 +235,7 @@ extern "C" { */ /** @defgroup SYSTEM_LL_DFSDM1_TIM4OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK02SEL * @{ - */ + */ #define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0 (uint32_t)0x00000000 #define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL /** @@ -243,7 +243,7 @@ extern "C" { */ /** @defgroup SYSTEM_LL_DFSDM1_TIM4OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM1CK13SEL * @{ - */ + */ #define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1 (uint32_t)0x00000000 #define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL /** @@ -259,7 +259,7 @@ extern "C" { */ /** @defgroup SYSTEM_LL_DFSDM1_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM1CKOSEL * @{ - */ + */ #define LL_SYSCFG_DFSDM1_CKOUT (uint32_t)0x00000000 #define LL_SYSCFG_DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL /** @@ -268,7 +268,7 @@ extern "C" { /** @defgroup SYSTEM_LL_DFSDM2_DataIn4_SourceSelection SYSCFG MCHDLY DFSDM2D4SEL * @{ - */ + */ #define LL_SYSCFG_DFSDM2_DataIn4_PAD (uint32_t)0x00000000 #define LL_SYSCFG_DFSDM2_DataIn4_DM SYSCFG_MCHDLYCR_DFSDM2D4SEL /** @@ -276,7 +276,7 @@ extern "C" { */ /** @defgroup SYSTEM_LL_DFSDM2_DataIn6_SourceSelection SYSCFG MCHDLY DFSDM2D6SEL * @{ - */ + */ #define LL_SYSCFG_DFSDM2_DataIn6_PAD (uint32_t)0x00000000 #define LL_SYSCFG_DFSDM2_DataIn6_DM SYSCFG_MCHDLYCR_DFSDM2D6SEL /** @@ -284,7 +284,7 @@ extern "C" { */ /** @defgroup SYSTEM_LL_DFSDM2_TIM3OC4_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK04SEL * @{ - */ + */ #define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0 (uint32_t)0x00000000 #define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL /** @@ -292,7 +292,7 @@ extern "C" { */ /** @defgroup SYSTEM_LL_DFSDM2_TIM3OC3_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK15SEL * @{ - */ + */ #define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1 (uint32_t)0x00000000 #define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL /** @@ -300,7 +300,7 @@ extern "C" { */ /** @defgroup SYSTEM_LL_DFSDM2_TIM3OC2_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK26SEL * @{ - */ + */ #define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2 (uint32_t)0x00000000 #define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL /** @@ -308,7 +308,7 @@ extern "C" { */ /** @defgroup SYSTEM_LL_DFSDM2_TIM3OC1_BitstreamDistribution SYSCFG MCHDLY DFSDM2CK37SEL * @{ - */ + */ #define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3 (uint32_t)0x00000000 #define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7 SYSCFG_MCHDLYCR_DFSDM2CK37SEL /** @@ -316,7 +316,7 @@ extern "C" { */ /** @defgroup SYSTEM_LL_DFSDM2_CLKIN_SourceSelection SYSCFG MCHDLY DFSDM2CFG * @{ - */ + */ #define LL_SYSCFG_DFSDM2_CKIN_PAD (uint32_t)0x00000000 #define LL_SYSCFG_DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG /** @@ -324,13 +324,13 @@ extern "C" { */ /** @defgroup SYSTEM_LL_DFSDM2_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM2CKOSEL * @{ - */ + */ #define LL_SYSCFG_DFSDM2_CKOUT (uint32_t)0x00000000 #define LL_SYSCFG_DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL /** * @} - */ -#endif /* SYSCFG_MCHDLYCR_BSCKSEL */ + */ +#endif /* SYSCFG_MCHDLYCR_BSCKSEL */ /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment * @{ @@ -487,8 +487,8 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) /** * @brief Enables the FMC Memory Mapping Swapping * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_EnableFMCMemorySwapping - * @note SDRAM is accessible at 0x60000000 and NOR/RAM - * is accessible at 0xC0000000 + * @note SDRAM is accessible at 0x60000000 and NOR/RAM + * is accessible at 0xC0000000 * @retval None */ __STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void) @@ -499,7 +499,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void) /** * @brief Disables the FMC Memory Mapping Swapping * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_DisableFMCMemorySwapping - * @note SDRAM is accessible at 0xC0000000 (default mapping) + * @note SDRAM is accessible at 0xC0000000 (default mapping) * and NOR/RAM is accessible at 0x60000000 (default mapping) * @retval None */ @@ -545,7 +545,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void) #if defined(SYSCFG_PMC_MII_RMII_SEL) /** - * @brief Select Ethernet PHY interface + * @brief Select Ethernet PHY interface * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_SetPHYInterface * @param Interface This parameter can be one of the following values: * @arg @ref LL_SYSCFG_PMC_ETHMII @@ -558,7 +558,7 @@ __STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface) } /** - * @brief Get Ethernet PHY interface + * @brief Get Ethernet PHY interface * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_GetPHYInterface * @retval Returned value can be one of the following values: * @arg @ref LL_SYSCFG_PMC_ETHMII @@ -570,7 +570,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void) return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL)); } #endif /* SYSCFG_PMC_MII_RMII_SEL */ - + #if defined(SYSCFG_MEMRMP_UFB_MODE) @@ -583,7 +583,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void) * @retval None */ __STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank) -{ +{ MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE, Bank); } @@ -736,7 +736,7 @@ __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) * @arg @ref LL_SYSCFG_TIMBREAK_PVD */ __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) -{ +{ return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK)); } #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */ @@ -792,7 +792,7 @@ __STATIC_INLINE void LL_SYSCFG_DFSDM_DisableDelayClock(uint32_t MCHDLY) } /** - * @brief Select the source for DFSDM1 or DFSDM2 DatIn0 + * @brief Select the source for DFSDM1 or DFSDM2 DatIn0 * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL LL_SYSCFG_DFSDM_SetDataIn0Source * @param Source This parameter can be one of the following values: * @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD @@ -823,7 +823,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn0Source(uint32_t Source) return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source)); } /** - * @brief Select the source for DFSDM1 or DFSDM2 DatIn2 + * @brief Select the source for DFSDM1 or DFSDM2 DatIn2 * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL LL_SYSCFG_DFSDM_SetDataIn2Source * @param Source This parameter can be one of the following values: * @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD @@ -855,7 +855,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn2Source(uint32_t Source) } /** - * @brief Select the distribution of the bitsream lock gated by TIM4 OC2 + * @brief Select the distribution of the bitsream lock gated by TIM4 OC2 * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK02SEL LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution * @param Source This parameter can be one of the following values: * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0 @@ -867,7 +867,7 @@ __STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution(uint32_t S MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL, Source); } /** - * @brief Get the distribution of the bitsream lock gated by TIM4 OC2 + * @brief Get the distribution of the bitsream lock gated by TIM4 OC2 * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution * @retval Returned value can be one of the following values: * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0 @@ -880,7 +880,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution(void) } /** - * @brief Select the distribution of the bitsream lock gated by TIM4 OC1 + * @brief Select the distribution of the bitsream lock gated by TIM4 OC1 * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK13SEL LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution * @param Source This parameter can be one of the following values: * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1 @@ -892,7 +892,7 @@ __STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution(uint32_t S MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL, Source); } /** - * @brief Get the distribution of the bitsream lock gated by TIM4 OC1 + * @brief Get the distribution of the bitsream lock gated by TIM4 OC1 * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution * @retval Returned value can be one of the following values: * @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1 @@ -905,7 +905,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution(void) } /** - * @brief Select the DFSDM1 Clock In + * @brief Select the DFSDM1 Clock In * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG LL_SYSCFG_DFSDM1_SetClockInSourceSelection * @param ClockSource This parameter can be one of the following values: * @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD @@ -930,7 +930,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockInSourceSelection(void) } /** - * @brief Select the DFSDM1 Clock Out + * @brief Select the DFSDM1 Clock Out * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL LL_SYSCFG_DFSDM1_SetClockOutSourceSelection * @param ClockSource This parameter can be one of the following values: * @arg @ref LL_SYSCFG_DFSDM1_CKOUT @@ -974,7 +974,7 @@ __STATIC_INLINE void LL_SYSCFG_DFSDM2_DisableDelayClock(void) CLEAR_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN); } /** - * @brief Select the source for DFSDM2 DatIn0 + * @brief Select the source for DFSDM2 DatIn0 * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL LL_SYSCFG_DFSDM2_SetDataIn0Source * @param Source This parameter can be one of the following values: * @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD @@ -999,7 +999,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn0Source(void) } /** - * @brief Select the source for DFSDM2 DatIn2 + * @brief Select the source for DFSDM2 DatIn2 * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL LL_SYSCFG_DFSDM2_SetDataIn2Source * @param Source This parameter can be one of the following values: * @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD @@ -1024,7 +1024,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn2Source(void) } /** - * @brief Select the source for DFSDM2 DatIn4 + * @brief Select the source for DFSDM2 DatIn4 * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL LL_SYSCFG_DFSDM2_SetDataIn4Source * @param Source This parameter can be one of the following values: * @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD @@ -1049,7 +1049,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn4Source(void) } /** - * @brief Select the source for DFSDM2 DatIn6 + * @brief Select the source for DFSDM2 DatIn6 * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL LL_SYSCFG_DFSDM2_SetDataIn6Source * @param Source This parameter can be one of the following values: * @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD @@ -1074,7 +1074,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn6Source(void) } /** - * @brief Select the distribution of the bitsream lock gated by TIM3 OC4 + * @brief Select the distribution of the bitsream lock gated by TIM3 OC4 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution * @param Source This parameter can be one of the following values: * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0 @@ -1086,7 +1086,7 @@ __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution(uint32_t S MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL, Source); } /** - * @brief Get the distribution of the bitsream lock gated by TIM3 OC4 + * @brief Get the distribution of the bitsream lock gated by TIM3 OC4 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution * @retval Returned value can be one of the following values: * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0 @@ -1099,7 +1099,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution(void) } /** - * @brief Select the distribution of the bitsream lock gated by TIM3 OC3 + * @brief Select the distribution of the bitsream lock gated by TIM3 OC3 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK15SEL LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution * @param Source This parameter can be one of the following values: * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1 @@ -1111,7 +1111,7 @@ __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution(uint32_t S MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL, Source); } /** - * @brief Get the distribution of the bitsream lock gated by TIM3 OC4 + * @brief Get the distribution of the bitsream lock gated by TIM3 OC4 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution * @retval Returned value can be one of the following values: * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1 @@ -1124,7 +1124,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution(void) } /** - * @brief Select the distribution of the bitsream lock gated by TIM3 OC2 + * @brief Select the distribution of the bitsream lock gated by TIM3 OC2 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK26SEL LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution * @param Source This parameter can be one of the following values: * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2 @@ -1136,7 +1136,7 @@ __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution(uint32_t S MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL, Source); } /** - * @brief Get the distribution of the bitsream lock gated by TIM3 OC2 + * @brief Get the distribution of the bitsream lock gated by TIM3 OC2 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution * @retval Returned value can be one of the following values: * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2 @@ -1149,7 +1149,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution(void) } /** - * @brief Select the distribution of the bitsream lock gated by TIM3 OC1 + * @brief Select the distribution of the bitsream lock gated by TIM3 OC1 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution * @param Source This parameter can be one of the following values: * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3 @@ -1161,7 +1161,7 @@ __STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution(uint32_t S MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL, Source); } /** - * @brief Get the distribution of the bitsream lock gated by TIM3 OC1 + * @brief Get the distribution of the bitsream lock gated by TIM3 OC1 * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution * @retval Returned value can be one of the following values: * @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3 @@ -1174,7 +1174,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution(void) } /** - * @brief Select the DFSDM2 Clock In + * @brief Select the DFSDM2 Clock In * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG LL_SYSCFG_DFSDM2_SetClockInSourceSelection * @param ClockSource This parameter can be one of the following values: * @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD @@ -1199,7 +1199,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockInSourceSelection(void) } /** - * @brief Select the DFSDM2 Clock Out + * @brief Select the DFSDM2 Clock Out * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL LL_SYSCFG_DFSDM2_SetClockOutSourceSelection * @param ClockSource This parameter can be one of the following values: * @arg @ref LL_SYSCFG_DFSDM2_CKOUT @@ -1389,7 +1389,7 @@ __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*) @@ -1406,7 +1406,7 @@ __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*) - * + * * (*) value not defined in all devices. * @retval None */ @@ -1441,7 +1441,7 @@ __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*) @@ -1458,7 +1458,7 @@ __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*) - * + * * (*) value not defined in all devices. * @retval None */ @@ -1707,5 +1707,3 @@ __STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void) #endif #endif /* __STM32F4xx_LL_SYSTEM_H */ - - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h index ed83b6c6..68fb927a 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h @@ -2518,4 +2518,3 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitS #endif #endif /* __STM32F4xx_LL_USART_H */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h index accdac7b..0393ef90 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h +++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h @@ -233,7 +233,7 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void) * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 (*) * @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 (*) * @arg @ref LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 (*) - * + * * (*) value not defined in all devices. */ __STATIC_INLINE uint32_t LL_GetPackageType(void) diff --git a/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt b/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt index 3edc4d14..1cbbc544 100644 --- a/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt +++ b/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt @@ -1,6 +1,6 @@ This software component is provided to you as part of a software package and applicable license terms are in the Package_license file. If you received this software component outside of a package or without applicable license terms, -the terms of the BSD-3-Clause license shall apply. +the terms of the BSD-3-Clause license shall apply. You may obtain a copy of the BSD-3-Clause at: https://opensource.org/licenses/BSD-3-Clause diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c index 862ec732..556b4b89 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c @@ -22,15 +22,15 @@ ============================================================================== [..] The common HAL driver contains a set of generic and common APIs that can be - used by the PPP peripheral drivers and the user to start using the HAL. + used by the PPP peripheral drivers and the user to start using the HAL. [..] - The HAL contains two APIs' categories: + The HAL contains two APIs' categories: (+) Common HAL APIs (+) Services HAL APIs @endverbatim ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" @@ -55,31 +55,31 @@ #define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32F4xx_HAL_VERSION_SUB1 (0x08U) /*!< [23:16] sub1 version */ #define __STM32F4xx_HAL_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */ -#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\ |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\ |(__STM32F4xx_HAL_VERSION_SUB2 << 8U )\ |(__STM32F4xx_HAL_VERSION_RC)) - + #define IDCODE_DEVID_MASK 0x00000FFFU /* ------------ RCC registers bit address in the alias region ----------- */ #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) -/* --- MEMRMP Register ---*/ -/* Alias word address of UFB_MODE bit */ -#define MEMRMP_OFFSET SYSCFG_OFFSET +/* --- MEMRMP Register ---*/ +/* Alias word address of UFB_MODE bit */ +#define MEMRMP_OFFSET SYSCFG_OFFSET #define UFB_MODE_BIT_NUMBER SYSCFG_MEMRMP_UFB_MODE_Pos -#define UFB_MODE_BB (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U)) +#define UFB_MODE_BB (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U)) -/* --- CMPCR Register ---*/ -/* Alias word address of CMP_PD bit */ -#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20U) +/* --- CMPCR Register ---*/ +/* Alias word address of CMP_PD bit */ +#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20U) #define CMP_PD_BIT_NUMBER SYSCFG_CMPCR_CMP_PD_Pos #define CMPCR_CMP_PD_BB (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U)) -/* --- MCHDLYCR Register ---*/ -/* Alias word address of BSCKSEL bit */ -#define MCHDLYCR_OFFSET (SYSCFG_OFFSET + 0x30U) +/* --- MCHDLYCR Register ---*/ +/* Alias word address of BSCKSEL bit */ +#define MCHDLYCR_OFFSET (SYSCFG_OFFSET + 0x30U) #define BSCKSEL_BIT_NUMBER SYSCFG_MCHDLYCR_BSCKSEL_Pos #define MCHDLYCR_BSCKSEL_BB (uint32_t)(PERIPH_BB_BASE + (MCHDLYCR_OFFSET * 32U) + (BSCKSEL_BIT_NUMBER * 4U)) /** @@ -104,41 +104,41 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ * @{ */ -/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions * @brief Initialization and de-initialization functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Initializes the Flash interface the NVIC allocation and initial clock - configuration. It initializes the systick also when timeout is needed + (+) Initializes the Flash interface the NVIC allocation and initial clock + configuration. It initializes the systick also when timeout is needed and the backup domain when enabled. (+) De-Initializes common part of the HAL. - (+) Configure the time base source to have 1ms time base with a dedicated - Tick interrupt priority. + (+) Configure the time base source to have 1ms time base with a dedicated + Tick interrupt priority. (++) SysTick timer is used by default as source of time base, but user - can eventually implement his proper time base source (a general purpose - timer for example or other time source), keeping in mind that Time base - duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and handled in milliseconds basis. - (++) Time base configuration function (HAL_InitTick ()) is called automatically - at the beginning of the program after reset by HAL_Init() or at any time - when clock is configured, by HAL_RCC_ClockConfig(). - (++) Source of time base is configured to generate interrupts at regular - time intervals. Care must be taken if HAL_Delay() is called from a - peripheral ISR process, the Tick interrupt line must have higher priority - (numerically lower) than the peripheral interrupt. Otherwise the caller - ISR process will be blocked. - (++) functions affecting time base configurations are declared as __weak + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak to make override possible in case of other implementations in user file. @endverbatim * @{ */ /** - * @brief This function is used to initialize the HAL Library; it must be the first + * @brief This function is used to initialize the HAL Library; it must be the first * instruction to be executed in the main program (before to call any other * HAL function), it performs the following: * Configure the Flash prefetch, instruction and Data caches. @@ -146,9 +146,9 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ * which is clocked by the HSI (at this stage, the clock is not yet * configured and thus the system is running from the internal HSI at 16 MHz). * Set NVIC Group Priority to 4. - * Calls the HAL_MspInit() callback function defined in user file - * "stm32f4xx_hal_msp.c" to do the global low level hardware initialization - * + * Calls the HAL_MspInit() callback function defined in user file + * "stm32f4xx_hal_msp.c" to do the global low level hardware initialization + * * @note SysTick is used as time base for the HAL_Delay() function, the application * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. @@ -156,7 +156,7 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ */ HAL_StatusTypeDef HAL_Init(void) { - /* Configure Flash prefetch, Instruction cache, Data cache */ + /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); #endif /* INSTRUCTION_CACHE_ENABLE */ @@ -184,7 +184,7 @@ HAL_StatusTypeDef HAL_Init(void) /** * @brief This function de-Initializes common part of the HAL and stops the systick. - * This function is optional. + * This function is optional. * @retval HAL status */ HAL_StatusTypeDef HAL_DeInit(void) @@ -207,7 +207,7 @@ HAL_StatusTypeDef HAL_DeInit(void) /* De-Init the low level hardware */ HAL_MspDeInit(); - + /* Return function status */ return HAL_OK; } @@ -231,18 +231,18 @@ __weak void HAL_MspDeInit(void) { /* NOTE : This function should not be modified, when the callback is needed, the HAL_MspDeInit could be implemented in the user file - */ + */ } /** * @brief This function configures the source of the time base. - * The time source is configured to have 1ms time base with a dedicated + * The time source is configured to have 1ms time base with a dedicated * Tick interrupt priority. * @note This function is called automatically at the beginning of program after * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). - * @note In the default implementation, SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals. - * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, * The SysTick interrupt must have higher priority (numerically lower) * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * The function is declared as __weak to be overwritten in case of other @@ -277,7 +277,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) * @} */ -/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions * @brief HAL Control functions * @verbatim @@ -305,7 +305,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) * used as application time base. * @note In the default implementation, this variable is incremented each 1ms * in SysTick ISR. - * @note This function is declared as __weak to be overwritten in case of other + * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ @@ -316,7 +316,7 @@ __weak void HAL_IncTick(void) /** * @brief Provides a tick value in millisecond. - * @note This function is declared as __weak to be overwritten in case of other + * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ @@ -377,7 +377,7 @@ HAL_TickFreqTypeDef HAL_GetTickFreq(void) } /** - * @brief This function provides minimum delay (in milliseconds) based + * @brief This function provides minimum delay (in milliseconds) based * on variable incremented. * @note In the default implementation , SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals where uwTick @@ -407,7 +407,7 @@ __weak void HAL_Delay(uint32_t Delay) * @brief Suspend Tick increment. * @note In the default implementation , SysTick timer is the source of time base. It is * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() - * is called, the SysTick interrupt will be disabled and so Tick increment + * is called, the SysTick interrupt will be disabled and so Tick increment * is suspended. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. @@ -423,7 +423,7 @@ __weak void HAL_SuspendTick(void) * @brief Resume Tick increment. * @note In the default implementation , SysTick timer is the source of time base. It is * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() - * is called, the SysTick interrupt will be enabled and so Tick increment + * is called, the SysTick interrupt will be enabled and so Tick increment * is resumed. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. @@ -519,7 +519,7 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void) /** * @brief Enables the I/O Compensation Cell. * @note The I/O compensation cell can be used only when the device supply - * voltage ranges from 2.4 to 3.6 V. + * voltage ranges from 2.4 to 3.6 V. * @retval None */ void HAL_EnableCompensationCell(void) @@ -530,7 +530,7 @@ void HAL_EnableCompensationCell(void) /** * @brief Power-down the I/O Compensation Cell. * @note The I/O compensation cell can be used only when the device supply - * voltage ranges from 2.4 to 3.6 V. + * voltage ranges from 2.4 to 3.6 V. * @retval None */ void HAL_DisableCompensationCell(void) @@ -569,11 +569,11 @@ uint32_t HAL_GetUIDw2(void) defined(STM32F469xx) || defined(STM32F479xx) /** * @brief Enables the Internal FLASH Bank Swapping. - * - * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. * - * @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) - * and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000) + * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. + * + * @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) + * and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000) * * @retval None */ @@ -584,12 +584,12 @@ void HAL_EnableMemorySwappingBank(void) /** * @brief Disables the Internal FLASH Bank Swapping. - * - * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. * - * @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) - * and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) - * + * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. + * + * @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) + * and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) + * * @retval None */ void HAL_DisableMemorySwappingBank(void) @@ -612,5 +612,3 @@ void HAL_DisableMemorySwappingBank(void) /** * @} */ - - diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c index c3d2ba8e..50bf4986 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c @@ -3,43 +3,43 @@ * @file stm32f4xx_hal_cortex.c * @author MCD Application Team * @brief CORTEX HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the CORTEX: * + Initialization and de-initialization functions - * + Peripheral Control functions + * + Peripheral Control functions * - @verbatim + @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== - [..] + [..] *** How to configure Interrupts using CORTEX HAL driver *** =========================================================== - [..] + [..] This section provides functions allowing to configure the NVIC interrupts (IRQ). The Cortex-M4 exceptions are managed by CMSIS functions. - + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function according to the following table. - (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). - (#) please refer to programming manual for details in how to configure priority. - - -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. + (#) please refer to programming manual for details in how to configure priority. + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. The pending IRQ priority will be managed only by the sub priority. - + -@- IRQ priority order (sorted by highest to lowest priority): (+@) Lowest preemption priority (+@) Lowest sub priority (+@) Lowest hardware priority (IRQ number) - - [..] + + [..] *** How to configure Systick using CORTEX HAL driver *** ======================================================== [..] Setup SysTick Timer for time base. - + (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which is a CMSIS function that: (++) Configures the SysTick Reload register with value passed as function parameter. @@ -48,22 +48,22 @@ (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). (++) Enables the SysTick Interrupt. (++) Starts the SysTick Counter. - + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined inside the stm32f4xx_hal_cortex.h file. (+) You can change the SysTick IRQ priority by calling the - HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. (+) To adjust the SysTick time base, use the following formula: - + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function (++) Reload Value should not exceed 0xFFFFFF - + @endverbatim ****************************************************************************** * @attention @@ -104,15 +104,15 @@ /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== [..] This section provides the CORTEX HAL driver functions allowing to configure Interrupts - Systick functionalities + Systick functionalities @endverbatim * @{ @@ -122,7 +122,7 @@ /** * @brief Sets the priority grouping field (preemption priority and subpriority) * using the required unlock sequence. - * @param PriorityGroup The priority grouping bits length. + * @param PriorityGroup The priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority * 4 bits for subpriority @@ -134,15 +134,15 @@ * 1 bits for subpriority * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority * 0 bits for subpriority - * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); } @@ -154,29 +154,29 @@ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) * @param PreemptPriority The preemption priority for the IRQn channel. * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority + * A lower priority value indicates a higher priority * @param SubPriority the subpriority level for the IRQ channel. * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority. + * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) -{ +{ uint32_t prioritygroup = 0x00U; - + /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); - + prioritygroup = NVIC_GetPriorityGrouping(); - + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); } /** * @brief Enables a device specific interrupt in the NVIC interrupt controller. * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. + * function should be called before. * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) @@ -186,7 +186,7 @@ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - + /* Enable interrupt */ NVIC_EnableIRQ(IRQn); } @@ -202,7 +202,7 @@ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - + /* Disable interrupt */ NVIC_DisableIRQ(IRQn); } @@ -233,17 +233,17 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) */ /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions - * @brief Cortex control functions + * @brief Cortex control functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral Control functions ##### - ============================================================================== + ============================================================================== [..] This subsection provides a set of functions allowing to control the CORTEX - (NVIC, SYSTICK, MPU) functionalities. - - + (NVIC, SYSTICK, MPU) functionalities. + + @endverbatim * @{ */ @@ -260,15 +260,15 @@ void HAL_MPU_Disable(void) /* Disable fault exceptions */ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; - + /* Disable the MPU and clear the control register*/ MPU->CTRL = 0U; } /** * @brief Enable the MPU. - * @param MPU_Control Specifies the control mode of the MPU during hard fault, - * NMI, FAULTMASK and privileged access to the default memory + * @param MPU_Control Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory * This parameter can be one of the following values: * @arg MPU_HFNMI_PRIVDEF_NONE * @arg MPU_HARDFAULT_NMI @@ -280,10 +280,10 @@ void HAL_MPU_Enable(uint32_t MPU_Control) { /* Enable the MPU */ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; - + /* Enable fault exceptions */ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; - + /* Ensure MPU setting take effects */ __DSB(); __ISB(); @@ -421,13 +421,13 @@ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - + /* Set interrupt pending */ NVIC_SetPendingIRQ(IRQn); } /** - * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * @brief Gets Pending Interrupt (reads the pending register in the NVIC * and returns the pending bit for the specified interrupt). * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration @@ -439,7 +439,7 @@ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - + /* Return 1 if pending else 0 */ return NVIC_GetPendingIRQ(IRQn); } @@ -455,7 +455,7 @@ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - + /* Clear pending interrupt */ NVIC_ClearPendingIRQ(IRQn); } @@ -472,7 +472,7 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) { /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - + /* Return 1 if active else 0 */ return NVIC_GetActive(IRQn); } @@ -535,4 +535,3 @@ __weak void HAL_SYSTICK_Callback(void) /** * @} */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c index 3dbb4776..e4f97636 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c @@ -3,26 +3,26 @@ * @file stm32f4xx_hal_dma.c * @author MCD Application Team * @brief DMA HAL module driver. - * - * This file provides firmware functions to manage the following + * + * This file provides firmware functions to manage the following * functionalities of the Direct Memory Access (DMA) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and errors functions - @verbatim + @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] (#) Enable and configure the peripheral to be connected to the DMA Stream - (except for internal SRAM/FLASH memories: no initialization is + (except for internal SRAM/FLASH memories: no initialization is necessary) please refer to Reference manual for connection between peripherals and DMA requests. (#) For a given Stream, program the required configuration through the following parameters: - Transfer Direction, Source and Destination data formats, - Circular, Normal or peripheral flow control mode, Stream Priority level, - Source and Destination Increment mode, FIFO mode and its Threshold (if needed), + Transfer Direction, Source and Destination data formats, + Circular, Normal or peripheral flow control mode, Stream Priority level, + Source and Destination Increment mode, FIFO mode and its Threshold (if needed), Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function. -@- Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros: @@ -31,9 +31,9 @@ *** Polling mode IO operation *** ================================= [..] - (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source address and destination address and the Length of data to be transferred. - (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this case a fixed Timeout can be configured by User depending from his application. (+) Use HAL_DMA_Abort() function to abort the current transfer. @@ -41,16 +41,16 @@ =================================== [..] (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() - (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() - (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of - Source address and destination address and the Length of data to be transferred. In this - case the DMA interrupt is configured + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. In this + case the DMA interrupt is configured (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine - (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can - add his own function by customization of function pointer XferCpltCallback and + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and XferErrorCallback (i.e a member of DMA handle structure). [..] - (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error detection. (#) Use HAL_DMA_Abort_IT() function to abort the current transfer @@ -71,10 +71,10 @@ ============================================= [..] Below the list of most used macros in DMA HAL driver. - + (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream. (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream. - (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. [..] (@) You can refer to the DMA HAL driver header file for more useful macros @@ -91,7 +91,7 @@ * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" @@ -135,7 +135,7 @@ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); /** * @} - */ + */ /* Exported functions ---------------------------------------------------------*/ /** @addtogroup DMA_Exported_Functions @@ -150,7 +150,7 @@ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); =============================================================================== [..] This section provides functions allowing to initialize the DMA Stream source - and destination addresses, incrementation and data sizes, transfer direction, + and destination addresses, incrementation and data sizes, transfer direction, circular/normal mode selection, memory-to-memory mode selection and Stream priority value. [..] The HAL_DMA_Init() function follows the DMA configuration procedures as described in @@ -159,12 +159,12 @@ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); @endverbatim * @{ */ - + /** * @brief Initialize the DMA according to the specified * parameters in the DMA_InitTypeDef and create the associated handle. * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. + * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) @@ -204,10 +204,10 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /* Allocate lock resource */ __HAL_UNLOCK(hdma); - + /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); - + /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) { @@ -216,14 +216,14 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - + /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; - + return HAL_TIMEOUT; } } - + /* Get the CR register value */ tmp = hdma->Instance->CR; @@ -245,9 +245,9 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) /* Get memory burst and peripheral burst */ tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; } - + /* Write to DMA Stream CR register */ - hdma->Instance->CR = tmp; + hdma->Instance->CR = tmp; /* Get the FCR register value */ tmp = hdma->Instance->FCR; @@ -263,7 +263,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { /* Get the FIFO threshold */ tmp |= hdma->Init.FIFOThreshold; - + /* Check compatibility between FIFO threshold level and size of the memory burst */ /* for INCR4, INCR8, INCR16 bursts */ if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) @@ -272,28 +272,28 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; - + /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - - return HAL_ERROR; + + return HAL_ERROR; } } } - + /* Write to DMA Stream FCR */ hdma->Instance->FCR = tmp; /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); - + /* Clear all interrupt flags */ regs->IFCR = 0x3FU << hdma->StreamIndex; /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; - + /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; @@ -301,9 +301,9 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) } /** - * @brief DeInitializes the DMA peripheral + * @brief DeInitializes the DMA peripheral * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. + * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) @@ -315,7 +315,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { return HAL_ERROR; } - + /* Check the DMA peripheral state */ if(hdma->State == HAL_DMA_STATE_BUSY) { @@ -340,16 +340,16 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) /* Reset DMA Streamx memory 0 address register */ hdma->Instance->M0AR = 0U; - + /* Reset DMA Streamx memory 1 address register */ hdma->Instance->M1AR = 0U; - + /* Reset DMA Streamx FIFO control register */ hdma->Instance->FCR = 0x00000021U; - - /* Get DMA steam Base Address */ + + /* Get DMA steam Base Address */ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); - + /* Clean all callbacks */ hdma->XferCpltCallback = NULL; hdma->XferHalfCpltCallback = NULL; @@ -379,17 +379,17 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) /** @addtogroup DMA_Exported_Functions_Group2 * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure the source, destination address and data length and Start DMA transfer - (+) Configure the source, destination address and data length and + (+) Configure the source, destination address and data length and Start DMA transfer with interrupt (+) Abort DMA transfer (+) Poll for transfer complete - (+) Handle DMA interrupt request + (+) Handle DMA interrupt request @endverbatim * @{ @@ -407,7 +407,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); @@ -418,10 +418,10 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; - + /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; - + /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); @@ -432,17 +432,17 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui { /* Process unlocked */ __HAL_UNLOCK(hdma); - + /* Return error status */ status = HAL_BUSY; - } - return status; + } + return status; } /** * @brief Start the DMA Transfer with interrupt enabled. * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. + * the configuration information for the specified DMA Stream. * @param SrcAddress The source memory Buffer address * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination @@ -454,47 +454,47 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; - + /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - + /* Process locked */ __HAL_LOCK(hdma); - + if(HAL_DMA_STATE_READY == hdma->State) { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; - + /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; - + /* Configure the source, destination address and the data length */ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - + /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; - + /* Enable Common interrupts*/ hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; - + if(hdma->XferHalfCpltCallback != NULL) { hdma->Instance->CR |= DMA_IT_HT; } - + /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); } else { /* Process unlocked */ - __HAL_UNLOCK(hdma); - + __HAL_UNLOCK(hdma); + /* Return error status */ status = HAL_BUSY; } - + return status; } @@ -502,28 +502,28 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, * @brief Aborts the DMA Transfer. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * - * @note After disabling a DMA Stream, a check for wait until the DMA Stream is - * effectively disabled is added. If a Stream is disabled + * + * @note After disabling a DMA Stream, a check for wait until the DMA Stream is + * effectively disabled is added. If a Stream is disabled * while a data transfer is ongoing, the current data will be transferred * and the Stream will be effectively disabled only after the transfer of - * this single data is finished. + * this single data is finished. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { /* calculate DMA base and stream number */ DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; - + uint32_t tickstart = HAL_GetTick(); - + if(hdma->State != HAL_DMA_STATE_BUSY) { hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - + /* Process Unlocked */ __HAL_UNLOCK(hdma); - + return HAL_ERROR; } else @@ -531,15 +531,15 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); hdma->Instance->FCR &= ~(DMA_IT_FE); - + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) { hdma->Instance->CR &= ~(DMA_IT_HT); } - + /* Disable the stream */ __HAL_DMA_DISABLE(hdma); - + /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) { @@ -548,23 +548,23 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - + /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; - + /* Process Unlocked */ __HAL_UNLOCK(hdma); - + return HAL_TIMEOUT; } } - + /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; - + /* Change the DMA state*/ hdma->State = HAL_DMA_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hdma); } @@ -588,7 +588,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { /* Set Abort State */ hdma->State = HAL_DMA_STATE_ABORT; - + /* Disable the stream */ __HAL_DMA_DISABLE(hdma); } @@ -603,17 +603,17 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) * @param CompleteLevel Specifies the DMA level complete. * @note The polling mode is kept in this version for legacy. it is recommended to use the IT model instead. * This model could be used for debug purpose. - * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). + * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status = HAL_OK; uint32_t mask_cpltlevel; - uint32_t tickstart = HAL_GetTick(); + uint32_t tickstart = HAL_GetTick(); uint32_t tmpisr; - + /* calculate DMA base and stream number */ DMA_Base_Registers *regs; @@ -631,7 +631,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; return HAL_ERROR; } - + /* Get the level transfer complete flag */ if(CompleteLevel == HAL_DMA_FULL_TRANSFER) { @@ -643,10 +643,10 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level /* Half Transfer Complete flag */ mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; } - + regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; tmpisr = regs->ISR; - + while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET)) { /* Check for the Timeout (Not applicable in circular mode)*/ @@ -656,13 +656,13 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - + /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hdma); - + return HAL_TIMEOUT; } } @@ -674,39 +674,39 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level { /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; - + /* Clear the transfer error flag */ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; } - + if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) { /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; - + /* Clear the FIFO error flag */ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; } - + if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) { /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; - + /* Clear the Direct Mode error flag */ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; } } - + if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) { HAL_DMA_Abort(hdma); - + /* Clear the half transfer and transfer complete flags */ regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; - + /* Change the DMA state */ hdma->State= HAL_DMA_STATE_READY; @@ -716,15 +716,15 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level return HAL_ERROR; } } - + /* Get the level transfer complete flag */ if(CompleteLevel == HAL_DMA_FULL_TRANSFER) { /* Clear the half transfer and transfer complete flags */ regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; - + hdma->State = HAL_DMA_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hdma); } @@ -733,14 +733,14 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level /* Clear the half transfer and transfer complete flags */ regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex; } - + return status; } /** * @brief Handles DMA interrupt request. * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. + * the configuration information for the specified DMA Stream. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) @@ -761,10 +761,10 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { /* Disable the transfer error interrupt */ hdma->Instance->CR &= ~(DMA_IT_TE); - + /* Clear the transfer error flag */ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; - + /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; } @@ -800,7 +800,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { /* Clear the half transfer complete flag */ regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; - + /* Multi_Buffering mode enabled */ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) { @@ -831,7 +831,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Disable the half transfer interrupt */ hdma->Instance->CR &= ~(DMA_IT_HT); } - + if(hdma->XferHalfCpltCallback != NULL) { /* Half transfer callback */ @@ -847,13 +847,13 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { /* Clear the transfer complete flag */ regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; - + if(HAL_DMA_STATE_ABORT == hdma->State) { /* Disable all the transfer interrupts */ hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); hdma->Instance->FCR &= ~(DMA_IT_FE); - + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) { hdma->Instance->CR &= ~(DMA_IT_HT); @@ -919,7 +919,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } } } - + /* manage error case */ if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) { @@ -960,10 +960,10 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) * the configuration information for the specified DMA Stream. * @param CallbackID User Callback identifier * a DMA_HandleTypeDef structure as parameter. - * @param pCallback pointer to private callback function which has pointer to + * @param pCallback pointer to private callback function which has pointer to * a DMA_HandleTypeDef structure as parameter. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)) { @@ -1014,7 +1014,7 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call /* Release Lock */ __HAL_UNLOCK(hdma); - + return status; } @@ -1025,14 +1025,14 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call * @param CallbackID User Callback identifier * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; - + /* Process locked */ __HAL_LOCK(hdma); - + if(HAL_DMA_STATE_READY == hdma->State) { switch (CallbackID) @@ -1040,27 +1040,27 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca case HAL_DMA_XFER_CPLT_CB_ID: hdma->XferCpltCallback = NULL; break; - + case HAL_DMA_XFER_HALFCPLT_CB_ID: hdma->XferHalfCpltCallback = NULL; break; - + case HAL_DMA_XFER_M1CPLT_CB_ID: hdma->XferM1CpltCallback = NULL; break; - + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: hdma->XferM1HalfCpltCallback = NULL; break; - + case HAL_DMA_XFER_ERROR_CB_ID: hdma->XferErrorCallback = NULL; break; - + case HAL_DMA_XFER_ABORT_CB_ID: hdma->XferAbortCallback = NULL; - break; - + break; + case HAL_DMA_XFER_ALL_CB_ID: hdma->XferCpltCallback = NULL; hdma->XferHalfCpltCallback = NULL; @@ -1068,8 +1068,8 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca hdma->XferM1HalfCpltCallback = NULL; hdma->XferErrorCallback = NULL; hdma->XferAbortCallback = NULL; - break; - + break; + default: status = HAL_ERROR; break; @@ -1079,10 +1079,10 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca { status = HAL_ERROR; } - + /* Release Lock */ __HAL_UNLOCK(hdma); - + return status; } @@ -1179,17 +1179,17 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t /** * @brief Returns the DMA Stream base address depending on stream number * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. + * the configuration information for the specified DMA Stream. * @retval Stream base address */ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) { uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; - + /* lookup table for necessary bitshift of flags within status registers */ static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; hdma->StreamIndex = flagBitshiftOffset[stream_number]; - + if (stream_number > 3U) { /* return pointer to HISR and HIFCR */ @@ -1200,21 +1200,21 @@ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) /* return pointer to LISR and LIFCR */ hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); } - + return hdma->StreamBaseAddress; } /** * @brief Check compatibility between FIFO threshold level and size of the memory burst * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. + * the configuration information for the specified DMA Stream. * @retval HAL status */ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmp = hdma->Init.FIFOThreshold; - + /* Memory Data size equal to Byte */ if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) { @@ -1239,7 +1239,7 @@ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) break; } } - + /* Memory Data size equal to Half-Word */ else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) { @@ -1260,12 +1260,12 @@ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) { status = HAL_ERROR; } - break; + break; default: break; } } - + /* Memory Data size equal to Word */ else { @@ -1285,9 +1285,9 @@ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) default: break; } - } - - return status; + } + + return status; } /** @@ -1302,4 +1302,3 @@ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) /** * @} */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c index 7167e77e..e3bd8205 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c @@ -3,7 +3,7 @@ * @file stm32f4xx_hal_dma_ex.c * @author MCD Application Team * @brief DMA Extension HAL module driver - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the DMA Extension peripheral: * + Extended features functions * @@ -15,12 +15,12 @@ The DMA Extension HAL driver can be used as follows: (#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode. - + -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed. -@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default. - -@- In Multi (Double) buffer mode, it is possible to update the base address for - the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. - + -@- In Multi (Double) buffer mode, it is possible to update the base address for + the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. + @endverbatim ****************************************************************************** * @attention @@ -71,17 +71,17 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddres /** @addtogroup DMAEx_Exported_Functions_Group1 * -@verbatim +@verbatim =============================================================================== ##### Extended features functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: - (+) Configure the source, destination address and data length and + (+) Configure the source, destination address and data length and Start MultiBuffer DMA transfer - (+) Configure the source, destination address and data length and + (+) Configure the source, destination address and data length and Start MultiBuffer DMA transfer with interrupt (+) Change on the fly the memory0 or memory1 address. - + @endverbatim * @{ */ @@ -90,20 +90,20 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddres /** * @brief Starts the multi_buffer DMA Transfer. * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. + * the configuration information for the specified DMA Stream. * @param SrcAddress The source memory Buffer address * @param DstAddress The destination memory Buffer address - * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - + /* Memory-to-memory transfer not supported in double buffering mode */ if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) { @@ -114,21 +114,21 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t S { /* Process Locked */ __HAL_LOCK(hdma); - + if(HAL_DMA_STATE_READY == hdma->State) { /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - + hdma->State = HAL_DMA_STATE_BUSY; + /* Enable the double buffer mode */ hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; - + /* Configure DMA Stream destination address */ hdma->Instance->M1AR = SecondMemAddress; - + /* Configure the source, destination address and the data length */ DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); - + /* Enable the peripheral */ __HAL_DMA_ENABLE(hdma); } @@ -144,54 +144,54 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t S /** * @brief Starts the multi_buffer DMA Transfer with interrupt enabled. * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. + * the configuration information for the specified DMA Stream. * @param SrcAddress The source memory Buffer address * @param DstAddress The destination memory Buffer address - * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - + /* Memory-to-memory transfer not supported in double buffering mode */ if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) { hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; return HAL_ERROR; } - + /* Check callback functions */ if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) || (NULL == hdma->XferErrorCallback)) { hdma->ErrorCode = HAL_DMA_ERROR_PARAM; return HAL_ERROR; } - + /* Process locked */ __HAL_LOCK(hdma); - + if(HAL_DMA_STATE_READY == hdma->State) { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; - + /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; - + /* Enable the Double buffer mode */ hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; - + /* Configure DMA Stream destination address */ hdma->Instance->M1AR = SecondMemAddress; - + /* Configure the source, destination address and the data length */ - DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); - + DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + /* Clear all flags */ __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); @@ -202,37 +202,37 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_ /* Enable Common interrupts*/ hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; hdma->Instance->FCR |= DMA_IT_FE; - + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) { hdma->Instance->CR |= DMA_IT_HT; } - + /* Enable the peripheral */ - __HAL_DMA_ENABLE(hdma); + __HAL_DMA_ENABLE(hdma); } else - { + { /* Process unlocked */ - __HAL_UNLOCK(hdma); - + __HAL_UNLOCK(hdma); + /* Return error status */ status = HAL_BUSY; - } - return status; + } + return status; } /** * @brief Change the memory0 or memory1 address on the fly. * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. + * the configuration information for the specified DMA Stream. * @param Address The new address - * @param memory the memory to be changed, This parameter can be one of + * @param memory the memory to be changed, This parameter can be one of * the following values: * MEMORY0 / * MEMORY1 * @note The MEMORY0 address can be changed only when the current transfer use - * MEMORY1 and the MEMORY1 address can be changed only when the current + * MEMORY1 and the MEMORY1 address can be changed only when the current * transfer use MEMORY0. * @retval HAL status */ @@ -267,23 +267,23 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre /** * @brief Set the DMA Transfer parameter. * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. + * the configuration information for the specified DMA Stream. * @param SrcAddress The source memory Buffer address * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ +{ /* Configure DMA Stream data length */ hdma->Instance->NDTR = DataLength; - + /* Peripheral to Memory */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) - { + { /* Configure DMA Stream destination address */ hdma->Instance->PAR = DstAddress; - + /* Configure DMA Stream source address */ hdma->Instance->M0AR = SrcAddress; } @@ -292,7 +292,7 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddres { /* Configure DMA Stream source address */ hdma->Instance->PAR = SrcAddress; - + /* Configure DMA Stream destination address */ hdma->Instance->M0AR = DstAddress; } @@ -310,4 +310,3 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddres /** * @} */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c index 3e463122..aa94c7cf 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c @@ -550,4 +550,3 @@ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) /** * @} */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c index 808949ea..14154732 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c @@ -773,4 +773,3 @@ static void FLASH_SetErrorCode(void) /** * @} */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c index 839c91b1..86995e01 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c @@ -1341,4 +1341,3 @@ void FLASH_FlushCaches(void) /** * @} */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c index e6ab3ac8..c3e09882 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c @@ -169,4 +169,3 @@ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void) /** * @} */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c index b3ce9bbc..95cef829 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c @@ -3,7 +3,7 @@ * @file stm32f4xx_hal_gpio.c * @author MCD Application Team * @brief GPIO HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: * + Initialization and de-initialization functions * + IO operation functions @@ -23,86 +23,86 @@ ============================================================================== ##### GPIO Peripheral features ##### ============================================================================== - [..] + [..] Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software in several modes: - (+) Input mode + (+) Input mode (+) Analog mode (+) Output mode (+) Alternate function mode (+) External interrupt/event lines - [..] - During and just after reset, the alternate functions and external interrupt + [..] + During and just after reset, the alternate functions and external interrupt lines are not active and the I/O ports are configured in input floating mode. - - [..] - All GPIO pins have weak internal pull-up and pull-down resistors, which can be + + [..] + All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not. [..] In Output or Alternate mode, each IO can be configured on open-drain or push-pull type and the IO speed can be selected depending on the VDD value. - [..] - All ports have external interrupt/event capability. To use external interrupt - lines, the port must be configured in input mode. All available GPIO pins are - connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. - [..] - The external interrupt/event controller consists of up to 23 edge detectors - (16 lines are connected to GPIO) for generating event/interrupt requests (each - input line can be independently configured to select the type (interrupt or event) - and the corresponding trigger event (rising or falling or both). Each line can - also be masked independently. + All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + [..] + The external interrupt/event controller consists of up to 23 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. ##### How to use this driver ##### - ============================================================================== + ============================================================================== [..] - (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure - (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef structure. - (++) In case of Output or alternate function mode selection: the speed is + (++) In case of Output or alternate function mode selection: the speed is configured through "Speed" member from GPIO_InitTypeDef structure. (++) In alternate mode is selection, the alternate function connected to the IO is configured through "Alternate" member from GPIO_InitTypeDef structure. - (++) Analog mode is required when a pin is to be used as ADC channel + (++) Analog mode is required when a pin is to be used as ADC channel or DAC output. - (++) In case of external interrupt/event selection the "Mode" member from - GPIO_InitTypeDef structure select the type (interrupt or event) and + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and the corresponding trigger event (rising or falling or both). - (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using HAL_NVIC_EnableIRQ(). - + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). - - (#) To set/reset the level of a pin configured in output mode use + + (#) To set/reset the level of a pin configured in output mode use HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). - + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). - - (#) During and just after reset, the alternate functions are not + + (#) During and just after reset, the alternate functions are not active and the GPIO pins are configured in input floating mode (except JTAG pins). - - (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose - (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has priority over the GPIO function. - - (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as - general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PH0 and PH1, respectively, when the HSE oscillator is off. The HSE has priority over the GPIO function. - + @endverbatim ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" @@ -140,14 +140,14 @@ /** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to initialize and de-initialize the GPIOs to be ready for use. - + @endverbatim * @{ */ @@ -191,7 +191,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ - temp = GPIOx->OSPEEDR; + temp = GPIOx->OSPEEDR; temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); temp |= (GPIO_Init->Speed << (position * 2U)); GPIOx->OSPEEDR = temp; @@ -207,7 +207,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { /* Check the parameters */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); - + /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); @@ -300,7 +300,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - + /* Configure the port pins */ for(position = 0U; position < GPIO_NUMBER; position++) { @@ -319,7 +319,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /* Clear EXTI line configuration */ EXTI->IMR &= ~((uint32_t)iocurrent); EXTI->EMR &= ~((uint32_t)iocurrent); - + /* Clear Rising Falling edge configuration */ EXTI->FTSR &= ~((uint32_t)iocurrent); EXTI->RTSR &= ~((uint32_t)iocurrent); @@ -352,7 +352,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) * @} */ -/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions * @brief GPIO Read and Write * @verbatim @@ -530,4 +530,3 @@ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) /** * @} */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c index d3f4262f..811c013b 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c @@ -4729,7 +4729,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA UNUSED(DevAddress); /* Abort Master transfer during Receive or Transmit process */ - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && ((CurrentMode == HAL_I2C_MODE_MASTER) || + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))) { /* Process Locked */ @@ -7564,4 +7564,3 @@ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) /** * @} */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c index 64aabaa4..af97fd4a 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c @@ -179,4 +179,3 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ /** * @} */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c index 5ccde648..6b298881 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c @@ -3,11 +3,11 @@ * @file stm32f4xx_hal_pwr.c * @author MCD Application Team * @brief PWR HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: * + Initialization and de-initialization functions - * + Peripheral Control functions - * + * + Peripheral Control functions + * ****************************************************************************** * @attention * @@ -18,7 +18,7 @@ * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" @@ -39,10 +39,10 @@ /** @addtogroup PWR_Private_Constants * @{ */ - + /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask * @{ - */ + */ #define PVD_MODE_IT 0x00010000U #define PVD_MODE_EVT 0x00020000U #define PVD_RISING_EDGE 0x00000001U @@ -53,7 +53,7 @@ /** * @} - */ + */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -63,7 +63,7 @@ * @{ */ -/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and de-initialization functions * @verbatim @@ -71,14 +71,14 @@ ##### Initialization and de-initialization functions ##### =============================================================================== [..] - After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted - write accesses. + After reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted + write accesses. To enable access to the RTC Domain and RTC registers, proceed as follows: (+) Enable the Power Controller (PWR) APB1 interface clock using the __HAL_RCC_PWR_CLK_ENABLE() macro. (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. - + @endverbatim * @{ */ @@ -94,9 +94,9 @@ void HAL_PWR_DeInit(void) } /** - * @brief Enables access to the backup domain (RTC registers, RTC + * @brief Enables access to the backup domain (RTC registers, RTC * backup data registers and backup SRAM). - * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @note The following sequence is required to bypass the delay between * DBP bit programming and the effective enabling of the backup domain. @@ -114,9 +114,9 @@ void HAL_PWR_EnableBkUpAccess(void) } /** - * @brief Disables access to the backup domain (RTC registers, RTC + * @brief Disables access to the backup domain (RTC registers, RTC * backup data registers and backup SRAM). - * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @note The following sequence is required to bypass the delay between * DBP bit programming and the effective disabling of the backup domain. @@ -137,22 +137,22 @@ void HAL_PWR_DisableBkUpAccess(void) * @} */ -/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions - * @brief Low Power modes configuration functions +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @brief Low Power modes configuration functions * @verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== - + *** PVD configuration *** ========================= [..] - (+) The PVD is used to monitor the VDD power supply by comparing it to a + (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). - (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower - than the PVD threshold. This event is internally connected to the EXTI + (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled. This is done through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. (+) The PVD is stopped in Standby mode. @@ -160,21 +160,21 @@ void HAL_PWR_DisableBkUpAccess(void) *** Wake-up pin configuration *** ================================ [..] - (+) Wake-up pin is used to wake up the system from Standby mode. This pin is + (+) Wake-up pin is used to wake up the system from Standby mode. This pin is forced in input pull-down configuration and is active on rising edges. (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00. (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13 - (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01 + (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01 *** Low Power modes configuration *** ===================================== [..] The devices feature 3 low-power modes: (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running. - (+) Stop mode: all clocks are stopped, regulator running, regulator + (+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode (+) Standby mode: 1.2V domain powered off. - + *** Sleep mode *** ================== [..] @@ -185,28 +185,28 @@ void HAL_PWR_DisableBkUpAccess(void) (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction (++) PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR: Enter SLEEP mode with WFE instruction and no clear of pending event before. - - -@@- The Regulator parameter is not used for the STM32F4 family - and is kept as parameter just to maintain compatibility with the + + -@@- The Regulator parameter is not used for the STM32F4 family + and is kept as parameter just to maintain compatibility with the lower power families (STM32L). (+) Exit: - Any peripheral interrupt acknowledged by the nested vectored interrupt + Any peripheral interrupt acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode. *** Stop mode *** ================= [..] In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, - and the HSE RC oscillators are disabled. Internal SRAM and register contents + and the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved. The voltage regulator can be configured either in normal or low-power mode. - To minimize the consumption In Stop mode, FLASH can be powered off before + To minimize the consumption In Stop mode, FLASH can be powered off before entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function. It can be switched on again by software after exiting the Stop mode using - the HAL_PWREx_DisableFlashPowerDown() function. + the HAL_PWREx_DisableFlashPowerDown() function. (+) Entry: - The Stop mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, STOPEntry) + The Stop mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, STOPEntry) function with: (++) Regulator: (+++) Main regulator ON. @@ -224,15 +224,15 @@ void HAL_PWR_DisableBkUpAccess(void) ==================== [..] (+) - The Standby mode allows to achieve the lowest power consumption. It is based - on the Cortex-M4 deep sleep mode, with the voltage regulator disabled. - The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and - the HSE oscillator are also switched off. SRAM and register contents are lost - except for the RTC registers, RTC backup registers, backup SRAM and Standby + The Standby mode allows to achieve the lowest power consumption. It is based + on the Cortex-M4 deep sleep mode, with the voltage regulator disabled. + The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and + the HSE oscillator are also switched off. SRAM and register contents are lost + except for the RTC registers, RTC backup registers, backup SRAM and Standby circuitry. - + The voltage regulator is OFF. - + (++) Entry: (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. (++) Exit: @@ -242,20 +242,20 @@ void HAL_PWR_DisableBkUpAccess(void) *** Auto-wake-up (AWU) from low-power mode *** ============================================= [..] - - (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC - Wake-up event, a tamper event or a time-stamp event, without depending on + + (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + Wake-up event, a tamper event or a time-stamp event, without depending on an external interrupt (Auto-wake-up mode). (+) RTC auto-wake-up (AWU) from the Stop and Standby modes - - (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to + + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. - (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it is necessary to configure the RTC to detect the tamper or time stamp event using the HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. - + (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function. @@ -268,7 +268,7 @@ void HAL_PWR_DisableBkUpAccess(void) * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration * information for the PVD. * @note Refer to the electrical characteristics of your device datasheet for - * more details about the voltage threshold corresponding to each + * more details about the voltage threshold corresponding to each * detection level. * @retval None */ @@ -277,34 +277,34 @@ void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) /* Check the parameters */ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); - + /* Set PLS[7:5] bits according to PVDLevel value */ MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); - + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); __HAL_PWR_PVD_EXTI_DISABLE_IT(); __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); - __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); /* Configure interrupt mode */ if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) { __HAL_PWR_PVD_EXTI_ENABLE_IT(); } - + /* Configure event mode */ if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) { __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); } - + /* Configure the edge */ if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); } - + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) { __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); @@ -359,20 +359,20 @@ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) { /* Check the parameter */ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); /* Disable the wake up pin */ CLEAR_BIT(PWR->CSR, WakeUpPinx); } - + /** * @brief Enters Sleep mode. - * + * * @note In Sleep mode, all I/O pins keep the same state as in Run mode. - * + * * @note In Sleep mode, the systick is stopped to avoid exit from this mode with - * systick interrupt when used as time base for Timeout - * + * systick interrupt when used as time base for Timeout + * * @param Regulator Specifies the regulator state in SLEEP mode. * This parameter can be one of the following values: * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON @@ -402,7 +402,7 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) /* Select SLEEP mode entry -------------------------------------------------*/ if(SLEEPEntry == PWR_SLEEPENTRY_WFI) - { + { /* Request Wait For Interrupt */ __WFI(); } @@ -421,21 +421,21 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) } /** - * @brief Enters Stop mode. + * @brief Enters Stop mode. * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting Stop mode by issuing an interrupt or a wake-up event, + * @note When exiting Stop mode by issuing an interrupt or a wake-up event, * the HSI RC oscillator is selected as system clock. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. * @param Regulator Specifies the regulator state in Stop mode. * This parameter can be one of the following values: * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: - * @arg PWR_STOPENTRY_WFI : Enter Stop mode with WFI instruction + * @arg PWR_STOPENTRY_WFI : Enter Stop mode with WFI instruction * @arg PWR_STOPENTRY_WFE : Enter Stop mode with WFE instruction and * clear of pending events before. * @arg PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and @@ -447,16 +447,16 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) /* Check the parameters */ assert_param(IS_PWR_REGULATOR(Regulator)); assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - + /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */ MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator); - + /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - + /* Select Stop mode entry --------------------------------------------------*/ if(STOPEntry == PWR_STOPENTRY_WFI) - { + { /* Request Wait For Interrupt */ __WFI(); } @@ -472,17 +472,17 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) __WFE(); } /* Reset SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); } /** * @brief Enters Standby mode. * @note In Standby mode, all I/O pins are high impedance except for: - * - Reset pad (still available) - * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC + * - Reset pad (still available) + * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC * Alarm out, or RTC clock calibration out. - * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. - * - WKUP pin 1 (PA0) if enabled. + * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. + * - WKUP pin 1 (PA0) if enabled. * @retval None */ void HAL_PWR_EnterSTANDBYMode(void) @@ -492,7 +492,7 @@ void HAL_PWR_EnterSTANDBYMode(void) /* Set SLEEPDEEP bit of Cortex System Control Register */ SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - + /* This option is used to ensure that store operations are completed */ #if defined ( __CC_ARM) __force_stores(); @@ -513,7 +513,7 @@ void HAL_PWR_PVD_IRQHandler(void) { /* PWR PVD interrupt user callback */ HAL_PWR_PVDCallback(); - + /* Clear PWR Exti pending bit */ __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); } @@ -527,15 +527,15 @@ __weak void HAL_PWR_PVDCallback(void) { /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PWR_PVDCallback could be implemented in the user file - */ + */ } /** - * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. - * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor * re-enters SLEEP mode when an interruption handling is over. * Setting this bit is useful when the processor is expected to run only on - * interruptions handling. + * interruptions handling. * @retval None */ void HAL_PWR_EnableSleepOnExit(void) @@ -545,9 +545,9 @@ void HAL_PWR_EnableSleepOnExit(void) } /** - * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. - * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. + * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. * @retval None */ void HAL_PWR_DisableSleepOnExit(void) @@ -557,8 +557,8 @@ void HAL_PWR_DisableSleepOnExit(void) } /** - * @brief Enables CORTEX M4 SEVONPEND bit. - * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + * @brief Enables CORTEX M4 SEVONPEND bit. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes * WFE to wake up when an interrupt moves from inactive to pended. * @retval None */ @@ -569,9 +569,9 @@ void HAL_PWR_EnableSEVOnPend(void) } /** - * @brief Disables CORTEX M4 SEVONPEND bit. - * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. + * @brief Disables CORTEX M4 SEVONPEND bit. + * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. * @retval None */ void HAL_PWR_DisableSEVOnPend(void) @@ -583,7 +583,7 @@ void HAL_PWR_DisableSEVOnPend(void) /** * @} */ - + /** * @} */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c index 77f9c35b..f18f4bf9 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c @@ -3,10 +3,10 @@ * @file stm32f4xx_hal_pwr_ex.c * @author MCD Application Team * @brief Extended PWR HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of PWR extension peripheral: + * This file provides firmware functions to manage the following + * functionalities of PWR extension peripheral: * + Peripheral Extended features functions - * + * ****************************************************************************** * @attention * @@ -17,7 +17,7 @@ * the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" @@ -37,7 +37,7 @@ /* Private define ------------------------------------------------------------*/ /** @addtogroup PWREx_Private_Constants * @{ - */ + */ #define PWR_OVERDRIVE_TIMEOUT_VALUE 1000U #define PWR_UDERDRIVE_TIMEOUT_VALUE 1000U #define PWR_BKPREG_TIMEOUT_VALUE 1000U @@ -46,7 +46,7 @@ * @} */ - + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -55,10 +55,10 @@ * @{ */ -/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions - * @brief Peripheral Extended features functions +/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions + * @brief Peripheral Extended features functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral extended features functions ##### @@ -66,66 +66,66 @@ *** Main and Backup Regulators configuration *** ================================================ - [..] - (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from - the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is + [..] + (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from + the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is retained even in Standby or VBAT mode when the low power backup regulator - is enabled. It can be considered as an internal EEPROM when VBAT is - always present. You can use the HAL_PWREx_EnableBkUpReg() function to - enable the low power backup regulator. + is enabled. It can be considered as an internal EEPROM when VBAT is + always present. You can use the HAL_PWREx_EnableBkUpReg() function to + enable the low power backup regulator. - (+) When the backup domain is supplied by VDD (analog switch connected to VDD) - the backup SRAM is powered from VDD which replaces the VBAT power supply to + (+) When the backup domain is supplied by VDD (analog switch connected to VDD) + the backup SRAM is powered from VDD which replaces the VBAT power supply to save battery life. - (+) The backup SRAM is not mass erased by a tamper event. It is read - protected to prevent confidential data, such as cryptographic private - key, from being accessed. The backup SRAM can be erased only through - the Flash interface when a protection level change from level 1 to - level 0 is requested. - -@- Refer to the description of Read protection (RDP) in the Flash + (+) The backup SRAM is not mass erased by a tamper event. It is read + protected to prevent confidential data, such as cryptographic private + key, from being accessed. The backup SRAM can be erased only through + the Flash interface when a protection level change from level 1 to + level 0 is requested. + -@- Refer to the description of Read protection (RDP) in the Flash programming manual. - (+) The main internal regulator can be configured to have a tradeoff between - performance and power consumption when the device does not operate at - the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() + (+) The main internal regulator can be configured to have a tradeoff between + performance and power consumption when the device does not operate at + the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() macro which configure VOS bit in PWR_CR register - + Refer to the product datasheets for more details. *** FLASH Power Down configuration **** ======================================= - [..] - (+) By setting the FPDS bit in the PWR_CR register by using the - HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power - down mode when the device enters Stop mode. When the Flash memory - is in power down mode, an additional startup delay is incurred when + [..] + (+) By setting the FPDS bit in the PWR_CR register by using the + HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power + down mode when the device enters Stop mode. When the Flash memory + is in power down mode, an additional startup delay is incurred when waking up from Stop mode. - - (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL - is OFF and the HSI or HSE clock source is selected as system clock. + + (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL + is OFF and the HSI or HSE clock source is selected as system clock. The new value programmed is active only when the PLL is ON. - When the PLL is OFF, the voltage scale 3 is automatically selected. + When the PLL is OFF, the voltage scale 3 is automatically selected. Refer to the datasheets for more details. *** Over-Drive and Under-Drive configuration **** ================================================= - [..] + [..] (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has 2 operating modes available: - (++) Normal mode: The CPU and core logic operate at maximum frequency at a given + (++) Normal mode: The CPU and core logic operate at maximum frequency at a given voltage scaling (scale 1, scale 2 or scale 3) - (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a - higher frequency than the normal mode for a given voltage scaling (scale 1, + (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a + higher frequency than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and - disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow + disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow the sequence described in Reference manual. - - (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator - supplies a low power voltage to the 1.2V domain, thus preserving the content of registers + + (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator + supplies a low power voltage to the 1.2V domain, thus preserving the content of registers and internal SRAM. 2 operating modes are available: - (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only - available when the main regulator or the low power regulator is used in Scale 3 or + (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only + available when the main regulator or the low power regulator is used in Scale 3 or low voltage mode. (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only available when the main regulator or the low power regulator is in low voltage mode. @@ -147,13 +147,13 @@ HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void) /* Get tick */ tickstart = HAL_GetTick(); - /* Wait till Backup regulator ready flag is set */ + /* Wait till Backup regulator ready flag is set */ while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET) { if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } return HAL_OK; } @@ -171,13 +171,13 @@ HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void) /* Get tick */ tickstart = HAL_GetTick(); - /* Wait till Backup regulator ready flag is set */ + /* Wait till Backup regulator ready flag is set */ while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET) { if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } return HAL_OK; } @@ -207,7 +207,7 @@ void HAL_PWREx_DisableFlashPowerDown(void) * - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode * - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode * - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode - */ + */ uint32_t HAL_PWREx_GetVoltageRange(void) { return (PWR->CR & PWR_CR_VOS); @@ -232,15 +232,15 @@ uint32_t HAL_PWREx_GetVoltageRange(void) HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { uint32_t tickstart = 0U; - + assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); - + /* Enable PWR RCC Clock Peripheral */ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Set Range */ __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); - + /* Get Start Tick*/ tickstart = HAL_GetTick(); while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) @@ -248,7 +248,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } return HAL_OK; @@ -268,7 +268,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) * the maximum value of fHCLK is 168 MHz. It can be extended to * 180 MHz by activating the over-drive mode. * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, - * the maximum value of fHCLK is 144 MHz. It can be extended to, + * the maximum value of fHCLK is 144 MHz. It can be extended to, * 168 MHz by activating the over-drive mode. * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode, * the maximum value of fHCLK is 120 MHz. @@ -277,32 +277,32 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) * - Call the HAL_RCC_OscConfig() to configure the PLL. * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale. * - Set the new system clock frequency using the HAL_RCC_ClockConfig(). - * @note The scale can be modified only when the HSI or HSE clock source is selected - * as system clock source, otherwise the API returns HAL_ERROR. + * @note The scale can be modified only when the HSI or HSE clock source is selected + * as system clock source, otherwise the API returns HAL_ERROR. * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits * value in the PWR_CR1 register are not taken in account. * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2. - * @note The new voltage scale is active only when the PLL is ON. + * @note The new voltage scale is active only when the PLL is ON. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { uint32_t tickstart = 0U; - + assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); - + /* Enable PWR RCC Clock Peripheral */ __HAL_RCC_PWR_CLK_ENABLE(); - + /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) { /* Disable the main PLL */ __HAL_RCC_PLL_DISABLE(); - + /* Get Start Tick */ - tickstart = HAL_GetTick(); - /* Wait till PLL is disabled */ + tickstart = HAL_GetTick(); + /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) @@ -310,24 +310,24 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) return HAL_TIMEOUT; } } - + /* Set Range */ __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); - + /* Enable the main PLL */ __HAL_RCC_PLL_ENABLE(); - + /* Get Start Tick */ tickstart = HAL_GetTick(); - /* Wait till PLL is ready */ + /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } - + /* Get Start Tick */ tickstart = HAL_GetTick(); while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) @@ -335,7 +335,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) { return HAL_TIMEOUT; - } + } } } else @@ -353,7 +353,7 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) /** * @brief Enables Main Regulator low voltage mode. * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ - * STM32F413xx/STM32F423xx devices. + * STM32F413xx/STM32F423xx devices. * @retval None */ void HAL_PWREx_EnableMainRegulatorLowVoltage(void) @@ -364,7 +364,7 @@ void HAL_PWREx_EnableMainRegulatorLowVoltage(void) /** * @brief Disables Main Regulator low voltage mode. * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ - * STM32F413xx/STM32F423xxdevices. + * STM32F413xx/STM32F423xxdevices. * @retval None */ void HAL_PWREx_DisableMainRegulatorLowVoltage(void) @@ -375,7 +375,7 @@ void HAL_PWREx_DisableMainRegulatorLowVoltage(void) /** * @brief Enables Low Power Regulator low voltage mode. * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ - * STM32F413xx/STM32F423xx devices. + * STM32F413xx/STM32F423xx devices. * @retval None */ void HAL_PWREx_EnableLowRegulatorLowVoltage(void) @@ -386,7 +386,7 @@ void HAL_PWREx_EnableLowRegulatorLowVoltage(void) /** * @brief Disables Low Power Regulator low voltage mode. * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ - * STM32F413xx/STM32F423xx devices. + * STM32F413xx/STM32F423xx devices. * @retval None */ void HAL_PWREx_DisableLowRegulatorLowVoltage(void) @@ -403,11 +403,11 @@ void HAL_PWREx_DisableLowRegulatorLowVoltage(void) * @brief Activates the Over-Drive mode. * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices. * This mode allows the CPU and the core logic to operate at a higher frequency - * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). - * @note It is recommended to enter or exit Over-drive mode when the application is not running - * critical tasks and when the system clock source is either HSI or HSE. - * During the Over-drive switch activation, no peripheral clocks should be enabled. - * The peripheral clocks must be enabled once the Over-drive mode is activated. + * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). + * @note It is recommended to enter or exit Over-drive mode when the application is not running + * critical tasks and when the system clock source is either HSI or HSE. + * During the Over-drive switch activation, no peripheral clocks should be enabled. + * The peripheral clocks must be enabled once the Over-drive mode is activated. * @retval HAL status */ HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) @@ -415,7 +415,7 @@ HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) uint32_t tickstart = 0U; __HAL_RCC_PWR_CLK_ENABLE(); - + /* Enable the Over-drive to extend the clock frequency to 180 Mhz */ __HAL_PWR_OVERDRIVE_ENABLE(); @@ -429,7 +429,7 @@ HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) return HAL_TIMEOUT; } } - + /* Enable the Over-drive switch */ __HAL_PWR_OVERDRIVESWITCHING_ENABLE(); @@ -442,7 +442,7 @@ HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) { return HAL_TIMEOUT; } - } + } return HAL_OK; } @@ -450,33 +450,33 @@ HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) * @brief Deactivates the Over-Drive mode. * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices. * This mode allows the CPU and the core logic to operate at a higher frequency - * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). - * @note It is recommended to enter or exit Over-drive mode when the application is not running - * critical tasks and when the system clock source is either HSI or HSE. - * During the Over-drive switch activation, no peripheral clocks should be enabled. + * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). + * @note It is recommended to enter or exit Over-drive mode when the application is not running + * critical tasks and when the system clock source is either HSI or HSE. + * During the Over-drive switch activation, no peripheral clocks should be enabled. * The peripheral clocks must be enabled once the Over-drive mode is activated. * @retval HAL status */ HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void) { uint32_t tickstart = 0U; - + __HAL_RCC_PWR_CLK_ENABLE(); - + /* Disable the Over-drive switch */ __HAL_PWR_OVERDRIVESWITCHING_DISABLE(); - + /* Get tick */ tickstart = HAL_GetTick(); - + while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) { if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } - } - + } + /* Disable the Over-drive */ __HAL_PWR_OVERDRIVE_DISABLE(); @@ -490,42 +490,42 @@ HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void) return HAL_TIMEOUT; } } - + return HAL_OK; } /** * @brief Enters in Under-Drive STOP mode. - * + * * @note This mode is only available for STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx devices. - * - * @note This mode can be selected only when the Under-Drive is already active - * + * + * @note This mode can be selected only when the Under-Drive is already active + * * @note This mode is enabled only with STOP low power mode. - * In this mode, the 1.2V domain is preserved in reduced leakage mode. This - * mode is only available when the main regulator or the low power regulator + * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + * mode is only available when the main regulator or the low power regulator * is in low voltage mode - * - * @note If the Under-drive mode was enabled, it is automatically disabled after - * exiting Stop mode. - * When the voltage regulator operates in Under-drive mode, an additional + * + * @note If the Under-drive mode was enabled, it is automatically disabled after + * exiting Stop mode. + * When the voltage regulator operates in Under-drive mode, an additional * startup delay is induced when waking up from Stop mode. - * + * * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * - * @note When exiting Stop mode by issuing an interrupt or a wake-up event, + * + * @note When exiting Stop mode by issuing an interrupt or a wake-up event, * the HSI RC oscillator is selected as system clock. - * - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption + * + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption * is higher although the startup time is reduced. - * + * * @param Regulator specifies the regulator state in STOP mode. * This parameter can be one of the following values: - * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode + * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode * and Flash memory in power-down when the device is in Stop under-drive mode - * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode + * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode * and Flash memory in power-down when the device is in Stop under-drive mode * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: @@ -540,33 +540,33 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t /* Check the parameters */ assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator)); assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - + /* Enable Power ctrl clock */ __HAL_RCC_PWR_CLK_ENABLE(); /* Enable the Under-drive Mode ---------------------------------------------*/ /* Clear Under-drive flag */ __HAL_PWR_CLEAR_ODRUDR_FLAG(); - - /* Enable the Under-drive */ + + /* Enable the Under-drive */ __HAL_PWR_UNDERDRIVE_ENABLE(); /* Select the regulator state in STOP mode ---------------------------------*/ tmpreg1 = PWR->CR; /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */ tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS); - + /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */ tmpreg1 |= Regulator; - + /* Store the new value */ PWR->CR = tmpreg1; - + /* Set SLEEPDEEP bit of Cortex System Control Register */ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - + /* Select STOP mode entry --------------------------------------------------*/ if(STOPEntry == PWR_SLEEPENTRY_WFI) - { + { /* Request Wait For Interrupt */ __WFI(); } @@ -578,7 +578,7 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t /* Reset SLEEPDEEP bit of Cortex System Control Register */ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - return HAL_OK; + return HAL_OK; } #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c index c18fa09b..918e6536 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c @@ -1121,4 +1121,3 @@ __weak void HAL_RCC_CSSCallback(void) /** * @} */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c index 04317181..bb886e7f 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c @@ -3830,4 +3830,3 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /** * @} */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c index 92757d85..d4f15c80 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c @@ -3942,4 +3942,3 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) /** * @} */ - diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c index cf6d201b..51ff7b0f 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c @@ -3804,4 +3804,3 @@ static void UART_SetConfig(UART_HandleTypeDef *huart) /** * @} */ - diff --git a/Inc/dma.h b/Inc/dma.h index afad30d1..d2b453a7 100644 --- a/Inc/dma.h +++ b/Inc/dma.h @@ -49,4 +49,3 @@ void MX_DMA_Init(void); #endif #endif /* __DMA_H__ */ - diff --git a/Inc/gpio.h b/Inc/gpio.h index 3c91c4dd..5cee1da4 100644 --- a/Inc/gpio.h +++ b/Inc/gpio.h @@ -46,4 +46,3 @@ void MX_GPIO_Init(void); } #endif #endif /*__ GPIO_H__ */ - diff --git a/Inc/i2c.h b/Inc/i2c.h index 4baa02a2..b6f46708 100644 --- a/Inc/i2c.h +++ b/Inc/i2c.h @@ -49,4 +49,3 @@ void MX_I2C1_Init(void); #endif #endif /* __I2C_H__ */ - diff --git a/Inc/spi.h b/Inc/spi.h index 030130a8..454b3926 100644 --- a/Inc/spi.h +++ b/Inc/spi.h @@ -52,4 +52,3 @@ void MX_SPI2_Init(void); #endif #endif /* __SPI_H__ */ - diff --git a/Inc/usart.h b/Inc/usart.h index f2b8e20a..5e223b13 100644 --- a/Inc/usart.h +++ b/Inc/usart.h @@ -61,4 +61,3 @@ void MX_USART3_UART_Init(void); #endif #endif /* __USART_H__ */ - diff --git a/Lib/FatFs/ff.c b/Lib/FatFs/ff.c index 6d412fa0..05ca02f0 100644 --- a/Lib/FatFs/ff.c +++ b/Lib/FatFs/ff.c @@ -7081,4 +7081,3 @@ FRESULT f_setcp ( return FR_OK; } #endif /* FF_CODE_PAGE == 0 */ - diff --git a/MDK-ARM/STM32F407-Demo.uvprojx b/MDK-ARM/STM32F407-Demo.uvprojx index c3cd6185..0d6ad718 100644 --- a/MDK-ARM/STM32F407-Demo.uvprojx +++ b/MDK-ARM/STM32F407-Demo.uvprojx @@ -16,7 +16,7 @@ STM32F407ZGTx STMicroelectronics - Keil.STM32F4xx_DFP.3.1.1 + Keil.STM32F4xx_DFP.3.0.0 https://www.keil.com/pack/ IRAM(0x20000000-0x2001BFFF) IRAM2(0x2001C000-0x2001FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) FPU2 CPUTYPE("Cortex-M4") TZ diff --git a/MDK-ARM/download_log.txt b/MDK-ARM/download_log.txt index ed7fc35e..4cc5939a 100644 --- a/MDK-ARM/download_log.txt +++ b/MDK-ARM/download_log.txt @@ -1,3 +1,3 @@ -Load "D:\\Code\\DTU \\STM32F4-Base\\MDK-ARM\\STM32F407-Demo\\STM32F407-Demo.axf" +Load "D:\\Code\\DTU \\STM32F4-Base\\MDK-ARM\\STM32F407-Demo\\STM32F407-Demo.axf" Erase Done.Programming Done.Verify OK.Application running ... Flash Load finished at 15:05:40 diff --git a/MDK-ARM/startup_stm32f407xx.s b/MDK-ARM/startup_stm32f407xx.s index b0722a1b..544fa0fc 100644 --- a/MDK-ARM/startup_stm32f407xx.s +++ b/MDK-ARM/startup_stm32f407xx.s @@ -1,7 +1,7 @@ ;******************************************************************************* ;* File Name : startup_stm32f407xx.s ;* Author : MCD Application Team -;* Description : STM32F407xx devices vector table for MDK-ARM toolchain. +;* Description : STM32F407xx devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler @@ -75,90 +75,90 @@ __Vectors DCD __initial_sp ; Top of Stack DCD SysTick_Handler ; SysTick Handler ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU - - + + __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors @@ -223,170 +223,170 @@ SysTick_Handler PROC Default_Handler PROC - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] EXPORT HASH_RNG_IRQHandler [WEAK] EXPORT FPU_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler HASH_RNG_IRQHandler -FPU_IRQHandler - +FPU_IRQHandler + B . ENDP @@ -397,16 +397,16 @@ FPU_IRQHandler ; User Stack and Heap initialization ;******************************************************************************* IF :DEF:__MICROLIB - + EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit - + ELSE - + IMPORT __use_two_region_memory EXPORT __user_initial_stackheap - + __user_initial_stackheap LDR R0, = Heap_Mem diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h index 711408a5..eac4d71c 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h @@ -39,7 +39,7 @@ * Version 1.02 * Control functions for short timeouts in microsecond resolution: * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec - * Removed: osSignalGet + * Removed: osSignalGet * Version 2.0.0 * OS objects creation without macros (dynamic creation and resource allocation): * - added: osXxxxNew functions which replace osXxxxCreate @@ -67,7 +67,7 @@ * - added: osThreadSuspend, osThreadResume * - added: osThreadJoin, osThreadDetach, osThreadExit * - added: osThreadGetCount, osThreadEnumerate - * - added: Thread Flags (moved from Signals) + * - added: Thread Flags (moved from Signals) * Signals: * - renamed osSignals to osThreadFlags (moved to Thread Flags) * - changed return value of Set/Clear/Wait functions @@ -110,7 +110,7 @@ * - added: osMessageQueueGetCapacity, osMessageQueueGetMsgSize * - added: osMessageQueueGetCount, osMessageQueueGetSpace * - added: osMessageQueueReset, osMessageQueueDelete - * Mail Queue: + * Mail Queue: * - deprecated (superseded by extended Message Queue functionality) * Version 2.1.0 * Support for critical and uncritical sections (nesting safe): @@ -119,7 +119,7 @@ * Updated Thread and Event Flags: * - changed flags parameter and return type from int32_t to uint32_t *---------------------------------------------------------------------------*/ - + #ifndef CMSIS_OS_H_ #define CMSIS_OS_H_ @@ -132,9 +132,9 @@ #define osCMSIS 0x20001U ///< API version (main[31:16].sub[15:0]) #define osCMSIS_FreeRTOS RTOS_ID_n ///< RTOS identification and version (main[31:16].sub[15:0]) - + #define osKernelSystemId RTOS_ID_s ///< RTOS identification string - + #define osFeature_MainThread 0 ///< main thread 1=main can be thread, 0=not available #define osFeature_Signals 24U ///< maximum number of Signal Flags available per thread #define osFeature_Semaphore 65535U ///< maximum count for \ref osSemaphoreCreate function @@ -143,7 +143,7 @@ #define osFeature_Pool 0 ///< Memory Pools: 1=available, 0=not available #define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available #define osFeature_MailQ 0 ///< Mail Queues: 1=available, 0=not available - + #if defined(__CC_ARM) #define os_InRegs __value_in_regs #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) @@ -151,17 +151,17 @@ #else #define os_InRegs #endif - + #include "cmsis_os2.h" - + #ifdef __cplusplus extern "C" { #endif - - + + // ==== Enumerations, structures, defines ==== - + /// Priority values. #if (osCMSIS < 0x20000U) typedef enum { @@ -181,10 +181,10 @@ typedef enum { /// Entry point of a thread. typedef void (*os_pthread) (void const *argument); - + /// Entry point of a timer call back function. typedef void (*os_ptimer) (void const *argument); - + /// Timer type. #if (osCMSIS < 0x20000U) typedef enum { @@ -194,10 +194,10 @@ typedef enum { #else #define os_timer_type osTimerType_t #endif - + /// Timeout value. #define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value. - + /// Status code values returned by CMSIS-RTOS functions. #if (osCMSIS < 0x20000U) typedef enum { @@ -229,48 +229,48 @@ typedef int32_t osStatus; #define osErrorValue (-127) #define osErrorPriority (-128) #endif - - + + // >>> the following data type definitions may be adapted towards a specific RTOS - + /// Thread ID identifies the thread. #if (osCMSIS < 0x20000U) typedef void *osThreadId; #else #define osThreadId osThreadId_t #endif - + /// Timer ID identifies the timer. #if (osCMSIS < 0x20000U) typedef void *osTimerId; #else #define osTimerId osTimerId_t #endif - + /// Mutex ID identifies the mutex. #if (osCMSIS < 0x20000U) typedef void *osMutexId; #else #define osMutexId osMutexId_t #endif - + /// Semaphore ID identifies the semaphore. #if (osCMSIS < 0x20000U) typedef void *osSemaphoreId; #else #define osSemaphoreId osSemaphoreId_t #endif - + /// Pool ID identifies the memory pool. typedef void *osPoolId; - + /// Message ID identifies the message queue. typedef void *osMessageQId; - + /// Mail ID identifies the mail queue. typedef void *osMailQId; - - + + /// Thread Definition structure contains startup information of a thread. #if (osCMSIS < 0x20000U) typedef struct os_thread_def { @@ -285,7 +285,7 @@ typedef struct os_thread_def { osThreadAttr_t attr; ///< thread attributes } osThreadDef_t; #endif - + /// Timer Definition structure contains timer parameters. #if (osCMSIS < 0x20000U) typedef struct os_timer_def { @@ -297,7 +297,7 @@ typedef struct os_timer_def { osTimerAttr_t attr; ///< timer attributes } osTimerDef_t; #endif - + /// Mutex Definition structure contains setup information for a mutex. #if (osCMSIS < 0x20000U) typedef struct os_mutex_def { @@ -306,7 +306,7 @@ typedef struct os_mutex_def { #else #define osMutexDef_t osMutexAttr_t #endif - + /// Semaphore Definition structure contains setup information for a semaphore. #if (osCMSIS < 0x20000U) typedef struct os_semaphore_def { @@ -315,7 +315,7 @@ typedef struct os_semaphore_def { #else #define osSemaphoreDef_t osSemaphoreAttr_t #endif - + /// Definition structure for memory block allocation. #if (osCMSIS < 0x20000U) typedef struct os_pool_def { @@ -330,7 +330,7 @@ typedef struct os_pool_def { osMemoryPoolAttr_t attr; ///< memory pool attributes } osPoolDef_t; #endif - + /// Definition structure for message queue. #if (osCMSIS < 0x20000U) typedef struct os_messageQ_def { @@ -343,7 +343,7 @@ typedef struct os_messageQ_def { osMessageQueueAttr_t attr; ///< message queue attributes } osMessageQDef_t; #endif - + /// Definition structure for mail queue. #if (osCMSIS < 0x20000U) typedef struct os_mailQ_def { @@ -360,8 +360,8 @@ typedef struct os_mailQ_def { osMessageQueueAttr_t mq_attr; ///< message queue attributes } osMailQDef_t; #endif - - + + /// Event structure contains detailed information about an event. typedef struct { osStatus status; ///< status code: event or error information @@ -375,44 +375,44 @@ typedef struct { osMessageQId message_id; ///< message id obtained by \ref osMessageCreate } def; ///< event definition } osEvent; - - + + // ==== Kernel Management Functions ==== - + /// Initialize the RTOS Kernel for creating objects. /// \return status code that indicates the execution status of the function. #if (osCMSIS < 0x20000U) osStatus osKernelInitialize (void); #endif - + /// Start the RTOS Kernel scheduler. /// \return status code that indicates the execution status of the function. #if (osCMSIS < 0x20000U) osStatus osKernelStart (void); #endif - + /// Check if the RTOS kernel is already started. /// \return 0 RTOS is not started, 1 RTOS is started. #if (osCMSIS < 0x20000U) int32_t osKernelRunning(void); #endif - + #if (defined(osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available - + /// Get the RTOS kernel system timer counter. -/// \return RTOS kernel system timer as 32-bit value +/// \return RTOS kernel system timer as 32-bit value #if (osCMSIS < 0x20000U) uint32_t osKernelSysTick (void); #else #define osKernelSysTick osKernelGetSysTimerCount #endif - + /// The RTOS kernel system timer frequency in Hz. /// \note Reflects the system timer setting and is typically defined in a configuration file. #if (osCMSIS < 0x20000U) #define osKernelSysTickFrequency 100000000 #endif - + /// Convert a microseconds value to a RTOS kernel system timer value. /// \param microsec time value in microseconds. /// \return time value normalized to the \ref osKernelSysTickFrequency @@ -421,12 +421,12 @@ uint32_t osKernelSysTick (void); #else #define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * osKernelGetSysTimerFreq()) / 1000000) #endif - + #endif // System Timer available - - + + // ==== Thread Management Functions ==== - + /// Create a Thread Definition with function, priority, and stack requirements. /// \param name name of the thread function. /// \param priority initial priority of the thread function. @@ -448,24 +448,24 @@ const osThreadDef_t os_thread_def_##name = \ 8*((stacksz+7)/8), \ (priority), 0U, 0U } } #endif - + /// Access a Thread definition. /// \param name name of the thread definition object. #define osThread(name) \ &os_thread_def_##name - + /// Create a thread and add it to Active Threads and set it to state READY. /// \param[in] thread_def thread definition referenced with \ref osThread. /// \param[in] argument pointer that is passed to the thread function as start argument. /// \return thread ID for reference by other functions or NULL in case of error. osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument); - + /// Return the thread ID of the current running thread. /// \return thread ID for reference by other functions or NULL in case of error. #if (osCMSIS < 0x20000U) osThreadId osThreadGetId (void); #endif - + /// Change priority of a thread. /// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. /// \param[in] priority new priority value for the thread function. @@ -473,70 +473,70 @@ osThreadId osThreadGetId (void); #if (osCMSIS < 0x20000U) osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); #endif - + /// Get current priority of a thread. /// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. /// \return current priority value of the specified thread. #if (osCMSIS < 0x20000U) osPriority osThreadGetPriority (osThreadId thread_id); #endif - + /// Pass control to next thread that is in state \b READY. /// \return status code that indicates the execution status of the function. #if (osCMSIS < 0x20000U) osStatus osThreadYield (void); #endif - + /// Terminate execution of a thread. /// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. /// \return status code that indicates the execution status of the function. #if (osCMSIS < 0x20000U) osStatus osThreadTerminate (osThreadId thread_id); #endif - - + + // ==== Signal Management ==== - + /// Set the specified Signal Flags of an active thread. /// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. /// \param[in] signals specifies the signal flags of the thread that should be set. /// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. int32_t osSignalSet (osThreadId thread_id, int32_t signals); - + /// Clear the specified Signal Flags of an active thread. /// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. /// \param[in] signals specifies the signal flags of the thread that shall be cleared. /// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR. int32_t osSignalClear (osThreadId thread_id, int32_t signals); - + /// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. /// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. /// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. /// \return event flag information or error code. os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec); - - + + // ==== Generic Wait Functions ==== - + /// Wait for Timeout (Time Delay). /// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value /// \return status code that indicates the execution status of the function. #if (osCMSIS < 0x20000U) osStatus osDelay (uint32_t millisec); #endif - + #if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available - + /// Wait for Signal, Message, Mail, or Timeout. /// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out /// \return event that contains signal, message, or mail information or error code. os_InRegs osEvent osWait (uint32_t millisec); - + #endif // Generic Wait available - - + + // ==== Timer Management Functions ==== - + /// Define a Timer object. /// \param name name of the timer object. /// \param function name of the timer call back function. @@ -549,19 +549,19 @@ static StaticTimer_t os_timer_cb_##name; \ const osTimerDef_t os_timer_def_##name = \ { (function), { NULL, 0U, (&os_timer_cb_##name), sizeof(StaticTimer_t) } } #endif - + /// Access a Timer definition. /// \param name name of the timer object. #define osTimer(name) \ &os_timer_def_##name - + /// Create and Initialize a timer. /// \param[in] timer_def timer object referenced with \ref osTimer. /// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. /// \param[in] argument argument to the timer call back function. /// \return timer ID for reference by other functions or NULL in case of error. osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument); - + /// Start or restart a timer. /// \param[in] timer_id timer ID obtained by \ref osTimerCreate. /// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer. @@ -569,24 +569,24 @@ osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void #if (osCMSIS < 0x20000U) osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); #endif - + /// Stop a timer. /// \param[in] timer_id timer ID obtained by \ref osTimerCreate. /// \return status code that indicates the execution status of the function. #if (osCMSIS < 0x20000U) osStatus osTimerStop (osTimerId timer_id); #endif - + /// Delete a timer. /// \param[in] timer_id timer ID obtained by \ref osTimerCreate. /// \return status code that indicates the execution status of the function. #if (osCMSIS < 0x20000U) osStatus osTimerDelete (osTimerId timer_id); #endif - - + + // ==== Mutex Management Functions ==== - + /// Define a Mutex. /// \param name name of the mutex object. #if defined (osObjectsExternal) // object is external @@ -598,17 +598,17 @@ static StaticSemaphore_t os_mutex_cb_##name; \ const osMutexDef_t os_mutex_def_##name = \ { NULL, osMutexRecursive | osMutexPrioInherit, (&os_mutex_cb_##name), sizeof(StaticSemaphore_t) } #endif - + /// Access a Mutex definition. /// \param name name of the mutex object. #define osMutex(name) \ &os_mutex_def_##name - + /// Create and Initialize a Mutex object. /// \param[in] mutex_def mutex definition referenced with \ref osMutex. /// \return mutex ID for reference by other functions or NULL in case of error. osMutexId osMutexCreate (const osMutexDef_t *mutex_def); - + /// Wait until a Mutex becomes available. /// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. /// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. @@ -618,26 +618,26 @@ osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); #else #define osMutexWait osMutexAcquire #endif - + /// Release a Mutex that was obtained by \ref osMutexWait. /// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. /// \return status code that indicates the execution status of the function. #if (osCMSIS < 0x20000U) osStatus osMutexRelease (osMutexId mutex_id); #endif - + /// Delete a Mutex object. /// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. /// \return status code that indicates the execution status of the function. #if (osCMSIS < 0x20000U) osStatus osMutexDelete (osMutexId mutex_id); #endif - - + + // ==== Semaphore Management Functions ==== - + #if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) // Semaphore available - + /// Define a Semaphore object. /// \param name name of the semaphore object. #if defined (osObjectsExternal) // object is external @@ -649,45 +649,45 @@ static StaticSemaphore_t os_semaphore_cb_##name; \ const osSemaphoreDef_t os_semaphore_def_##name = \ { NULL, 0U, (&os_semaphore_cb_##name), sizeof(StaticSemaphore_t) } #endif - + /// Access a Semaphore definition. /// \param name name of the semaphore object. #define osSemaphore(name) \ &os_semaphore_def_##name - + /// Create and Initialize a Semaphore object. /// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. /// \param[in] count maximum and initial number of available tokens. /// \return semaphore ID for reference by other functions or NULL in case of error. osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count); - + /// Wait until a Semaphore token becomes available. /// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. /// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. /// \return number of available tokens, or -1 in case of incorrect parameters. int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); - + /// Release a Semaphore token. /// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. /// \return status code that indicates the execution status of the function. #if (osCMSIS < 0x20000U) osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); #endif - + /// Delete a Semaphore object. /// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. /// \return status code that indicates the execution status of the function. #if (osCMSIS < 0x20000U) osStatus osSemaphoreDelete (osSemaphoreId semaphore_id); #endif - + #endif // Semaphore available - - + + // ==== Memory Pool Management Functions ==== #if (defined(osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool available - + /// \brief Define a Memory Pool. /// \param name name of the memory pool. /// \param no maximum number of blocks (objects) in the memory pool. @@ -700,40 +700,40 @@ extern const osPoolDef_t os_pool_def_##name const osPoolDef_t os_pool_def_##name = \ { (no), sizeof(type), {NULL} } #endif - + /// \brief Access a Memory Pool definition. /// \param name name of the memory pool #define osPool(name) \ &os_pool_def_##name - + /// Create and Initialize a Memory Pool object. /// \param[in] pool_def memory pool definition referenced with \ref osPool. /// \return memory pool ID for reference by other functions or NULL in case of error. osPoolId osPoolCreate (const osPoolDef_t *pool_def); - + /// Allocate a memory block from a Memory Pool. /// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. /// \return address of the allocated memory block or NULL in case of no memory available. void *osPoolAlloc (osPoolId pool_id); - + /// Allocate a memory block from a Memory Pool and set memory block to zero. /// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. /// \return address of the allocated memory block or NULL in case of no memory available. void *osPoolCAlloc (osPoolId pool_id); - + /// Return an allocated memory block back to a Memory Pool. /// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. /// \param[in] block address of the allocated memory block to be returned to the memory pool. /// \return status code that indicates the execution status of the function. osStatus osPoolFree (osPoolId pool_id, void *block); - + #endif // Memory Pool available - - + + // ==== Message Queue Management Functions ==== - + #if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queue available - + /// \brief Create a Message Queue Definition. /// \param name name of the queue. /// \param queue_sz maximum number of messages in the queue. @@ -750,38 +750,38 @@ const osMessageQDef_t os_messageQ_def_##name = \ { NULL, 0U, (&os_mq_cb_##name), sizeof(StaticQueue_t), \ (&os_mq_data_##name), sizeof(os_mq_data_##name) } } #endif - + /// \brief Access a Message Queue Definition. /// \param name name of the queue #define osMessageQ(name) \ &os_messageQ_def_##name - + /// Create and Initialize a Message Queue object. /// \param[in] queue_def message queue definition referenced with \ref osMessageQ. /// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. /// \return message queue ID for reference by other functions or NULL in case of error. osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id); - + /// Put a Message to a Queue. /// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. /// \param[in] info message information. /// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. /// \return status code that indicates the execution status of the function. osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); - + /// Get a Message from a Queue or timeout if Queue is empty. /// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. /// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. /// \return event information that includes status code. os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); - + #endif // Message Queue available - - + + // ==== Mail Queue Management Functions ==== - + #if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queue available - + /// \brief Create a Mail Queue Definition. /// \param name name of the queue. /// \param queue_sz maximum number of mails in the queue. @@ -794,53 +794,53 @@ extern const osMailQDef_t os_mailQ_def_##name const osMailQDef_t os_mailQ_def_##name = \ { (queue_sz), sizeof(type), NULL } #endif - + /// \brief Access a Mail Queue Definition. /// \param name name of the queue #define osMailQ(name) \ &os_mailQ_def_##name - + /// Create and Initialize a Mail Queue object. /// \param[in] queue_def mail queue definition referenced with \ref osMailQ. /// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. /// \return mail queue ID for reference by other functions or NULL in case of error. osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id); - + /// Allocate a memory block for mail from a mail memory pool. /// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. /// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out /// \return pointer to memory block that can be filled with mail or NULL in case of error. void *osMailAlloc (osMailQId queue_id, uint32_t millisec); - + /// Allocate a memory block for mail from a mail memory pool and set memory block to zero. /// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. /// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out /// \return pointer to memory block that can be filled with mail or NULL in case of error. void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); - + /// Put a Mail into a Queue. /// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. /// \param[in] mail pointer to memory with mail to put into a queue. /// \return status code that indicates the execution status of the function. osStatus osMailPut (osMailQId queue_id, const void *mail); - + /// Get a Mail from a Queue or timeout if Queue is empty. /// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. /// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. /// \return event information that includes status code. os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec); - + /// Free a memory block by returning it to a mail memory pool. /// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. /// \param[in] mail pointer to memory block that was obtained with \ref osMailGet. /// \return status code that indicates the execution status of the function. osStatus osMailFree (osMailQId queue_id, void *mail); - + #endif // Mail Queue available - - + + #ifdef __cplusplus } #endif - + #endif // CMSIS_OS_H_ diff --git a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c index 69ac328c..7c91f42b 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c +++ b/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c @@ -121,7 +121,7 @@ static osKernelState_t KernelState = osKernelInactive; HeapRegion_t array. */ #define HEAP_5_REGION_SETUP 1 - + #ifndef configHEAP_5_REGIONS #define configHEAP_5_REGIONS xHeapRegions @@ -1564,7 +1564,7 @@ osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, cons #endif } } - + #if (configQUEUE_REGISTRY_SIZE > 0) if (hSemaphore != NULL) { if (attr != NULL) { diff --git a/Middlewares/Third_Party/FreeRTOS/Source/LICENSE b/Middlewares/Third_Party/FreeRTOS/Source/LICENSE index 2ce47118..d2873092 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/LICENSE +++ b/Middlewares/Third_Party/FreeRTOS/Source/LICENSE @@ -15,4 +15,3 @@ FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/croutine.c b/Middlewares/Third_Party/FreeRTOS/Source/croutine.c index 9ce50030..91aedab4 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/croutine.c +++ b/Middlewares/Third_Party/FreeRTOS/Source/croutine.c @@ -350,4 +350,3 @@ BaseType_t xReturn; } #endif /* configUSE_CO_ROUTINES == 0 */ - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c b/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c index bf4ec246..dbf90911 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c +++ b/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c @@ -749,5 +749,3 @@ BaseType_t xWaitConditionMet = pdFALSE; #endif /* configUSE_TRACE_FACILITY */ /*-----------------------------------------------------------*/ - - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h b/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h index ceb469a7..256aca9f 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h @@ -1292,4 +1292,3 @@ typedef StaticStreamBuffer_t StaticMessageBuffer_t; #endif #endif /* INC_FREERTOS_H */ - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h b/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h index 56439917..b211e5a2 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h @@ -130,4 +130,3 @@ #endif /* STACK_MACROS_H */ - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h b/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h index 21657b9d..5b63246e 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h @@ -276,4 +276,3 @@ projects should not use them. */ #endif #endif /* DEPRECATED_DEFINITIONS_H */ - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h b/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h index a87fdf37..91083ec6 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h @@ -753,5 +753,3 @@ void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToCl #endif #endif /* EVENT_GROUPS_H */ - - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/list.h b/Middlewares/Third_Party/FreeRTOS/Source/include/list.h index a3e30249..5c9db047 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/list.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/list.h @@ -409,4 +409,3 @@ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTIO #endif #endif - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h index a21b7a66..482d37fe 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h @@ -157,4 +157,3 @@ StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeByt #endif /* MPU_PROTOTYPES_H */ - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h index 5f63d4f2..f6a4aafd 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h @@ -186,4 +186,3 @@ only for ports that are using the MPU. */ #endif /* MPU_WRAPPERS_H */ - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h b/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h index a2099c33..15d185db 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h @@ -196,4 +196,3 @@ void vPortEndScheduler( void ) PRIVILEGED_FUNCTION; #endif #endif /* PORTABLE_H */ - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h b/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h index 0d95130b..a237d9ee 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h @@ -119,6 +119,3 @@ itself. */ #endif /* PROJDEFS_H */ - - - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h b/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h index 52ccca55..c3afbda4 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h @@ -1652,4 +1652,3 @@ uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; #endif #endif /* QUEUE_H */ - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h b/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h index 787c7912..cfacf60b 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h @@ -1136,5 +1136,3 @@ typedef QueueHandle_t SemaphoreHandle_t; #define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) ) #endif /* SEMAPHORE_H */ - - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h b/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h index b5bac083..271b55f9 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h @@ -126,4 +126,3 @@ #endif /* STACK_MACROS_H */ - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/task.h b/Middlewares/Third_Party/FreeRTOS/Source/include/task.h index b0cc60b6..6fdbd244 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/task.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/task.h @@ -2538,6 +2538,3 @@ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNC } #endif #endif /* INC_TASK_H */ - - - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h b/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h index 307ea1f9..6dbc5458 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h @@ -1304,6 +1304,3 @@ BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommand } #endif #endif /* TIMERS_H */ - - - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/list.c b/Middlewares/Third_Party/FreeRTOS/Source/list.c index 7618ee8b..2b8a530f 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/list.c +++ b/Middlewares/Third_Party/FreeRTOS/Source/list.c @@ -195,4 +195,3 @@ List_t * const pxList = pxItemToRemove->pxContainer; return pxList->uxNumberOfItems; } /*-----------------------------------------------------------*/ - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c index eaf443f4..eee21160 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c +++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c @@ -489,4 +489,3 @@ size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY use } taskEXIT_CRITICAL(); } - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c index 6cd7542a..eecb15b5 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c +++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c @@ -784,5 +784,3 @@ __asm uint32_t vPortGetIPSR( void ) } #endif /* configASSERT_DEFINED */ - - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h index 2b07ff1d..0118a088 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h +++ b/Middlewares/Third_Party/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h @@ -195,7 +195,7 @@ static portFORCE_INLINE void vPortClearBASEPRIFromISR( void ) __asm { /* Set BASEPRI to 0 so no interrupts are masked. This function is only - used to lower the mask in an interrupt, so memory barriers are not + used to lower the mask in an interrupt, so memory barriers are not used. */ msr basepri, #0 } @@ -249,4 +249,3 @@ BaseType_t xReturn; #endif #endif /* PORTMACRO_H */ - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/queue.c b/Middlewares/Third_Party/FreeRTOS/Source/queue.c index b3203b80..b880f108 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/queue.c +++ b/Middlewares/Third_Party/FreeRTOS/Source/queue.c @@ -1082,7 +1082,7 @@ Queue_t * const pxQueue = xQueue; { mtCOVERAGE_TEST_MARKER(); } - + /* Not used in this path. */ ( void ) uxPreviousMessagesWaiting; } @@ -2931,15 +2931,3 @@ Queue_t * const pxQueue = xQueue; } #endif /* configUSE_QUEUE_SETS */ - - - - - - - - - - - - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/tasks.c b/Middlewares/Third_Party/FreeRTOS/Source/tasks.c index f6a6a9b4..72a7d6f5 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/tasks.c +++ b/Middlewares/Third_Party/FreeRTOS/Source/tasks.c @@ -5306,5 +5306,3 @@ when performing module tests). */ #endif #endif - - diff --git a/Middlewares/Third_Party/FreeRTOS/Source/timers.c b/Middlewares/Third_Party/FreeRTOS/Source/timers.c index 00200b8f..d9df6614 100644 --- a/Middlewares/Third_Party/FreeRTOS/Source/timers.c +++ b/Middlewares/Third_Party/FreeRTOS/Source/timers.c @@ -1122,6 +1122,3 @@ Timer_t * const pxTimer = xTimer; to include software timer functionality. If you want to include software timer functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */ #endif /* configUSE_TIMERS == 1 */ - - - diff --git a/Src/dma.c b/Src/dma.c index 9b224df3..6c6122ae 100644 --- a/Src/dma.c +++ b/Src/dma.c @@ -68,4 +68,3 @@ void MX_DMA_Init(void) /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ - diff --git a/Src/freertos.c b/Src/freertos.c index 4e60452a..d3ecac37 100644 --- a/Src/freertos.c +++ b/Src/freertos.c @@ -320,4 +320,3 @@ void StartUiTask(void *argument) /* USER CODE BEGIN Application */ /* USER CODE END Application */ - diff --git a/Src/i2c.c b/Src/i2c.c index 15e409b1..fd22ebf5 100644 --- a/Src/i2c.c +++ b/Src/i2c.c @@ -114,4 +114,3 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle) /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ - diff --git a/Src/spi.c b/Src/spi.c index bd35db96..c875b811 100644 --- a/Src/spi.c +++ b/Src/spi.c @@ -297,4 +297,3 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle) /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ - diff --git a/Src/stm32f4xx_hal_timebase_tim.c b/Src/stm32f4xx_hal_timebase_tim.c index 4116faf9..1b245c97 100644 --- a/Src/stm32f4xx_hal_timebase_tim.c +++ b/Src/stm32f4xx_hal_timebase_tim.c @@ -135,4 +135,3 @@ void HAL_ResumeTick(void) /* Enable TIM7 Update interrupt */ __HAL_TIM_ENABLE_IT(&htim7, TIM_IT_UPDATE); } - diff --git a/Src/system_stm32f4xx.c b/Src/system_stm32f4xx.c index 7a61e9cf..c7071c06 100644 --- a/Src/system_stm32f4xx.c +++ b/Src/system_stm32f4xx.c @@ -4,16 +4,16 @@ * @author MCD Application Team * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * - * This file provides two functions and one global variable to be called from + * This file provides two functions and one global variable to be called from * user application: - * - SystemInit(): This function is called at startup just after reset and + * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32f4xx.s" file. * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick + * by the user application to setup the SysTick * timer or configure other parameters. - * + * * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * be called whenever the core clock is changed * during program execution. @@ -38,8 +38,8 @@ /** @addtogroup stm32f4xx_system * @{ - */ - + */ + /** @addtogroup STM32F4xx_System_Private_Includes * @{ */ @@ -47,7 +47,7 @@ #include "stm32f4xx.h" -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ #endif /* HSE_VALUE */ @@ -79,7 +79,7 @@ /* #define DATA_IN_ExtSRAM */ #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ STM32F412Zx || STM32F412Vx */ - + #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* #define DATA_IN_ExtSDRAM */ @@ -129,7 +129,7 @@ /* This variable is updated in three ways: 1) by calling CMSIS function SystemCoreClockUpdate() 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency Note: If you use this function to configure the system clock; then there is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. @@ -146,7 +146,7 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; */ #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) - static void SystemInit_ExtMemCtl(void); + static void SystemInit_ExtMemCtl(void); #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ /** @@ -159,7 +159,7 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; /** * @brief Setup the microcontroller system - * Initialize the FPU setting, vector table location and External memory + * Initialize the FPU setting, vector table location and External memory * configuration. * @param None * @retval None @@ -172,7 +172,7 @@ void SystemInit(void) #endif #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) - SystemInit_ExtMemCtl(); + SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ /* Configure the Vector Table location -------------------------------------*/ @@ -186,41 +186,41 @@ void SystemInit(void) * The SystemCoreClock variable contains the core clock (HCLK), it can * be used by the user application to setup the SysTick timer or configure * other parameters. - * + * * @note Each time the core clock (HCLK) changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: - * + * * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * + * * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * + * * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * + * in voltage and temperature. + * * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value * depends on the application requirements), user has to ensure that HSE_VALUE * is same as the real frequency of the crystal used. Otherwise, this function * may have wrong result. - * + * * - The result of this function could be not correct when using fractional * value for HSE crystal. - * + * * @param None * @retval None */ void SystemCoreClockUpdate(void) { uint32_t tmp, pllvco, pllp, pllsource, pllm; - + /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; @@ -236,10 +236,10 @@ void SystemCoreClockUpdate(void) /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N SYSCLK = PLL_VCO / PLL_P - */ + */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - + if (pllsource != 0) { /* HSE used as PLL clock source */ @@ -288,79 +288,79 @@ void SystemInit_ExtMemCtl(void) /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); - + /* Connect PDx pins to FMC Alternate function */ GPIOD->AFR[0] = 0x00CCC0CC; GPIOD->AFR[1] = 0xCCCCCCCC; - /* Configure PDx pins in Alternate function mode */ + /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xAAAA0A8A; - /* Configure PDx pins speed to 100 MHz */ + /* Configure PDx pins speed to 100 MHz */ GPIOD->OSPEEDR = 0xFFFF0FCF; - /* Configure PDx pins Output type to push-pull */ + /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ + /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FMC Alternate function */ GPIOE->AFR[0] = 0xC00CC0CC; GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ + /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xAAAA828A; - /* Configure PEx pins speed to 100 MHz */ + /* Configure PEx pins speed to 100 MHz */ GPIOE->OSPEEDR = 0xFFFFC3CF; - /* Configure PEx pins Output type to push-pull */ + /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ + /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; - + /* Connect PFx pins to FMC Alternate function */ GPIOF->AFR[0] = 0xCCCCCCCC; GPIOF->AFR[1] = 0xCCCCCCCC; - /* Configure PFx pins in Alternate function mode */ + /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xAA800AAA; - /* Configure PFx pins speed to 50 MHz */ + /* Configure PFx pins speed to 50 MHz */ GPIOF->OSPEEDR = 0xAA800AAA; - /* Configure PFx pins Output type to push-pull */ + /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ + /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FMC Alternate function */ GPIOG->AFR[0] = 0xCCCCCCCC; GPIOG->AFR[1] = 0xCCCCCCCC; - /* Configure PGx pins in Alternate function mode */ + /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0xAAAAAAAA; - /* Configure PGx pins speed to 50 MHz */ + /* Configure PGx pins speed to 50 MHz */ GPIOG->OSPEEDR = 0xAAAAAAAA; - /* Configure PGx pins Output type to push-pull */ + /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ + /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; - + /* Connect PHx pins to FMC Alternate function */ GPIOH->AFR[0] = 0x00C0CC00; GPIOH->AFR[1] = 0xCCCCCCCC; - /* Configure PHx pins in Alternate function mode */ + /* Configure PHx pins in Alternate function mode */ GPIOH->MODER = 0xAAAA08A0; - /* Configure PHx pins speed to 50 MHz */ + /* Configure PHx pins speed to 50 MHz */ GPIOH->OSPEEDR = 0xAAAA08A0; - /* Configure PHx pins Output type to push-pull */ + /* Configure PHx pins Output type to push-pull */ GPIOH->OTYPER = 0x00000000; - /* No pull-up, pull-down for PHx pins */ + /* No pull-up, pull-down for PHx pins */ GPIOH->PUPDR = 0x00000000; - + /* Connect PIx pins to FMC Alternate function */ GPIOI->AFR[0] = 0xCCCCCCCC; GPIOI->AFR[1] = 0x00000CC0; - /* Configure PIx pins in Alternate function mode */ + /* Configure PIx pins in Alternate function mode */ GPIOI->MODER = 0x0028AAAA; - /* Configure PIx pins speed to 50 MHz */ + /* Configure PIx pins speed to 50 MHz */ GPIOI->OSPEEDR = 0x0028AAAA; - /* Configure PIx pins Output type to push-pull */ + /* Configure PIx pins Output type to push-pull */ GPIOI->OTYPER = 0x00000000; - /* No pull-up, pull-down for PIx pins */ + /* No pull-up, pull-down for PIx pins */ GPIOI->PUPDR = 0x00000000; - + /*-- FMC Configuration -------------------------------------------------------*/ /* Enable the FMC interface clock */ RCC->AHB3ENR |= 0x00000001; @@ -368,53 +368,53 @@ void SystemInit_ExtMemCtl(void) tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); FMC_Bank5_6->SDCR[0] = 0x000019E4; - FMC_Bank5_6->SDTR[0] = 0x01115351; - + FMC_Bank5_6->SDTR[0] = 0x01115351; + /* SDRAM initialization sequence */ /* Clock enable command */ - FMC_Bank5_6->SDCMR = 0x00000011; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } /* Delay */ for (index = 0; index<1000; index++); - + /* PALL command */ - FMC_Bank5_6->SDCMR = 0x00000012; + FMC_Bank5_6->SDCMR = 0x00000012; tmpreg = FMC_Bank5_6->SDSR & 0x00000020; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } - + /* Auto refresh command */ FMC_Bank5_6->SDCMR = 0x00000073; tmpreg = FMC_Bank5_6->SDSR & 0x00000020; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } - + /* MRD register program */ FMC_Bank5_6->SDCMR = 0x00046014; tmpreg = FMC_Bank5_6->SDSR & 0x00000020; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + /* Set refresh count */ tmpreg = FMC_Bank5_6->SDRTR; FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); - + /* Disable write protection */ - tmpreg = FMC_Bank5_6->SDCR[0]; + tmpreg = FMC_Bank5_6->SDCR[0]; FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) @@ -422,7 +422,7 @@ void SystemInit_ExtMemCtl(void) FMC_Bank1->BTCR[2] = 0x00001011; FMC_Bank1->BTCR[3] = 0x00000201; FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ #if defined(STM32F469xx) || defined(STM32F479xx) /* Configure and enable Bank1_SRAM2 */ FMC_Bank1->BTCR[2] = 0x00001091; @@ -430,7 +430,7 @@ void SystemInit_ExtMemCtl(void) FMC_Bank1E->BWTR[2] = 0x0fffffff; #endif /* STM32F469xx || STM32F479xx */ - (void)(tmp); + (void)(tmp); } #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) @@ -456,13 +456,13 @@ void SystemInit_ExtMemCtl(void) clock */ RCC->AHB1ENR |= 0x0000007D; #else - /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ RCC->AHB1ENR |= 0x000001F8; -#endif /* STM32F446xx */ +#endif /* STM32F446xx */ /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); - + #if defined(STM32F446xx) /* Connect PAx pins to FMC Alternate function */ GPIOA->AFR[0] |= 0xC0000000; @@ -492,78 +492,78 @@ void SystemInit_ExtMemCtl(void) /* Connect PDx pins to FMC Alternate function */ GPIOD->AFR[0] = 0x000000CC; GPIOD->AFR[1] = 0xCC000CCC; - /* Configure PDx pins in Alternate function mode */ + /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xA02A000A; - /* Configure PDx pins speed to 50 MHz */ + /* Configure PDx pins speed to 50 MHz */ GPIOD->OSPEEDR = 0xA02A000A; - /* Configure PDx pins Output type to push-pull */ + /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ + /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FMC Alternate function */ GPIOE->AFR[0] = 0xC00000CC; GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ + /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xAAAA800A; - /* Configure PEx pins speed to 50 MHz */ + /* Configure PEx pins speed to 50 MHz */ GPIOE->OSPEEDR = 0xAAAA800A; - /* Configure PEx pins Output type to push-pull */ + /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ + /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; /* Connect PFx pins to FMC Alternate function */ GPIOF->AFR[0] = 0xCCCCCCCC; GPIOF->AFR[1] = 0xCCCCCCCC; - /* Configure PFx pins in Alternate function mode */ + /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xAA800AAA; - /* Configure PFx pins speed to 50 MHz */ + /* Configure PFx pins speed to 50 MHz */ GPIOF->OSPEEDR = 0xAA800AAA; - /* Configure PFx pins Output type to push-pull */ + /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ + /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FMC Alternate function */ GPIOG->AFR[0] = 0xCCCCCCCC; GPIOG->AFR[1] = 0xCCCCCCCC; - /* Configure PGx pins in Alternate function mode */ + /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0xAAAAAAAA; - /* Configure PGx pins speed to 50 MHz */ + /* Configure PGx pins speed to 50 MHz */ GPIOG->OSPEEDR = 0xAAAAAAAA; - /* Configure PGx pins Output type to push-pull */ + /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ + /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ - || defined(STM32F469xx) || defined(STM32F479xx) + || defined(STM32F469xx) || defined(STM32F479xx) /* Connect PHx pins to FMC Alternate function */ GPIOH->AFR[0] = 0x00C0CC00; GPIOH->AFR[1] = 0xCCCCCCCC; - /* Configure PHx pins in Alternate function mode */ + /* Configure PHx pins in Alternate function mode */ GPIOH->MODER = 0xAAAA08A0; - /* Configure PHx pins speed to 50 MHz */ + /* Configure PHx pins speed to 50 MHz */ GPIOH->OSPEEDR = 0xAAAA08A0; - /* Configure PHx pins Output type to push-pull */ + /* Configure PHx pins Output type to push-pull */ GPIOH->OTYPER = 0x00000000; - /* No pull-up, pull-down for PHx pins */ + /* No pull-up, pull-down for PHx pins */ GPIOH->PUPDR = 0x00000000; - + /* Connect PIx pins to FMC Alternate function */ GPIOI->AFR[0] = 0xCCCCCCCC; GPIOI->AFR[1] = 0x00000CC0; - /* Configure PIx pins in Alternate function mode */ + /* Configure PIx pins in Alternate function mode */ GPIOI->MODER = 0x0028AAAA; - /* Configure PIx pins speed to 50 MHz */ + /* Configure PIx pins speed to 50 MHz */ GPIOI->OSPEEDR = 0x0028AAAA; - /* Configure PIx pins Output type to push-pull */ + /* Configure PIx pins Output type to push-pull */ GPIOI->OTYPER = 0x00000000; - /* No pull-up, pull-down for PIx pins */ + /* No pull-up, pull-down for PIx pins */ GPIOI->PUPDR = 0x00000000; #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - + /*-- FMC Configuration -------------------------------------------------------*/ /* Enable the FMC interface clock */ RCC->AHB3ENR |= 0x00000001; @@ -573,68 +573,68 @@ void SystemInit_ExtMemCtl(void) /* Configure and enable SDRAM bank1 */ #if defined(STM32F446xx) FMC_Bank5_6->SDCR[0] = 0x00001954; -#else +#else FMC_Bank5_6->SDCR[0] = 0x000019E4; #endif /* STM32F446xx */ - FMC_Bank5_6->SDTR[0] = 0x01115351; - + FMC_Bank5_6->SDTR[0] = 0x01115351; + /* SDRAM initialization sequence */ /* Clock enable command */ - FMC_Bank5_6->SDCMR = 0x00000011; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } /* Delay */ for (index = 0; index<1000; index++); - + /* PALL command */ - FMC_Bank5_6->SDCMR = 0x00000012; + FMC_Bank5_6->SDCMR = 0x00000012; tmpreg = FMC_Bank5_6->SDSR & 0x00000020; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } - + /* Auto refresh command */ #if defined(STM32F446xx) FMC_Bank5_6->SDCMR = 0x000000F3; -#else +#else FMC_Bank5_6->SDCMR = 0x00000073; #endif /* STM32F446xx */ tmpreg = FMC_Bank5_6->SDSR & 0x00000020; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } - + /* MRD register program */ #if defined(STM32F446xx) FMC_Bank5_6->SDCMR = 0x00044014; -#else +#else FMC_Bank5_6->SDCMR = 0x00046014; #endif /* STM32F446xx */ tmpreg = FMC_Bank5_6->SDSR & 0x00000020; timeout = 0xFFFF; while((tmpreg != 0) && (timeout-- > 0)) { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + /* Set refresh count */ tmpreg = FMC_Bank5_6->SDRTR; #if defined(STM32F446xx) FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); -#else +#else FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); #endif /* STM32F446xx */ - + /* Disable write protection */ - tmpreg = FMC_Bank5_6->SDCR[0]; + tmpreg = FMC_Bank5_6->SDCR[0]; FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); #endif /* DATA_IN_ExtSDRAM */ #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ @@ -649,55 +649,55 @@ void SystemInit_ExtMemCtl(void) RCC->AHB1ENR |= 0x00000078; /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); - + /* Connect PDx pins to FMC Alternate function */ GPIOD->AFR[0] = 0x00CCC0CC; GPIOD->AFR[1] = 0xCCCCCCCC; - /* Configure PDx pins in Alternate function mode */ + /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xAAAA0A8A; - /* Configure PDx pins speed to 100 MHz */ + /* Configure PDx pins speed to 100 MHz */ GPIOD->OSPEEDR = 0xFFFF0FCF; - /* Configure PDx pins Output type to push-pull */ + /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ + /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FMC Alternate function */ GPIOE->AFR[0] = 0xC00CC0CC; GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ + /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xAAAA828A; - /* Configure PEx pins speed to 100 MHz */ + /* Configure PEx pins speed to 100 MHz */ GPIOE->OSPEEDR = 0xFFFFC3CF; - /* Configure PEx pins Output type to push-pull */ + /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ + /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; /* Connect PFx pins to FMC Alternate function */ GPIOF->AFR[0] = 0x00CCCCCC; GPIOF->AFR[1] = 0xCCCC0000; - /* Configure PFx pins in Alternate function mode */ + /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xAA000AAA; - /* Configure PFx pins speed to 100 MHz */ + /* Configure PFx pins speed to 100 MHz */ GPIOF->OSPEEDR = 0xFF000FFF; - /* Configure PFx pins Output type to push-pull */ + /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ + /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FMC Alternate function */ GPIOG->AFR[0] = 0x00CCCCCC; GPIOG->AFR[1] = 0x000000C0; - /* Configure PGx pins in Alternate function mode */ + /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0x00085AAA; - /* Configure PGx pins speed to 100 MHz */ + /* Configure PGx pins speed to 100 MHz */ GPIOG->OSPEEDR = 0x000CAFFF; - /* Configure PGx pins Output type to push-pull */ + /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ + /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; - + /*-- FMC/FSMC Configuration --------------------------------------------------*/ /* Enable the FMC/FSMC interface clock */ RCC->AHB3ENR |= 0x00000001; @@ -709,7 +709,7 @@ void SystemInit_ExtMemCtl(void) FMC_Bank1->BTCR[2] = 0x00001011; FMC_Bank1->BTCR[3] = 0x00000201; FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ #if defined(STM32F469xx) || defined(STM32F479xx) /* Delay after an RCC peripheral clock enabling */ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); @@ -730,8 +730,8 @@ void SystemInit_ExtMemCtl(void) #endif /* DATA_IN_ExtSRAM */ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ - STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ - (void)(tmp); + STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ + (void)(tmp); } #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ /** diff --git a/Src/usart.c b/Src/usart.c index 38b3f8b3..eff7555d 100644 --- a/Src/usart.c +++ b/Src/usart.c @@ -483,4 +483,3 @@ int fputc(int ch, FILE *f) return ch; } /* USER CODE END 1 */ - diff --git a/docs/嵌入式C语言代码规范（V1.0）.md b/docs/嵌入式C语言代码规范（V1.0）.md index 3f423ee7..91cb4ceb 100644 --- a/docs/嵌入式C语言代码规范（V1.0）.md +++ b/docs/嵌入式C语言代码规范（V1.0）.md @@ -204,11 +204,11 @@ for(i=0;i<10;i++){ ```c int calculate_sum(int a, int b, int c, int d) { int sum; - - sum = a + b - + c + + sum = a + b + + c + d; - + return sum; } ``` @@ -272,7 +272,7 @@ while (1) ; void delay_ms(unsigned int ms) { unsigned int i; unsigned int j; - + for (i = 0; i < ms; i++) { for (j = 0; j < 123; j++) { } @@ -302,12 +302,12 @@ uint16_t crc_calculate(uint8_t *data, uint16_t length) uint16_t crc = 0xFFFF; uint16_t i; uint16_t j; - + /* 遍历所有数据字节 */ for (i = 0; i < length; i++) { /* 将当前字节与CRC寄存器低8位异或 */ crc ^= data[i]; - + /* 对每个位进行处理 */ for (j = 0; j < 8; j++) { /* 检查最低位是否为1 */ @@ -320,7 +320,7 @@ uint16_t crc_calculate(uint8_t *data, uint16_t length) } } } - + /* 返回计算得到的CRC值 */ return crc; } @@ -338,14 +338,14 @@ void function(void) { uint8_t status = 0; uint16_t count = 0; uint8_t *p_data = NULL; - + p_data = (uint8_t *)malloc(100); if (p_data == NULL) { return; } - + /* 使用p_data */ - + free(p_data); p_data = NULL; } @@ -372,11 +372,11 @@ switch (command) { case COMMAND_START: start_process(); break; - + case COMMAND_STOP: stop_process(); break; - + default: handle_unknown_command(); break; @@ -395,13 +395,13 @@ uint8_t uart_send_data(uint8_t *data, uint16_t length) { if (data == NULL) { return UART_STATUS_ERROR; } - + if (length == 0 || length > UART_BUFFER_SIZE) { return UART_STATUS_ERROR; } - + /* 发送数据 */ - + return UART_STATUS_OK; } ``` @@ -492,4 +492,4 @@ uint8_t led_toggle(uint8_t led_num); #endif #endif /* __LED_H */ -``` \ No newline at end of file +``` diff --git a/docs/测试文档模板规范.md b/docs/测试文档模板规范.md index d981af09..86bc33a8 100644 --- a/docs/测试文档模板规范.md +++ b/docs/测试文档模板规范.md @@ -218,4 +218,4 @@ DP-{NN} | 原则 | 覆盖用例 | |------|----------| -``` +``` diff --git a/docs/测试说明/GD5F2GQ5UE_Test_Guide.md b/docs/测试说明/GD5F2GQ5UE_Test_Guide.md index d1ff06ac..562068c0 100644 --- a/docs/测试说明/GD5F2GQ5UE_Test_Guide.md +++ b/docs/测试说明/GD5F2GQ5UE_Test_Guide.md @@ -738,4 +738,3 @@ ECC 状态（`ECCS1:ECCS0`）：`00`=无错；`01/10/11`=纠正 1/2/3 bit；`10` | Feature 寄存器 | 0xB0；ECC_EN=4, QE=0 | | Protect 寄存器 | 0xA0；init 后写 0x00 解除保护 | | SPI 引脚 | CS=PE0, SCK=PB3, MISO=PB4, MOSI=PB5, WP=PB8, HOLD=PE1 | - diff --git a/docs/芯片手册/CH395F.md b/docs/芯片手册/CH395F.md index 829a0ab5..ab495fb4 100644 --- a/docs/芯片手册/CH395F.md +++ b/docs/芯片手册/CH395F.md @@ -1363,4 +1363,4 @@ T1 是 ethernet 网络变压器，其中心抽头分别通过电容 C8 和 C9 CH395P 可通过 J2、J3 跳线帽选择所需通信接口。关于接口配置详参 6.1 章节。 -从 CH395L 升级到 CH395P，虽然两者引脚基本兼容，但网络变压器等外围电路连接可能需要调整，具体改动请参考 WCH 官方论坛相关文章或联系技术支持。 \ No newline at end of file +从 CH395L 升级到 CH395P，虽然两者引脚基本兼容，但网络变压器等外围电路连接可能需要调整，具体改动请参考 WCH 官方论坛相关文章或联系技术支持。 diff --git a/docs/芯片手册/GD5F2GQ5UExxG.md b/docs/芯片手册/GD5F2GQ5UExxG.md index 4196cefb..196cfa06 100644 --- a/docs/芯片手册/GD5F2GQ5UExxG.md +++ b/docs/芯片手册/GD5F2GQ5UExxG.md @@ -68,13 +68,13 @@ ## 9 PROGRAM OPERATIONS.... ..38 -9.1 PAGE PROGRAM ........ .... 38 -9.2 PROGRAM LOAD (PL) (02H)... .. 39 -9.3 PROGRAM LOAD X4 (PL X4) (32H) ...... -9.4 PROGRAM EXECUTE (PE) (10H) . . 41 -9.5 PROGRAM EXECUTE BACKGROUND (10H + ADDRESS + 15H).. ..... 42 -9.6 INTERNAL DATA MOVE .. . 44 -9.7 PROGRAM LOAD RANDOM DATA (84H) ..... ...... 45 +9.1 PAGE PROGRAM ........ .... 38 +9.2 PROGRAM LOAD (PL) (02H)... .. 39 +9.3 PROGRAM LOAD X4 (PL X4) (32H) ...... +9.4 PROGRAM EXECUTE (PE) (10H) . . 41 +9.5 PROGRAM EXECUTE BACKGROUND (10H + ADDRESS + 15H).. ..... 42 +9.6 INTERNAL DATA MOVE .. . 44 +9.7 PROGRAM LOAD RANDOM DATA (84H) ..... ...... 45 9.8 PROGRAM LOAD RANDOM DATA X4 (C4H/34H)...... ...... 46 ## 10 ERASE OPERATIONS .. ..47 @@ -83,16 +83,16 @@ ## 11 RESET OPERATIONS..... -11.1 SOFT RESET (FFH) . .. 48 +11.1 SOFT RESET (FFH) . .. 48 11.2 ENABLE POWER ON RESET (66H) AND POWER ON RESET (99H).. ..... 49 ## 12 FEATURE OPERATIONS...... .50 -12.1 GET FEATURES (0FH) AND SET FEATURES (1FH) . . 50 -12.2 STATUS REGISTER AND DRIVER REGISTER.. . 53 -12.3 OTP REGION....... .... 54 -12.4 ASSISTANT BAD BLOCK MANAGEMENT ... .. 55 -12.5 BLOCK PROTECTION.. .. 56 +12.1 GET FEATURES (0FH) AND SET FEATURES (1FH) . . 50 +12.2 STATUS REGISTER AND DRIVER REGISTER.. . 53 +12.3 OTP REGION....... .... 54 +12.4 ASSISTANT BAD BLOCK MANAGEMENT ... .. 55 +12.5 BLOCK PROTECTION.. .. 56 12.6 INTERNAL ECC.. . 57 ## 13 POWER ON TIMING..... .59 @@ -109,7 +109,7 @@ ## 19 ORDERING INFORMATION... ...66 -20 PACKAGE INFORMATION..... ....67 +20 PACKAGE INFORMATION..... ....67 REVISION HISTORY .... ....70 ## 1 FEATURE @@ -202,15 +202,15 @@ Note: (1) ECC is on default, which can be disable by user. SPI (Serial Peripheral Interface) NAND Flash provides an ultra-cost effective while high density non-volatile memory storage solution for embedded systems, based on an industry-standard NAND Flash memory core. It is an attractive alternative to SPI-NOR and standard parallel NAND Flash, with advanced features. -• Total pin count is 8, including VCC and GND -• Density 2Gb -• Superior write performance and cost per bit over SPI-NOR +• Total pin count is 8, including VCC and GND +• Density 2Gb +• Superior write performance and cost per bit over SPI-NOR • Significant low cost than parallel NAND This low-pin-count NAND Flash memory follows the industry-standard serial peripheral interface, and always remains the same pin out from one density to another. The command sets resemble common SPI-NOR command sets, modified to handle NAND specific functions and added new features. GigaDevice SPI NAND is an easy-to-integrate NAND Flash memory, with specified designed features to ease host management: -• User-selectable internal ECC. ECC parity is generated internally during a page program operation. When a page is read to the cache register, the ECC parity is detected and corrects the errors when necessary. The device outputs corrected data and returns an ECC error status. -• Internal data move or copy back with internal ECC. The device can be easily refreshed and manage garbage collection task, without need of shift in and out of data. This command string can only be used on blocks with the same parity attribute. +• User-selectable internal ECC. ECC parity is generated internally during a page program operation. When a page is read to the cache register, the ECC parity is detected and corrects the errors when necessary. The device outputs corrected data and returns an ECC error status. +• Internal data move or copy back with internal ECC. The device can be easily refreshed and manage garbage collection task, without need of shift in and out of data. This command string can only be used on blocks with the same parity attribute. • Power on Read with internal ECC. The device will automatically read first page of fist block to cache after power on, then host can directly read data from cache for easy boot. Also the data is promised correct by internal ECC when ECC enabled. It is programmed and read in page-based operations, and erased in block-based operations. Data is transferred to or from the NAND Flash memory array, page by page, to a data register and a cache register. The cache register is closest to I/O control circuits and acts as a data buffer for the I/O data; the data register is closest to the memory array and acts as a data buffer for the NAND Flash memory array operation. The cache register functions as the buffer memory to enable page and random data READ/WRITE and copy back operations. These devices also use a SPI status register that reports the status of device operation. @@ -225,7 +225,7 @@ Note: (1) Industrial+: F grade has implemented additional test flows to ensure h ## 2.2 CONNECTION DIAGRAM -Figure 2-1.Connect Diagram +Figure 2-1.Connect Diagram ![](images/aabcb50ecd150cac1381cae03d26d2043e276d1247bf7ba20937e6ab3390da9f.jpg) ![](images/b196abbdc8befa63ccd45faeb7c5c8adae6ca3a07fa73a08d3dce0ccd02f3d92.jpg) @@ -254,13 +254,13 @@ NC NC NC NC
Pin NameI/ODescription
CS#IChip Select input, active low
SO/SIO1I/OSerial Data Output / Serial Data Input Output 1
WP#/SIO2I/OWrite Protect, active low / Serial Data Input Output 2
VSSGroundGround
SI/SIO0I/OSerial Data Input / Serial Data Input Output 0
SCLKISerial Clock input
HOLD#/SIO3I/OHold Input/Serial Data Input Output 3
DQS (only for BGA24)OData Strobe Signal Output
VCCSupplyPower Supply
NCNot Connect, Not internal connection; can be driven or floated.
-Note： -1. CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on. +Note： +1. CS# must be driven high if chip is not selected. Please don’t leave CS# floating any time after power is on. 2. If the DQS Function is not used, this pin must be floating. ## 2.4 BLOCK DIAGRAM -Figure 2-2.Block Diagram +Figure 2-2.Block Diagram ![](images/ceba4f83b170efebf3759e0c718679d5ae2af33e9bea308e57867c09d42e091a.jpg)
@@ -285,7 +285,7 @@ graph TD ## 3 MEMORY MAPPING -For 2G +For 2G ![](images/f3958476281234049cbc69364b427e40440d9777400cec28188cdaf1e02c88dc.jpg)
@@ -315,8 +315,8 @@ graph LR ```
-Note: -1. CA: Column Address. The 12-bit address is capable of addressing from 0 to 4095 bytes; however, only bytes 0 through 2175 are valid. Bytes 2176 through 4095 of each page are “out of bounds,” do not exist in the device, and cannot be addressed. +Note: +1. CA: Column Address. The 12-bit address is capable of addressing from 0 to 4095 bytes; however, only bytes 0 through 2175 are valid. Bytes 2176 through 4095 of each page are “out of bounds,” do not exist in the device, and cannot be addressed. 2. RA: Row Address. RA<5:0>selects a page inside a block, and RA<16:6>selects a block. ## 4 ARRAY ORGANIZATION @@ -372,7 +372,7 @@ Internal ECC = ON ## Note: -1.When Internal ECC is enabled，user can program the first 64 bytes of the entire 128 bytes spare area and the last 64 bytes of the whole spare area cannot be programed，user can read the entire 128 Byte spare area. +1.When Internal ECC is enabled，user can program the first 64 bytes of the entire 128 bytes spare area and the last 64 bytes of the whole spare area cannot be programed，user can read the entire 128 Byte spare area. 2.When Internal ECC is disabled，user can read and program the entire 128 bytes spare area. ## 5 DEVICE OPERATION @@ -381,15 +381,15 @@ Internal ECC = ON SPI NAND supports two SPI modes: -• CPOL = 0, CPHA = 0 (Mode 0) +• CPOL = 0, CPHA = 0 (Mode 0) • CPOL = 1, CPHA = 1 (Mode 3) Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK for both modes. All timing diagrams shown in this data sheet are mode 0. See Figure5-1 for more details. -Figure 5-1. SPI Modes Timing Diagram -![](images/5adddb568ef448df4679e84c8dbeb3c7ac66462b4314ad576c31571a21816932.jpg) -Note: While CS# is HIGH, keep SCLK at VCC or GND (determined by mode 0 or mode 3). Do not toggle SCLK until CS# is driven LOW. -We recommend that the user pull CS# to high when user don’t use SPI flash, otherwise the flash is always in the read state, which is not good for flash. +Figure 5-1. SPI Modes Timing Diagram +![](images/5adddb568ef448df4679e84c8dbeb3c7ac66462b4314ad576c31571a21816932.jpg) +Note: While CS# is HIGH, keep SCLK at VCC or GND (determined by mode 0 or mode 3). Do not toggle SCLK until CS# is driven LOW. +We recommend that the user pull CS# to high when user don’t use SPI flash, otherwise the flash is always in the read state, which is not good for flash. When CS# is high and SCLK at VCC or GND state, the device is in idle state. ## Standard SPI @@ -420,7 +420,7 @@ The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and then CS# must be at low. -Figure5-2. Hold Condition +Figure5-2. Hold Condition ![](images/26cc48d89db717a20fc4ba65d779836eafd444f616474db40cd1a1f0f15f8085.jpg)
@@ -451,8 +451,8 @@ Table 6-1. Commands Set ## Note: -1. The dummy has 8 clock. -03H/0BH/3BH/6BH has 1 byte dummy. BBH has 2 bytes dummy. +1. The dummy has 8 clock. +03H/0BH/3BH/6BH has 1 byte dummy. BBH has 2 bytes dummy. EBH has 4 bytes dummy. EEH has 8 bytes dummy. 2. The A15-A0 (03H/0BH/3BH/6BH) has 16 clock, include 4 clock dummy. @@ -463,12 +463,12 @@ The A15-A0 (EBH) has 4 clock, include 1 clock dummy. The A31-A0 (EEH) has 4 clock, include 2.5 clock dummy. -3. The A15-A0 has 16 clock, include 4 clock dummy. -4. MID is Manufacture ID (C8h for GigaDevice), DID is Device ID. +3. The A15-A0 has 16 clock, include 4 clock dummy. +4. MID is Manufacture ID (C8h for GigaDevice), DID is Device ID. 5. Reset command: -• Reset will reset PAGE READ/PROGRAM/ERASE operation. -• Reset will reset status register bits P\_FAIL/E\_FAIL/WEL/OIP/CBSY/ECCS/ECCSE. +• Reset will reset PAGE READ/PROGRAM/ERASE operation. +• Reset will reset status register bits P\_FAIL/E\_FAIL/WEL/OIP/CBSY/ECCS/ECCSE. 6. Power on reset: Retrieve status register and data in cache to power on status. @@ -481,13 +481,13 @@ Retrieve status register and data in cache to power on status. The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to following operations that change the contents of the memory array: -• Page program -• OTP program/OTP protection +• Page program +• OTP program/OTP protection • Block erase The WEL bit can be cleared after a reset command. -Figure 7-1.Write Enable Timing Diagram +Figure 7-1.Write Enable Timing Diagram ![](images/343f7b3c31c7222d5f6f45041cdcd903fbb8b6f15ea145f0a79be413b11bbf7b.jpg)
@@ -507,11 +507,11 @@ SO The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The WEL bit is reset by following condition: -• Page program -• OTP program/OTP protection +• Page program +• OTP program/OTP protection • Block erase -Figure 7-2.Write Disable Timing Diagram +Figure 7-2.Write Disable Timing Diagram ![](images/7441b7c3bb1b3d617b08706cc77d8099c3e619b8f2ad82d6751a3fd0bf589a1c.jpg)
@@ -533,20 +533,20 @@ SO The PAGE READ (13H) command transfers the data from the NAND Flash array to the cache register. The command sequence is as follows: -• 13H (PAGE READ to cache) -• 0FH (GET FEATURES command to read the status) +• 13H (PAGE READ to cache) +• 0FH (GET FEATURES command to read the status) • 03H or 0BH (Read from cache)/3BH (Read from cache x2)/6BH (Read from cache x4)/BBH/EBH/EEH (Read from cache DTR x4) The PAGE READ command requires a 24-bit address. After the block/page addresses are registered, the device starts the transfer from the main array to the cache register, and is busy for tRD time. During this time, the GET FEATURE (0FH) command can be issued to monitor the status. Followed the page read operation, the RANDOM DATA READ (03H/0BH/3BH/6BH/EEH) command must be issued in order to read out the data from cache. The output data starts at the initial address specified in the command, once it reaches the ending boundary of whole page section, the output will wrap around from the beginning boundary until CS# is pulled high to terminate this operation. Refer waveforms to view the entire READ operation. -Note:(1) The command 6BH (Read from cache x4)/EBH (Read from cache Quad IO)/EEH (Read from cache Quad IO DTR) is only available with the QE enable. +Note:(1) The command 6BH (Read from cache x4)/EBH (Read from cache Quad IO)/EEH (Read from cache Quad IO DTR) is only available with the QE enable. (2) When user read to the end of 64-Byte spare area, it won’t wrap around from the beginning boundary and an additional 64Byte ECC code will be read. (Internal ECC enabled) ## 8.2 Page Read to Cache (13H) The command page read to cache is read the data from flash array to cache register. -Figure 8-1.Page Read to cache Timing Diagram +Figure 8-1.Page Read to cache Timing Diagram ![](images/4af5305727b1bb17fb0a9669a56b6401806a645327f604a28dc2c9743ba940ea.jpg) ## 8.3 Cache Read Function (31H/3FH) @@ -567,21 +567,21 @@ Table 8-1.Cache Read instruction description ## Notes: -1. Upon powered up, SPI NAND will automatically load Block-0/Page-0 data into the Cache Register. If this is the starting page of the data that is to be read out, it is not necessary to issue a “Page Read to Cache (13h)” command to initiate the “Cache Read” operation. +1. Upon powered up, SPI NAND will automatically load Block-0/Page-0 data into the Cache Register. If this is the starting page of the data that is to be read out, it is not necessary to issue a “Page Read to Cache (13h)” command to initiate the “Cache Read” operation. 2. Before issuing 31h/3Fh, CBSY bit must be checked to make sure CBSY=0, device is not performing any internal operations. The command sequence is as follows: -• 13H (PAGE READ to cache) -• 0FH (GET FEATURES command to read the status until OIP status bit is changed from 1 to 0) -• 31H (NEXT PAGE CACHE READ command to transfer data from data register to cache register and kick off the next page transfer from array to data register) -• 0FH (GET FEATURES command to read the status until CBSY=0) -• 03H or 0BH (Read from cache)/3BH (Read from cache x2)/6BH (Read from cache x4)/BBH/EBH/EEH (Read from cache DTR x4) -• 3FH (LAST PAGE CACHE READ command to end the read page cache sequence and copy a last page from the data register to cache register) -• 0FH (GET FEATURES command to read the status until CBSY=0) +• 13H (PAGE READ to cache) +• 0FH (GET FEATURES command to read the status until OIP status bit is changed from 1 to 0) +• 31H (NEXT PAGE CACHE READ command to transfer data from data register to cache register and kick off the next page transfer from array to data register) +• 0FH (GET FEATURES command to read the status until CBSY=0) +• 03H or 0BH (Read from cache)/3BH (Read from cache x2)/6BH (Read from cache x4)/BBH/EBH/EEH (Read from cache DTR x4) +• 3FH (LAST PAGE CACHE READ command to end the read page cache sequence and copy a last page from the data register to cache register) +• 0FH (GET FEATURES command to read the status until CBSY=0) • 03H or 0BH (Read from cache)/3BH (Read from cache x2)/6BH (Read from cache x4)/BBH/EBH/EEH (Read from cache DTR x4) -Figure 8-2.Cache Read operation flow chart +Figure 8-2.Cache Read operation flow chart ![](images/e3503671df72f45ed106fb3d776cc9470593584d6bad0a8b281258044b32c694.jpg)
@@ -611,7 +611,7 @@ graph TD ```
-Figure 8-3.Page Read to Cache Timing Diagram +Figure 8-3.Page Read to Cache Timing Diagram ![](images/ea8cff647c04b2e0ac8d1a3060e1bd9d9c4f50cbd06ce45c8542cc1559200a18.jpg)
@@ -688,7 +688,7 @@ SO MSB
-Figure 8-5.Page Read to Cache Timing Diagram +Figure 8-5.Page Read to Cache Timing Diagram ![](images/31c34d53aa5fbde9fac6df83c5c12c8dbd4bfd5158ed1898f585f3103e18bb97.jpg)
@@ -724,7 +724,7 @@ SO MSB
-Figure 8-6.Page Read to Cache Timing Diagram +Figure 8-6.Page Read to Cache Timing Diagram ![](images/339900a74423153c5c2f48ae3b9f82a7f463ca764e808410d077aa8b6ca0c835.jpg)
@@ -797,20 +797,20 @@ Data byte 1 Data byte N SI 0 0 0 0 11 10 -3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 +3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5
## Note： -1. Command 03h/0Bh/3Bh/6Bh/BBh/EBh is available to read out the data in the Cache Register. -2. For high speed performance, we recommend to use EBh to read out the data in the Cache Register. (Please refer to 8.8 Read From Cache Quad IO) +1. Command 03h/0Bh/3Bh/6Bh/BBh/EBh is available to read out the data in the Cache Register. +2. For high speed performance, we recommend to use EBh to read out the data in the Cache Register. (Please refer to 8.8 Read From Cache Quad IO) 3. We recommend to use GET FEATURES command (0Fh) to read the status until CBSY=0. ## 8.4 Read From Cache (03H or 0BH) The command sequence is shown below. -Figure 8-7.Read From Cache Timing Diagram +Figure 8-7.Read From Cache Timing Diagram ![](images/09c5172dc7c3328e5e10b532a26a7e97ffd02c5da26241e7ee3520222914159f.jpg)
@@ -844,7 +844,7 @@ MSB The command sequence is shown below. -Figure 8-8.Read From Cache x2 Timing Diagram +Figure 8-8.Read From Cache x2 Timing Diagram ![](images/c935e090628694cb5b7c2d5b5e5cdd970504fbe6ce4b4164ea41e6d1a37437bf.jpg)
@@ -883,7 +883,7 @@ MSB The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read from cache x4 command. The command sequence is shown below. -Figure 8-9.Read From Cache x4 Timing Diagram +Figure 8-9.Read From Cache x4 Timing Diagram ![](images/4654ffcb1c75a72cebdd19cdd5562ac345b2d2f84f37efb7cce5ac83a3043823.jpg)
@@ -911,7 +911,7 @@ Byte0 Byte1 Byte2 Byte3 The Read from Cache Dual I/O command (BBH) is similar to the Read form Cache x2 command (3BH) but with the capability to input the 4 Dummy bits, followed by a 12-bit column address for the starting byte address and dummy bytes by SIO0 and SIO1, each bit being latched in during the rising edge of SCLK, then the cache contents are shifted out 2-bit per clock cycle from SIO0 and SIO1. The first address byte can be at any location. The address increments automatically to the next higher address after each byte of data shifted out. The command sequence is shown below. -Figure 8-10.Read From Cache Dual IO Timing Diagram +Figure 8-10.Read From Cache Dual IO Timing Diagram ![](images/e2e726866d1895649ec7e388b5035a8500e43a91b7baa3d45c2c7f0637baad86.jpg)
@@ -953,7 +953,7 @@ byte 3 The Read from Cache Quad IO command is similar to the Read from Cache x4 command but with the capability to input the 4 dummy bits, followed a 12-bit column address for the starting byte address and dummy bytes by SIO0, SIO1, SIO3, SIO4, each bit being latched in during the rising edge of SCLK, then the cache contents are shifted out 4-bit per clock cycle from SIO0, SIO1, SIO2, SIO3. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read from cache quad IO command. The command sequence is shown below. -Figure 8-11.Read From Cache Quad IO Timing Diagram +Figure 8-11.Read From Cache Quad IO Timing Diagram ![](images/b4f48eb41fe925af5d8eefab289e736bdec20ce1083c66cc7aabc2b65ef62d11.jpg)
@@ -976,7 +976,7 @@ The DTR QIO command enables Double Transfer Rate throughput on quad I/O of Seria The first address Byte can be at any location. The address is automatically increased to the next higher address after each Byte data is shifted out, so the whole page can be read out at a single DTR QIO command. The address counter rolls over to 0 when the highest address has been reached. -Figure 8-12.Read From Cache Quad I/O DTR Timing Diagram +Figure 8-12.Read From Cache Quad I/O DTR Timing Diagram ![](images/65b603938a3331f3f449c2c6ed5cd6aa5126d90244b8116c97c76afa4d3407f1.jpg)
@@ -1021,7 +1021,7 @@ The READ ID command is used to identify the NAND Flash device. • With address 00H, the READ ID command outputs the Manufacturer ID and the device ID. See Table 8-2 for details. -Figure 8-13.Read ID Timing Diagram +Figure 8-13.Read ID Timing Diagram ![](images/4fdbdfd9298bda9175599f45dc0d85b9a37c97dcb8ce4fdf5f0e2037c6691d9f.jpg)
@@ -1063,13 +1063,13 @@ The UID data may be stored within the Flash array. To allow the host to determin ## Sequence is as follows: -1. Use Set Feature command to set B0 register, to enable OTP\_EN. -2. Use Get Feature command to get data from B0 register and check if the OTP\_EN is enable. -3. Use Page Read to Cache (13h) command with address 24’h000006h, read data from array to cache. -4. Use 0FH (GET FEATURES command) read the status. +1. Use Set Feature command to set B0 register, to enable OTP\_EN. +2. Use Get Feature command to get data from B0 register and check if the OTP\_EN is enable. +3. Use Page Read to Cache (13h) command with address 24’h000006h, read data from array to cache. +4. Use 0FH (GET FEATURES command) read the status. 5. User can use Read from cache command (03H/0BH), read 16 bytes UID from cache. -Figure 8-14. Read UID to cache and Get Feature command Timing Diagram +Figure 8-14. Read UID to cache and Get Feature command Timing Diagram ![](images/64d79f7353b7ae65411a1c43d8d7b3d0a12c6e96df699da85b21a00f2133abad.jpg)
@@ -1113,13 +1113,13 @@ The Read Parameter Page function retrieves the data structure that describes the Sequences as follows: -1. Use Set Feature command to set B0 register, to enable OTP\_EN. -2. Use Get Feature command to get data from B0 register and check if the OTP\_EN is enable. -3. Use Page Read to Cache (13h) command with address 24’h000004. Load parameter page from array to cache. -4. Use 0Fh (GET FEATURES command) read the status +1. Use Set Feature command to set B0 register, to enable OTP\_EN. +2. Use Get Feature command to get data from B0 register and check if the OTP\_EN is enable. +3. Use Page Read to Cache (13h) command with address 24’h000004. Load parameter page from array to cache. +4. Use 0Fh (GET FEATURES command) read the status 5. User can use Read from cache command (03h/0Bh), read parameter page from cache. -Figure 8-15. Read parameter page to cache and Get Feature command Timing Diagram +Figure 8-15. Read parameter page to cache and Get Feature command Timing Diagram ![](images/09ca7246ee158e984bf4611476216ff1782ecd917d21b0a0ccc3d34b29398ee8.jpg) Parameter page table as follow @@ -1130,8 +1130,8 @@ Parameter page table as follow ## Notes: -1. “O” Stands for Optional, “M” for Mandatory -2. The Integrity CRC (Cycling Redundancy Check) field is used to verify that the contents of the parameters page were transferred correctly to the host. Please refer to ONFI 1.0 specifications for details. The CRC shall be calculated using the following 16-bit generator polynomial: $\mathsf { G } ( \mathsf { X } ) = \mathsf { X } ^ { 1 6 } + \mathsf { X } ^ { 1 5 } + \mathsf { X } ^ { 2 } + 1$ ，This polynomial in hex may be represented as 8005h. +1. “O” Stands for Optional, “M” for Mandatory +2. The Integrity CRC (Cycling Redundancy Check) field is used to verify that the contents of the parameters page were transferred correctly to the host. Please refer to ONFI 1.0 specifications for details. The CRC shall be calculated using the following 16-bit generator polynomial: $\mathsf { G } ( \mathsf { X } ) = \mathsf { X } ^ { 1 6 } + \mathsf { X } ^ { 1 5 } + \mathsf { X } ^ { 2 } + 1$ ，This polynomial in hex may be represented as 8005h. 3．The CRC value shall be initialized with a value of 4F4Eh before the calculation begins. There is no XOR applied to the final CRC value after it is calculated. There is no reversal of the data bytes or the CRC calculated value.
Device ModelORGANIZATIONVCC RANGECRC value B254/B255
“GD5F2GQ5UxxxG”X42.7v ~ 3.6v5BH/05H
“GD5F2GQ5RxxxG”X41.7v ~ 2.0v96H/48H
@@ -1142,26 +1142,26 @@ Parameter page table as follow The PAGE PROGRAM operation sequence programs 1 byte to whole page bytes of data within a page. The page program sequence is as follows: -• 02H (PROGRAM LOAD)/32H (PROGRAM LOAD x4) -• 06H (WRITE ENABLE) -• 10H (PROGRAM EXECUTE) +• 02H (PROGRAM LOAD)/32H (PROGRAM LOAD x4) +• 06H (WRITE ENABLE) +• 10H (PROGRAM EXECUTE) • 0FH (GET FEATURE command to read the status) Firstly, a PROGRAM LOAD (02H/32H) command is issued. PROGRAM LOAD consists of an 8-bit Op code, followed by 4 dummy bits and a 12-bit column address, then the data bytes to be programmed. The Program address should be in sequential order in a block. The data bytes are loaded into a cache register that is whole page long. If more than one page data are loaded, then those additional bytes are ignored by the cache register. The command sequence ends when CS# goes from LOW to HIGH. Figure 9-1 shows the PROGRAM LOAD operation. Secondly, prior to performing the PROGRAM EXECUTE operation, a WRITE ENABLE (06H) command must be issued. As with any command that changes the memory contents, the WRITE ENABLE must be executed in order to set the WEL bit. If this command is not issued, then the rest of the program sequence is ignored. ## Note: -1. The contents of Cache Register don’t reset when Program Random Load (84h) command and RESET (FFh) command. -2. When Program Execute (10h) command was issued just after Program Load (02h) command, the 0xFF is output to the address that data was not loaded by Program Load (02h) command. -3. When Program Execute (10h) command was issued just after Program Load Random Data (84h) command, the contents of Cache Register are output to the NAND array. -4. The Program address should be in sequential order in a block. +1. The contents of Cache Register don’t reset when Program Random Load (84h) command and RESET (FFh) command. +2. When Program Execute (10h) command was issued just after Program Load (02h) command, the 0xFF is output to the address that data was not loaded by Program Load (02h) command. +3. When Program Execute (10h) command was issued just after Program Load Random Data (84h) command, the contents of Cache Register are output to the NAND array. +4. The Program address should be in sequential order in a block. 5. Program Load x4 is only available with the QE enable. ## 9.2 Program Load (PL) (02H) The command sequence is shown below. -Figure 9-1. Program Load Timing Diagram +Figure 9-1. Program Load Timing Diagram ![](images/96a851b255ea13b19d69011401becadc5fda55a205daa3061da824f5d39269bb.jpg)
@@ -1192,15 +1192,15 @@ Note: When internal ECC disabled the Data Byte is 2176, when internal ECC enable The Program Load x4 command (32H) is similar to the Program Load command (02H) but with the capability to input the data bytes by four pins: SIO0, SIO1, SIO2, and SIO3. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the program load x4 command. The command sequence is shown below. -Figure 9-2. Program Load x4 Timing Diagram -![](images/b660c2be6cd0f35871a725005cd39d61d55e0712c188b10f3060221330d68b26.jpg) +Figure 9-2. Program Load x4 Timing Diagram +![](images/b660c2be6cd0f35871a725005cd39d61d55e0712c188b10f3060221330d68b26.jpg) Note: When internal ECC disabled the Data Byte is 2176, when internal ECC enabled the Data Byte is 2112. ## 9.4 Program Execute (PE) (10H) After the data is loaded, a PROGRAM EXECUTE (10H) command must be issued to initiate the transfer of data from the cache registers to the main array. PROGRAM EXECUTE consists of an 8-bit Op code, followed by a 24-bit address. After the page/block address is registered, the memory device starts the transfer from the cache register to the main array, and is busy for tPROG time. This operation shown in Figure 9-3. During this busy time, the status register can be polled to monitor the status of the operation (refer to Status Register). When the operation completes successfully, the next series of data can be loaded with the PROGRAM LOAD command. -Figure 9-3. Program Execute Timing Diagram +Figure 9-3. Program Execute Timing Diagram ![](images/23355b92f7c8598e09f40a15770d923a15aee870f89915343a1335487c3e83b6.jpg) ## 9.5 Program Execute Background (10h + address + 15h) @@ -1215,7 +1215,7 @@ When the last page of one block to be program and the OIP bit is 0, the program The program execute command (10h+address+15h) is allowed to cross blocks before reaching the last block. -Figure 9-4. Program Execute Background Operation Flow Chart +Figure 9-4. Program Execute Background Operation Flow Chart ![](images/305761c95e760f28ce942527a3b942b95011ae4b7b7fb6b139818940ca41ae56.jpg)
@@ -1239,7 +1239,7 @@ graph TD ```
-Figure 9-5. Program Execute Background Timing +Figure 9-5. Program Execute Background Timing ![](images/58ae5c4adb2ba5406689db21c0730acd47b49e05982433f44acabd1fbf1353e2.jpg)
@@ -1304,10 +1304,10 @@ High-Z The INTERNAL DATA MOVE command sequence programs or replaces data in a page with existing data. The INTERNAL DATA MOVE command sequence is as follows: -• 13H (PAGE READ to cache) -• Optional 84H/C4H/34H (PROGRAM LOAD RANDOM DATA) -• 06H (WRITE ENABLE) -• 10H (PROGRAM EXECUTE) +• 13H (PAGE READ to cache) +• Optional 84H/C4H/34H (PROGRAM LOAD RANDOM DATA) +• 06H (WRITE ENABLE) +• 10H (PROGRAM EXECUTE) • 0FH (GET FEATURE command to read the status) Prior to performing an internal data move operation, the target page content must be read out into the cache register by issuing a PAGE READ (13H) command. The PROGRAM LOAD RANDOM DATA (84H/C4H) command can be issued, if user wants to update bytes of data in the page. New data is loaded in the 12-bit column address. If the random data is not sequential, another PROGRAM LOAD RANDOM DATA (84H/C4H) command must be issued with the new column address. After the data is loaded, the WRITE ENABLE command must be issued, and then PROGRAMEXECUTE (10H) command can be issued to start the programming operation. Only the block with the same parity attribute can use the command. @@ -1316,7 +1316,7 @@ Prior to performing an internal data move operation, the target page content mus The Program Load Random Data command programs or replaces data in a page with existing data. This command consists of an 8-bit Op code, followed by 4 dummy bits, and a 12-bit column address. New data is loaded in the column address provided with the 12 bits. If the random data is not sequential, then another PROGRAM LOAD RANDOM DATA (84H) command must be issued with a new column address, see Figure 9-6 for details. -Figure 9-6. Program Load Random Data Timing Diagram +Figure 9-6. Program Load Random Data Timing Diagram ![](images/3a5cd052e863303d1a72acb4cfc8001882b3bba1c697960e9933f0d3ced6b269.jpg)
@@ -1339,7 +1339,7 @@ MSB The Program Load Random Data x4 command (C4H/34H) is similar to the Program Load Random Data command (84H) but with the capability to input the data bytes by four pins: SIO0, SIO1, SIO2, and SIO3. The command sequence is shown below. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable for the program load random data x4 command. See Figure 9-7 for details. -Figure 9-7. Program Load Random Data x4 Timing Diagram +Figure 9-7. Program Load Random Data x4 Timing Diagram ![](images/d2689b1999b01197d306d53971378631bbe3472f017cbb2affe7c340e362d484.jpg)
@@ -1367,13 +1367,13 @@ HOLD#(SIO3) 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 The BLOCK ERASE (D8H) command is used to erase at the block level. The BLOCK ERASE command (D8H) operates on one block at a time. The command sequence for the BLOCK ERASE operation is as follows: -• 06H (WRITE ENBALE command) -• D8H (BLOCK ERASE command) +• 06H (WRITE ENBALE command) +• D8H (BLOCK ERASE command) • 0FH (GET FEATURES command to read the status register) Prior to performing the BLOCK ERASE operation, the WRITE ENABLE (06H) command must be issued. As with any command that changes the memory contents, the WRITE ENABLE command must be executed in order to set the WEL bit. If the WRITE ENABLE command is not issued, then the rest of the erase sequence is ignored. The WRITE ENABLE command must be followed by the BLOCK ERASE (D8H) command. This command requires a 24-bit address. After the row address is registered, the control logic automatically controls timing and erase-verify operations. The device is busy for tBERS time during the BLOCK ERASE operation. The GET FEATURES (0FH) command can be used to monitor the status of the operation. -Figure10-1. Block Erase Timing Diagram +Figure10-1. Block Erase Timing Diagram ![](images/f921480c0cb742615c5a7244738d62e37798d90a0da0dbed5107f7f047e9df06.jpg) ## 11 RESET OPERATIONS @@ -1384,7 +1384,7 @@ The RESET (FFH) command stops all operations and the status. For example, in cas During a cache program or cache read, a reset can also stops the previous operation and the pending operation. -Figure11-1. Reset Timing Diagram +Figure11-1. Reset Timing Diagram ![](images/15f15746a12a6271d2735432e42186d37c619e700e811c711153eda6a69acecc.jpg)
@@ -1428,7 +1428,7 @@ If the Power on Reset command is accepted, any on-going internal operation will The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in SPI mode. The “Reset (99H)” command sequence as follow: CS# goes low -> Sending Enable Reset command ->CS# goes high ->CS# goes low.->Sending Reset command ->CS# goes high. Once the Reset command is accepted by the device, the device will take approximately tVSL to reset. During this period, no command will be accepted. It is recommended to check the OIP bit in Status Register before issuing any other command sequence. The contents of the memory location being programmed or the block being erased are no longer valid. -Figure11-2. Reset Timing Diagram +Figure11-2. Reset Timing Diagram ![](images/b5cf335087123fa59f61f0fcb0621602888481ae28eab8e186d1d981f87357aa.jpg)
@@ -1459,18 +1459,18 @@ Table 12-1. Features Settings
RegisterAddr.76543210
ProtectionA0HBRWDReservedBP2BP1BP0INVCMPReserved
FeatureB0HOTP_PRTOTP_ENReservedECC_ENReservedReservedReservedQE
StatusC0HReservedReservedECCS1ECCS0P_FAILE_FAILWELOIP
FeatureD0HReservedDS_IO[1]DS_IO[0]ReservedReservedReservedReservedReserved
StatusF0HReservedReservedECCSE1ECCSE0BPSReservedReservedCBSY
-Note: 1. If BRWD is enabled and WP# is LOW, then the block lock register cannot be changed. -2. If QE is enabled, the quad IO operations can be executed. -3. All the reserved bits must be held low when the feature is set. -4. These registers A0H/B0H/D0H are write/read type, and Registers C0H/F0H are read only. -5. The OTP\_PRT is non-volatile, others bits are volatile. +Note: 1. If BRWD is enabled and WP# is LOW, then the block lock register cannot be changed. +2. If QE is enabled, the quad IO operations can be executed. +3. All the reserved bits must be held low when the feature is set. +4. These registers A0H/B0H/D0H are write/read type, and Registers C0H/F0H are read only. +5. The OTP\_PRT is non-volatile, others bits are volatile. 6. The Register Bit default value after power-up refers to Table 12-2. Register Bit Descriptions. Table 12-2. Register Bit Descriptions
BitBit NameAfter Power up or Power on Reset(66H-99H)After Reset command (FFH)Description
BRWDBlock register write disable0No ChangeWhich is used combined with WP#, If BRWD is high enabled and WP# is LOW, then the Protection register cannot be changed
BP2Block1No ChangeUsed combination, refer to chapter Block Protection
BP11
BP0Protection1
INVbits0
CMP0
OTP_PRTOTP0No ChangeUsed combination, refer to chapter OTP Region
OTP_ENRegion0
bitsBefore OTP Set
ECC_ENECC1No ChangeThe device offers data corruption protection by offering optional internal ECC. READs and PROGRAMs with internal ECC can be enabled or disabled by setting feature bit ECC_EN. ECC is enabled by default when device powered on, so the default READ and PROGRAM commands operate with internal ECC in the “active” state when ECC enable.
Enable
Latch
QEThe Quad0No ChangeThis bit indicates that whether the quad IO operations can be executed. If QE is set to 1, the quad IO operations can be executed.
Enable bit
ECCS0ECC StatusPage 0 Status0ECCS provides ECC status as the following table. ECCS and ECCSE are set to 00b either following a RESET, or at the beginning of the READ. They are then updated after the device completes a valid READ operation. ECCS and ECCSE are invalid if internal ECC is disabled (via a SET FEATURES command to reset ECC_EN to 0). After power-on RESET, ECC status is set to reflect the contents of block 0, page 0.
ECCS10
ECCSE00
ECCSE10
P_FAILProgram Fail00This bit indicates that a program failure has occurred (P_FAIL =1). It will also be set if the user attempts to program a protected region, including the OTP area. This bit is cleared during the PROGRAM EXECUTE command sequence or a RESET command (P_FAIL = 0).
E_FAILErase Fail00This bit indicates that an erase failure has occurred (E_FAIL = 1). It will also be set if the user attempts to erase a locked region. This bit is cleared (E_FAIL = 0) at the start of the BLOCK ERASE command sequence or the RESET command.
WELWrite Enable Latch00This bit indicates the current status of the write enable latch (WEL) and must be set (WEL = 1), prior to issuing a PROGRAM EXECUTE or BLOCK ERASE command. It is set by issuing the WRITE ENABLE command. WEL can also be disabled (WEL = 0), by issuing the WRITE DISABLE command.
OIPOperation In Progress00This bit is set (OIP = 1) when a PROGRAM EXECUTE, PAGE READ, BLOCK ERASE, or RESET command is executing, indicating the device is busy. When the bit is 0, the interface is in the ready state.
DS_IO[0] DS_IO[1]Driven Strength register00No ChangeIO driver strength setting. Default is 00b.
BPSBlock Protection Status1No ChangeBlock protection statusBPS is 1, selected block is protectedBPS is 0, selected block is unprotected.
CBSYCache Busy status bit00CBSY is to indicate whether cache is busy, non-available for data read or data load. This bit is the status, which indicates if the cache is busy or ready, 1 is busy, 0 is ready.
-Figure12-1. Get Features Timing Diagram +Figure12-1. Get Features Timing Diagram ![](images/755b7da828ecf51f8b7bb32f3e782c4fe37dd23584f907ad1032a5bba08b0251.jpg)
@@ -1492,7 +1492,7 @@ MSB MSB
-Figure12-2. Set Features Timing Diagram +Figure12-2. Set Features Timing Diagram ![](images/84a2b2bbda5fd48f94be290045d18e4ed46209ceb284bdc5da7ff6d48b8195a8.jpg)
@@ -1536,17 +1536,17 @@ Note: The OTP space cannot be erased and after it has been protected, it cannot Access to OTP data -• Issue the SET FEATURES command (1FH) -• Set feature bit OTP\_EN +• Issue the SET FEATURES command (1FH) +• Set feature bit OTP\_EN • Issue the PAGE PROGRAM (only when OTP\_PRT is 0) or PAGE READ command Protect OTP region Only when the following steps are completed, the OTP\_PRT will be set and users can get this feature out with 0FH command. -• Issue the SET FEATURES command (1FH) -• Set feature bit OTP\_EN and OTP\_PRT -• 06H (WRITE ENABLE) +• Issue the SET FEATURES command (1FH) +• Set feature bit OTP\_EN and OTP\_PRT +• 06H (WRITE ENABLE) • Issue the PROGRAM EXECUTE (10H) command. ## 12.4 Assistant Bad Block Management @@ -1575,8 +1575,8 @@ Table 12-7. Block Lock Register Block Protect Bits (2Gb)
CMPINVBP2BP1BP0Protect Row AddressProtect Rows
2Gb
xx000NONENone—all unlocked
000011F800h ~ 1FFFFhUpper 1/64 locked
000101F000h ~ 1FFFFhUpper 1/32 locked
000111E000h ~ 1FFFFhUpper 1/16 locked
001001C000h ~ 1FFFFhUpper 1/8 locked
0010118000h ~ 1FFFFhUpper 1/4 locked
0011010000h ~ 1FFFFhUpper 1/2 locked
xx1110000h ~ 1FFFFhAll locked (default)
010010000h ~7FFhLower 1/64 locked
010100000h ~FFFhLower 1/32 locked
010110000h ~ 1FFFhLower 1/16 locked
011000000h ~ 3FFFhLower 1/8 locked
011010000h ~ 7FFFhLower 1/4 locked
011100000h ~ FFFFhLower 1/2 locked
100010000h ~ 1F7FFhLower 63/64 locked
100100000h ~ 1FFFFhLower31/32 locked
100110000h ~ 1DFFFhLower 15/16 locked
101000000h ~ 1BFFFhLower7/8 locked
101010000h ~ 17FFFhLower3/4 locked
101100000h ~ 003FhBlock0
110010800h ~ 1FFFFhUpper 63/64 locked
110101000h ~ 1FFFFhUpper31/32 locked
110112000h ~ 1FFFFhUpper 15/16 locked
111004000h ~ 1FFFFhUpper7/8 locked
111018000h ~ 1FFFFhUpper3/4 locked
111100000h ~ 003FhBlock0
-When WP# is not LOW, user can issue bellows commands to alter the protection states as want. -• Issue SET FEATURES register write (1FH) +When WP# is not LOW, user can issue bellows commands to alter the protection states as want. +• Issue SET FEATURES register write (1FH) • Issue the feature bit address (A0h) and the feature bits combination as the table ## 12.6 Internal ECC @@ -1587,7 +1587,7 @@ To enable/disable ECC, perform the following command sequence: • Issue the SET FEATURES command (1FH) to set the feature bit ECC\_EN: -1. To enable ECC, Set ECC\_EN to 1. +1. To enable ECC, Set ECC\_EN to 1. 2. To disable ECC, Clear ECC\_EN to 0. During a PROGRAM operation, the device calculates an ECC code on the 2k page in the cache register, before the page is written to the NAND Flash array. @@ -1610,13 +1610,13 @@ Table 12-9. ECC Protection and Spare Area ## Note -1. 800H is reserved for initial bad block mark. -2. When Internal ECC is enabled, user cannot program the Address 840H\~87FH, but user can read the Address 840H\~87FH. +1. 800H is reserved for initial bad block mark. +2. When Internal ECC is enabled, user cannot program the Address 840H\~87FH, but user can read the Address 840H\~87FH. When Internal ECC is disabled, the whole page area is open for user. And we recommend the user to provide external ECC protection. ## 13POWER ON TIMING -Figure13-1. Power on Timing Sequence +Figure13-1. Power on Timing Sequence ![](images/fc2ca4121a17b855a4c8a71f284d70319d2bc8b9fca9d2b20f302b19c512cd19.jpg)
@@ -1643,7 +1643,7 @@ Table 14-1.Absolute Maximum Ratings Figure14-1. Input Test Waveform and Measurement Level -Maximum Negative Overshoot Waveform +Maximum Negative Overshoot Waveform ![](images/5ab9164ef39545ab8995032a9593308a8e83278273c448fa9d38eccfff56b99c.jpg)
@@ -1656,7 +1656,7 @@ Vss-2.0V 20ns
-Maximum Positive Overshoot Waveform +Maximum Positive Overshoot Waveform ![](images/36919d0fe4bdd81447f6d77ddf3e347ad916ab43a2f5d3ba7c47afd64a7e6893.jpg)
@@ -1672,7 +1672,7 @@ Vcc + 2.0V
SymbolParameterMinTypMaxUnitConditions
CINInput Capacitance6pFVIN=0V
COUTOutput Capacitance8pFVOUT=0V
CLLoad Capacitance30pF
Input Rise And Fall time5ns
Input Pulse Voltage0.1VCC to 0.8VCCV
Input Timing Reference Voltage0.2VCC to 0.7VCCV
Output Timing Reference Voltage0.5VCCV
-Figure15-1. Input Test Waveform and Measurement Level +Figure15-1. Input Test Waveform and Measurement Level ![](images/e9b06380ede32fb2048221570af522de84505438d4d429602d78b8d5248f9ea0.jpg)
@@ -1709,7 +1709,7 @@ Note: Value guaranteed by design and/or characterization, not 100% tested in pro ## Note: -1. Value guaranteed by design and/or characterization, not 100% tested in production +1. Value guaranteed by design and/or characterization, not 100% tested in production 2. Please contact GigaDevice when there is a need to use the EEh command for DTR. The max clock rate for DTR depends on the tCLQV (clock to data output valid). Per datasheet, with output load capacitance of 30pf, the tCLQV is about 11ns. This will limit the max rate to 45Mhz. @@ -1722,7 +1722,7 @@ GigaDevice recommend customers measure the tCLQV and then set the clock rate to
SymbolParameterMin.Typ.Max.Unit.
tRSTCS# High To Next Command After Reset(FFh)500us
tRDRead From Array25us
tRD_ECCRead From Array with ECC4560us
tPROGPage Programming Time300600us
tPROG_ECCPage Programming Time with ECC400600us
tBERSBlock Erase Time35ms
tCBSYWCache busy time for Cache Program5tPROGus
tCBSYW_ECCCache busy time for Cache Program with ECC30tPROG_ECCus
tCBSYRCache busy time for Cache Read5tRDus
tCBSYR_ECCCache busy time for Cache Read with ECC30tRD_ECCus
-Figure18-1. Serial Input Timing +Figure18-1. Serial Input Timing ![](images/881b2dfbbbb8230fb7af423e755404286621abc6443eff5afc5c06cc0c664d47.jpg)
@@ -1745,7 +1745,7 @@ tSHCL tSHSL
-Figure18-2. Output Timing +Figure18-2. Output Timing ![](images/862fdcc50b0a0a0903dfcef387b75249359e0361a7d63a958d4a67596c973807.jpg)
@@ -1766,7 +1766,7 @@ SI Least significant address bit (LIB) in
-Figure18-3. Hold Timing +Figure18-3. Hold Timing ![](images/6e6e3f492d6a3bcaf451ad36a791b73d3bd48ab15ff9722b61aa57f64c01c4d3.jpg)
@@ -1788,13 +1788,13 @@ Sl do not care during HOLD operation. ## 19ORDERING INFORMATION -![](images/35356c13b1070de72632d77901f1c5c94ab8bdcb460e745577a05a11ca95ea6b.jpg) +![](images/35356c13b1070de72632d77901f1c5c94ab8bdcb460e745577a05a11ca95ea6b.jpg) Note: (1) Industrial+: F grade has implemented additional test flows to ensure higher product quality than I grade. ## 20 PACKAGE INFORMATION -Figure 20-1.WSON8 (8\*6mm) -![](images/d72dc2e6eb040b370a50a8b5b5b57cf54cc5974bd404967d05fd4adf0cfe3562.jpg) +Figure 20-1.WSON8 (8\*6mm) +![](images/d72dc2e6eb040b370a50a8b5b5b57cf54cc5974bd404967d05fd4adf0cfe3562.jpg) Bottom View ![](images/74a98a721fb00f3476cd1d40fc6b762a4fce0c57c2885119aa8012aef7a70f84.jpg) @@ -1813,15 +1813,15 @@ Dimensions
SymbolAA1cbDD2EE2eL
Unit
mmMin0.700.000.1800.357.903.305.904.201.270.45
Nom0.750.020.2030.408.003.406.004.300.50
Max0.800.050.2500.458.103.506.104.400.55
InchMin0.02800.0070.0140.3110.1300.2320.1650.050.018
Nom0.0300.0010.0080.0160.3150.1340.2360.1690.020
Max0.0320.0020.0100.0180.3190.1380.2400.1730.022
-Figure 20-2.TFBGA-24BALL (5\*5-1 ball array) -![](images/309918a65f99632a28c75a9aeae076c813083d9dfa76271cea0dd3611eea32b9.jpg) +Figure 20-2.TFBGA-24BALL (5\*5-1 ball array) +![](images/309918a65f99632a28c75a9aeae076c813083d9dfa76271cea0dd3611eea32b9.jpg) Dimensions
SymbolAA1A2bDD1EE1eSESD
Unit
mmMin0.250.750.355.904.00 BSC7.904.00 BSC1.00 BSC1.00 TYP1.00 TYP
Nom0.300.800.406.008.00
Max1.200.350.850.456.108.10
InchMin0.0100.0300.0140.2320.157 BSC0.3110.157 BSC0.039 BSC0.039 TYP0.039 TYP
Nom0.0120.0310.0160.2360.315
Max0.0470.0140.0330.0180.2400.319
Note：Both package length and width do not include mold flash. -Figure20-3. TFBGA-24BALL (4\*6 ball array) +Figure20-3. TFBGA-24BALL (4\*6 ball array) ![](images/08d3fc107d74ce1b70a342f0d55cddefae442ab529e89cfab2eef1f18c12f9d6.jpg) Dimensions @@ -1840,4 +1840,4 @@ This document is the property of GigaDevice Semiconductor (Beijing) Inc. and its The Company makes no warranty of any kind, express or implied, with regard to this document or any Product, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. The Company does not assume any liability arising out of the application or use of any Product described in this document. Any information provided in this document is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Except for customized products which has been expressly identified in the applicable agreement, the Products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only. The Products are not designed, intended, or authorized for use as components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, atomic energy control instruments, combustion control instruments, airplane or spaceship instruments, traffic signal instruments, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or Product could cause personal injury, death, property or environmental damage ("Unintended Uses"). Customers shall take any and all actions to ensure using and selling the Products in accordance with the applicable laws and regulations. The Company is not liable, in whole or in part, and customers shall and hereby do release the Company as well as it’s suppliers and/or distributors from any claim, damage, or other liability arising from or related to all Unintended Uses of the Products. Customers shall indemnify and hold the Company as well as it’s suppliers and/or distributors harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of the Products. Customers shall discard the device according to the local environmental law. -Information in this document is provided solely in connection with the Products. The Company reserves the right to make changes, corrections, modifications or improvements to this document and the Products and services described herein at any time, without notice. \ No newline at end of file +Information in this document is provided solely in connection with the Products. The Company reserves the right to make changes, corrections, modifications or improvements to this document and the Products and services described herein at any time, without notice. diff --git a/docs/芯片手册/RTL8305NBI-CG.md b/docs/芯片手册/RTL8305NBI-CG.md index 6e7d0b20..201860ad 100644 --- a/docs/芯片手册/RTL8305NBI-CG.md +++ b/docs/芯片手册/RTL8305NBI-CG.md @@ -40,24 +40,24 @@ REVISION HISTORY ## Table of Contents -1. GENERAL DESCRIPTION....1 -2. FEATURES....2 -3. SYSTEM APPLICATIONS....3 -4. BLOCK DIAGRAM....4 +1. GENERAL DESCRIPTION....1 +2. FEATURES....2 +3. SYSTEM APPLICATIONS....3 +4. BLOCK DIAGRAM....4 5. PIN ASSIGNMENTS ....5 -5.1. PIN ASSIGNMENTS DIAGRAM....5 -5.2. PACKAGE IDENTIFICATION....5 +5.1. PIN ASSIGNMENTS DIAGRAM....5 +5.2. PACKAGE IDENTIFICATION....5 5.3. PIN ASSIGNMENTS TABLE....6 6. PIN DESCRIPTIONS....7 -6.1. PIN ASSIGNMENT CODES 7 -6.2. MEDIA CONNECTION PINS 7 -6.3. MISCELLANEOUS PINS 8 -6.4. PORT LED PINS 8 -6.5. STRAPPING PINS....9 -6.6. REGULATOR PINS....9 +6.1. PIN ASSIGNMENT CODES 7 +6.2. MEDIA CONNECTION PINS 7 +6.3. MISCELLANEOUS PINS 8 +6.4. PORT LED PINS 8 +6.5. STRAPPING PINS....9 +6.6. REGULATOR PINS....9 6.7. POWER AND GND PINS....9 7. BASIC FUNCTION DESCRIPTIONS....10 @@ -66,51 +66,51 @@ REVISION HISTORY 7.1.1. Flow Control....10 -7.1.1.1 IEEE 802.3x Full Duplex Flow Control....10 +7.1.1.1 IEEE 802.3x Full Duplex Flow Control....10 7.1.1.2 Half Duplex Back Pressure....10 -7.1.2. Address Search, Learning, and Aging....11 -7.1.3. Half Duplex Operation....11 -7.1.4. InterFrame Gap....11 +7.1.2. Address Search, Learning, and Aging....11 +7.1.3. Half Duplex Operation....11 +7.1.4. InterFrame Gap....11 7.1.5. Illegal Frame....11 7.2. PHYSICAL LAYER FUNCTIONAL OVERVIEW 12 -7.2.1. Auto-Negotiation....12 -7.2.2. 10Base-T Transmit Function....12 -7.2.3. 10Base-T Receive Function....12 -7.2.4. Link Monitor....12 -7.2.5. 100Base-TX Transmit Function....12 -7.2.6. 100Base-TX Receive Function....12 -7.2.7. Power-Down Mode....13 -7.2.8. Crossover Detection and Auto Correction....13 +7.2.1. Auto-Negotiation....12 +7.2.2. 10Base-T Transmit Function....12 +7.2.3. 10Base-T Receive Function....12 +7.2.4. Link Monitor....12 +7.2.5. 100Base-TX Transmit Function....12 +7.2.6. 100Base-TX Receive Function....12 +7.2.7. Power-Down Mode....13 +7.2.8. Crossover Detection and Auto Correction....13 7.2.9. Polarity Detection and Correction....13 7.3. GENERAL FUNCTION OVERVIEW....14 -7.3.1. Power-On Sequence 14 -7.3.2. Setup and Configuration....15 +7.3.1. Power-On Sequence 14 +7.3.2. Setup and Configuration....15 7.3.3. Serial EEPROM Example....16 -7.3.3.1 EEPROM Device Operation....16 +7.3.3.1 EEPROM Device Operation....16 7.3.3.2 EEPROM Size Selection....18 -7.3.4. SMI....18 -7.3.5. Head-Of-Line Blocking 18 -7.3.6. Filtering/Forwarding Reserved Control Frame....19 -7.3.7. Loop Detection....19 -7.3.8. Reg.0.14 PHY Digital Loopback Return to Internal....21 -7.3.9. LDO for 1.0V Power Generation 22 +7.3.4. SMI....18 +7.3.5. Head-Of-Line Blocking 18 +7.3.6. Filtering/Forwarding Reserved Control Frame....19 +7.3.7. Loop Detection....19 +7.3.8. Reg.0.14 PHY Digital Loopback Return to Internal....21 +7.3.9. LDO for 1.0V Power Generation 22 7.3.10. Crystal/Oscillator 22 ## 8. ADVANCED FUNCTION DESCRIPTIONS ....23 8.1. VLAN FUNCTION ....23 -8.1.1. VLAN Description ....23 -8.1.2. Port-Based VLAN....24 -8.1.3. IEEE 802.1Q Tagged-VID Based VLAN 24 -8.1.4. Insert/Remove/Replace Tag....24 +8.1.1. VLAN Description ....23 +8.1.2. Port-Based VLAN....24 +8.1.3. IEEE 802.1Q Tagged-VID Based VLAN 24 +8.1.4. Insert/Remove/Replace Tag....24 8.1.5. Ingress and Egress Rules....25 8.2. IEEE 802.1P REMARKING FUNCTION....25 @@ -119,46 +119,46 @@ REVISION HISTORY 8.3.1. Bandwidth Control 26 -8.3.1.1 Output (TX) Bandwidth Control....26 +8.3.1.1 Output (TX) Bandwidth Control....26 8.3.1.2 Input (RX) Bandwidth Control 27 8.3.2. Priority Assignment....27 -8.3.2.1 Queue Number Selection....27 -8.3.2.2 Port-Based Priority Assignment....27 -8.3.2.3 IEEE 802.1p/Q-Based Priority Assignment....28 -8.3.2.4 DSCP-Based Priority Assignment 28 -8.3.2.5 IP Address-Based Priority....28 -8.3.2.6 Reassigned Priority....28 -8.3.2.7 RLDP-Based Priority....28 +8.3.2.1 Queue Number Selection....27 +8.3.2.2 Port-Based Priority Assignment....27 +8.3.2.3 IEEE 802.1p/Q-Based Priority Assignment....28 +8.3.2.4 DSCP-Based Priority Assignment 28 +8.3.2.5 IP Address-Based Priority....28 +8.3.2.6 Reassigned Priority....28 +8.3.2.7 RLDP-Based Priority....28 8.3.2.8 Packet Priority Selection....29 8.4. LOOKUP TABLE FUNCTION ....30 -8.4.1. Function Description....30 -8.4.2. Address Search, Learning, and Aging....30 +8.4.1. Function Description....30 +8.4.2. Address Search, Learning, and Aging....30 8.4.3. Lookup Table Definition....31 -8.5. STORM FILTER FUNCTION....32 -8.6. INPUT AND OUTPUT DROP FUNCTION 32 -8.7. LED FUNCTION....33 -8.8. ENERGY-EFFICIENT ETHERNET (EEE)....34 +8.5. STORM FILTER FUNCTION....32 +8.6. INPUT AND OUTPUT DROP FUNCTION 32 +8.7. LED FUNCTION....33 +8.8. ENERGY-EFFICIENT ETHERNET (EEE)....34 8.9. CABLE DIAGNOSIS 34 ## 9. CHARACTERISTICS....35 -9.1. ELECTRICAL CHARACTERISTICS/MAXIMUM RATINGS ....35 -9.2. OPERATING RANGE....35 -9.3. DC CHARACTERISTICS....35 +9.1. ELECTRICAL CHARACTERISTICS/MAXIMUM RATINGS ....35 +9.2. OPERATING RANGE....35 +9.3. DC CHARACTERISTICS....35 9.4. THERMAL CHARACTERISTICS....36 -9.4.1. Simulation Conditions 36 +9.4.1. Simulation Conditions 36 9.4.2. Thermal Characteristics Results ....36 9.5. DIGITAL TIMING CHARACTERISTICS ....37 -9.5.1. LED Timing....37 -9.5.2. Reception/Transmission Data Timing of SMI Interface 37 +9.5.1. LED Timing....37 +9.5.2. Reception/Transmission Data Timing of SMI Interface 37 9.5.3. EEPROM Auto-Load Timing....38 ## 10. MECHANICAL DIMENSIONS....39 @@ -221,26 +221,26 @@ TABLE 25. ORDERING INFORMATION ....41 ## List of Figures -FIGURE 1. BLOCK DIAGRAM....4 -FIGURE 2. PIN ASSIGNMENTS ....5 -FIGURE 3. COLLISION-BASED BACKPRESSURE SIGNAL TIMING....10 -FIGURE 4. POWER-ON SEQUENCE....14 -FIGURE 5. RESET 15 -FIGURE 6. START AND STOP DEFINITION....17 -FIGURE 7. OUTPUT ACKNOWLEDGE ....17 -FIGURE 8. RANDOM READ....17 -FIGURE 9. SEQUENTIAL READ ....17 -FIGURE 10. LOOP EXAMPLE ....19 -FIGURE 11. LED AND BUZZER CONTROL SIGNAL FOR LOOP DETECTION ....20 -FIGURE 12. LOOP EXAMPLE 2 ....21 -FIGURE 13. REG. 0.14 LOOPBACK ....21 -FIGURE 14. PACKET-SCHEDULING DIAGRAM....26 -FIGURE 15. RTL8305NBI PRIORITY ASSIGNMENT DIAGRAM....27 -FIGURE 16. BROADCAST INPUT DROP VS. OUTPUT DROP....32 -FIGURE 17. MULTICAST INPUT DROP VS. OUTPUT DROP....32 -FIGURE 18. FLOATING AND PULL-HIGH OF LED PINS FOR LED ....33 -FIGURE 19. RECEPTION DATA TIMING OF SMI INTERFACE....37 -FIGURE 20. TRANSMISSION DATA TIMING OF SMI INTERFACE....37 +FIGURE 1. BLOCK DIAGRAM....4 +FIGURE 2. PIN ASSIGNMENTS ....5 +FIGURE 3. COLLISION-BASED BACKPRESSURE SIGNAL TIMING....10 +FIGURE 4. POWER-ON SEQUENCE....14 +FIGURE 5. RESET 15 +FIGURE 6. START AND STOP DEFINITION....17 +FIGURE 7. OUTPUT ACKNOWLEDGE ....17 +FIGURE 8. RANDOM READ....17 +FIGURE 9. SEQUENTIAL READ ....17 +FIGURE 10. LOOP EXAMPLE ....19 +FIGURE 11. LED AND BUZZER CONTROL SIGNAL FOR LOOP DETECTION ....20 +FIGURE 12. LOOP EXAMPLE 2 ....21 +FIGURE 13. REG. 0.14 LOOPBACK ....21 +FIGURE 14. PACKET-SCHEDULING DIAGRAM....26 +FIGURE 15. RTL8305NBI PRIORITY ASSIGNMENT DIAGRAM....27 +FIGURE 16. BROADCAST INPUT DROP VS. OUTPUT DROP....32 +FIGURE 17. MULTICAST INPUT DROP VS. OUTPUT DROP....32 +FIGURE 18. FLOATING AND PULL-HIGH OF LED PINS FOR LED ....33 +FIGURE 19. RECEPTION DATA TIMING OF SMI INTERFACE....37 +FIGURE 20. TRANSMISSION DATA TIMING OF SMI INTERFACE....37 FIGURE 21. EEPROM AUTO-LOAD TIMING....38 ## 1. General Description @@ -251,9 +251,9 @@ In order to accomplish diagnostics in complex network systems, the RTL8305NBI pr The RTL8305NBI supports several advanced QoS functions with four-level priority queues to improve multimedia or real-time networking applications, including: -• Multi-priority assignment -- Differential queue weight -• Port-based rate limitation +• Multi-priority assignment +- Differential queue weight +• Port-based rate limitation - Queue-based rate limitation ## DRAFT @@ -274,67 +274,67 @@ To simplify the peripheral power circuit, the RTL8305NBI integrates one LDO regu ## DRAFT -■ 5-port switch controller with memory and transceiver for 10Base-T and 100Base-TX -■ Non-blocking wire-speed reception and transmission and non-head-of-line-blocking forwarding -■ Complies with IEEE 802.3/802.3u auto-negotiation -■ Built-in high efficiency SRAM for packet buffer, with 2K-entry lookup table and two 4-way associative hash algorithms -■ 2048 byte maximum packet length -■ Flow control fully supported -◆ Half duplex: Back pressure flow control +■ 5-port switch controller with memory and transceiver for 10Base-T and 100Base-TX +■ Non-blocking wire-speed reception and transmission and non-head-of-line-blocking forwarding +■ Complies with IEEE 802.3/802.3u auto-negotiation +■ Built-in high efficiency SRAM for packet buffer, with 2K-entry lookup table and two 4-way associative hash algorithms +■ 2048 byte maximum packet length +■ Flow control fully supported +◆ Half duplex: Back pressure flow control ◆ Full duplex: IEEE 802.3x flow control ## Service Quality -■ Supports high performance QoS function on each port -◆ Supports 4-level priority queues -◆ Weighted round robin service -◆ Supports strict priority -◆ Input/Output port bandwidth control -◆ Queue-based bandwidth control -◆ 1Q-based, Port-based, DSCP-based, IP address-based, and other types of priority assignments +■ Supports high performance QoS function on each port +◆ Supports 4-level priority queues +◆ Weighted round robin service +◆ Supports strict priority +◆ Input/Output port bandwidth control +◆ Queue-based bandwidth control +◆ 1Q-based, Port-based, DSCP-based, IP address-based, and other types of priority assignments ■ Supports IEEE 802.1p Traffic Remarking ## DRAFT ## Security and Management -■ Supports reserved control frame filtering -■ Supports advanced storm filtering +■ Supports reserved control frame filtering +■ Supports advanced storm filtering ■ Optional EEPROM interface for configuration ## VLAN Functions -■ Supports up to 16 VLAN groups -■ Flexible 802.1Q port/tag-based VLAN -■ Supports four IVLs +■ Supports up to 16 VLAN groups +■ Flexible 802.1Q port/tag-based VLAN +■ Supports four IVLs ■ Leaky VLAN for unicast/multicast/broadcast/ARP packets ## Power Saving Functions -■ Supports Energy-Efficient Ethernet (EEE) function (IEEE 802.3az) +■ Supports Energy-Efficient Ethernet (EEE) function (IEEE 802.3az) ■ Link Down Power Saving Mode ## Diagnostic Functions -■ Supports hardware loop detection function with LEDs and buzzer to indicate the existence of a loop -■ Supports cable diagnosis (RTCT function) -■ Flexible LED indicators -◆ RTCT status indication -◆ Loop status indication +■ Supports hardware loop detection function with LEDs and buzzer to indicate the existence of a loop +■ Supports cable diagnosis (RTCT function) +■ Flexible LED indicators +◆ RTCT status indication +◆ Loop status indication ◆ LEDs blink upon reset for LED diagnostics ## Other Features ■ Optional MDI/MDIX auto crossover for plug-and-play -■ Physical layer port Polarity Detection and Correction function -■ Robust baseline wander correction for improved 100Base-TX performance +■ Physical layer port Polarity Detection and Correction function +■ Robust baseline wander correction for improved 100Base-TX performance ■ 25MHz crystal or 3.3V OSC input ## DRAFT -■ Single 3.3V power input can be transformed by integrating an LDO regulator to generate 1.0V from 3.3V via a low-cost external diode -■ Low power, 1.0/3.3V, 55nm CMOS technology +■ Single 3.3V power input can be transformed by integrating an LDO regulator to generate 1.0V from 3.3V via a low-cost external diode +■ Low power, 1.0/3.3V, 55nm CMOS technology ■ 48-pin QFN ‘Green’ package ## 3. System Applications @@ -560,8 +560,8 @@ If the buffer is ready to overflow, this mechanism will force a collision. When The Reschedule procedure is: -- The RTL8305NBI will drive TXEN to high and send the preamble; SFD and a 4-byte Jam signal (pattern is 0xAA). The RTL8305NBI will then drive TXEN to low -- When the link partner receives the Jam signal, it will feedback a 4-byte signal (pattern is CRC^0x01), it will then drive RXDV to low +- The RTL8305NBI will drive TXEN to high and send the preamble; SFD and a 4-byte Jam signal (pattern is 0xAA). The RTL8305NBI will then drive TXEN to low +- When the link partner receives the Jam signal, it will feedback a 4-byte signal (pattern is CRC^0x01), it will then drive RXDV to low - The link partner waits for a random back-off time then re-sends the packet. The timing is shown in Figure 3 ![](images/645c55aea70b2e7ea978cce17c9de05b162cc555c8c34ff94a7ab9144348c03d.jpg) @@ -687,10 +687,10 @@ When the RTL8305NBI operates in 10Base-T mode, it automatically reverses the pol Two power voltage types are required for RTL8305NBI normal operation; 3.3V and 1.0V. The 1.0V is converted from 3.3V via the LDO of the RTL8305NBI. -- Ta is the moment when 3.3V power is higher than 2.6V (±5%). 3.3V power never falls lower than 2.6V (±5%) after Ta -- Tb is the moment when 1.0V power is higher than 0.71V (±10%). 1.0V power never falls lower than 0.71V (±10%) after Tb -- Tc is the moment when both 3.3V and 1.0V power are stable (the voltage is always in the legal operating range) -- Td is the moment that the pin reset signal is de-asserted +- Ta is the moment when 3.3V power is higher than 2.6V (±5%). 3.3V power never falls lower than 2.6V (±5%) after Ta +- Tb is the moment when 1.0V power is higher than 0.71V (±10%). 1.0V power never falls lower than 0.71V (±10%) after Tb +- Tc is the moment when both 3.3V and 1.0V power are stable (the voltage is always in the legal operating range) +- Td is the moment that the pin reset signal is de-asserted - Te is the moment that the RTL8305NBI device is ready to be accessed by an external CPU ![](images/c61a49ca2a243089749f3dccd0833f0a71f3aede6b8a7e61b4ad73951ddb7f65.jpg) @@ -712,15 +712,15 @@ Figure 4. Power-On Sequence ## The requirements are: -- The time of Ta should be between $500\mu \mathrm{s}$ and $20\mathrm{ms}$ -- The sequence of Ta is always less than Tb for the LDO of the RTL8305NBI. In principle, the sequence of Td and Ta/Tb/Tc is also not required. The sequence of Td > 5ms is recommended -- The time from Te to the later of Ta/Tb/Td is the sum of the time of the EEPROM loading + 30ms. The EEPROM loading time varies according to the autoloaded data bytes in the serial EEPROM +- The time of Ta should be between $500\mu \mathrm{s}$ and $20\mathrm{ms}$ +- The sequence of Ta is always less than Tb for the LDO of the RTL8305NBI. In principle, the sequence of Td and Ta/Tb/Tc is also not required. The sequence of Td > 5ms is recommended +- The time from Te to the later of Ta/Tb/Td is the sum of the time of the EEPROM loading + 30ms. The EEPROM loading time varies according to the autoloaded data bytes in the serial EEPROM - Reset Depending on the type of reset, the whole or just part of the RTL8305NBI is initialized. There are several ways to reset the RTL8305NBI. -- Hardware reset for the whole chip via pin RESET# or power-on -- Soft reset for packet buffer, queue, and MIB counter via register SoftReset +- Hardware reset for the whole chip via pin RESET# or power-on +- Soft reset for packet buffer, queue, and MIB counter via register SoftReset • PHY software reset for each PHY by register reset Hardware Reset: Power-on, or pull the RESET# pin low for at least 1μs. The RTL8305NBI resets the whole chip and after all power is ready and the RESET# pin is de-asserted, it gets initial values from pins and serial EEPROM. @@ -729,7 +729,7 @@ Soft Reset: The RTL8305NBI does not reset the LUT, LED circuit, and all register PHY Software Reset: Write bit15 of Reg0 of a PHY as 1. The RTL8305NBI will then reset this PHY. -![](images/4e7f1972851669ee7813932cc0ad1873e0e5703e864a4861aede3708b17ab9f8.jpg) +![](images/4e7f1972851669ee7813932cc0ad1873e0e5703e864a4861aede3708b17ab9f8.jpg) Figure 5. Reset Some setting values for operation modes are latched from those corresponding mode pins upon hardware reset. ‘Upon reset’ is defined as a short time after the end of a hardware reset. Other advanced configuration parameters may be latched from serial EEPROM. @@ -738,19 +738,19 @@ Some setting values for operation modes are latched from those corresponding mod The RTL8305NBI can be configured easily and flexibly by: -• Hardware pins upon reset -- Optional serial EEPROM upon reset (contact Realtek for detailed EEPROM configuration settings) +• Hardware pins upon reset +- Optional serial EEPROM upon reset (contact Realtek for detailed EEPROM configuration settings) - Internal registers (including PHY registers for each port and global MAC registers) accessed via SMI (Serial Management Interface: MDC/MDIO, also known as MII Management Interface) There are three methods of configuration: -- Only hardware pins for normal switch applications -• Hardware pins and serial EEPROM for advanced switch applications +- Only hardware pins for normal switch applications +• Hardware pins and serial EEPROM for advanced switch applications - Hardware pins and internal registers via SMI for applications with processor Two types of pins, each with internal pull-high or pull-low resistors, are used for configuration: -- Input/Output pins used for strapping upon reset and used as output pins after reset +- Input/Output pins used for strapping upon reset and used as output pins after reset - Input/Output pins used for strapping upon reset and used as LED indicator pins after reset. The LED statuses are represented as active-low or high depending on input strapping Pins with default value=0 are internal pull-low and use I/O pads. They can be left floating to set the input value as low, but should not be connected to VDD without a pull-high resistor. @@ -889,7 +889,7 @@ The RTL8305NBI incorporates a mechanism to prevent Head-Of-Line blocking problem The RTL8305NBI supports the ability to forward or drop the frames of the IEEE 802.1 specified reserved Ethernet multicast addresses. -Table 10. Reserved Ethernet Multicast Addresses +Table 10. Reserved Ethernet Multicast Addresses B: Broadcast (Search the Look-Up Table) D: Drop
AssignmentValueAvailable Action
Bridge Group Address01-80-C2-00-00-00D, B (Default)
IEEE Std 802.3, 1988 Edition, Full Duplex PAUSE Operation01-80-C2-00-00-01D (Default), B
IEEE 802.3ad Slow_Protocols-Multicast Address01-80-C2-00-00-02D (Default), B
IEEE 802.1X PAE Address01-80-C2-00-00-03D, B (Default)
Reserved for Future Standards01-80-C2-00-00-04~01-80-C2-00-00-0D, 01-80-C2-00-00-0FD (Default), B
LLDP IEEE Std 802.1AB Link Layer Discovery Protocol Multicast Address01-80-C2-00-00-0ED, B (Default)
All LANs Bridge Management Group Address01-80-C2-00-00-10D (Default), B
Reserved for 01-80-C2-00-00-1x01-80-C2-00-00-11~01-80-C2-00-00-1FD, B (Default)
GMRP Address01-80-C2-00-00-20D (Default), B
GVRP Address01-80-C2-00-00-21D, B (Default)
Reserved for use by Multiple Registration Protocol (MRP) Applications01-80-C2-00-00-22~01-80-C2-00-00-2FD (Default), B
802.1ag PDU CCM/LTM01-80-C2-00-00-31~01-80-C2-00-00-3FD, B (Default)
@@ -915,18 +915,18 @@ Figure 10. Loop Example The loop detect function can be enabled/disabled via strapping pin or registers. When the loop detection function is enabled, the RTL8305NBI sends out a broadcast 64-byte loop frame (the frequency is configured by register) and sniffs for the sent loop frame on each port to detect whether there is a network loop (or bridge loop). If a loop is detected, the RTL8305NBI will drive the external LEDs and buzzer alarm. -• The LED driven by the LDIND pin will blink -- The LEDs driven by port LED pins (see Table 4, page 8) of the ports on which the network loop is detected will all blink simultaneously +• The LED driven by the LDIND pin will blink +- The LEDs driven by port LED pins (see Table 4, page 8) of the ports on which the network loop is detected will all blink simultaneously - The buzzer driven by the LDIND pin will buzz at the same frequency as the LED blinking Both passive and active buzzers can be supported. The resonant frequency for the passive buzzer is approximately 2kHz. The buzzer and all LEDs will turn on/off simultaneously. In Figure 11, T1 is the turned-off period and T2 is the turned-on period. T1 and T2 are equal and can be configured to 400ms or 800ms. -![](images/6124cfe6c8b70c02b7c7fa66a9a697e10decded4f8828c08287acdbdafd71dbe.jpg) +![](images/6124cfe6c8b70c02b7c7fa66a9a697e10decded4f8828c08287acdbdafd71dbe.jpg) Figure 11. LED and Buzzer Control Signal for Loop Detection Loop status, LED, and buzzer indications can be cleared when one of the following conditions occurs. -- Loop frame is not detected in the next loop detection period +- Loop frame is not detected in the next loop detection period • The loop port links down The Loop frame length is 64 bytes. Its format is shown below. @@ -1014,11 +1014,11 @@ The priority assigned to all ingress packets of the VLAN specified by the VID fi The main VLAN features of the RTL8305NBI are as follows: -• Supports up to 16 VLAN groups -• Flexible IEEE 802.1Q port/tag-based VLAN -- Four IVLs -- Leaky VLAN for ARP broadcast/unicast/multicast packets -- Leaky inter-VLAN mirror function +• Supports up to 16 VLAN groups +• Flexible IEEE 802.1Q port/tag-based VLAN +- Four IVLs +- Leaky VLAN for ARP broadcast/unicast/multicast packets +- Leaky inter-VLAN mirror function - VLAN tag Insert/Remove function ## 8.1.2. Port-Based VLAN @@ -1047,8 +1047,8 @@ The RTL8305NBI supports the VLAN Insertion/Removal/replacing action for each por The RTL8305NBI provides flexible VLAN ingress and egress rules to permit comprehensive traffic control. The RTL8305NBI can filter packets on ingress according to the tag condition of the packet. For a normalized VLAN application and VLAN translation application, each of the RTL8305NBI ports can be independently configured to: -- ‘admit all frames’ -- ‘admit only tagged frames’ +- ‘admit all frames’ +- ‘admit only tagged frames’ - ‘admit only untagged frames’ Note: The priority tagged frame (VID=0) will be treated as an untagged frame. @@ -1057,10 +1057,10 @@ The RTL8305NBI can optionally discard a frame associated with a VLAN of which th For the egress filter, the RTL8305NBI drops the frame if this frame belongs to a VLAN but its egress port is not one of the VLAN's member ports. However, there are 5 leaky options to provide exceptions for special applications. -- ‘Unicast leaky VLAN’ enables inter-VLAN unicast packet forwarding. That is, if the layer 2 lookup table search has a hit, then the unicast packet will be forwarded to the egress port, ignoring the egress rule -- ‘Multicast leaky VLAN’ enables inter-VLAN multicast packet forwarding. Packets may be flooded to all the multicast address group member sets, ignoring the VLAN member set domain limitation -- ‘Broadcast leaky VLAN’ enables inter-VLAN broadcast packet forwarding. Packets may be flooded to all the other ports, ignoring the VLAN member set domain limitation -- ‘ARP leaky VLAN’ enables broadcasting of ARP packets to all other ports, ignoring the egress rule +- ‘Unicast leaky VLAN’ enables inter-VLAN unicast packet forwarding. That is, if the layer 2 lookup table search has a hit, then the unicast packet will be forwarded to the egress port, ignoring the egress rule +- ‘Multicast leaky VLAN’ enables inter-VLAN multicast packet forwarding. Packets may be flooded to all the multicast address group member sets, ignoring the VLAN member set domain limitation +- ‘Broadcast leaky VLAN’ enables inter-VLAN broadcast packet forwarding. Packets may be flooded to all the other ports, ignoring the VLAN member set domain limitation +- ‘ARP leaky VLAN’ enables broadcasting of ARP packets to all other ports, ignoring the egress rule - ‘Inter-VLAN mirror function’ enables the inter-VLAN mirror function, ignoring the VLAN member set domain limitation. The default value is ‘Enable the inter-VLAN mirror’ ## 8.2. IEEE 802.1p Remarking Function @@ -1083,8 +1083,8 @@ The RTL8305NBI supports MIN-MAX packet scheduling. Packet scheduling offers three modes: -- Type I leaky bucket, which specifies the average rate of one queue (see Figure 14; only Q2 and Q3 have leaky bucket, Q0 and Q1 do not). The queue rate can be configured from 0kbps to the line rate in steps of 64kbps -- Weighted Round Robin (WRR), which decides which queue is selected in one slot time to guarantee the minimal packet rate of one queue +- Type I leaky bucket, which specifies the average rate of one queue (see Figure 14; only Q2 and Q3 have leaky bucket, Q0 and Q1 do not). The queue rate can be configured from 0kbps to the line rate in steps of 64kbps +- Weighted Round Robin (WRR), which decides which queue is selected in one slot time to guarantee the minimal packet rate of one queue - Port bandwidth control (type II leaky bucket) to control the bandwidth of the whole port. The port rate can be configured from 0kbps to the line rate in steps of 64kbps In addition, the RTL8305NBI can select one of the two sets of packet-scheduling configurations according to the packet-scheduling mode. Figure 14 shows the RTL8305NBI packet-scheduling diagram. @@ -1131,11 +1131,11 @@ Priority assignment specifies the priority of a received packet according to var The RTL8305NBI identifies the priority of packets based on several types of QoS priority information: -• Port-based priority -• IEEE 802.1p/Q VLAN Priority Tag -- DSCP Priority field -- IP Address -• Reassigned priority +• Port-based priority +• IEEE 802.1p/Q VLAN Priority Tag +- DSCP Priority field +- IP Address +• Reassigned priority - RLDP priority Below is a block diagram of the priority assignment. @@ -1204,9 +1204,9 @@ To support the loop detection effectively, the RTL8305NBI provides the RLDP-base As one received packet may simultaneously support several priority assignment mechanisms, e.g., Port-Based Priority, 1Q-Based Priority, DSCP-Based Priority, it may get several different priority values. -- RLDP-based priority has the highest priority -- If RLDP-based priority is disabled, the final priority is equal to the reassigned priority -- If RLDP-based priority and reassigned priority is disabled, the final priority is equal to the IP address priority +- RLDP-based priority has the highest priority +- If RLDP-based priority is disabled, the final priority is equal to the reassigned priority +- If RLDP-based priority and reassigned priority is disabled, the final priority is equal to the IP address priority - If RLDP-based priority, reassigned priority and IP address priority are disabled, the following rules are used to decide a final priority for the other five types of priority There is a 2-bit register for each of the three types of priority that represent the weight of the priority. The higher value in the register indicates a higher weight for the priority. If more than one of the three types of priority is the same, the final priority will be the one of the three types, whose priority value is greatest. @@ -1219,8 +1219,8 @@ The 2-bit priority has four numbers; however, every port has at most four output ## 8.4.1. Function Description -• 2048-entry Lookup Table (LUT) -• 4-way entry for each entry index +• 2048-entry Lookup Table (LUT) +• 4-way entry for each entry index - Supports LRU (Least Recently Used) function for lookup table learning ## 8.4.2. Address Search, Learning, and Aging @@ -1291,12 +1291,12 @@ If some destination ports are blocking, or the buffer is full, the frames to the There are two types of drop: -- Input Drop: Drop the frame directly. Do not forward to any port +- Input Drop: Drop the frame directly. Do not forward to any port - Output Drop: Forward only to non-blocking ports For the RTL8305NBI, the dropping of broadcast, multicast, and unknown DA frames can be controlled independently. -1. Broadcast packet from Port 0. +1. Broadcast packet from Port 0. 2. Buffer of Port 4 is full, others are not full. ![](images/4fe8f9acb653060f87c94c3c6953b00ba53ca74abddd65eb47add29d9aaa4aea.jpg) @@ -1332,7 +1332,7 @@ graph LR Figure 16. Broadcast Input Drop vs. Output Drop -1. Multicast packet from Port 0. +1. Multicast packet from Port 0. 2. Buffer of Port 4 is full, Port 1 is not full. ![](images/3135275e347bf51648ad50ff6efa0c45e2cd3bc7d7c5339fd025eefb82ae4f75.jpg) @@ -1381,7 +1381,7 @@ Some LED pins are dual function pins: input operation for configuration upon res Figure 18 shows example circuits for LEDs. Typical values for pull-down resistors are 10KΩ. -![](images/0adbe7f62e1c38cd50ea0890e6ebd215d7c8805643091907bd9562688f173534.jpg) +![](images/0adbe7f62e1c38cd50ea0890e6ebd215d7c8805643091907bd9562688f173534.jpg) Figure 18. Floating and Pull-High of LED Pins for LED ## 8.8. Energy-Efficient Ethernet (EEE) @@ -1392,7 +1392,7 @@ At the transmitter side, the RTL8305NBI port 0\~4 can automatically enter or qui There are two types of wake-up: -- Packets in a high priority queue or a control packet (e.g., a PAUSE frame). These can wake up the port immediately +- Packets in a high priority queue or a control packet (e.g., a PAUSE frame). These can wake up the port immediately - Packet in a low priority queue that reach a preset number. A port in LPI mode can be woken up by low priority packets when the number of the cumulated low priority packets exceeds the preset threshold or a delay timer expires At the receiver side, each embedded PHY of the RTL8305NBI will automatically respond to the request from the link partner to enter or quit the LPI mode. @@ -1429,11 +1429,11 @@ Table 18. DC Characteristics
ParameterSYMConditionMinTypicalMaxUnits
TTL Input High Voltage $V_{ih}$ -2.0--V
TTL Input Low Voltage $V_{il}$ ---0.8V
TTL Input Current $I_{in}$ --10-10μA
TTL Input Capacitance $C_{in}$ --3-pF
Output High Voltage $V_{oh}$ -2.25--V
Output Low Voltage $V_{ol}$ ---0.4V
Output Three State Leakage Current $|I_{OZ}|$ ---10μA
Power Supply Current for 1.0VIcc10Base-T, idle-31-mA
10Base-T, Peak continuous 100% utilization-32-
100Base-TX, idle-81-
100Base-TX, Peak continuous 100% utilization-81-
Link down-30-
Power Supply Current for 3.3VIcc10Base-T, idle-18-mA
10Base-T, Peak continuous 100% utilization-81-
100Base-TX, idle-95-
100Base-TX, Peak continuous 100% utilization-95-
Link down-18-
Total Power Consumption for All PortsPS10Base-T, idle-89.4-mW
10Base-T, Peak continuous 100% utilization-301.6-
100Base-TX, idle-391.5-
100Base-TX, Peak continuous 100% utilization-393.5-
Link down-89.4-
-Note: All power supply currents are measured under the following conditions: -1. DVDDL=AVDDL=AVDDHPLL=1.0V; DVDDH=AVDDH=AVDDHPLL=3.3V. -2. Room temperature. -3. The EEE and Green features are disabled. -4. All LEDs are in low-active mode. +Note: All power supply currents are measured under the following conditions: +1. DVDDL=AVDDL=AVDDHPLL=1.0V; DVDDH=AVDDH=AVDDHPLL=3.3V. +2. Room temperature. +3. The EEE and Green features are disabled. +4. All LEDs are in low-active mode. 5. LDO power is not included. ## 9.4. Thermal Characteristics @@ -1525,7 +1525,7 @@ Table 24. EEPROM Auto-Load Timing Characteristics
SymbolDimension in mmDimension in inch
MinNomMaxMinNomMax
A0.750.851.000.0300.0340.039
A10.000.020.050.0000.0010.002
A30.20 REF0.008 REF
b0.150.200.250.0060.0080.010
D/E6.00BSC0.236BSC
D2/E24.154.44.650.1630.1730.183
e0.40BSC0.016BSC
L0.300.400.500.0120.0160.020
-Note 1: CONTROLLING DIMENSION: MILLIMETER (mm). +Note 1: CONTROLLING DIMENSION: MILLIMETER (mm). Note 2: REFERENCE DOCUMENT: JEDEC MO-220. ## 11. Ordering Information @@ -1546,4 +1546,4 @@ Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047 -www.realtek.com \ No newline at end of file +www.realtek.com diff --git a/docs/芯片手册/SD2506API-G.md b/docs/芯片手册/SD2506API-G.md index 71e53bda..d6e389f8 100644 --- a/docs/芯片手册/SD2506API-G.md +++ b/docs/芯片手册/SD2506API-G.md @@ -16,34 +16,34 @@ SD2506API内置单路定时/报警中断输出,报警中断时间可最长设至 ## 2.特性 -低功耗： 0.8μA 典型值(内部电池供电，Ta=25℃)。 -工作电压：2.7V～5.5V，工作温度：-30℃～+80℃。 -标准IIC总线接口方式,最高速度400KHZ(4.5V～5.5V)。 - 年、月、日、星期、时、分、秒的BCD码输入/输出,并可通过独立的地址访问各时间寄存器。 -闰年自动调整功能(从2000年～2099年)。 -可选择12/24小时制式. -. 内置年、月、日、星期、时、分、秒共7字节的报警数据寄存器及1字节的报警允许寄存器。 -内置70字节通用SRAM寄存器可用于存储用户的一般数据。 -三种中断均可选择从INT脚输出,并具有两个中断标志位。 - 内置年、月、日、星期、时、分、秒共7字节的报警数据寄存器及1字节的报警允许寄存器，共有96种组合报警方式，并有单事件报警和周期性报警两种中断输出模式，报警时间最长可设至100年。 +低功耗： 0.8μA 典型值(内部电池供电，Ta=25℃)。 +工作电压：2.7V～5.5V，工作温度：-30℃～+80℃。 +标准IIC总线接口方式,最高速度400KHZ(4.5V～5.5V)。 + 年、月、日、星期、时、分、秒的BCD码输入/输出,并可通过独立的地址访问各时间寄存器。 +闰年自动调整功能(从2000年～2099年)。 +可选择12/24小时制式. +. 内置年、月、日、星期、时、分、秒共7字节的报警数据寄存器及1字节的报警允许寄存器。 +内置70字节通用SRAM寄存器可用于存储用户的一般数据。 +三种中断均可选择从INT脚输出,并具有两个中断标志位。 + 内置年、月、日、星期、时、分、秒共7字节的报警数据寄存器及1字节的报警允许寄存器，共有96种组合报警方式，并有单事件报警和周期性报警两种中断输出模式，报警时间最长可设至100年。 周期性频率中断输出:从4096Hz～1/16Hz……1秒共十四种方波脉冲. -自动重置的三字节共24位的倒计时定时器,可选的2种时钟源（4096Hz、1024Hz）。 - 内置8bit转换结果的数字温度传感器，为了节省电池电量消耗，设为VDD模式下60S间隔测温一次，电池模式600S间隔测温一次。 - 内置记录历史高、低温发生时刻及相关温度值的功能；可设置高、低温报警值并从INT脚输出中断。 - 内置晶振和谐振电容，模块内部通过高精度补偿方法，实现在宽温范围内高精度的计时功能，其中25℃精度<±3.8ppm，即时钟年误差小于2分钟(在25±1℃下)。 - 内置充电电池及充电电路，累计电池电量超过550mAH,在电池满充的常温情况下内部时钟走时时间在8个月左右，电池使用寿命为5～8年时间。 - 内置电池电压检测功能，可读取当前电池电压值(三位有效数)，设置高低电池报警电压值并从INT脚输出中断。 -模块依据不同的电压自动从VDD切换到VBAT或从VBAT切换到VDD。当模块检测到主电源VDD掉到2.4V电压以下且VDD小于VBAT,模块会转为由接在VBAT的后备电池供电；当VDD大于VBAT或VDD大于2.4V,则模块会转为由VDD供电。（内置电源模式指示位PMF,VDD模式时PMF=0，VBAT模式时PMF=1）。 - 内置总线0.5秒自动复位功能(从Start命令开始计时)，保证时钟数据的有效性及可靠性,避免IIC总线挂死问题。 - 内置三个时钟数据写保护位, 避免对数据的误写操作，可更好地保护数据。 - 内置软件可控VBAT模式IIC总线通信禁止功能（BATIIC=0，VBAT模式下禁止IIC通信；BATIIC=1，VBAT模式下允许IIC通信.上电默认值BATIIC=0)，从而避免在电池供电时CPU对时钟操作所消耗的电池电量，也可避免在VDD上、下电的过程中因CPU的I/O端口所输出的不受控的杂波信号对时钟模块的误写操作，进一步提高时钟模块的可靠性。 - 在VBAT模式下，模块具有中断输出允许或禁止的功能,可满足在备用电池供电时输出中断的需要。 - 内置上电复位电路及指示位RTCF，当包括电池在内的所有电源第一次上电时该位置1。 -内置电源稳压,内部计时电压可低至2.0V。 -内置8字节的ID码，模块出厂之前设定的、全球唯一的身份识别码。 -模块在兴威帆的评估板上可通过4KV的群脉冲(EFT)干扰 -CMOS工艺。 +自动重置的三字节共24位的倒计时定时器,可选的2种时钟源（4096Hz、1024Hz）。 + 内置8bit转换结果的数字温度传感器，为了节省电池电量消耗，设为VDD模式下60S间隔测温一次，电池模式600S间隔测温一次。 + 内置记录历史高、低温发生时刻及相关温度值的功能；可设置高、低温报警值并从INT脚输出中断。 + 内置晶振和谐振电容，模块内部通过高精度补偿方法，实现在宽温范围内高精度的计时功能，其中25℃精度<±3.8ppm，即时钟年误差小于2分钟(在25±1℃下)。 + 内置充电电池及充电电路，累计电池电量超过550mAH,在电池满充的常温情况下内部时钟走时时间在8个月左右，电池使用寿命为5～8年时间。 + 内置电池电压检测功能，可读取当前电池电压值(三位有效数)，设置高低电池报警电压值并从INT脚输出中断。 +模块依据不同的电压自动从VDD切换到VBAT或从VBAT切换到VDD。当模块检测到主电源VDD掉到2.4V电压以下且VDD小于VBAT,模块会转为由接在VBAT的后备电池供电；当VDD大于VBAT或VDD大于2.4V,则模块会转为由VDD供电。（内置电源模式指示位PMF,VDD模式时PMF=0，VBAT模式时PMF=1）。 + 内置总线0.5秒自动复位功能(从Start命令开始计时)，保证时钟数据的有效性及可靠性,避免IIC总线挂死问题。 + 内置三个时钟数据写保护位, 避免对数据的误写操作，可更好地保护数据。 + 内置软件可控VBAT模式IIC总线通信禁止功能（BATIIC=0，VBAT模式下禁止IIC通信；BATIIC=1，VBAT模式下允许IIC通信.上电默认值BATIIC=0)，从而避免在电池供电时CPU对时钟操作所消耗的电池电量，也可避免在VDD上、下电的过程中因CPU的I/O端口所输出的不受控的杂波信号对时钟模块的误写操作，进一步提高时钟模块的可靠性。 + 在VBAT模式下，模块具有中断输出允许或禁止的功能,可满足在备用电池供电时输出中断的需要。 + 内置上电复位电路及指示位RTCF，当包括电池在内的所有电源第一次上电时该位置1。 +内置电源稳压,内部计时电压可低至2.0V。 +内置8字节的ID码，模块出厂之前设定的、全球唯一的身份识别码。 +模块在兴威帆的评估板上可通过4KV的群脉冲(EFT)干扰 +CMOS工艺。 封装形式:8脚的DIP封装。 ## 3.原理框图和管脚定义 @@ -162,8 +162,8 @@ GND 注: -1.在上电复位时，芯片内部不对实时时钟数据寄存器作清零或置位处理。 -2.当写实时时间数据时 $\mathrm { ( 0 0 H \widetilde { \Omega } 0 6 H ) }$ ,不可以单独对 7 个时间数据中的某一位进行写操作,否则可能会引起时间数据的错误进位,所以要修改其中某一个数据, 应一次性写入全部 7 个实时时钟数据。 +1.在上电复位时，芯片内部不对实时时钟数据寄存器作清零或置位处理。 +2.当写实时时间数据时 $\mathrm { ( 0 0 H \widetilde { \Omega } 0 6 H ) }$ ,不可以单独对 7 个时间数据中的某一位进行写操作,否则可能会引起时间数据的错误进位,所以要修改其中某一个数据, 应一次性写入全部 7 个实时时钟数据。 3. 当芯片收到读实时时钟数据命令,则所有实时时钟数据被锁存（时钟走时并不受影 响）,此功能可以避免时间数据的错读现象。 @@ -198,7 +198,7 @@ INT脚中断输出选通表 特别： -1.当日报警与星期报警均被允许即 EAD=EAW=1时，只有日报警有效,而星期报警无效，所以时间报警中断共有 96种组合方式。 +1.当日报警与星期报警均被允许即 EAD=EAW=1时，只有日报警有效,而星期报警无效，所以时间报警中断共有 96种组合方式。 2.星期报警寄存器的数据格式与实时时钟数据星期的格式不同,星期报警寄存器的位AW6、AW5、AW4、AW3、AW2、AW1、AW0分别对应星期六、星期五、星期四、星期三、星期二、 星期一、星期日,并可多位置 1,例如 AW6,AW1=1,其它位为 0,则对应在星期六，星期一会有报警。 @@ -534,10 +534,10 @@ SD2506API 写数据示例(向 14H,15H 地址写数据): 特别注意: -1．除了 WRTC1、WRTC2、WRTC3 三个写允许位，对寄存器(00H\~71H)的写操作必须确认模块处于写允状态,否则写无效。 -2．写时间同步：每次对实时时间秒寄存器的写操作时，当秒数据的 8个 bit完全写入并收到 ACK信号后，就会对秒以下的内部计数器清零，使时间同步。 -3. 从当前地址开始,每次读写完一个字节地址自动加 1。 -4．如果写入的时间数据不存在,则不改写相对应的时间寄存器的值。 +1．除了 WRTC1、WRTC2、WRTC3 三个写允许位，对寄存器(00H\~71H)的写操作必须确认模块处于写允状态,否则写无效。 +2．写时间同步：每次对实时时间秒寄存器的写操作时，当秒数据的 8个 bit完全写入并收到 ACK信号后，就会对秒以下的内部计数器清零，使时间同步。 +3. 从当前地址开始,每次读写完一个字节地址自动加 1。 +4．如果写入的时间数据不存在,则不改写相对应的时间寄存器的值。 5．为了提高数据的可靠性，当写完成后，应将模块置于写禁止状态。（参见 5.7） （4）SD2506API 数据传输的读模式 @@ -606,7 +606,7 @@ SD2506API 内置电池充电电路,当 VDD 电压正常时,内部充电自动进 ## 特别提示： -1.为了保证充电功能的正常运行，用户的程序须在每一次上电时重置 18H 寄存器的值为 82H。 +1.为了保证充电功能的正常运行，用户的程序须在每一次上电时重置 18H 寄存器的值为 82H。 2.对内置充电电池的时钟模块不上电充电时间不能超过 8 个月，不要等电池的电耗光后再去充电，否则会减少电池的使用寿命。 ## 8.上电复位 @@ -615,7 +615,7 @@ SD2506API 内置电池充电电路,当 VDD 电压正常时,内部充电自动进 ## 9.使用说明 -1.为了防止电路噪声问题,请在此模块的旁边放置两个旁路电容,分别是 0.1uF 电容和10uF 电容。 +1.为了防止电路噪声问题,请在此模块的旁边放置两个旁路电容,分别是 0.1uF 电容和10uF 电容。 2.为了防止干扰,在 PCB 制作时请保证模块底部无大电流信号通过,最好能铺地。 ## 10. 应用参考电路 @@ -645,7 +645,7 @@ VDD 、VBAT 、SCL、SDA 和 INT 引脚上的电压（相对于地）……… 注： -1.因模块内置电池本体的表面温度不能超过 85℃，本产品不可以采用回流焊或波峰焊方式，最好采用烙铁焊接方式。 +1.因模块内置电池本体的表面温度不能超过 85℃，本产品不可以采用回流焊或波峰焊方式，最好采用烙铁焊接方式。 2.强度超出所列的极限参数可能导致器件的永久性损坏。这些仅仅是极限参数，并不意味着在极限条件下或在任何其它超出推荐工作条件所示参数的情况下器件能有效地工作。延长在极限参数条件上的工作时间会影响器件的可靠性。 ## 12.直流特性 @@ -662,7 +662,7 @@ Note1:此时最大电流 2mA主要是充电电流.当内部电池电压为 0V时
符号参数条件标准模式(fSCL=100kHz)快速模式(fSCL I=400kHz)单位
最小值典型值最大值最小值典型值最大值
fSCLSCL 频率100400kHz
VILSDA 和 SCL 低电平输入电压-0.30.3×VDD-0.30.3×VDDV
VIHSDA 和 SCL 高电平输入电压0.7×VDDVDD+0.30.7×VDDVDD+0.3V
VhysSDA 和 SCL 施密特触发输入滞后0.05×VDD0.05×VDDV
VOL低电平输出电压SDA 输出低电平状态下,吸收 2mA 电流时的电压0.40.4V
CpinSDA 和 SCL引脚电容TA=25°C f=1MHzVDD=5V VIN=0V VOUT=0V1010pF
tINSDA 和 SCL 输入端的脉冲宽度抑制时间10050ns
tAASCL 下降沿到 SDA 输出数据有效SCL 下降到 0.3×VDD,直到 SDA 不在 0.3×VDD至 0.7×VDD区间。900900ns
tBUF总线在 STOP 和 START之间的空闲时间SDA 在 STOP 条件下上升到 0.7×VDD,在开始条件下下降到 0.7×VDD。47001300ns
tLOW时钟低电平时间在 0.3×VDD处测量47001300ns
tHIGH时钟高电平时间在 0.7×VDD处测量4000600ns
tSU:STAIIC 启动信号的建立时间SCL 上升到 0.7×VDD至 SDA 下降沿到 0.7×VDD4700600ns
tHD:STAIIC 停止信号的保持时间在 SDA 下降沿到 0.3×VDD, SCL 下降沿到 0.7×VDD4000600ns
tSU:DAT输入数据的建立时间从 SDA 不在 0.3×VDD至 0.7×VDD范围,到 SCL 上升沿的 0.3×VDD250100ns
tHD:DAT输入数据保持时间SCL 下降沿的 0.3×VDD,到 SDA 在 0.3×VDD至 0.7×VDD区间00ns
tSU:STO停止条件的建立时间从 SCL 上升沿经过 0.7×VDD,到 SDA上升沿 0.3×VDD4000600ns
tDH数据输出的保持时间从 SCL 下降沿 0.7×VDD,到 SDA 0.3×VDD至 0.7×VDD区间00ns
$t_{R}$ SDA 和 SCL 的上升时间 $0.3 \times V_{DD}$ 至 $0.7 \times V_{DD}$ 区间1000300ns
$t_{F}$ SDA 和 SCL 的下降时间 $0.3 \times V_{DD}$ 至 $0.7 \times V_{DD}$ 区间300300ns
-IIC Timing Chart +IIC Timing Chart ![](images/28e2f0df5c853c92033967c174cdd1cf7055764c95077034acfde0e7e1c3edae.jpg)
@@ -802,12 +802,12 @@ SD2506 封装尺寸（管脚尺寸：0.5\*0.3mm，管脚公差±0.05mm） ## 一. SD2506系列应用中硬件注意事项: -(1) 对 SD2506 及 MCU 的电源\~地之间加 104 电容去高频。 -(2) 对SD2506及MCU所在的板数字电源\~地的输入端加220uF以上的电解及104电容去除电源扰动. -(3) 为了防止干扰,在 PCB 制作时请保证模块底部无大电流信号通过,最好能铺地. +(1) 对 SD2506 及 MCU 的电源\~地之间加 104 电容去高频。 +(2) 对SD2506及MCU所在的板数字电源\~地的输入端加220uF以上的电解及104电容去除电源扰动. +(3) 为了防止干扰,在 PCB 制作时请保证模块底部无大电流信号通过,最好能铺地. (4) 对MCU的复位端尽量采用可靠的复位方式,而摒弃阻容复位或直接连到VDD的方式.以下推荐廉价的三极管复位方式,当然用电压检测器或专用复位电路就更好啦. -![](images/4a911065bebf54af10afdb0752802a3b875abcff3cc81619e5b9403ea2fcc977.jpg) +![](images/4a911065bebf54af10afdb0752802a3b875abcff3cc81619e5b9403ea2fcc977.jpg) 图中 R2,R3 为分压电阻,其选值可用以下公式: Vbe/Vrst=R2/(R2+R3) @@ -822,9 +822,9 @@ D1为延时电容的放电二极管,可选用. ## 二. SD2506系列应用中软件注意事项 -1) 软件上电开始做一个几百毫秒的延时，等 MCU端口稳定后再去进行读写操作。 -2) 时钟最多半秒才读一次：这样做主要目的是考虑到时间数据的改变需要 1S，频繁去读的话是在做无用功，不但会加大电源功耗，而且会引入干扰。 -3） IIC 总线”START”里:在置 SDA 为高后要再判断 SDA 是否为高,即 SDA 是否被箝位为低,否则等 SDA 线 +1) 软件上电开始做一个几百毫秒的延时，等 MCU端口稳定后再去进行读写操作。 +2) 时钟最多半秒才读一次：这样做主要目的是考虑到时间数据的改变需要 1S，频繁去读的话是在做无用功，不但会加大电源功耗，而且会引入干扰。 +3） IIC 总线”START”里:在置 SDA 为高后要再判断 SDA 是否为高,即 SDA 是否被箝位为低,否则等 SDA 线 置高。在写命令字时:要判断ACK 是否正常,否则退出 4）IIC 总线”STOP”里:在置 SDA 为高后要再判断 SDA 是否为高,即 SDA 是否被箝位为低,否则多置 SCL 脉 @@ -847,4 +847,4 @@ https://www.whwave.com.cn/filedownload/420894 ## (2) 温度对精度的影响: -SD2506时钟具有温度补偿功能。 \ No newline at end of file +SD2506时钟具有温度补偿功能。 diff --git a/docs/芯片手册/TPAFE5160.md b/docs/芯片手册/TPAFE5160.md index ea6d09c0..6a5985fa 100644 --- a/docs/芯片手册/TPAFE5160.md +++ b/docs/芯片手册/TPAFE5160.md @@ -2,24 +2,24 @@ ## Features -• 8 Simultaneously Sampled Inputs -- Single 5-V Analog Supply and 1.71-V to 5-V $V_{DRIVE}$ -• 16-Bit ADC with 350 kSPS on All Channels -• Bipolar Inputs Ranges: ±10 V, ±5 V -- Analog Input Clamp Protection -• 1-MΩ Analog Input Impedance -- On-Chip Reference and Buffer -• On-Chip Oversampling Digital Filter -- SPI Compatible Interface -• Temperature Range: -40°C to 125°C +• 8 Simultaneously Sampled Inputs +- Single 5-V Analog Supply and 1.71-V to 5-V $V_{DRIVE}$ +• 16-Bit ADC with 350 kSPS on All Channels +• Bipolar Inputs Ranges: ±10 V, ±5 V +- Analog Input Clamp Protection +• 1-MΩ Analog Input Impedance +- On-Chip Reference and Buffer +• On-Chip Oversampling Digital Filter +- SPI Compatible Interface +• Temperature Range: -40°C to 125°C • Package: LQFP10×10-64 ## Applications -- Power Line Monitor -• Power Line Protection Relays -- Motor Control -• Data Acquisition System (DAS) +- Power Line Monitor +• Power Line Protection Relays +- Motor Control +• Data Acquisition System (DAS) • Industrial Automation and Controls ## Description @@ -32,7 +32,7 @@ The TPAFE5160 can accept ±10-V or ± 5-V true bipolar inputs with a single 5-V The zero-latency conversion with high performance also makes the device suitable for industrial automation and control applications. -Typical Application Circuit +Typical Application Circuit ![](images/2762ffa4db2bc51143440506cde64b960997e1a64f0903688628d389c1dc0a9d.jpg)
@@ -193,15 +193,15 @@ All test conditions: $T_{A} = 25^{\circ}C$ , unless otherwise noted.
ParameterMinMaxUnit
AVDD to AGND-0.37V
DVDD to DGND-0.37V
AGND to DGND-0.30.3V
Analog Input Voltage to AGND-1515V
Digital Input to DGND-0.3DVDD + 0.3V
REFIN to AGND-0.3AVDD + 0.3V
Input Current to Any Pin Except Supplies-1010mA
$T_J$ Maximum Junction Temperature-40150°C
$T_A$ Operating Temperature Range-40125°C
$T_{STG}$ Storage Temperature Range-65150°C
$T_L$ Lead Temperature (Soldering, 10 sec)260°C
-(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. -(2) This data was taken with the JEDEC low effective thermal conductivity test board. +(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. +(2) This data was taken with the JEDEC low effective thermal conductivity test board. (3) This data was taken with the JEDEC standard multilayer test boards. ESD, Electrostatic Discharge Protection
SymbolParameterConditionMinimum LevelUnit
HBMHuman Body Model ESD for all pins except analog input pinsANSI/ESDA/JEDEC JS-001 (1)±5000V
HBMHuman Body Model ESD for analog input pins onlyANSI/ESDA/JEDEC JS-001 (1)±7000V
CDMCharged Device Model ESDANSI/ESDA/JEDEC JS-002 (2)±1500V
-(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. +(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Recommended Operating Conditions @@ -250,7 +250,7 @@ All test conditions: $AV_{CC} = 5 V$ , $V_{DRIVE} = 1.7 V$ to 5.5 V, $V_{REF} = ## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs -Timing Diagrams +Timing Diagrams ![](images/ab9ed3131120172d9148c4c79d2214382249a502455cbe52ed18950d9dacc404.jpg)
@@ -318,7 +318,7 @@ V7 V8
-Figure 3. Parallel Mode, Separate CS and RD Pulses +Figure 3. Parallel Mode, Separate CS and RD Pulses ![](images/e4c998e58453c5f862866d953ac1e8da6de4b497a7140586ea5abc631c5e785d.jpg)
@@ -649,7 +649,7 @@ Information in the following application sections is not part of the 3PEAK's com ## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs -Tape and Reel Information +Tape and Reel Information ![](images/4749eae1dd6c621d0dbd7c811bca00b8cf3bd13593146bd28dc8bb4182d566ea.jpg)
@@ -689,8 +689,8 @@ K0 LQFP10x10-64 -Package Outline Dimensions -QP5(LQFP10X10-64-A) +Package Outline Dimensions +QP5(LQFP10X10-64-A) ![](images/9ce7a4caaa2788c2c2561d9e7d69c3d74fccea3315ea0ee307ae562847d01c1b.jpg)
@@ -751,7 +751,7 @@ DETAIL Y ## NOTES -1. Do not include mold flash or protrusion. +1. Do not include mold flash or protrusion. 2. This drawing is subject to change without notice.
SymbolDimensions In MillimetersDimensions In Inches
MINMAXMINMAX
A1.4001.6000.0550.063
A10.0500.1500.0020.006
A21.3501.4500.0530.057
b0.1700.2700.0070.011
c0.0900.2000.0040.008
D11.80012.2000.4650.480
D19.90010.1000.3900.398
E11.80012.2000.4650.480
E19.90010.1000.3900.398
e0.500 BSC0.020 BSC
L0.4500.7500.0180.030
θ07°07°
@@ -774,4 +774,4 @@ Trademarks. Any of the 思瑞浦 or 3PEAK trade names, trademarks, graphic marks Performance Information. Performance tests or performance range contained in this document/material are either results of design simulation or actual tests conducted under designated testing environment. Any variation in testing environment or simulation environment, including but not limited to testing method, testing process or testing temperature, may affect actual performance of the product. -Disclaimer. 3PEAK provides technical and reliability data (including data sheets), design resources (including reference designs), application or other design recommendations, networking tools, security information and other resources "As Is". 3PEAK makes no warranty as to the absence of defects, and makes no warranties of any kind, express or implied, including without limitation, implied warranties as to merchantability, fitness for a particular purpose or non-infringement of any third-party's intellectual property rights. Unless otherwise specified in writing, products supplied by 3PEAK are not designed to be used in any life-threatening scenarios, including critical medical applications, automotive safety-critical systems, aviation, aerospace, or any situations where failure could result in bodily harm, loss of life, or significant property damage. 3PEAK disclaims all liability for any such unauthorized use. \ No newline at end of file +Disclaimer. 3PEAK provides technical and reliability data (including data sheets), design resources (including reference designs), application or other design recommendations, networking tools, security information and other resources "As Is". 3PEAK makes no warranty as to the absence of defects, and makes no warranties of any kind, express or implied, including without limitation, implied warranties as to merchantability, fitness for a particular purpose or non-infringement of any third-party's intellectual property rights. Unless otherwise specified in writing, products supplied by 3PEAK are not designed to be used in any life-threatening scenarios, including critical medical applications, automotive safety-critical systems, aviation, aerospace, or any situations where failure could result in bodily harm, loss of life, or significant property damage. 3PEAK disclaims all liability for any such unauthorized use. diff --git a/docs/问题记录/GD5F2GQ5UE_Trap_Records.md b/docs/问题记录/GD5F2GQ5UE_Trap_Records.md index 26836787..fb84c90f 100644 --- a/docs/问题记录/GD5F2GQ5UE_Trap_Records.md +++ b/docs/问题记录/GD5F2GQ5UE_Trap_Records.md @@ -132,4 +132,3 @@ if (ok) { - 返回“连续区间”的辅助函数，其返回值是起点还是终点必须在注释/命名中明确， 调用方与实现必须一致 - 这类错位 bug 往往只在“区间贴到设备边界”时才触发，正常情况能过，建议测试覆盖边界块 - diff --git a/fix_chinese_final.py b/fix_chinese_final.py index ec32ee71..4cd5131d 100644 --- a/fix_chinese_final.py +++ b/fix_chinese_final.py @@ -122,16 +122,16 @@ for fname, file_fixes in fixes.items(): raw = f.read() text = raw.decode('utf-8', errors='replace') before = text.count(rep) - + for needle, replacement in file_fixes: while needle in text: text = text.replace(needle, replacement) - + after = text.count(rep) fixed = before - after total_fixed += fixed print('{}: fixed {} ({} -> {})'.format(fname, fixed, before, after)) - + with open(path, 'wb') as f: f.write(text.encode('utf-8')) diff --git a/fix_chinese_generic.py b/fix_chinese_generic.py index 4575f89e..bbd94c75 100644 --- a/fix_chinese_generic.py +++ b/fix_chinese_generic.py @@ -53,11 +53,11 @@ for fname in files: if before == 0: print('{}: clean'.format(fname)) continue - + # Apply generic pattern fixes for pattern, replacement in generic_fixes: text = re.sub(pattern, replacement, text) - + # Manual patterns for each file if 'ch395f.c' in fname: text = text.replace(rep + '?' + u'DMA 接收缓冲区偏移', u'从 DMA 接收缓冲区偏移') @@ -107,14 +107,14 @@ for fname in files: text = text.replace(u'主循环' + rep + '?s_buf_a', u'主循环读 s_buf_a') text = text.replace(u'GPIO ' + rep + '?NVIC', u'GPIO 和 NVIC') text = text.replace(u'调用' + rep + '? * 入口参数', u'调用）* 入口参数') - + after = text.count(rep) fixed = before - after total_fixed += fixed - + with open(path, 'wb') as f: f.write(text.encode('utf-8')) - + print('{}: fixed {} ({} -> {})'.format(fname, fixed, before, after)) print('\nTotal fixed: {}'.format(total_fixed)) diff --git a/fix_remaining.py b/fix_remaining.py index 28aacc7e..fd7cec38 100644 --- a/fix_remaining.py +++ b/fix_remaining.py @@ -5,23 +5,23 @@ base = 'D:\\Code\\DTU 程序\\STM32F4-Base\\' all_fixes = [ # (filename, pattern_to_match, replacement_full_line_fragment) - + # ch395f.c ('ch395f.c', 'rx_buf[' + rep + '? * 阻塞', 'rx_buf] * 阻塞'), ('ch395f.c', '默认值10' + rep + '?秒）', '默认值10 秒）'), ('ch395f.c', '默认值3' + rep + '? uint8_t', '默认值3 uint8_t'), - + # ch395f_test.c ('ch395f_test.c', '回显' + rep + '? \ufffd?PING', '回显，PING'), ('ch395f_test.c', '创建' + rep + '? UDP', '创建 UDP'), ('ch395f_test.c', 'IP，打印结果 ' + rep + '?广播', 'IP，打印结果，广播'), - + # gd5f2gq5ue.c ('gd5f2gq5ue.c', '块对' + rep + '? * size', '块对齐 * size'), - + # sd2506.c ('sd2506.c', '个位存入' + rep + '4 ）', '个位存入低 4 ）'), - + # tpafe5160.c ('tpafe5160.c', '6位数据总线' + rep + '?GPIOG', '16位数据总线（GPIOG'), ('tpafe5160.c', '滞后约 18-24ns' + rep + '? *', '滞后约 18-24ns，*'), @@ -61,7 +61,7 @@ for fname, needle, replacement in all_fixes: raw = f.read() text = raw.decode('utf-8', errors='replace') before = text.count(rep) - + if needle in text: text = text.replace(needle, replacement) after = text.count(rep) @@ -82,7 +82,7 @@ for fname, needle, replacement in all_fixes: break if not found: print('{}: pattern not found at all'.format(fname)) - + with open(path, 'wb') as f: f.write(text.encode('utf-8')) diff --git a/test/ch395f_test_task.c b/test/ch395f_test_task.c index 0a2bd414..b9f1ab2a 100644 --- a/test/ch395f_test_task.c +++ b/test/ch395f_test_task.c @@ -377,9 +377,9 @@ static void phase2_tc201(void) HAL_Delay(10); /* 10ms 轮询周期，直至 CONNECT 或超时退出 */ } TEST_CHECK(ok, "TC201 step4 connected"); - if (!ok) { - ch395f_close_socket(sock); - return; + if (!ok) { + ch395f_close_socket(sock); + return; } HAL_Delay(100); @@ -391,17 +391,17 @@ static void phase2_tc201(void) uint16_t int_st = ch395f_get_glob_int_status_all(); if (int_st & (1U << (sock + 4))) { uint8_t si = ch395f_get_sock_int_status(sock); - if (si & CH395F_SINT_STAT_SENBUF_FREE) { - ok = 1; - break; + if (si & CH395F_SINT_STAT_SENBUF_FREE) { + ok = 1; + break; } } HAL_Delay(10); } TEST_CHECK(ok, "TC201 step5 sendbuf_free"); - if (!ok) { - ch395f_close_socket(sock); - return; + if (!ok) { + ch395f_close_socket(sock); + return; } /* 步6：等待回显并逐字节验证（递增模式 0x00..0x3F） @@ -445,9 +445,9 @@ static void phase2_tc201(void) /* 与发送的递增模式逐字节比对：tx[k]=k，任一不符立即置 FAIL 退出 */ for (p = 0; p < n; p++) { - if (rx[p] != tx[p]) { - match = 0; - break; + if (rx[p] != tx[p]) { + match = 0; + break; } } TEST_CHECK(match, "TC201 step6 echo verify"); @@ -487,9 +487,9 @@ static void phase2_tc201(void) while (HAL_GetTick() - tick < 5000) { uint8_t st[2]; ch395f_get_socket_status(sock, st); - if (st[0] == CH395F_SOCKET_CLOSED) { - ok = 1; - break; + if (st[0] == CH395F_SOCKET_CLOSED) { + ok = 1; + break; } HAL_Delay(50); } diff --git a/test/net_test_task.c b/test/net_test_task.c index 43e8257c..93d1a86f 100644 --- a/test/net_test_task.c +++ b/test/net_test_task.c @@ -160,8 +160,8 @@ static int32_t phase7_session(uint16_t local_port) uint32_t tick = HAL_GetTick(); while (HAL_GetTick() - tick < PHASE7_CONN_TIMEOUT_MS) { net_sock_t *sk = net_get_sock(sockfd); - if (sk && sk->state == NET_SOCK_STATE_ESTABLISHED) { - connected = 1; break; + if (sk && sk->state == NET_SOCK_STATE_ESTABLISHED) { + connected = 1; break; } if (sk && sk->state == NET_SOCK_STATE_CLOSED) { break; /* 连接失败 */ diff --git a/ui_cn_chars.txt b/ui_cn_chars.txt index 786bd31b..23b523fd 100644 --- a/ui_cn_chars.txt +++ b/ui_cn_chars.txt @@ -1 +1 @@ -主事交件位作信值元入全出制功动占厂压参双变号告复字定实家开强归录恢息手护据操故数时显未本查检波流测版现电界直看示系络维网置能自节装警认讯记设询调通遥部配量间零面默（） \ No newline at end of file +主事交件位作信值元入全出制功动占厂压参双变号告复字定实家开强归录恢息手护据操故数时显未本查检波流测版现电界直看示系络维网置能自节装警认讯记设询调通遥部配量间零面默（） diff --git a/待处理内容.md b/待处理内容.md index 3a8d164f..1c401819 100644 --- a/待处理内容.md +++ b/待处理内容.md @@ -1 +1 @@ -* 严格的内存使用情况排查，现在所有任务的内存都是往大的给的，导致内存不够用，后面要仔细排查内存的预算情况。 \ No newline at end of file +* 严格的内存使用情况排查，现在所有任务的内存都是往大的给的，导致内存不够用，后面要仔细排查内存的预算情况。