关键芯片都驱动，且测试成功
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docs/CH395F.md
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docs/FlashDB使用说明.md
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# FlashDB 使用说明
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## 1. 概述
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本项目使用 [FlashDB](https://github.com/armink/FlashDB) 嵌入式数据库，提供两种数据库：
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- **KVDB**（键值数据库）：存储键值对，类似 Redis 简化版
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- **TSDB**（时序数据库）：存储带时间戳的日志记录，支持按时间范围查询
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底层存储介质为 GD5F2GQ5UE SPI NAND Flash（256MB），通过 FAL（Flash Abstraction Layer）抽象层访问。
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## 2. 软件架构
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```
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┌─────────────────────────────────────────┐
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│ 用户应用（main.c） │
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├──────────────┬──────────────────────────┤
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│ fdb_kvdb │ fdb_tsdb │
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│ （键值数据库） │ （时序数据库） │
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├──────────────┴──────────────────────────┤
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│ FlashDB 核心 │
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│ Lib/FlashDB/src/ │
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├─────────────────────────────────────────┤
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│ FAL 抽象层 │
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│ Lib/FlashDB/port/fal/src/ │
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├─────────────────────────────────────────┤
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│ FAL 设备适配层 │
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│ fal_flash_gd5f2gq5ue.c │
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├─────────────────────────────────────────┤
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│ GD5F2GQ5UE SPI NAND 驱动 │
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│ gd5f2gq5ue.c │
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├─────────────────────────────────────────┤
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│ SPI1 硬件外设 + HAL 驱动 │
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└─────────────────────────────────────────┘
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```
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## 3. 文件清单
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| 文件 | 说明 | 是否自编 |
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|------|------|----------|
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| `Drivers/BSP/GD5F2GQ5UE/gd5f2gq5ue.h` | NAND 驱动头文件 | 是 |
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| `Drivers/BSP/GD5F2GQ5UE/gd5f2gq5ue.c` | NAND 驱动实现 | 是 |
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| `Drivers/BSP/GD5F2GQ5UE/fal_flash_gd5f2gq5ue.c` | FAL 设备适配 | 是 |
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| `Drivers/BSP/GD5F2GQ5UE/fal_cfg.h` | FAL 设备表 + 分区表 | 是 |
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| `Drivers/BSP/GD5F2GQ5UE/fdb_cfg.h` | FlashDB 功能配置 | 是 |
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| `Lib/FlashDB/src/` | FlashDB 核心源码 | 否 |
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| `Lib/FlashDB/port/fal/src/` | FAL 硬件抽象框架源码 | 否 |
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## 4. 硬件配置
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### 4.1 Flash 芯片参数
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| 参数 | 值 |
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|------|-----|
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| 型号 | GD5F2GQ5UE（GigaDevice） |
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| 总容量 | 2Gbit = 256MB |
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| 页大小 | 2048 字节 |
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| Spare 区 | 64 字节 |
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| 每块页数 | 64 页 |
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| 块大小 | 128KB（64 × 2048） |
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| 总块数 | 2048 |
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| SPI 模式 | Mode 0（CPOL=0, CPHA=0） |
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| SPI 时钟 | 42MHz（APB2=84MHz, 分频=2） |
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| MID | 0xC8 |
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| DID | 0x52 |
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### 4.2 引脚连接
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| 信号 | STM32 引脚 | 方向 | 说明 |
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|------|-----------|------|------|
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| CS# | PE0 | OUT | 片选，低有效 |
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| SCLK | PB3 | OUT | SPI1 时钟 |
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| MOSI | PB5 | OUT | SPI1 主出从入 |
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| MISO | PB4 | IN | SPI1 主入从出 |
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| WP# | PB8 | OUT | 写保护，低有效（拉高禁用） |
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| HOLD# | PE1 | OUT | 保持，低有效（拉高禁用） |
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### 4.3 GPIO 初始化
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CubeMX 中需确保以下 GPIO 上电默认电平：
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- **CS#** (PE0)：上电输出 **高电平**（未选中）
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- **HOLD#** (PE1)：上电输出 **高电平**（不保持）
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- **WP#** (PB8)：上电输出 **高电平**（不禁用写保护）
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> 若 GPIO 初始电平错误，SPI 通信将完全无响应。
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## 5. 分区规划
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| 分区名 | 设备 | 偏移 | 大小 | 用途 |
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|--------|------|------|------|------|
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| fdb_kvdb1 | gd5f2gq5ue | 0 | 64MB | KVDB 键值数据库 |
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| fdb_tsdb1 | gd5f2gq5ue | 64MB | 64MB | TSDB 时序数据库 |
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| （未分配） | - | 128MB | 128MB | 剩余空间 |
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共使用 128MB / 256MB，剩余 128MB 可扩展。
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## 6. 初始化流程
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```
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1. HAL_Init()
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2. SystemClock_Config()
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3. MX_GPIO_Init() ← CS#/HOLD#/WP# 初始电平
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4. MX_USART1_UART_Init() ← 调试串口
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5. MX_SPI2_Init() ← CH395F 以太网
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6. MX_SPI1_Init() ← GD5F2GQ5UE NAND
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7. gd5f2gq5ue_init() ← NAND 初始化
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8. fdb_kvdb_init() ← FlashDB KVDB 初始化
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```
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### 6.1 gd5f2gq5ue_init() 内部步骤
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```
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1. CS#/WP#/HOLD# 拉高
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2. 发送复位命令（FFh），等待 5ms
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3. 读取芯片 ID（9Fh），校验 MID=0xC8, DID=0x52
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4. 使能内部 ECC：SET_FEATURE(B0h, 10h)
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5. 解除块保护：SET_FEATURE(A0h, 00h)
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```
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> **关键点**：SET_FEATURE 命令前必须先发写使能（06h），否则设置不生效。
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## 7. KVDB 使用方法
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### 7.1 初始化
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```c
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#include "flashdb.h"
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static struct fdb_kvdb kvdb;
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/* path 参数对应分区表中的分区名 "fdb_kvdb1" */
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/* default_kv 传 NULL 表示不使用默认键值 */
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int ret = fdb_kvdb_init(&kvdb, "db", "fdb_kvdb1", NULL, NULL);
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if (ret != FDB_NO_ERR) {
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/* 初始化失败处理 */
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}
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```
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### 7.2 字符串读写
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```c
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/* 写入字符串 */
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fdb_kv_set(&kvdb, "device_name", "STM32F407-DTU");
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/* 读取字符串（返回内部缓存指针，下次写入同一 key 后失效） */
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char *val = fdb_kv_get(&kvdb, "device_name");
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if (val) {
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printf("device_name = %s\n", val);
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}
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```
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### 7.3 二进制数据读写（Blob）
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```c
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#include <string.h>
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/* 写入二进制数据 */
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uint32_t temp = 2560;
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fdb_kv_set_blob(&kvdb, "temperature",
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fdb_blob_make(NULL, &temp, sizeof(temp)));
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/* 读取二进制数据 */
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uint32_t read_temp = 0;
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fdb_kv_get_blob(&kvdb, "temperature",
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fdb_blob_make(NULL, &read_temp, sizeof(read_temp)));
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printf("temperature = %u\n", read_temp);
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```
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### 7.4 删除键
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```c
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fdb_kv_del(&kvdb, "device_name");
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```
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### 7.5 遍历所有键
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```c
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struct fdb_kv kv;
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struct fdb_kv_iterator itr;
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fdb_kv_iterator_init(&kvdb, &itr);
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while (fdb_kv_iterate(&kvdb, &itr)) {
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kv = itr.curr;
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printf("key: %s\n", kv.name);
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}
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```
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### 7.6 打印所有键值
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```c
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fdb_kv_print(&kvdb);
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```
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## 8. TSDB 使用方法
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### 8.1 获取时间戳
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FlashDB 需要用户提供时间戳获取函数。本项目使用 HAL_GetTick()（毫秒）：
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```c
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static fdb_time_t get_time(void)
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{
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return (fdb_time_t)HAL_GetTick();
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}
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```
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### 8.2 初始化
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```c
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static struct fdb_tsdb tsdb;
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/* max_len 参数限制单条记录最大长度 */
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int ret = fdb_tsdb_init(&tsdb, "tsdb", "fdb_tsdb1",
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get_time, 256, NULL);
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```
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### 8.3 追加记录
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```c
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/* 写入二进制数据，自动附加当前时间戳 */
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uint32_t sensor_val = 3200;
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fdb_tsl_append(&tsdb,
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fdb_blob_make(NULL, &sensor_val, sizeof(sensor_val)));
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```
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### 8.4 遍历记录
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```c
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/* 正序遍历 */
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fdb_tsl_iter(&tsdb, tsl_cb_func, NULL);
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/* 逆序遍历 */
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fdb_tsl_iter_reverse(&tsdb, tsl_cb_func, NULL);
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/* 按时间范围遍历 */
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fdb_tsl_iter_by_time(&tsdb, from_time, to_time, tsl_cb_func, NULL);
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```
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回调函数原型：
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```c
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static void tsl_cb_func(struct fdb_tsl *tsl, void *arg)
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{
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struct fdb_blob blob;
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uint32_t val;
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/* 读取数据 */
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fdb_blob_read((fdb_db_t)&tsl,
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fdb_tsl_to_blob(tsl, fdb_blob_make(&blob, &val, sizeof(val))));
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printf("ts=%lu, val=%lu\n", tsl->time, val);
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}
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```
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### 8.5 查询记录数量
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```c
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size_t count = fdb_tsl_query_count(&tsdb, from_time, to_time,
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FDB_TSL_STATUS_APPEND);
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```
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### 8.6 清理所有记录
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```c
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fdb_tsl_clean(&tsdb);
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```
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## 9. 配置文件说明
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### 9.1 fdb_cfg.h
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| 宏 | 说明 |
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|----|------|
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| `FDB_USING_KVDB` | 启用 KVDB |
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| `FDB_USING_TSDB` | 启用 TSDB |
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| `FDB_USING_FAL_MODE` | 使用 FAL 模式（非文件系统） |
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| `FDB_WRITE_GRAN` | 写入粒度 8（字节可编程） |
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| `FDB_DEBUG_ENABLE` | 启用调试输出 |
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| `FDB_KV_AUTO_UPDATE` | KVDB 版本变化时自动更新（默认关闭） |
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### 9.2 fal_cfg.h
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分区表定义，修改分区大小需同时调整偏移和大小：
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```c
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#define FAL_PART_TABLE \
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{ \
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{FAL_PART_MAGIC_WORD, "fdb_kvdb1", "gd5f2gq5ue", 0, 64*1024*1024, 0}, \
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{FAL_PART_MAGIC_WORD, "fdb_tsdb1", "gd5f2gq5ue", 64*1024*1024, 64*1024*1024, 0}, \
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}
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```
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字段顺序：`{魔数, 分区名, 设备名, 偏移, 大小, 标志}`
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## 10. Keil 工程配置
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### 10.1 头文件搜索路径
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在 Keil 工程 Options → C/C++ → Include Paths 中添加：
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```
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../Drivers/BSP/GD5F2GQ5UE
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../Lib/FlashDB/inc
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../Lib/FlashDB/port/fal/inc
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```
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### 10.2 编译的源文件
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需在 Keil 工程中添加以下源文件：
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```
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Drivers/BSP/GD5F2GQ5UE/gd5f2gq5ue.c
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Drivers/BSP/GD5F2GQ5UE/fal_flash_gd5f2gq5ue.c
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Lib/FlashDB/src/fdb.c
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Lib/FlashDB/src/fdb_kvdb.c
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Lib/FlashDB/src/fdb_tsdb.c
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Lib/FlashDB/src/fdb_utils.c
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Lib/FlashDB/port/fal/src/fal.c
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Lib/FlashDB/port/fal/src/fal_flash.c
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Lib/FlashDB/port/fal/src/fal_partition.c
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```
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### 10.3 全局宏定义
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确保工程中定义了：
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```
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USE_HAL_DRIVER, STM32F407xx
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```
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## 11. 注意事项
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### 11.1 NAND Flash 特性
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1. **写前必须擦除**：NAND 只能将 1→0，不能 0→1。写入前目标块必须先擦除（全部变为 0xFF）
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2. **擦除单位是块**：最小擦除单位 128KB，不能按页擦除
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3. **写入单位是页**：单次写入不超过一页（2048 字节），跨页需驱动层拆分
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4. **Spare 区不可直接访问**：驱动已使能内部 ECC，Spare 区由芯片硬件管理
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### 11.2 驱动层注意事项
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1. **每次 SPI 事务前**：必须 `CS_LOW()` 拉低片选
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2. **每次 SPI 事务后**：必须 `CS_HIGH()` 拉高片选
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3. **SET_FEATURE 前必须写使能**：先发 06h，再发 1Fh + 地址 + 数据
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4. **块擦除地址是字节地址**：D8h 命令的参数 = 块编号 × 128KB（不是块编号本身）
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5. **读取 ID 需跳过 dummy 字节**：9Fh 返回 3 字节，第 0 字节无意义，第 1 字节 MID，第 2 字节 DID
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### 11.3 FlashDB 使用注意事项
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1. **fdb_kv_get 返回值是内部缓存**：下次对同一 key 写入后，之前返回的指针失效
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2. **TSDB 需要用户提供时间戳**：通过 `get_time` 回调，本项目使用 `HAL_GetTick()`
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3. **fdb_kvdb_init 的 path 参数**：对应分区表中的分区名 `"fdb_kvdb1"`
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4. **FlashDB 开启 FDB_DEBUG_ENABLE 后**：会通过 `fdb_print()` 输出调试信息，需确保有可用的输出（如 printf 重定向到串口）
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5. **分区大小修改后**：需同步更新 `fal_cfg.h` 中的偏移和大小
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### 11.4 常见问题
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| 现象 | 可能原因 | 解决方法 |
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|------|----------|----------|
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| init 返回 -6 (ID_MISMATCH) | SPI 通信失败或芯片未上电 | 检查接线、GPIO 初始电平、虚焊 |
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| KVDB init 失败 | 分区名不匹配 | 确认 `fdb_kvdb_init` 的 path 与 `fal_cfg.h` 一致 |
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| 写入后读取为空 | 未擦除或写入失败 | 检查写入返回值，确认目标块已擦除 |
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| 读取数据异常 | ECC 错误 | 检查 `gd5f2gq5ue_init` 是否成功使能 ECC |
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| SET_FEATURE 未生效 | 缺少写使能命令 | 确认 `gd5f_set_feature` 中先调用 `gd5f_write_enable()` |
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## 12. 调试方法
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||||
### 12.1 串口调试输出
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||||
FlashDB 调试输出通过 `fdb_print` 宏实现。在 `fdb_cfg.h` 中定义 `FDB_DEBUG_ENABLE` 后，FlashDB 内部操作会自动输出到标准输出。
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||||
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确保 Keil 工程中 `printf` 已重定向到 USART1（PA9/PA10, 115200bps）。
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||||
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||||
### 12.2 NAND 驱动调试
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||||
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||||
可通过串口输出以下信息验证驱动工作正常：
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||||
|
||||
```c
|
||||
/* 读取芯片 ID */
|
||||
uint8_t mid, did;
|
||||
gd5f2gq5ue_read_id(&mid, &did);
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||||
printf("MID=0x%02X DID=0x%02X\n", mid, did);
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||||
/* 预期输出：MID=0xC8 DID=0x52 */
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||||
|
||||
/* 初始化测试 */
|
||||
int ret = gd5f2gq5ue_init();
|
||||
printf("init ret=%d\n", ret);
|
||||
/* 预期输出：init ret=0 */
|
||||
```
|
||||
|
||||
### 12.3 FAL 设备注册验证
|
||||
|
||||
```c
|
||||
#include "fal.h"
|
||||
|
||||
/* 检查 FAL 是否初始化成功 */
|
||||
int ret = fal_init();
|
||||
printf("fal_init ret=%d\n", ret);
|
||||
/* 预期输出：fal_init ret=0 */
|
||||
```
|
||||
1843
docs/GD5F2GQ5UExxG.md
Normal file
1843
docs/GD5F2GQ5UExxG.md
Normal file
File diff suppressed because one or more lines are too long
1549
docs/RTL8305NBI-CG.md
Normal file
1549
docs/RTL8305NBI-CG.md
Normal file
File diff suppressed because it is too large
Load Diff
850
docs/SD2506API-G.md
Normal file
850
docs/SD2506API-G.md
Normal file
File diff suppressed because one or more lines are too long
777
docs/TPAFE5160.md
Normal file
777
docs/TPAFE5160.md
Normal file
@@ -0,0 +1,777 @@
|
||||
# 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
## Features
|
||||
|
||||
• 8 Simultaneously Sampled Inputs
|
||||
- Single 5-V Analog Supply and 1.71-V to 5-V $V_{DRIVE}$
|
||||
• 16-Bit ADC with 350 kSPS on All Channels
|
||||
• Bipolar Inputs Ranges: ±10 V, ±5 V
|
||||
- Analog Input Clamp Protection
|
||||
• 1-MΩ Analog Input Impedance
|
||||
- On-Chip Reference and Buffer
|
||||
• On-Chip Oversampling Digital Filter
|
||||
- SPI Compatible Interface
|
||||
• Temperature Range: -40°C to 125°C
|
||||
• Package: LQFP10×10-64
|
||||
|
||||
## Applications
|
||||
|
||||
- Power Line Monitor
|
||||
• Power Line Protection Relays
|
||||
- Motor Control
|
||||
• Data Acquisition System (DAS)
|
||||
• Industrial Automation and Controls
|
||||
|
||||
## Description
|
||||
|
||||
The TPAFE5160 is a 16-bit, 8-channel simultaneous sampling, successive approximation (SAR) ADC. Each channel has a complete analog front end, as well as an ADC operating at 350 kSPS per channel. The analog front end features the input clamp, a programmable gain amplifier (PGA) with a high input impedance of 1 MΩ, a low pass filter, and an ADC input driver.
|
||||
|
||||
The device features an internal precision reference with buffer to drive the ADC. A digital interface supports serial, parallel and parallel byte communication, which can be used with various host controllers.
|
||||
|
||||
The TPAFE5160 can accept ±10-V or ± 5-V true bipolar inputs with a single 5-V supply. Also, the high input impedance allows direct connection to transformers or other sensors without external driver circuits.
|
||||
|
||||
The zero-latency conversion with high performance also makes the device suitable for industrial automation and control applications.
|
||||
|
||||
Typical Application Circuit
|
||||
|
||||
|
||||
<details>
|
||||
<summary>flowchart</summary>
|
||||
|
||||
This diagram illustrates the architecture and signal flow of an electronic circuit, specifically detailing the signal processing flow from input AIN to digital interface, including amplification, ADC driver, and feedback loops.
|
||||
</details>
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
## Table of Contents
|
||||
|
||||
Features....1
|
||||
|
||||
Applications....1
|
||||
|
||||
Description....1
|
||||
|
||||
Typical Application Circuit....1
|
||||
|
||||
Product Family Table....3
|
||||
|
||||
Revision History....4
|
||||
|
||||
Pin Configuration and Functions....5
|
||||
|
||||
Specifications....8
|
||||
|
||||
Absolute Maximum Ratings (1)....8
|
||||
|
||||
ESD, Electrostatic Discharge Protection....8
|
||||
|
||||
Recommended Operating Conditions....8
|
||||
|
||||
Thermal Information....9
|
||||
|
||||
Electrical Characteristics....10
|
||||
|
||||
Timing Specifications....13
|
||||
|
||||
Timing Diagrams....16
|
||||
|
||||
Detailed Description....18
|
||||
|
||||
Overview....18
|
||||
|
||||
Feature Description....18
|
||||
|
||||
Device Functional Modes....19
|
||||
|
||||
Device Modes of Operation....21
|
||||
|
||||
Application and Implementation....24
|
||||
|
||||
Tape and Reel Information....25
|
||||
|
||||
Package Outline Dimensions....26
|
||||
|
||||
LQFP10x10-64....26
|
||||
|
||||
Order Information....27
|
||||
|
||||
IMPORTANT NOTICE AND DISCLAIMER....28
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
Product Family Table
|
||||
|
||||
<table><tr><td>Order Number</td><td>Input Range (V)</td><td>Package</td></tr><tr><td>TPAFE5160SI08-QP7R</td><td>±10, ±5</td><td>LQFP10×10-64</td></tr></table>
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
Revision History
|
||||
|
||||
<table><tr><td>Date</td><td>Revision</td><td>Notes</td></tr><tr><td>2021-11-15</td><td>Rev.Pre.0</td><td>Pre-release version.</td></tr><tr><td>2022-03-01</td><td>Rev.Pre.1</td><td>Updated the diagram and the EC table.</td></tr><tr><td>2022-05-10</td><td>Rev.Pre.2</td><td>Updated the EC table.</td></tr><tr><td>2022-05-22</td><td>Rev.Pre.3</td><td>Updated the tape and reel parameters.</td></tr><tr><td>2022-06-20</td><td>Rev.Pre.4</td><td>Updated the EC table.</td></tr><tr><td>2022-11-21</td><td>Rev.Pre.5</td><td>Updated Timing Specifications and Timing Diagrams.</td></tr><tr><td>2023-07-10</td><td>Rev.A.0</td><td>Initial released version.</td></tr><tr><td>2024-11-26</td><td>Rev.A.1</td><td>Updated to a new datasheet format.Updated Timing Specifications.</td></tr></table>
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
## Pin Configuration and Functions
|
||||
|
||||
|
||||
|
||||
<details>
|
||||
<summary>text_image</summary>
|
||||
|
||||
AIN_8GND
|
||||
AIN_8P
|
||||
AIN_7GND
|
||||
AIN_7P
|
||||
AIN_6GND
|
||||
AIN_6P
|
||||
AIN_5GND
|
||||
AIN_5P
|
||||
AIN_4GND
|
||||
AIN_4P
|
||||
AIN_3GND
|
||||
AIN_3P
|
||||
AIN_2GND
|
||||
AIN_2P
|
||||
AIN_1GND
|
||||
AIN_1P
|
||||
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
|
||||
AVDD 1
|
||||
AGND 2
|
||||
OS0 3
|
||||
OS1 4
|
||||
OS2 5
|
||||
PAR/SER/BYTE SEL 6
|
||||
STBY 7
|
||||
RANGE 8
|
||||
CONVSTA 9
|
||||
CONVSTB 10
|
||||
RESET 11
|
||||
RD/SCLK 12
|
||||
OS 13
|
||||
BUSY 14
|
||||
FRSTDATA 15
|
||||
DB0 16
|
||||
48 AVDD
|
||||
47 AGND
|
||||
46 REF/GND
|
||||
45 REF/CAPB
|
||||
44 REF/CAPA
|
||||
43 REF/GND
|
||||
42 REF/IN/REFOUT
|
||||
41 AGND
|
||||
40 AGND
|
||||
39 REGCAP2
|
||||
38 AVDD
|
||||
37 AVDD
|
||||
36 REGCAP1
|
||||
35 AGND
|
||||
34 REF/SEL
|
||||
33 DB15/BYTE SEL
|
||||
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
|
||||
DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14/HBEN
|
||||
</details>
|
||||
|
||||
Table 1. Pin Functions
|
||||
|
||||
<table><tr><td colspan="2">Pin</td><td rowspan="2">I/O</td><td rowspan="2">Description</td></tr><tr><td>No.</td><td>Name</td></tr><tr><td>1</td><td>AVDD</td><td>P</td><td>Analog supply pin.</td></tr><tr><td>2</td><td>AGND</td><td>P</td><td>Analog ground pin.</td></tr><tr><td>3</td><td>OS0</td><td>DI</td><td>Oversampling control pin.</td></tr><tr><td>4</td><td>OS1</td><td>DI</td><td>Oversampling control pin.</td></tr><tr><td>5</td><td>OS2</td><td>DI</td><td>Oversampling control pin.</td></tr><tr><td>6</td><td> $\overline{PAR/SER/BYTE SEL}$ </td><td>DI</td><td>Control pin to select the serial, parallel, or parallel byte interface mode.</td></tr><tr><td>7</td><td> $\overline{STBY}$ </td><td>DI</td><td>Control pin to select the standby or shutdown mode, active low.</td></tr><tr><td>8</td><td>RANGE</td><td>DI</td><td>Multi-function logic input pin:When STBY is low, this pin selects between the standby and shutdown modes.When STBY is high, this pin selects an input range of ±10 V or ±5 V.</td></tr><tr><td>9</td><td>CONVSTA</td><td>DI</td><td>Active high logic input to control the start of the conversion for the first half count of the input channels of the device.</td></tr><tr><td>10</td><td>CONVSTB</td><td>DI</td><td>Active high logic input to control the start of the conversion for the second half count of the input channels of the device.</td></tr><tr><td>11</td><td>RESET</td><td>DI</td><td>Active high logic input to reset the digital logic of the device.</td></tr><tr><td>12</td><td> $\overline{RD/SCLK}$ </td><td>DI</td><td>Multi-function logic input pin:This pin is active-low ready input pin in the parallel and parallel byte interface.This pin is the clock input pin in the serial interface mode.</td></tr><tr><td>13</td><td> $\overline{CS}$ </td><td>DI</td><td>Active low logic input chip-select signal.</td></tr><tr><td>14</td><td>BUSY</td><td>DO</td><td>Active high digital output indicating ongoing conversion.</td></tr><tr><td>15</td><td>FRSTDATA</td><td>DO</td><td>Active high digital output indicating data read back from channel 1 of the device.</td></tr><tr><td>16</td><td>DB0</td><td>DO</td><td>Data output DB0 (LSB) in the parallel interface mode.</td></tr></table>
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
<table><tr><td colspan="2">Pin</td><td rowspan="2">I/O</td><td rowspan="2">Description</td></tr><tr><td>No.</td><td>Name</td></tr><tr><td>17</td><td>DB1</td><td>DO</td><td>Data output DB1 in the parallel interface mode.</td></tr><tr><td>18</td><td>DB2</td><td>DO</td><td>Data output DB2 in the parallel interface mode.</td></tr><tr><td>19</td><td>DB3</td><td>DO</td><td>Data output DB3 in the parallel interface mode.</td></tr><tr><td>20</td><td>DB4</td><td>DO</td><td>Data output DB4 in the parallel interface mode.</td></tr><tr><td>21</td><td>DB5</td><td>DO</td><td>Data output DB5 in the parallel interface mode.</td></tr><tr><td>22</td><td>DB6</td><td>DO</td><td>Data output DB6 in the parallel interface mode.</td></tr><tr><td>23</td><td>DVDD</td><td>P</td><td>Digital supply pin; decouple with AGND on pin 26.</td></tr><tr><td>24</td><td>DB7/ DOUTA</td><td>DO</td><td>Multi-function logic output pin:This pin is data output DB7 in the parallel and parallel byte interface mode.This pin is a data output pin in serial interface mode.</td></tr><tr><td>25</td><td>DB8/ DOUTB</td><td>DO</td><td>Multi-function logic output pin:This pin is data output DB8 in the parallel and parallel byte interface mode.This pin is a data output pin in the serial interface mode.</td></tr><tr><td>26</td><td>AGND</td><td>P</td><td>Analog ground pin.</td></tr><tr><td>27</td><td>DB9</td><td>DO</td><td>Data output DB9 in the parallel interface mode.</td></tr><tr><td>28</td><td>DB10</td><td>DO</td><td>Data output DB10 in the parallel interface mode.</td></tr><tr><td>29</td><td>DB11</td><td>DO</td><td>Data output DB11 in the parallel interface mode.</td></tr><tr><td>30</td><td>DB12</td><td>DO</td><td>Data output DB12 in the parallel interface mode.</td></tr><tr><td>31</td><td>DB13</td><td>DO</td><td>Data output DB13 in the parallel interface mode.</td></tr><tr><td>32</td><td>DB14/ HBEN</td><td>DO</td><td>Multi-function logic input or output pin:This pin is data output DB14 in the parallel interface mode.This pin is a control input pin for byte selection (high or low) in the parallel byte interface mode.</td></tr><tr><td>33</td><td>DB15/ BYTE SEL</td><td>DO</td><td>Multi-function logic input or output pin:This pin is data output DB15 (MSB) in parallel interface mode.This pin is an active high-control input pin to enable the parallel byte interface mode.</td></tr><tr><td>34</td><td>REFSEL</td><td>DI</td><td>Active high logic input to enable the internal reference.</td></tr><tr><td>35</td><td>AGND</td><td>P</td><td>Analog ground pin.</td></tr><tr><td>36</td><td>REGCAP1</td><td>AO</td><td>Output pin 1 for the internal voltage regulator; decouple separately to AGND using a 1-μF capacitor. Typical 4 V.</td></tr><tr><td>37</td><td>AVDD</td><td>P</td><td>Analog supply pin.</td></tr><tr><td>38</td><td>AVDD</td><td>P</td><td>Analog supply pin.</td></tr><tr><td>39</td><td>REGCAP2</td><td>AO</td><td>Output pin 2 for the internal voltage regulator; decouple separately to AGND using a 1-μF capacitor. Typical 4 V.</td></tr><tr><td>40</td><td>AGND</td><td>P</td><td>Analog ground pin.</td></tr><tr><td>41</td><td>AGND</td><td>P</td><td>Analog ground pin.</td></tr><tr><td>42</td><td>REFIN/ REFOUT</td><td>AIO</td><td>This pin acts as an internal 2.5 V reference output when REFSEL is high.This pin functions as an input pin for the external reference when REFSEL is low; decouple with REFGND on pin 43 using a 10-μF capacitor.</td></tr></table>
|
||||
|
||||
16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
<table><tr><td colspan="2">Pin</td><td rowspan="2">I/O</td><td rowspan="2">Description</td></tr><tr><td>No.</td><td>Name</td></tr><tr><td>43</td><td>REFGND</td><td>P</td><td>Reference GND pin. This pin must be shorted to the analog GND plane and decoupled with REFIN/REFOUT on pin 42 using a 10-μF capacitor.</td></tr><tr><td>44</td><td>REFCAPA</td><td>AO</td><td>Reference amplifier output pins. This pin must be shorted to REFCAPB and decoupled to AGND using a low ESR, 10-μF ceramic capacitor. Typical 4 V.</td></tr><tr><td>45</td><td>REFCAPB</td><td>AO</td><td>Reference amplifier output pins. This pin must be shorted to REFCAPA and decoupled to AGND using a low ESR, 10-μF ceramic capacitor. Typical 4 V.</td></tr><tr><td>46</td><td>REFGND</td><td>P</td><td>Reference GND pin. This pin must be shorted to the analog GND plane and decoupled with REFIN/REFOUT on pin 42 using a 10-μF capacitor.</td></tr><tr><td>47</td><td>AGND</td><td>P</td><td>Analog ground pin.</td></tr><tr><td>48</td><td>AVDD</td><td>P</td><td>Analog supply pin.</td></tr><tr><td>49</td><td>AIN_1P</td><td>AIO</td><td>Analog input channel 1: positive input.</td></tr><tr><td>50</td><td>AIN_1GND</td><td>AIO</td><td>Analog input channel 1: negative input.</td></tr><tr><td>51</td><td>AIN_2P</td><td>AIO</td><td>Analog input channel 2: positive input.</td></tr><tr><td>52</td><td>AIN_2GND</td><td>AIO</td><td>Analog input channel 2: negative input.</td></tr><tr><td>53</td><td>AIN_3P</td><td>AIO</td><td>Analog input channel 3: positive input.</td></tr><tr><td>54</td><td>AIN_3GND</td><td>AIO</td><td>Analog input channel 3: negative input.</td></tr><tr><td>55</td><td>AIN_4P</td><td>AIO</td><td>Analog input channel 4: positive input.</td></tr><tr><td>56</td><td>AIN_4GND</td><td>AIO</td><td>Analog input channel 4: negative input.</td></tr><tr><td>57</td><td>AIN_5P</td><td>AIO</td><td>Analog input channel 5: positive input.</td></tr><tr><td>58</td><td>AIN_5GND</td><td>AIO</td><td>Analog input channel 5: negative input.</td></tr><tr><td>59</td><td>AIN_6P</td><td>AIO</td><td>Analog input channel 6: positive input.</td></tr><tr><td>60</td><td>AIN_6GND</td><td>AIO</td><td>Analog input channel 6: negative input.</td></tr><tr><td>61</td><td>AIN_7P</td><td>AIO</td><td>Analog input channel 7: positive input.</td></tr><tr><td>62</td><td>AIN_7GND</td><td>AIO</td><td>Analog input channel 7: negative input.</td></tr><tr><td>63</td><td>AIN_8P</td><td>AIO</td><td>Analog input channel 8: positive input.</td></tr><tr><td>64</td><td>AIN_8GND</td><td>AIO</td><td>Analog input channel 8: negative input.</td></tr></table>
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
## Specifications
|
||||
|
||||
## Absolute Maximum Ratings (1)
|
||||
|
||||
All test conditions: $T_{A} = 25^{\circ}C$ , unless otherwise noted.
|
||||
|
||||
<table><tr><td colspan="2">Parameter</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td></td><td>AVDD to AGND</td><td>-0.3</td><td>7</td><td>V</td></tr><tr><td></td><td>DVDD to DGND</td><td>-0.3</td><td>7</td><td>V</td></tr><tr><td></td><td>AGND to DGND</td><td>-0.3</td><td>0.3</td><td>V</td></tr><tr><td></td><td>Analog Input Voltage to AGND</td><td>-15</td><td>15</td><td>V</td></tr><tr><td></td><td>Digital Input to DGND</td><td>-0.3</td><td>DVDD + 0.3</td><td>V</td></tr><tr><td></td><td>REFIN to AGND</td><td>-0.3</td><td>AVDD + 0.3</td><td>V</td></tr><tr><td></td><td>Input Current to Any Pin Except Supplies</td><td>-10</td><td>10</td><td>mA</td></tr><tr><td> $T_J$ </td><td>Maximum Junction Temperature</td><td>-40</td><td>150</td><td>°C</td></tr><tr><td> $T_A$ </td><td>Operating Temperature Range</td><td>-40</td><td>125</td><td>°C</td></tr><tr><td> $T_{STG}$ </td><td>Storage Temperature Range</td><td>-65</td><td>150</td><td>°C</td></tr><tr><td> $T_L$ </td><td>Lead Temperature (Soldering, 10 sec)</td><td></td><td>260</td><td>°C</td></tr></table>
|
||||
|
||||
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.
|
||||
(2) This data was taken with the JEDEC low effective thermal conductivity test board.
|
||||
(3) This data was taken with the JEDEC standard multilayer test boards.
|
||||
|
||||
ESD, Electrostatic Discharge Protection
|
||||
|
||||
<table><tr><td>Symbol</td><td>Parameter</td><td>Condition</td><td>Minimum Level</td><td>Unit</td></tr><tr><td>HBM</td><td>Human Body Model ESD for all pins except analog input pins</td><td>ANSI/ESDA/JEDEC JS-001 (1)</td><td>±5000</td><td>V</td></tr><tr><td>HBM</td><td>Human Body Model ESD for analog input pins only</td><td>ANSI/ESDA/JEDEC JS-001 (1)</td><td>±7000</td><td>V</td></tr><tr><td>CDM</td><td>Charged Device Model ESD</td><td>ANSI/ESDA/JEDEC JS-002 (2)</td><td>±1500</td><td>V</td></tr></table>
|
||||
|
||||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
|
||||
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
|
||||
|
||||
Recommended Operating Conditions
|
||||
|
||||
<table><tr><td colspan="2">Parameter</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td>AVDD</td><td>Analog Supply Voltage</td><td>4.75</td><td>5</td><td>5.25</td><td>V</td></tr><tr><td>DVDD</td><td>Digital Supply Voltage</td><td>1.71</td><td>3.3</td><td>AVDD</td><td>V</td></tr></table>
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
Thermal Information
|
||||
|
||||
<table><tr><td>Package Type</td><td> $\theta_{JA}$ </td><td> $\theta_{JC}$ </td><td>Unit</td></tr><tr><td>LQFP10×10-64</td><td>46</td><td>7.8</td><td>°C/W</td></tr></table>
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
## Electrical Characteristics
|
||||
|
||||
All test conditions: $V_{REF} = 2.5$ V external/internal, AVDD = 4.75 V to 5.25 V, $V_{DRIVE} = 1.71$ V to AVDD, $f_{SAMPLE} = 350$ kSPS, $T_{A} = -40^{\circ}C$ to $125^{\circ}C$ , Low Bandwidth Mode, unless otherwise noted.
|
||||
|
||||
<table><tr><td>Symbol</td><td>Parameter</td><td colspan="2">Test condition</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td colspan="8">Dynamic Performance</td></tr><tr><td rowspan="4">SNR</td><td rowspan="4">Signal-to-Noise Ratio</td><td rowspan="2">fin = 1 kHz sine wave, unless otherwise noted</td><td>±10 V No oversampling</td><td>86</td><td>89.7</td><td></td><td>dB</td></tr><tr><td>±5 V No oversampling</td><td>85.5</td><td>89.5</td><td></td><td>dB</td></tr><tr><td>fin = 130 Hz</td><td>Oversampling by 16, ±10-V Range</td><td>91</td><td>95.2</td><td></td><td>dB</td></tr><tr><td>fin = 130 Hz</td><td>Oversampling by 16, ±5-V Range</td><td>91</td><td>94.7</td><td></td><td>dB</td></tr><tr><td rowspan="2">SINAD</td><td rowspan="2">Signal to Noise + Distortion Ratio</td><td rowspan="2">fin = 1 kHz sine wave, unless otherwise noted</td><td>±10 V No oversampling</td><td></td><td>89.5</td><td></td><td>dB</td></tr><tr><td>±5 V No oversampling</td><td></td><td>89.4</td><td></td><td>dB</td></tr><tr><td>THD</td><td>Total Harmonic Distortion</td><td>All input range, fin =1 kHz</td><td></td><td></td><td>-106</td><td></td><td>dB</td></tr><tr><td>SFDR</td><td>Spurious Free Dynamic Range</td><td>fin = 1 kHz</td><td></td><td></td><td>-106</td><td></td><td>dB</td></tr><tr><td colspan="8">Analog Input Filter</td></tr><tr><td rowspan="4">BW (-3 dB)</td><td rowspan="4">Small Signal Bandwidth</td><td>Low Bandwidth Mode</td><td>-3 dB, ±10 V</td><td></td><td>20.0</td><td></td><td>kHz</td></tr><tr><td>Low Bandwidth Mode</td><td>-3 dB, ±5 V</td><td></td><td>12.7</td><td></td><td>kHz</td></tr><tr><td>High Bandwidth Mode</td><td>-3 dB, ±10 V</td><td></td><td>26.5</td><td></td><td>kHz</td></tr><tr><td>High Bandwidth Mode</td><td>-3 dB, ±5 V</td><td></td><td>16.4</td><td></td><td>kHz</td></tr><tr><td rowspan="4">BW (-0.1 dB)</td><td rowspan="4">Small Signal Bandwidth</td><td>Low Bandwidth Mode</td><td>-0.1 dB, ±10 V</td><td></td><td>3.3</td><td></td><td>kHz</td></tr><tr><td>Low Bandwidth Mode</td><td>-0.1 dB, ±5 V</td><td></td><td>2.2</td><td></td><td>kHz</td></tr><tr><td>High Bandwidth Mode</td><td>-0.1 dB, ±10 V</td><td></td><td>4.3</td><td></td><td>kHz</td></tr><tr><td>High Bandwidth Mode</td><td>-0.1 dB, ±5 V</td><td></td><td>2.6</td><td></td><td>kHz</td></tr><tr><td rowspan="4">Tgroup_delay</td><td rowspan="4">Group Delay</td><td>Low Bandwidth Mode</td><td>±10 V</td><td></td><td>10</td><td></td><td>μs</td></tr><tr><td>Low Bandwidth Mode</td><td>±5 V</td><td></td><td>16</td><td></td><td>μs</td></tr><tr><td>High Bandwidth Mode</td><td>±10 V</td><td></td><td>8</td><td></td><td>μs</td></tr><tr><td>High Bandwidth Mode</td><td>±5 V</td><td></td><td>12</td><td></td><td>μs</td></tr><tr><td colspan="8">DC Accuracy</td></tr><tr><td></td><td>Resolution</td><td></td><td>NO missing code</td><td></td><td>16</td><td></td><td>bit</td></tr><tr><td>DNL</td><td>Differential Nonlinearity</td><td colspan="2"> $f_{SAMPLE}$ = 200 kSPS, -40~85°C</td><td>-0.99</td><td>±0.5</td><td>1.5</td><td>LSB</td></tr><tr><td rowspan="2">INL</td><td rowspan="2">Integral Nonlinearity</td><td colspan="2"> $f_{SAMPLE}$ = 200 kSPS, -40~85°C</td><td></td><td>±0.7</td><td>±2</td><td>LSB</td></tr><tr><td colspan="2"> $f_{SAMPLE}$ = 350 kSPS, -40~85°C</td><td></td><td>±1</td><td>±2.5</td><td>LSB</td></tr></table>
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
<table><tr><td rowspan="2"></td><td rowspan="2">Positive and Negative Full-Scale Error</td><td>Ext reference</td><td></td><td></td><td>±4</td><td>±50</td><td>LSB</td></tr><tr><td>Int reference</td><td></td><td></td><td>±15</td><td></td><td>LSB</td></tr><tr><td rowspan="2"></td><td rowspan="2">Positive Full-Scale Error Drift</td><td>Ext reference</td><td></td><td></td><td>±2</td><td></td><td>ppm/C</td></tr><tr><td>Int reference</td><td></td><td></td><td>±10</td><td></td><td>ppm/C</td></tr><tr><td rowspan="2"></td><td rowspan="2">Negative Full-Scale Error Drift</td><td>Ext reference</td><td></td><td></td><td>±2</td><td></td><td>ppm/C</td></tr><tr><td>Int reference</td><td></td><td></td><td>±10</td><td></td><td>ppm/C</td></tr><tr><td rowspan="2"></td><td rowspan="2">Bipolar Zero Code Error</td><td></td><td>±10 V</td><td></td><td rowspan="2">±1</td><td rowspan="2">±15</td><td rowspan="2">LSB</td></tr><tr><td></td><td>±5 V</td><td></td></tr><tr><td rowspan="2"></td><td rowspan="2">Bipolar Zero Code Error Drift</td><td></td><td>±10 V</td><td></td><td>±10</td><td></td><td>μV/C</td></tr><tr><td></td><td>±5 V</td><td></td><td>±5</td><td></td><td>μV/C</td></tr><tr><td></td><td>Bipolar Full-Scale Error Matching</td><td></td><td></td><td></td><td>±6</td><td>±22</td><td>LSB</td></tr><tr><td></td><td>Bipolar Zero Code Error matching</td><td></td><td>±5 V±10 V</td><td></td><td>±3</td><td>±20</td><td>LSB</td></tr><tr><td colspan="8">Analog Input</td></tr><tr><td rowspan="2"></td><td rowspan="2">Input Range</td><td rowspan="2">Vx - VxGND</td><td>RANGE = 1, ±10-V range</td><td>-10</td><td></td><td>10</td><td rowspan="2">V</td></tr><tr><td>RANGE = 0, ±5-V range</td><td>-5</td><td></td><td>5</td></tr><tr><td rowspan="2"></td><td rowspan="2">Analog Input Current</td><td></td><td>10-V range</td><td></td><td rowspan="2">(VIN - 2) / RIN</td><td></td><td>μA</td></tr><tr><td></td><td>5-V range</td><td></td><td></td><td>μA</td></tr><tr><td>CIN</td><td>Input Capacitance</td><td></td><td></td><td></td><td>5</td><td></td><td>pF</td></tr><tr><td>RIN</td><td>Input Resistance</td><td></td><td></td><td></td><td>1</td><td></td><td>Mohm</td></tr><tr><td></td><td>Input Impedance Drift</td><td></td><td></td><td></td><td>±20</td><td></td><td>ppm/C</td></tr><tr><td colspan="8">Reference Input/Output</td></tr><tr><td></td><td>Reference Input Voltage</td><td colspan="2">REF SELECT = 0, select Ext Ref, force voltage on REFIN/REFOUT</td><td>2.475</td><td>2.5</td><td>2.525</td><td>V</td></tr><tr><td></td><td>Reference Output Voltage</td><td colspan="2">REF_SELECT = 1, REFIN/REFOUT output voltage TA = 25°C</td><td>2.495</td><td>2.5</td><td>2.505</td><td>V</td></tr><tr><td></td><td>Reference Voltage TC</td><td colspan="2"></td><td></td><td>±10</td><td></td><td>ppm/C</td></tr><tr><td></td><td>V (REFCAPA/B)</td><td colspan="2">Voltage on REFCAPA and REFCAPB, also used for ADC</td><td></td><td>4</td><td></td><td>V</td></tr><tr><td colspan="8">Logic Input</td></tr><tr><td>VIH</td><td>Input High Voltage</td><td>Input logic high voltage</td><td></td><td>0.7 × VDRIVE</td><td></td><td></td><td>V</td></tr><tr><td>VIL</td><td>Input Low Voltage</td><td>Input logic low voltage</td><td></td><td></td><td></td><td>0.3 × VDRIVE</td><td>V</td></tr><tr><td>CI</td><td>Input Capacitance</td><td>Input capacitance</td><td></td><td></td><td>5</td><td></td><td>pF</td></tr><tr><td>I1</td><td>Input Current</td><td>Input current</td><td></td><td></td><td></td><td>±2</td><td>μA</td></tr></table>
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
<table><tr><td colspan="8">Logic Output</td></tr><tr><td> $V_{OH}$ </td><td>Output High Voltage</td><td></td><td>Current source = 100 μA</td><td> $V_{DRIVE}$ - 0.2</td><td></td><td></td><td>V</td></tr><tr><td> $V_{OL}$ </td><td>Output Low Voltage</td><td></td><td>Current sink = 100 μA</td><td></td><td></td><td>0.2</td><td>V</td></tr><tr><td></td><td>Float State Leakage Current</td><td></td><td></td><td></td><td>±1</td><td>±20</td><td>μA</td></tr><tr><td> $C_O$ </td><td>Output Capacitance</td><td></td><td></td><td></td><td>5</td><td></td><td>pF</td></tr><tr><td colspan="8">Conversion Rate</td></tr><tr><td></td><td>Conversion Time</td><td></td><td></td><td></td><td>1.65</td><td></td><td>μs</td></tr><tr><td></td><td>Acquisition Time</td><td></td><td></td><td></td><td>1.2</td><td></td><td>μs</td></tr><tr><td></td><td>Throughput Rate</td><td>Per channel</td><td></td><td></td><td></td><td>350</td><td>kSPS</td></tr><tr><td colspan="8">Timing specifications</td></tr><tr><td rowspan="2">SCLK</td><td rowspan="2">Frequency of Serial Interface</td><td></td><td> $V_{DRIVE}$ > 2.7 V</td><td></td><td></td><td>23.5</td><td>MHz</td></tr><tr><td></td><td> $V_{DRIVE}$ > 1.7 V</td><td></td><td></td><td>15</td><td>MHz</td></tr><tr><td></td><td>AVCC Normal</td><td></td><td></td><td></td><td>41</td><td>51</td><td>mA</td></tr><tr><td></td><td>AVCC Standby</td><td></td><td></td><td></td><td>5</td><td>9</td><td>mA</td></tr><tr><td></td><td>AVCC Shutdown</td><td></td><td></td><td></td><td>11</td><td>25</td><td>μA</td></tr></table>
|
||||
|
||||
(1) 100% tested at $T_{A} = 25^{\circ}C$ .
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
## Timing Specifications
|
||||
|
||||
All test conditions: $AV_{CC} = 5 V$ , $V_{DRIVE} = 1.7 V$ to 5.5 V, $V_{REF} = 2.5 V$ , $T_{A} = T_{MIN}$ to $T_{MAX}$ , unless otherwise noted.
|
||||
|
||||
<table><tr><td rowspan="2">Parameter</td><td colspan="3">Limit at TMIN, TMAX (0.1 × VDRIVE and 0.9 × VDRIVE Logic Input Levels)</td><td rowspan="2">Unit</td><td rowspan="2">Description</td></tr><tr><td>Min</td><td>Typ</td><td>Max</td></tr><tr><td colspan="6">Parallel/Serial/Byte Mode</td></tr><tr><td rowspan="4">tCYCLE</td><td></td><td></td><td></td><td></td><td>1/throughput rate</td></tr><tr><td></td><td>2.85</td><td></td><td>μs</td><td>Parallel mode, reading during or after conversion; or serial mode: VDRIVE = 2.7 V to 5.5 V, reading during conversion using DOUTA and DOUTB lines</td></tr><tr><td></td><td>4.5</td><td></td><td>μs</td><td>Serial mode: VDRIVE = 2.7 V, reading after a conversion using DOUTA and DOUTB lines</td></tr><tr><td></td><td>6</td><td></td><td>μs</td><td>Serial mode: VDRIVE = 1.7 V, reading after a conversion using DOUTA and DOUTB lines</td></tr><tr><td rowspan="8">tCONV</td><td></td><td></td><td></td><td></td><td>Conversion time</td></tr><tr><td></td><td>1.74</td><td></td><td>μs</td><td>Oversampling off</td></tr><tr><td></td><td>4.4</td><td></td><td>μs</td><td>Oversampling by 2</td></tr><tr><td></td><td>9.6</td><td></td><td>μs</td><td>Oversampling by 4</td></tr><tr><td></td><td>20</td><td></td><td>μs</td><td>Oversampling by 8</td></tr><tr><td></td><td>41</td><td></td><td>μs</td><td>Oversampling by 16</td></tr><tr><td></td><td>83</td><td></td><td>μs</td><td>Oversampling by 32</td></tr><tr><td></td><td>167</td><td></td><td>μs</td><td>Oversampling by 64</td></tr><tr><td>tWAKE-UP STANDBY</td><td></td><td>100</td><td></td><td>μs</td><td>STBY rising edge to CONVST × rising edge; power-up time from standby mode</td></tr><tr><td>tWAKE-UP SHUTDOWN Internal Reference</td><td></td><td>180</td><td></td><td>ms</td><td>STBY rising edge to CONVST × rising edge; power-up time from shutdown mode</td></tr><tr><td>tWAKE-UP SHUTDOWN External Reference</td><td></td><td>13</td><td></td><td>ms</td><td>STBY rising edge to CONVST × rising edge; power-up time from shutdown mode</td></tr><tr><td>tRESET</td><td></td><td>100</td><td></td><td>ns</td><td>RESET high pulse width</td></tr><tr><td>t1</td><td></td><td>40</td><td></td><td>ns</td><td>CONVST × high to BUSY high</td></tr><tr><td>t2</td><td>25</td><td></td><td></td><td>ns</td><td>Minimum CONVST × low pulse</td></tr><tr><td>t3</td><td>25</td><td></td><td></td><td>ns</td><td>Minimum CONVST × high pulse</td></tr><tr><td>t4</td><td>45</td><td></td><td></td><td>ns</td><td>BUSY falling edge to CS falling edge setup time</td></tr><tr><td>t5</td><td></td><td>0.5</td><td></td><td>ms</td><td>Maximum delay allowed between CONVST A, CONVST B rising edges</td></tr></table>
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
<table><tr><td>t6</td><td>110</td><td></td><td></td><td>ns</td><td>Minimum time between last $\overline{CS}$ rising edge and BUSY falling edge</td></tr><tr><td>t7</td><td>200</td><td></td><td></td><td>ns</td><td>Minimum delay between RESET low to CONVST × high</td></tr><tr><td colspan="6">Parallel/Byte Read Operation</td></tr><tr><td>t8</td><td>0</td><td></td><td></td><td>ns</td><td> $\overline{CS}$ to $\overline{RD}$ setup time</td></tr><tr><td>t9</td><td>0</td><td></td><td></td><td>ns</td><td> $\overline{CS}$ to $\overline{RD}$ hold time</td></tr><tr><td rowspan="3">t10</td><td></td><td></td><td></td><td></td><td> $\overline{RD}$ low pulse width</td></tr><tr><td>22</td><td></td><td></td><td>ns</td><td> $V_{DRIVE}$ above 2.7 V</td></tr><tr><td>32</td><td></td><td></td><td>ns</td><td> $V_{DRIVE}$ above 1.7 V</td></tr><tr><td>t11</td><td>10</td><td></td><td></td><td>ns</td><td> $\overline{RD}$ high pulse width</td></tr><tr><td>t12</td><td>10</td><td></td><td></td><td>ns</td><td> $\overline{CS}$ high pulse width; $\overline{CS}$ and $\overline{RD}$ linked</td></tr><tr><td rowspan="3">t13</td><td></td><td></td><td></td><td></td><td>Delay from $\overline{CS}$ until DB [15:0] three-state disabled</td></tr><tr><td></td><td></td><td>21</td><td>ns</td><td> $V_{DRIVE}$ above 2.7 V</td></tr><tr><td></td><td></td><td>30</td><td>ns</td><td> $V_{DRIVE}$ above 1.7 V</td></tr><tr><td rowspan="3">t14</td><td></td><td></td><td></td><td></td><td>Data access time after $\overline{RD}$ falling edge</td></tr><tr><td></td><td></td><td>21</td><td>ns</td><td> $V_{DRIVE}$ above 2.7 V</td></tr><tr><td></td><td></td><td>30</td><td>ns</td><td> $V_{DRIVE}$ above 1.7 V</td></tr><tr><td>t15</td><td>6</td><td></td><td></td><td>ns</td><td>Data hold time after $\overline{RD}$ falling edge</td></tr><tr><td>t16</td><td>6</td><td></td><td></td><td>ns</td><td> $\overline{CS}$ to DB [15:0] hold time</td></tr><tr><td>t17</td><td></td><td></td><td>20</td><td>ns</td><td>Delay from $\overline{CS}$ rising edge to DB [15:0] three-state enabled</td></tr><tr><td colspan="6">Serial Read Operation</td></tr><tr><td rowspan="3">fSCLK</td><td></td><td></td><td></td><td></td><td>Frequency of serial read clock</td></tr><tr><td></td><td></td><td>23.5</td><td>MHz</td><td> $V_{DRIVE}$ above 2.7 V</td></tr><tr><td></td><td></td><td>15</td><td>MHz</td><td> $V_{DRIVE}$ above 1.7 V</td></tr><tr><td rowspan="3">t18</td><td></td><td></td><td></td><td></td><td>Delay from CS until $D_{OUTA}/D_{OUTB}$ three-state disabled/delay from $\overline{CS}$ until MSB valid</td></tr><tr><td></td><td></td><td>10</td><td>ns</td><td> $V_{DRIVE}$ above 2.7 V</td></tr><tr><td></td><td></td><td>15</td><td>ns</td><td> $V_{DRIVE}$ above 1.7 V</td></tr><tr><td rowspan="3">t19</td><td></td><td></td><td></td><td></td><td>Data access time after SCLK rising edge</td></tr><tr><td></td><td></td><td>21</td><td>ns</td><td> $V_{DRIVE}$ above 2.7 V</td></tr><tr><td></td><td></td><td>30</td><td>ns</td><td> $V_{DRIVE}$ above 1.7 V</td></tr><tr><td>t20</td><td>0.4tSCLK</td><td></td><td></td><td>ns</td><td>SCLK low pulse width</td></tr><tr><td>t21</td><td>0.4tSCLK</td><td></td><td></td><td>ns</td><td>SCLK high pulse width</td></tr><tr><td>t22</td><td>6</td><td></td><td></td><td>ns</td><td>SCLK rising edge to $D_{OUTA}/D_{OUTB}$ valid hold time</td></tr><tr><td>t23</td><td></td><td></td><td>15</td><td>ns</td><td> $\overline{CS}$ rising edge to $D_{OUTA}/D_{OUTB}$ three-state enabled</td></tr><tr><td colspan="6">FRATDATA Operation</td></tr><tr><td>t24</td><td></td><td></td><td></td><td></td><td>Delay from $\overline{CS}$ falling edge until FRSTDATA three-state disabled</td></tr></table>
|
||||
|
||||
16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
<table><tr><td rowspan="2">t24</td><td></td><td></td><td>11</td><td>ns</td><td>VDRIVE above 2.7 V</td></tr><tr><td></td><td></td><td>20</td><td>ns</td><td>VDRIVE above 1.7 V</td></tr><tr><td rowspan="3">t25</td><td></td><td></td><td></td><td></td><td>Delay from CS falling edge until FRSTDATA high, serial mode</td></tr><tr><td></td><td></td><td>11</td><td>ns</td><td>VDRIVE above 2.7 V</td></tr><tr><td></td><td></td><td>20</td><td>ns</td><td>VDRIVE above 1.7 V</td></tr><tr><td rowspan="3">t26</td><td></td><td></td><td></td><td></td><td>Delay from RD falling edge to FRSTDATA high</td></tr><tr><td></td><td></td><td>22</td><td>ns</td><td>VDRIVE above 2.7 V</td></tr><tr><td></td><td></td><td>32</td><td>ns</td><td>VDRIVE above 1.7 V</td></tr><tr><td rowspan="3">t27</td><td></td><td></td><td></td><td></td><td>Delay from RD falling edge to FRSTDATA low</td></tr><tr><td></td><td></td><td>22</td><td>ns</td><td>VDRIVE above 2.7 V</td></tr><tr><td></td><td></td><td>32</td><td>ns</td><td>VDRIVE above 1.7 V</td></tr><tr><td rowspan="3">t28</td><td></td><td></td><td></td><td></td><td>Delay from the 16th SCLK falling edge to FRSTDATA low</td></tr><tr><td></td><td></td><td>22</td><td>ns</td><td>VDRIVE above 2.7 V</td></tr><tr><td></td><td></td><td>32</td><td>ns</td><td>VDRIVE above 1.7 V</td></tr><tr><td>t29</td><td></td><td></td><td>20</td><td>ns</td><td>Delay from CS rising edge until FRSTDATA three-state enabled</td></tr></table>
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
Timing Diagrams
|
||||
|
||||
|
||||
<details>
|
||||
<summary>flowchart</summary>
|
||||
|
||||
```mermaid
|
||||
graph LR
|
||||
CONVST_A["CONVST A, CONVST B"] -->|t5| CONVST_B["CONVST A, CONVST B"]
|
||||
CONVST_B -->|tCYCLE| CONVST_B
|
||||
CONVST_B -->|t2| CONVST_B
|
||||
CONVST_B -->|t3| BUSY["BUSY"]
|
||||
BUSY -->|t1| CS["CS"]
|
||||
CS -->|t4| CS
|
||||
CONVST_B -->|tCONV| CS
|
||||
CONVST_B -->|tRESET| RESET["RESET"]
|
||||
```
|
||||
</details>
|
||||
|
||||
Figure 1. CONVST Timing-Reading After a Conversion
|
||||
|
||||
|
||||
|
||||
<details>
|
||||
<summary>flowchart</summary>
|
||||
|
||||
This diagram illustrates the timing relationships and signal flow between a system, including convolutional and busy states, reset, and synchronization intervals.
|
||||
</details>
|
||||
|
||||
Figure 2. CONVST Timing-Reading During a Conversion
|
||||
|
||||
|
||||
|
||||
<details>
|
||||
<summary>text_image</summary>
|
||||
|
||||
CS
|
||||
RD
|
||||
DATA:
|
||||
DB[15:0]
|
||||
FRSTDATA
|
||||
t8
|
||||
t10
|
||||
t11
|
||||
t13
|
||||
t14
|
||||
t15
|
||||
t16
|
||||
t17
|
||||
t24
|
||||
t26
|
||||
t27
|
||||
t29
|
||||
t8
|
||||
t10
|
||||
t11
|
||||
t14
|
||||
t15
|
||||
t16
|
||||
t17
|
||||
V1
|
||||
V2
|
||||
V3
|
||||
V4
|
||||
V7
|
||||
V8
|
||||
</details>
|
||||
|
||||
Figure 3. Parallel Mode, Separate CS and RD Pulses
|
||||
|
||||
|
||||
<details>
|
||||
<summary>text_image</summary>
|
||||
|
||||
CS AND RD
|
||||
DATA:
|
||||
DB[15:0]
|
||||
V1 V2 V3 V4 V5 V6 V7 V8
|
||||
t12
|
||||
t13
|
||||
t16
|
||||
t17
|
||||
FRSTDATA
|
||||
</details>
|
||||
|
||||
Figure 4. CS and RD, Linked Parallel Mode
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
|
||||
|
||||
<details>
|
||||
<summary>text_image</summary>
|
||||
|
||||
CS
|
||||
SCLK
|
||||
DOUTA,
|
||||
DOUTB
|
||||
FRSTDATA
|
||||
t18
|
||||
t19
|
||||
t21
|
||||
t20
|
||||
t22
|
||||
t23
|
||||
t25
|
||||
DB15
|
||||
DB14
|
||||
DB13
|
||||
DB1
|
||||
DB0
|
||||
t28
|
||||
t29
|
||||
</details>
|
||||
|
||||
Figure 5. Serial Read Operation (Channel 1)
|
||||
|
||||
|
||||
|
||||
<details>
|
||||
<summary>text_image</summary>
|
||||
|
||||
CS
|
||||
RD
|
||||
DATA:
|
||||
DB[7:0]
|
||||
FRSTDATA
|
||||
t8
|
||||
t10
|
||||
t11
|
||||
t9
|
||||
t13
|
||||
t14
|
||||
t15
|
||||
t16
|
||||
t17
|
||||
t24
|
||||
t26
|
||||
t27
|
||||
t29
|
||||
INVALID
|
||||
HIGH BYTE V1
|
||||
LOW BYTE V1
|
||||
HIGH BYTE V8
|
||||
LOW BYTE V8
|
||||
</details>
|
||||
|
||||
Figure 6. BYTE Mode Read Operation
|
||||
|
||||
# 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
## Detailed Description
|
||||
|
||||
## Overview
|
||||
|
||||
The TPAFE5160 is a 16-bit, 8-channel simultaneous sampling, successive approximation (SAR) ADC. Each channel has a complete analog front end, as well as an ADC operating at 350 kSPS per channel. The analog front end features the input clamp, a programmable gain amplifier (PGA) with a high input impedance of 1 MΩ, a low pass filter, and an ADC input driver.
|
||||
|
||||
The device features an internal precision reference with a buffer to drive the ADC. A digital interface supports serial, parallel, and parallel byte communication, which can be used with various host controllers.
|
||||
|
||||
The TPAFE5160 can accept ±10-V or ±5-V true bipolar inputs with a single 5-V supply. Also, the high input impedance allows direct connection to transformers or other sensors without external driver circuits.
|
||||
|
||||
## Feature Description
|
||||
|
||||
## Analog Inputs
|
||||
|
||||
The TPAFE5160 has 8 analog input channels, and positive inputs AIN\_nP (n = 1 to 8) are the single-ended analog inputs. The negative inputs AIN\_nGND should be tied to GND.
|
||||
|
||||
The input voltage range can be configured to bipolar ±10 V or ±5 V by the RANGE pin.
|
||||
|
||||
The device allows a ±0.3-V range on the AIN\_nGND.
|
||||
|
||||
## Analog Input Impedance
|
||||
|
||||
Each analog input channel in the device presents a constant resistive impedance of 1 MΩ.
|
||||
|
||||
Matching the external source impedance on the AIN\_nP input pin with an equivalent resistance on the AIN\_nGND pin is recommended to cancel any additional offset error contributed by the external resistance.
|
||||
|
||||
## Input Clamp Protection Circuit
|
||||
|
||||
The input clamp protection circuit allows the analog input to swing up to ±30 V (typical). The input clamp circuit turns on beyond the clamp voltage.
|
||||
|
||||
For input voltages above the clamp threshold, make sure that the input current never exceeds the absolute maximum rating to prevent any damage to the device.
|
||||
|
||||
Don't keep the device in a state such that the clamp circuit is activated for extended periods of time, because this fault condition can degrade the performance and reliability of the device.
|
||||
|
||||
## Programmable Gain Amplifier (PGA)
|
||||
|
||||
The device has a programmable gain amplifier (PGA) at each individual input channel. The PGA converts the single-ended input signal into a fully-differential signal to drive internal ADC. The PGA also adjusts the common-mode voltage feeding into the ADC to ensure maximum usage of the ADC input dynamic range. The PGA gain is adjusted by configuring the RANGE pin of the ADC accordingly.
|
||||
|
||||
## Low Pass Filter
|
||||
|
||||
Each channel of the TPAFE5160 features a second-order antialiasing low pass filter (LPF) at the output of the PGA, to remove the noise of the front-end amplifiers and gain resistors of the PGA.
|
||||
|
||||
## ADC Driver
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
There is an integrated ADC input driver before each ADC channel. This integrated ADC driver eliminates the need of any external amplifier, helping inputs of the ADC to settle to better than 16-bit accuracy before any sampled analog voltage gets converted. And thus, the signal chain design for the user is simplified.
|
||||
|
||||
## Digital Filter
|
||||
|
||||
The TPAFE5160 has an optional digital averaging filter that can be used in slower throughput applications requiring lower noise and higher dynamic range. The oversampling ratio of the digital filter is determined by the configuration of the OS[2:0] pins.
|
||||
|
||||
In oversampling mode, the samples are averaged to reduce the noise of the signal chain as well as to improve the SNR of the ADC. The final output is also decimated to provide data for each channel.
|
||||
|
||||
<table><tr><td>OS [2:0]</td><td>OS RATIO</td><td>MAX THROUGHPUT PER CHANNEL (kSPS)</td></tr><tr><td>000</td><td>NO OS</td><td>350</td></tr><tr><td>001</td><td>2</td><td>175</td></tr><tr><td>010</td><td>4</td><td>87.5</td></tr><tr><td>011</td><td>8</td><td>43.75</td></tr><tr><td>100</td><td>16</td><td>21.875</td></tr><tr><td>101</td><td>32</td><td>10.94</td></tr><tr><td>110</td><td>64</td><td>5.47</td></tr><tr><td>111</td><td>NA</td><td>350</td></tr></table>
|
||||
|
||||
## Reference
|
||||
|
||||
The TPAFE5160 can operate with either an internal voltage reference or an external voltage reference. The internal or external reference selection is determined by an external REFSEL pin,
|
||||
|
||||
The REFIN/REFOUT pin outputs the internal band-gap voltage (in the internal reference mode) or functions as the input pin to the external reference voltage (in the external reference mode). The on-chip amplifier is enabled in both modes to drive the actual reference input of the internal ADC core. The REFCAPA and REFCAPB pins must be shorted together externally and a ceramic capacitor of a minimum 10 μF should be connected between this node and REFGND to ensure that the internal reference buffer is operating as a closed loop.
|
||||
|
||||
## ADC Transfer Function
|
||||
|
||||
The TPAFE5160 outputs 16-bit data in binary twos complement format for both bipolar input ranges. The format for the output codes is the same across all analog channels.
|
||||
|
||||
<table><tr><td>Input Range (V)</td><td>Full-Scale Range (V)</td><td>LSB (μV)</td></tr><tr><td>±10</td><td>20</td><td>305.18</td></tr><tr><td>±5</td><td>10</td><td>152.59</td></tr></table>
|
||||
|
||||
## Device Functional Modes
|
||||
|
||||
Device Interface: Pin Description
|
||||
|
||||
REFSEL (Input)
|
||||
|
||||
The REFSEL pin selects between the internal and external reference modes of the device.
|
||||
|
||||
If the REFSEL pin is set to logic high, then the internal reference is enabled and selected.
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
If the REFSEL pin is set to logic low, then the internal reference circuit is disabled and powered down. In this mode, an external reference voltage must be provided to the REFIN/REFOUT pin.
|
||||
|
||||
The internal reference buffer is always enabled under both conditions.
|
||||
|
||||
The reference mode after power-up depends on the state of the REFSEL input pin.
|
||||
|
||||
## RANGE (Input)
|
||||
|
||||
The RANGE pin selects the input range for all analog input channels.
|
||||
|
||||
If this pin is set to logic high, the device is configured to operate in the ±10-V input range.
|
||||
|
||||
If this pin is set to logic low, the device is configured to operate in the ±5-V input range.
|
||||
|
||||
The RANGE pin is also used to put the device in standby or shutdown mode depending on the state of the STBY input pin, as explained in the Power Down Modes.
|
||||
|
||||
## STBY (Input)
|
||||
|
||||
The STBY pin puts the device into one of the two power-down modes: standby and power down.
|
||||
|
||||
If this pin is set to logic high, the device is in normal operation mode.
|
||||
|
||||
If this pin is set to logic low, the device is in the standby or power down mode, depending on the state of the RANGE pin.
|
||||
|
||||
In the shutdown mode, all internal circuitry is powered down,
|
||||
|
||||
In the standby mode, the internal reference remains powered up to enable a relatively quicker recovery to normal operation mode.
|
||||
|
||||
## PAR/SER/BYTE SEL (Input)
|
||||
|
||||
The PAR/SER/BYTE SEL pin selects between the parallel, serial, and parallel byte interface modes for reading data from the device.
|
||||
|
||||
If this pin is set to logic high, then the serial or parallel byte interface mode is selected depending on the state of the DB15/BYTE SEL pin. If the DB15/BYTE SEL pin is high, the parallel byte interface is selected, and if the DB15/BYTE SEL is low, then the serial mode is selected.
|
||||
|
||||
## CONVSTA, CONVSTB (Input)
|
||||
|
||||
CONVSTA, and CONVSTB (Input) are conversion control input pins.
|
||||
|
||||
CONVSTA can be used to simultaneously sample and initiate the conversion process for the first half count of the input channels (channels 1-4), and CONVSTB can be used to simultaneously sample and initiate the conversion process for the latter half count of the input channels (channels 5-8).
|
||||
|
||||
On the rising edge of the CONVSTA, CONVSTB signals, the internal track-and-hold circuits for each analog input channel are placed into the hold mode and the sampled input signal is converted.
|
||||
|
||||
The CONVSTA, and CONVSTB signals can be pulled low when the internal conversion is over, as indicated by the BUSY signal. At this point, the front-end circuit for all analog input channels acquires the respective input signals and the internal ADC is not converting.
|
||||
|
||||
The output data can be read from the device irrespective of the status of the CONVSTA and CONVSTB pins.
|
||||
|
||||
## RESET (Input)
|
||||
|
||||
The RESET pin can be used to reset the device at any time in an asynchronous manner. When the RESET pin is set to logic high, the device is in the reset mode and remains in the state until the pin returns low.
|
||||
|
||||
The device should be reset after power-up or recovery from the shut down mode when all the supplies and references have settled to the required accuracy.
|
||||
|
||||
## RD/SCLK (Input)
|
||||
|
||||
RD/SCLK (Input) is a dual-function pin to be used in different interface modes.
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
<table><tr><td colspan="2">Device Operating Condition</td><td>Functionality of RD/SCLK(Input)</td></tr><tr><td>Parallel Interface</td><td>PAR/SER/BYTR SEL = 0DB15/BYTE = 0</td><td rowspan="2">The active-low digital input pin to read the output data from the device.In the parallel or parallel byte interface mode, the output bus is enabled when both the CS and RD inputs are tied to a logic-low input.</td></tr><tr><td>Parallel Byte Interface</td><td>PAR/SER/BYTR SEL = 1DB15/BYTE = 1</td></tr><tr><td>Serial Interface</td><td>PAR/SER/BYTR SEL = 1DB15/BYTE = 0</td><td>The external clock input for the serial data interface. In the serial mode, all synchronous accesses to the device are timed with respect to the rising edge of the SCLK signal.</td></tr></table>
|
||||
|
||||
## $\overline{CS}$ (Input)
|
||||
|
||||
The $\overline{CS}$ pin is an active-low, chip-select signal.
|
||||
|
||||
A rising edge on the $\overline{CS}$ signal outputs all the data lines in tri-state mode.
|
||||
|
||||
A falling edge of the $\overline{CS}$ signal marks the beginning of the output data transfer frame in any interface mode of operation for the device.
|
||||
|
||||
## OS [2:0]
|
||||
|
||||
The OS [2:0] pins are active-high digital input pins used to configure the oversampling ratio for the internal digital filter on the device.
|
||||
|
||||
When OS [2:0] = 111, a higher filter bandwidth of $\sim$ 30 kHz is selected.
|
||||
|
||||
## Device Modes of Operation
|
||||
|
||||
## Power Down Modes
|
||||
|
||||
The device supports two power-down modes: standby mode and shutdown mode. The device can enter either power-down mode by pulling the STBY pin to a logic level. Additionally, the selection between these two power-down modes is done by the state of the RANGE pin.
|
||||
|
||||
<table><tr><td>Power Down Mode</td><td> $\overline{STBY}$ </td><td>Range</td></tr><tr><td>Standby</td><td>0</td><td>1</td></tr><tr><td>Shutdown</td><td>0</td><td>0</td></tr></table>
|
||||
|
||||
## Standby Mode
|
||||
|
||||
In the standby mode, only the internal reference of the circuit is powered up, and the analog front-end, signal-conditioning circuit for each channel remains powered down.
|
||||
|
||||
## Shutdown Mode
|
||||
|
||||
In the shutdown mode, the entire internal circuitry is powered down.
|
||||
|
||||
## Conversion Control
|
||||
|
||||
The device offers precise control of simultaneously sampling all analog input channels.
|
||||
|
||||
## Simultaneous Sampling on All Input Channels
|
||||
|
||||
All the analog input channels are to be simultaneously sampled by connecting CONVSTA and CONVSTB signals together, and a single CONVST signal should be used to control the sampling of all analog input channels of the device.
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
## Simultaneous Sampling Two Sets of Input Channels
|
||||
|
||||
Two sets of analog input channels can be simultaneously sampled by separating CONVSTA and CONVSTB signals. And the device could not operate in oversampling mode in this state.
|
||||
|
||||
## Data read operation
|
||||
|
||||
The device updates the internal data registers with the conversion data for all analog channels at the end of every conversion phase (when BUSY goes low).
|
||||
|
||||
If the output data are read after BUSY goes low, then the device outputs the conversion results for the current sample.
|
||||
|
||||
If the output data are read when BUSY is high, then the device outputs conversion results for the previous sample.
|
||||
|
||||
There are three interface modes:
|
||||
|
||||
<table><tr><td>Interface mode</td><td> $\overline{PAR}/SER/BYTE SEL$ </td><td>DB15/BYTE SEL</td></tr><tr><td>Parallel Interface</td><td>0</td><td>0</td></tr><tr><td>Parallel Byte Interface</td><td>1</td><td>1</td></tr><tr><td>Serial Interface</td><td>1</td><td>0</td></tr></table>
|
||||
|
||||
## Parallel Data Read
|
||||
|
||||
The device supports a parallel interface mode for reading the output data of the device using the control inputs ( $\overline{CS}$ and $\overline{RD}$ ), the parallel output bus (DB [15:0]), and the BUSY indicator.
|
||||
|
||||
For applications that use only one device in the system and do not share the parallel output bus with any other devices, the CS and RD input signals can be tied together, or the CS signal can be permanently tied low. At the first falling edge of the CS and RD signal, the output data of channel 1 becomes available on the parallel bus to be read by the digital host. At this instant, the FRSTDATA output also goes high, indicating channel 1 data is ready to be read back. The output data for the remaining channels are clocked out on the parallel bus on subsequent falling edges of the CS and RD signal in a sequential manner.
|
||||
|
||||
For applications that use multiple devices in the system, the CS and RD input signals must be driven separately.
|
||||
|
||||
## Parallel Byte Data Read
|
||||
|
||||
The parallel byte interface mode is very similar to the parallel interface mode, except that the output data for each channel is read in two data transfers of 8-bit byte sizes.
|
||||
|
||||
In the parallel byte mode, the DB14/HBEN pin decides the order of the most significant byte (MSB byte) and the least significant byte (LSB byte). When the DB14/HBEN pin is tied high, the MSB byte of the conversion results is output first followed by the LSB byte. This order is reversed when DB14/HBEN is tied to logic low.
|
||||
|
||||
At the first falling edge of the $\overline{RD}$ signal, the first byte of the channel 1 conversion result becomes available on DB [7:0]. This byte is followed by the second byte of conversion data on the next falling edge of the RD signal.
|
||||
|
||||
## Serial Data Read
|
||||
|
||||
This interface mode uses a CS control input, a communication clock input (SCLK), BUSY and FRSTDATA output indicators, and serial data output lines DOUTA and DOUTB.
|
||||
|
||||
A total of 16 SCLK cycles are required to clock out 16 bits of conversion result for each channel and the same process can be repeated for the remaining channels in an ascending order.
|
||||
|
||||
The conversion results from the first set of channels appear first on DOUTA, followed by the second set of channels if only DOUTA is used for reading data. This order is reversed for DOUTB, in which the second set of channels appear first followed by the first set of channels. The use of both data output lines reduces the time needed for data retrieval and a higher throughput can therefore be achieved in this mode.
|
||||
|
||||
## Data Read During Conversion
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
The device allows data read when the ADC is converting and the BUSY output is high status. In this case, the ADC outputs conversion results for previous samples.
|
||||
|
||||
The data read back during conversion mode allows faster throughput to be achieved from the device.
|
||||
|
||||
## Data Read During Conversion
|
||||
|
||||
The device can be configured in the oversampling mode by the OS [2:0] pins. The input on the OS pins is latched on the falling edge of the BUSY signal to configure the oversampling rate for the next conversion.
|
||||
|
||||
In this mode, the CONVST A and CONVST B signals should be tied or driven together.
|
||||
|
||||
The BUSY signal duration varies with the OSR setting because the conversion time increases with the OSR setting.
|
||||
|
||||
Oversampling the input signal reduces noise during the conversion process, thus reducing the histogram code spread for a DC input signal to the ADC.
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
## Application and Implementation
|
||||
|
||||
Note
|
||||
|
||||
Information in the following application sections is not part of the 3PEAK's component specification and 3PEAK does not warrant its accuracy or completeness. 3PEAK's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
Tape and Reel Information
|
||||
|
||||
|
||||
<details>
|
||||
<summary>natural_image</summary>
|
||||
|
||||
Technical line drawing of a wheel with four spokes and a central hub, no text or symbols present
|
||||
</details>
|
||||
|
||||
D1:Reel Diameter
|
||||
|
||||
|
||||
|
||||
<details>
|
||||
<summary>natural_image</summary>
|
||||
|
||||
Pure diagram of a vertical structure with horizontal lines and a central horizontal bar, labeled W1 at the bottom (no text or symbols beyond label)
|
||||
</details>
|
||||
|
||||
|
||||
|
||||
<details>
|
||||
<summary>text_image</summary>
|
||||
|
||||
Direction of Feed
|
||||
W0
|
||||
P0
|
||||
A0
|
||||
B0
|
||||
K0
|
||||
</details>
|
||||
|
||||
<table><tr><td>Order Number</td><td>Package</td><td>D1 (mm)</td><td>W1 (mm)</td><td>A0 (mm)</td><td>B0 (mm)</td><td>K0 (mm)</td><td>P0 (mm)</td><td>W0 (mm)</td><td>Pin1 Quadrant</td></tr><tr><td>TPAFE5160SI08-QP7R</td><td>LQFP10×10-64</td><td>330</td><td>28.4</td><td>12.085</td><td>12.085</td><td>2.1</td><td>16</td><td>24</td><td>Q2</td></tr></table>
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
## Package Outline Dimensions
|
||||
|
||||
LQFP10x10-64
|
||||
|
||||
Package Outline Dimensions
|
||||
QP5(LQFP10X10-64-A)
|
||||
|
||||
|
||||
<details>
|
||||
<summary>text_image</summary>
|
||||
|
||||
D
|
||||
D1
|
||||
64
|
||||
1
|
||||
PIN 1
|
||||
E1
|
||||
E
|
||||
</details>
|
||||
|
||||
|
||||
|
||||
<details>
|
||||
<summary>text_image</summary>
|
||||
|
||||
WITH PLATING
|
||||
b
|
||||
c
|
||||
BASE
|
||||
METAL
|
||||
</details>
|
||||
|
||||
SECTION N-N
|
||||
|
||||
|
||||
|
||||
<details>
|
||||
<summary>natural_image</summary>
|
||||
|
||||
Pure electrical circuit lines without any symbols
|
||||
</details>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<details>
|
||||
<summary>text_image</summary>
|
||||
|
||||
A
|
||||
A2
|
||||
SEATING
|
||||
PLANE
|
||||
A1
|
||||
C
|
||||
e
|
||||
b
|
||||
θ
|
||||
L
|
||||
N
|
||||
</details>
|
||||
|
||||
DETAIL Y
|
||||
|
||||
## NOTES
|
||||
|
||||
1. Do not include mold flash or protrusion.
|
||||
2. This drawing is subject to change without notice.
|
||||
|
||||
<table><tr><td rowspan="2">Symbol</td><td colspan="2">Dimensions In Millimeters</td><td colspan="2">Dimensions In Inches</td></tr><tr><td>MIN</td><td>MAX</td><td>MIN</td><td>MAX</td></tr><tr><td>A</td><td>1.400</td><td>1.600</td><td>0.055</td><td>0.063</td></tr><tr><td>A1</td><td>0.050</td><td>0.150</td><td>0.002</td><td>0.006</td></tr><tr><td>A2</td><td>1.350</td><td>1.450</td><td>0.053</td><td>0.057</td></tr><tr><td>b</td><td>0.170</td><td>0.270</td><td>0.007</td><td>0.011</td></tr><tr><td>c</td><td>0.090</td><td>0.200</td><td>0.004</td><td>0.008</td></tr><tr><td>D</td><td>11.800</td><td>12.200</td><td>0.465</td><td>0.480</td></tr><tr><td>D1</td><td>9.900</td><td>10.100</td><td>0.390</td><td>0.398</td></tr><tr><td>E</td><td>11.800</td><td>12.200</td><td>0.465</td><td>0.480</td></tr><tr><td>E1</td><td>9.900</td><td>10.100</td><td>0.390</td><td>0.398</td></tr><tr><td>e</td><td colspan="2">0.500 BSC</td><td colspan="2">0.020 BSC</td></tr><tr><td>L</td><td>0.450</td><td>0.750</td><td>0.018</td><td>0.030</td></tr><tr><td>θ</td><td>0</td><td>7°</td><td>0</td><td>7°</td></tr></table>
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
Order Information
|
||||
|
||||
<table><tr><td>Order Number</td><td>Operating Temperature Range</td><td>Package</td><td>Marking Information</td><td>MSL</td><td>Transport Media, Quantity</td><td>Eco Plan</td></tr><tr><td>TPAFE5160SI08-QP7R</td><td>-40 to 125°C</td><td>LQFP10×10-64</td><td>AFE5160</td><td>3</td><td>Tape and Reel, 1000</td><td>Green</td></tr></table>
|
||||
|
||||
Green: 3PEAK defines "Green" to mean RoHS compatible and free of halogen substances.
|
||||
|
||||
# 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
## IMPORTANT NOTICE AND DISCLAIMER
|
||||
|
||||
Copyright© 3PEAK 2012-2024. All rights reserved.
|
||||
|
||||
Trademarks. Any of the 思瑞浦 or 3PEAK trade names, trademarks, graphic marks, and domain names contained in this document /material are the property of 3PEAK. You may NOT reproduce, modify, publish, transmit or distribute any Trademark without the prior written consent of 3PEAK.
|
||||
|
||||
Performance Information. Performance tests or performance range contained in this document/material are either results of design simulation or actual tests conducted under designated testing environment. Any variation in testing environment or simulation environment, including but not limited to testing method, testing process or testing temperature, may affect actual performance of the product.
|
||||
|
||||
Disclaimer. 3PEAK provides technical and reliability data (including data sheets), design resources (including reference designs), application or other design recommendations, networking tools, security information and other resources "As Is". 3PEAK makes no warranty as to the absence of defects, and makes no warranties of any kind, express or implied, including without limitation, implied warranties as to merchantability, fitness for a particular purpose or non-infringement of any third-party's intellectual property rights. Unless otherwise specified in writing, products supplied by 3PEAK are not designed to be used in any life-threatening scenarios, including critical medical applications, automotive safety-critical systems, aviation, aerospace, or any situations where failure could result in bodily harm, loss of life, or significant property damage. 3PEAK disclaims all liability for any such unauthorized use.
|
||||
495
docs/嵌入式C语言代码规范（V1.0）.md
Normal file
495
docs/嵌入式C语言代码规范（V1.0）.md
Normal file
@@ -0,0 +1,495 @@
|
||||
## 1. 文档概述
|
||||
|
||||
### 1.1 目的
|
||||
本文档旨在统一嵌入式C语言代码的编写风格，提高代码的可读性、可维护性、可移植性和可靠性，降低团队协作成本，减少代码缺陷。
|
||||
### 1.2 适用范围
|
||||
本规范适用于所有基于C语言的嵌入式软件开发项目，包括但不限于51单片机、STM32、ARM、DSP等平台。
|
||||
### 1.3 修订记录
|
||||
| 版本号 | 修订日期 | 修订内容 | 修订人 |
|
||||
| ---- | ---------- | ------ | --- |
|
||||
| V1.0 | 2026-05-11 | 创建初始版本 | 王建锋 |
|
||||
## 2. 文件结构规范
|
||||
|
||||
### 2.1 头文件(.h)结构
|
||||
```c
|
||||
#ifndef __MODULE_NAME_H
|
||||
#define __MODULE_NAME_H
|
||||
|
||||
/*
|
||||
* 模块名称：模块英文名称
|
||||
* 模块功能：简要描述模块的主要功能
|
||||
* 适用平台：列出支持的硬件平台
|
||||
* 作者：作者姓名
|
||||
* 创建日期：YYYY-MM-DD
|
||||
* 修改记录：
|
||||
* YYYY-MM-DD 修改人 修改内容说明
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* 头文件包含区 - 仅包含本模块必需的头文件 */
|
||||
#include "stdint.h"
|
||||
|
||||
/* 宏定义区 */
|
||||
#define MODULE_NAME_CONSTANT 100
|
||||
|
||||
/* 类型定义区 */
|
||||
typedef enum {
|
||||
MODULE_NAME_STATUS_OK = 0,
|
||||
MODULE_NAME_STATUS_ERROR
|
||||
} module_name_status_t;
|
||||
|
||||
/* 函数声明区 */
|
||||
void module_name_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MODULE_NAME_H */
|
||||
```
|
||||
### 2.2 源文件(.c)结构
|
||||
```c
|
||||
/*
|
||||
* 模块名称：模块英文名称
|
||||
* 模块功能：简要描述模块的主要功能
|
||||
* 适用平台：列出支持的硬件平台
|
||||
* 作者：作者姓名
|
||||
* 创建日期：YYYY-MM-DD
|
||||
* 修改记录：
|
||||
* YYYY-MM-DD 修改人 修改内容说明
|
||||
*/
|
||||
|
||||
/* 头文件包含区 - 先包含系统头文件，再包含自定义头文件 */
|
||||
#include "module_name.h"
|
||||
|
||||
/* 私有宏定义区 */
|
||||
#define MODULE_NAME_PRIVATE_CONSTANT 200
|
||||
|
||||
/* 私有类型定义区 */
|
||||
typedef struct {
|
||||
uint8_t data;
|
||||
} module_name_private_t;
|
||||
|
||||
/* 全局变量定义区 - 尽量避免使用全局变量 */
|
||||
uint8_t g_module_name_global_var = 0;
|
||||
|
||||
/* 静态变量定义区 */
|
||||
static module_name_private_t s_module_name_private_var;
|
||||
|
||||
/* 私有函数声明区 */
|
||||
static void module_name_private_function(void);
|
||||
|
||||
/* 函数定义区 - 先写公共函数，再写私有函数 */
|
||||
void module_name_init(void) {
|
||||
/* 函数实现 */
|
||||
}
|
||||
|
||||
static void module_name_private_function(void) {
|
||||
/* 函数实现 */
|
||||
}
|
||||
```
|
||||
### 2.3 头文件包含规则
|
||||
1. 头文件必须包含头文件保护宏，格式为`__MODULE_NAME_H`
|
||||
2. 头文件中只包含本模块接口必需的其他头文件
|
||||
3. 源文件中先包含系统头文件，再包含自定义头文件
|
||||
4. 禁止在头文件中定义变量和函数体
|
||||
5. 禁止使用相对路径包含头文件
|
||||
## 3. 命名规范
|
||||
### 3.1 通用命名原则
|
||||
1. 所有名称必须使用英文，禁止使用拼音和中文
|
||||
2. 名称必须准确反映其实际含义，做到"见名知意"
|
||||
3. 名称长度适中，避免过长或过短
|
||||
4. 禁止使用单个字母作为变量名（循环变量i、j、k除外）
|
||||
5. 禁止使用关键字和保留字作为名称
|
||||
### 3.2 变量命名
|
||||
1. 采用**小写字母+下划线**命名法
|
||||
2. 全局变量以`g_`前缀开头
|
||||
3. 静态变量以`s_`前缀开头
|
||||
4. 指针变量以`p_`前缀开头
|
||||
5. 数组变量以`a_`前缀开头
|
||||
6. 布尔变量以`is_`、`has_`、`can_`等前缀开头
|
||||
**示例：**
|
||||
```c
|
||||
uint8_t g_system_status; /* 全局系统状态变量 */
|
||||
static uint16_t s_timer_count; /* 静态定时器计数变量 */
|
||||
uint8_t *p_data_buffer; /* 数据缓冲区指针 */
|
||||
uint16_t a_adc_value[10]; /* ADC采样值数组 */
|
||||
bool is_button_pressed; /* 按钮是否按下标志 */
|
||||
```
|
||||
### 3.3 函数命名
|
||||
1. 采用**小写字母+下划线**命名法
|
||||
2. 公共函数以**模块名**作为前缀
|
||||
3. 私有函数以**模块名+private**作为前缀
|
||||
4. 函数名应为"动词+名词"结构，明确表示函数功能
|
||||
**示例：**
|
||||
```c
|
||||
/* 公共函数 */
|
||||
void uart_init(uint32_t baud_rate);
|
||||
uint8_t uart_send_byte(uint8_t data);
|
||||
|
||||
/* 私有函数 */
|
||||
static void uart_private_handle_interrupt(void);
|
||||
```
|
||||
### 3.4 宏和常量命名
|
||||
1. 采用**大写字母+下划线**命名法
|
||||
2. 以**模块名**作为前缀
|
||||
3. 常量优先使用`const`定义，而非`#define`
|
||||
**示例：**
|
||||
```c
|
||||
#define UART_BAUD_RATE_9600 9600
|
||||
#define UART_BUFFER_SIZE 128
|
||||
|
||||
const uint8_t UART_DEFAULT_DATA_BITS = 8;
|
||||
```
|
||||
### 3.5 类型定义命名
|
||||
1. 采用**小写字母+下划线**命名法
|
||||
2. 以`_t`作为后缀
|
||||
3. 枚举类型成员以**模块名**作为前缀
|
||||
**示例：**
|
||||
```c
|
||||
typedef enum {
|
||||
UART_STATUS_OK = 0,
|
||||
UART_STATUS_ERROR,
|
||||
UART_STATUS_TIMEOUT
|
||||
} uart_status_t;
|
||||
|
||||
typedef struct {
|
||||
uint8_t data_bits;
|
||||
uint8_t stop_bits;
|
||||
uint32_t baud_rate;
|
||||
} uart_config_t;
|
||||
```
|
||||
## 4. 格式与排版规范
|
||||
|
||||
### 4.1 缩进
|
||||
1. 使用**4个空格**进行缩进，禁止使用Tab键
|
||||
2. 所有包含关系的内容必须缩进
|
||||
3. 同一级别的代码保持相同的缩进级别
|
||||
### 4.2 空格使用
|
||||
1. 所有赋值语句、比较语句、算术运算符前后必须加空格
|
||||
2. 函数参数列表中，逗号后面必须加空格
|
||||
3. 关键字后面必须加空格
|
||||
4. 括号内部两侧不加空格
|
||||
5. 一元运算符前后不加空格
|
||||
**正确示例：**
|
||||
```c
|
||||
int a = 10;
|
||||
if (a > 5) {
|
||||
b = a + 3;
|
||||
}
|
||||
for (i = 0; i < 10; i++) {
|
||||
c[i] = 0;
|
||||
}
|
||||
```
|
||||
**错误示例：**
|
||||
```c
|
||||
int a=10;
|
||||
if(a>5){
|
||||
b=a+3;
|
||||
}
|
||||
for(i=0;i<10;i++){
|
||||
c[i]=0;
|
||||
}
|
||||
```
|
||||
### 4.3 换行与空行
|
||||
1. 每行代码长度不超过80个字符
|
||||
2. 函数之间必须空一行
|
||||
3. 逻辑上相关的代码块之间可以空一行
|
||||
4. 函数内变量声明区和代码执行区之间必须空一行
|
||||
5. 长表达式应在运算符处换行，新行与运算符对齐
|
||||
**示例：**
|
||||
```c
|
||||
int calculate_sum(int a, int b, int c, int d) {
|
||||
int sum;
|
||||
|
||||
sum = a + b
|
||||
+ c
|
||||
+ d;
|
||||
|
||||
return sum;
|
||||
}
|
||||
```
|
||||
### 4.4 大括号使用
|
||||
1. **所有包含关系必须加大括号**，即使只有一条语句或为空
|
||||
2. 左大括号`{`与前面的语句在同一行，前面加一个空格
|
||||
3. 右大括号`}`单独占一行，与对应的左大括号缩进级别相同
|
||||
4. 空函数体的大括号也必须单独占一行
|
||||
**正确示例：**
|
||||
```c
|
||||
if (condition) {
|
||||
do_something();
|
||||
}
|
||||
|
||||
while (1) {
|
||||
}
|
||||
```
|
||||
**错误示例：**
|
||||
```c
|
||||
if (condition)
|
||||
do_something();
|
||||
|
||||
while (1) ;
|
||||
```
|
||||
## 5. 注释规范
|
||||
|
||||
### 5.1 通用注释原则
|
||||
1. 注释必须清晰、准确、简洁，与代码保持一致
|
||||
2. 解释性注释使用`/* */`，调试性注释使用`//`
|
||||
3. 注释应解释"为什么这么做"，而不是"做了什么"
|
||||
4. 代码修改时，必须同步修改相关注释
|
||||
5. 禁止注释掉的代码提交到版本库
|
||||
### 5.2 文件头注释
|
||||
每个文件开头必须包含文件头注释，格式见2.1和2.2节。
|
||||
### 5.3 函数注释
|
||||
所有函数（包括私有函数）必须包含完整的函数注释，格式如下：
|
||||
```c
|
||||
/*
|
||||
* 函数功能：详细描述函数的功能
|
||||
* 入口参数：param1 - 参数1说明 类型 取值范围
|
||||
* param2 - 参数2说明 类型 取值范围
|
||||
* 出口参数：param3 - 参数3说明 类型 取值范围
|
||||
* 返回值：返回值说明 类型 取值范围
|
||||
* 限定条件：函数使用的前提条件和限制
|
||||
* 函数说明：1. 函数的详细说明
|
||||
* 2. 注意事项
|
||||
* 3. 其他需要说明的内容
|
||||
*/
|
||||
```
|
||||
**示例：**
|
||||
```c
|
||||
/*
|
||||
* 函数功能：毫秒级软件延时函数
|
||||
* 入口参数：ms - 需要延时的毫秒数 unsigned int 0 - 65535
|
||||
* 限定条件：0 <= ms <= 65535
|
||||
* 函数说明：1. 采用空指令循环方式实现延时，会阻塞CPU运行
|
||||
* 2. 延时精度依赖系统时钟，默认适配12MHz时钟（12T模式）
|
||||
* 3. 系统时钟改变时，需重新调整内层循环次数
|
||||
* 4. 当ms为0时，函数立即返回
|
||||
*/
|
||||
void delay_ms(unsigned int ms) {
|
||||
unsigned int i;
|
||||
unsigned int j;
|
||||
|
||||
for (i = 0; i < ms; i++) {
|
||||
for (j = 0; j < 123; j++) {
|
||||
}
|
||||
}
|
||||
}
|
||||
```
|
||||
### 5.4 变量注释
|
||||
1. 全局变量和静态变量必须添加注释
|
||||
2. 重要的局部变量应添加注释
|
||||
3. 注释可以写在变量定义的同一行或上一行
|
||||
**示例：**
|
||||
```c
|
||||
/* 系统运行时间，单位：毫秒 */
|
||||
uint32_t g_system_time = 0;
|
||||
|
||||
static uint8_t s_uart_rx_buffer[UART_BUFFER_SIZE]; /* UART接收缓冲区 */
|
||||
```
|
||||
### 5.5 代码行注释
|
||||
1. **关键逻辑代码每一行都要添加注释**
|
||||
2. 复杂的算法和逻辑必须添加详细注释
|
||||
3. 注释应单独占一行，与被注释代码缩进级别相同
|
||||
**示例：**
|
||||
```c
|
||||
/* 计算CRC校验值 */
|
||||
uint16_t crc_calculate(uint8_t *data, uint16_t length)
|
||||
{
|
||||
uint16_t crc = 0xFFFF;
|
||||
uint16_t i;
|
||||
uint16_t j;
|
||||
|
||||
/* 遍历所有数据字节 */
|
||||
for (i = 0; i < length; i++) {
|
||||
/* 将当前字节与CRC寄存器低8位异或 */
|
||||
crc ^= data[i];
|
||||
|
||||
/* 对每个位进行处理 */
|
||||
for (j = 0; j < 8; j++) {
|
||||
/* 检查最低位是否为1 */
|
||||
if (crc & 0x0001) {
|
||||
/* 最低位为1，右移并与多项式异或 */
|
||||
crc = (crc >> 1) ^ 0xA001;
|
||||
} else {
|
||||
/* 最低位为0，直接右移 */
|
||||
crc = crc >> 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* 返回计算得到的CRC值 */
|
||||
return crc;
|
||||
}
|
||||
```
|
||||
## 6. 编程实践规范
|
||||
### 6.1 变量声明与初始化
|
||||
1. 变量应在使用前声明，并尽可能在靠近使用的地方声明
|
||||
2. 所有变量必须初始化，禁止使用未初始化的变量
|
||||
3. 尽量使用局部变量，避免使用全局变量
|
||||
4. 指针变量必须初始化为`NULL`
|
||||
5. 使用标准数据类型（`uint8_t`、`int32_t`等），避免使用`char`、`int`等不确定长度的类型
|
||||
**示例：**
|
||||
```c
|
||||
void function(void) {
|
||||
uint8_t status = 0;
|
||||
uint16_t count = 0;
|
||||
uint8_t *p_data = NULL;
|
||||
|
||||
p_data = (uint8_t *)malloc(100);
|
||||
if (p_data == NULL) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* 使用p_data */
|
||||
|
||||
free(p_data);
|
||||
p_data = NULL;
|
||||
}
|
||||
```
|
||||
### 6.2 函数设计原则
|
||||
1. 函数应遵循"单一职责原则"，一个函数只做一件事
|
||||
2. 函数长度不宜过长，一般不超过50行
|
||||
3. 函数参数不宜过多，一般不超过5个
|
||||
4. 函数必须有明确的返回值，用于表示执行状态
|
||||
5. 避免使用函数参数作为返回值
|
||||
6. 私有函数必须声明为`static`
|
||||
### 6.3 控制结构
|
||||
1. `if`语句中，常量应写在比较运算符的左边
|
||||
2. `switch`语句必须包含`default`分支
|
||||
3. 避免使用`goto`语句，除非用于错误处理
|
||||
4. 循环嵌套不宜超过3层
|
||||
**示例：**
|
||||
```c
|
||||
if (0 == status) {
|
||||
do_something();
|
||||
}
|
||||
|
||||
switch (command) {
|
||||
case COMMAND_START:
|
||||
start_process();
|
||||
break;
|
||||
|
||||
case COMMAND_STOP:
|
||||
stop_process();
|
||||
break;
|
||||
|
||||
default:
|
||||
handle_unknown_command();
|
||||
break;
|
||||
}
|
||||
```
|
||||
### 6.4 错误处理
|
||||
1. 所有可能失败的函数都必须检查返回值
|
||||
2. 对输入参数进行合法性检查
|
||||
3. 对指针进行非空检查
|
||||
4. 数组访问时检查下标是否越界
|
||||
5. 使用断言`assert`检查开发阶段的错误
|
||||
**示例：**
|
||||
```c
|
||||
uint8_t uart_send_data(uint8_t *data, uint16_t length) {
|
||||
/* 检查输入参数合法性 */
|
||||
if (data == NULL) {
|
||||
return UART_STATUS_ERROR;
|
||||
}
|
||||
|
||||
if (length == 0 || length > UART_BUFFER_SIZE) {
|
||||
return UART_STATUS_ERROR;
|
||||
}
|
||||
|
||||
/* 发送数据 */
|
||||
|
||||
return UART_STATUS_OK;
|
||||
}
|
||||
```
|
||||
## 7. 可移植性与安全规范
|
||||
1. 避免使用编译器特有的扩展功能
|
||||
2. 避免使用硬编码的数值，使用宏定义代替
|
||||
3. 注意字节序问题，多字节数据传输时进行字节序转换
|
||||
4. 注意数据类型的长度和符号问题
|
||||
5. 避免使用不安全的函数，如`strcpy`、`sprintf`等，使用`strncpy`、`snprintf`代替
|
||||
6. 禁止使用可变参数函数
|
||||
7. 禁止使用递归函数
|
||||
## 8. 版本控制规范
|
||||
1. 每次提交必须填写清晰、准确的提交信息
|
||||
2. 提交信息格式：`[模块名] 修改内容说明`
|
||||
3. 每次提交只包含一个逻辑修改
|
||||
4. 提交前必须进行代码编译和测试
|
||||
5. 禁止提交编译错误的代码
|
||||
6. 禁止提交调试信息和注释掉的代码
|
||||
## 9. 附录
|
||||
### 9.1 完整示例代码
|
||||
```c
|
||||
#ifndef __LED_H
|
||||
#define __LED_H
|
||||
|
||||
/*
|
||||
* 模块名称：LED控制模块
|
||||
* 模块功能：提供LED初始化、点亮、熄灭和翻转功能
|
||||
* 适用平台：STM32F103系列单片机
|
||||
* 作者：张三
|
||||
* 创建日期：2026-05-11
|
||||
* 修改记录：
|
||||
* 2026-05-11 张三 创建初始版本
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "stdint.h"
|
||||
|
||||
/* LED编号定义 */
|
||||
#define LED_NUM_1 0
|
||||
#define LED_NUM_2 1
|
||||
#define LED_NUM_MAX 2
|
||||
|
||||
/* LED状态定义 */
|
||||
#define LED_OFF 0
|
||||
#define LED_ON 1
|
||||
|
||||
/*
|
||||
* 函数功能：LED初始化函数
|
||||
* 入口参数：led_num - LED编号 uint8_t 0 - LED_NUM_MAX-1
|
||||
* 返回值：0 - 成功，其他 - 失败
|
||||
* 限定条件：无
|
||||
* 函数说明：初始化LED对应的GPIO引脚为推挽输出模式
|
||||
*/
|
||||
uint8_t led_init(uint8_t led_num);
|
||||
|
||||
/*
|
||||
* 函数功能：点亮LED
|
||||
* 入口参数：led_num - LED编号 uint8_t 0 - LED_NUM_MAX-1
|
||||
* 返回值：0 - 成功，其他 - 失败
|
||||
* 限定条件：led_init()函数已成功调用
|
||||
* 函数说明：将LED对应的GPIO引脚置为低电平
|
||||
*/
|
||||
uint8_t led_on(uint8_t led_num);
|
||||
|
||||
/*
|
||||
* 函数功能：熄灭LED
|
||||
* 入口参数：led_num - LED编号 uint8_t 0 - LED_NUM_MAX-1
|
||||
* 返回值：0 - 成功，其他 - 失败
|
||||
* 限定条件：led_init()函数已成功调用
|
||||
* 函数说明：将LED对应的GPIO引脚置为高电平
|
||||
*/
|
||||
uint8_t led_off(uint8_t led_num);
|
||||
|
||||
/*
|
||||
* 函数功能：翻转LED状态
|
||||
* 入口参数：led_num - LED编号 uint8_t 0 - LED_NUM_MAX-1
|
||||
* 返回值：0 - 成功，其他 - 失败
|
||||
* 限定条件：led_init()函数已成功调用
|
||||
* 函数说明：将LED对应的GPIO引脚电平取反
|
||||
*/
|
||||
uint8_t led_toggle(uint8_t led_num);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LED_H */
|
||||
```
|
||||
Reference in New Issue
Block a user