Arm® Cortex®-M4 32b MCU+FPU, 210DMIPS, up to 1MB flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces, and camera

Datasheet - production data

## Features

- Includes ST state-of-the-art patented technology
- Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
- Memories

- Up to 1 Mbyte of flash memory
- Up to 192+4 Kbytes of SRAM including 64-Kbyte of CCM (core coupled memory) data RAM
- 512 bytes of OTP memory
- Flexible static memory controller supporting CompactFlash™, SRAM, PSRAM, NOR and NAND memories

• LCD parallel interface, 8080/6800 modes
- Clock, reset, and supply management

– 1.8 V to 3.6 V application supply and I/Os
- POR, PDR, PVD and BOR
– 4-to-26 MHz crystal oscillator
- Internal 16 MHz factory-trimmed RC (1% accuracy)
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration

\- Low-power operation

– Sleep, Stop, and Standby modes
- $V_{BAT}$ supply for RTC, 20×32-bit backup registers + optional 4 KB backup SRAM

- 3×12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode
- $2 \times 12$ -bit D/A converters
- General-purpose DMA: 16-stream DMA controller with FIFOs and burst support

![](images/08b4f54513b86fafb08fb766fe3c944e53309dae4638aff8252d8d92fc672065.jpg)

LQFP64 (10 × 10 mm)

LQFP100 (14 × 14 mm)

LQFP144 (20 × 20 mm)

LQFP176 (24 × 24 mm)

![](images/bec658301e9ff8fa9bd148d9f5b559e8900842d0de3627a21b010f68144488e1.jpg)

UFBGA176

(10 × 10 mm)

![](images/a5acec4ac89ccd559e6be64bec85c5c989bd493dc324367b5d2dcba46599328b.jpg)

WLCSP90

(4.223×3.969 mm)

- Up to 17 timers: up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
- Debug mode

- Serial wire debug (SWD) & JTAG interfaces
– Cortex-M4 Embedded Trace Macrocell™

\- Up to 140 I/O ports with interrupt capability

– Up to 136 fast I/Os up to 84 MHz
– Up to 138 5 V-tolerant I/Os

\- Up to 15 communication interfaces

- Up to $3 \times \mathrm{I}^{2}\mathrm{C}$ interfaces (SMBus/PMBus)
- Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control)
- Up to 3 SPIs (42 Mbits/s), 2 with muxed full-duplex I²S to achieve audio class accuracy via internal audio PLL or external clock

- $2 \times$ CAN interfaces (2.0B Active)
- SDIO interface

\- Advanced connectivity

- USB 2.0 full-speed device/host/OTG controller with on-chip PHY
- USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI
- 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII

- 8- to 14-bit parallel camera interface up to 54 Mbytes/s
- True random number generator
- CRC calculation unit

- 96-bit unique ID
- RTC: subsecond accuracy, hardware calendar
- All packages are ECOPACK2 compliant

Table 1. Device summary

<table><tr><td>Reference</td><td>Part number</td></tr><tr><td>STM32F405xx</td><td>STM32F405RG, STM32F405VG, STM32F405ZG, STM32F405OG, STM32F405OE</td></tr><tr><td>STM32F407xx</td><td>STM32F407VG, STM32F407IG, STM32F407ZG, STM32F407VE, STM32F407ZE, STM32F407IE</td></tr></table>

## Contents

## 1 Introduction 13

## 2 Description....14

2.1 Full compatibility throughout the family .... 17

## 3 Functional overview 20

3.1 Arm® Cortex®-M4 core with FPU and embedded flash and SRAM . . . . 21

3.2 Adaptive real-time memory accelerator (ART Accelerator) ..... 21

3.3 Memory protection unit 21

3.4 Embedded flash memory 22

3.5 CRC (cyclic redundancy check) calculation unit 22

3.6 Embedded SRAM 22

3.7 Multi-AHB bus matrix 22

3.8 DMA controller (DMA) 23

3.9 Flexible static memory controller (FSMC) 24

3.9.1 LCD parallel interface 24

3.10 Nested vectored interrupt controller (NVIC) 24

3.11 External interrupt/event controller (EXTI) 25

3.12 Clocks and startup 25

3.13 Boot modes 25

3.14 Power supply schemes 25

3.15 Power supply supervisor 26

3.15.1 Internal reset ON 26

3.15.2 Internal reset OFF 26

3.16 Voltage regulator 28

3.16.1 Regulator ON 28

3.16.2 Regulator OFF 29

3.17 Regulator ON/OFF and internal reset ON/OFF availability .... 31

3.18 Real-time clock (RTC), backup SRAM and backup registers ..... 31

3.19 Low-power modes 32

3.20 $V_{BAT}$ operation 33

3.21 Timers and watchdogs 33

3.21.1 Advanced-control timers (TIM1, TIM8) 34
3.21.2 General-purpose timers (TIMx) 35
3.21.3 Basic timers TIM6 and TIM7 35

3.22 Inter-integrated circuit interface (I²C) 36
3.23 Universal synchronous/asynchronous receiver transmitters (USART) .. 36
3.24 Serial peripheral interface (SPI) 37
3.25 Inter-integrated sound (I2S) 37
3.26 Audio PLL (PLLI2S) 38
3.27 Secure digital input/output interface (SDIO) 38
3.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 38
3.29 Controller area network (bxCAN) 39
3.30 Universal serial bus on-the-go full-speed (OTG\_FS) 39
3.31 Universal serial bus on-the-go high-speed (OTG\_HS) 40
3.32 Digital camera interface (DCMI) 40
3.33 True random number generator (RNG) 40
3.34 General-purpose input/outputs (GPIOs) 41
3.35 Analog-to-digital converters (ADCs) 41
3.36 Temperature sensor 41
3.37 Digital-to-analog converter (DAC) 41
3.38 Serial wire JTAG debug port (SWJ-DP) 42
3.39 Embedded Trace Macrocell™ 42

4 Pinouts and pin description 43
5 Memory mapping 73
6 Electrical characteristics 78

6.1 Parameter conditions 78

6.1.1 Minimum and maximum values .... 78
6.1.2 Typical values 78
6.1.3 Typical curves 78
6.1.4 Loading capacitor 78
6.1.5 Pin input voltage 78
6.1.6 Power supply scheme 79
6.1.7 Current consumption measurement ....80

6.2 Absolute maximum ratings .... 80

6.3 Operating conditions 81

6.3.1 General operating conditions 81

6.3.2 VCAP\_1/VCAP\_2 external capacitor 84

6.3.3 Operating conditions at power-up / power-down (regulator ON) ..... 84

6.3.4 Operating conditions at power-up / power-down (regulator OFF) ..... 84

6.3.5 Embedded reset and power control block characteristics ..... 85

6.3.6 Supply current characteristics 86

6.3.7 Wakeup time from low-power mode 100

6.3.8 External clock source characteristics ..... 101

6.3.9 Internal clock source characteristics 105

6.3.10 PLL characteristics 106

6.3.11 PLL spread spectrum clock generation (SSCG) characteristics ..... 108

6.3.12 Memory characteristics 110

6.3.13 EMC characteristics 112

6.3.14 Absolute maximum ratings (electrical sensitivity) 114

6.3.15 I/O current injection characteristics 115

6.3.16 I/O port characteristics 116

6.3.17 NRST pin characteristics 121

6.3.18 TIM timer characteristics 121

6.3.19 Communications interfaces 123

6.3.20 CAN (controller area network) interface .... 135

6.3.21 12-bit ADC characteristics 135

6.3.22 Temperature sensor characteristics 140

6.3.23 $V_{BAT}$ monitoring characteristics ..... 141

6.3.24 Embedded reference voltage 141

6.3.25 DAC electrical characteristics 141

6.3.26 FSMC characteristics 144

6.3.27 Camera interface (DCMI) timing specifications .... 162

6.3.28 SD/SDIO MMC card host interface (SDIO) characteristics ..... 163

6.3.29 RTC characteristics 164

## 7 Package information 165

7.1 Device marking 165

7.2 WLCSP90 package information 166

7.3 LQFP64 package information (5W) 169

7.4 LQFP100 package information (1L) 172
7.5 LQFP144 package information (1A) 175
7.6 UFBGA(176+25) package information (A0E7) 179
7.7 LQFP176 package information (1T) 181
7.8 Thermal characteristics 185

## 8 Ordering information 186

## Appendix A Application block diagrams 187

A.1 USB OTG full speed (FS) interface solutions ..... 187
A.2 USB OTG high speed (HS) interface solutions....189
A.3 Ethernet interface solutions.... 190

## 9 Important security notice .... 192

## 10 Revision history 193

## List of tables

Table 1. Device summary....2

Table 2. STM32F405xx and STM32F407xx: features and peripheral counts. 15

Table 3. Regulator ON/OFF and internal reset ON/OFF availability....31

Table 4. Timer feature comparison....33

Table 5. USART feature comparison 37

Table 6. Legend/abbreviations used in the pinout table 48

Table 7. STM32F40xxx pin and ball definitions 49

Table 8. FSMC pin definition 61

Table 9. Alternate function mapping 64

Table 10. Register boundary addresses....74

Table 11. Voltage characteristics 80

Table 12. Current characteristics 81

Table 13. Thermal characteristics....81

Table 14. General operating conditions 81

Table 15. Limitations depending on the operating power supply range ..... 83

Table 16. VCAP\_1/VCAP\_2 operating conditions 84

Table 17. Operating conditions at power-up / power-down (regulator ON) 84

Table 18. Operating conditions at power-up / power-down (regulator OFF). 84

Table 19. Embedded reset and power control block characteristics. 85

Table 20. Typical and maximum current consumption in Run mode, code with data processing running from flash memory (ART accelerator enabled) or RAM 87

Table 21. Typical and maximum current consumption in Run mode, code with data processing running from flash memory (ART accelerator disabled) 88

Table 22. Typical and maximum current consumption in Sleep mode 91

Table 23. Typical and maximum current consumptions in Stop mode 92

Table 24. Typical and maximum current consumptions in Standby mode ..... 92

Table 25. Typical and maximum current consumptions in $V_{BAT}$ mode.....93

Table 26. Typical current consumption in Run mode, code with data processing running from flash memory, regulator ON (ART accelerator enabled except prefetch), $V_{DD} = 1.8 V$ ..... 95

Table 27. Switching output I/O current consumption 97

Table 28. Peripheral current consumption 98

Table 29. Low-power mode wakeup timings 101

Table 30. High-speed external user clock characteristics....101

Table 31. Low-speed external user clock characteristics 102

Table 32. HSE 4-26 MHz oscillator characteristics 103

Table 33. LSE oscillator characteristics ( $f_{LSE} = 32.768$ kHz) 104

Table 34. HSI oscillator characteristics 105

Table 35. LSI oscillator characteristics 105

Table 36. Main PLL characteristics....106

Table 37. PLLI2S (audio PLL) characteristics 107

Table 38. SSCG parameters constraint 108

Table 39. Flash memory characteristics....110

Table 40. Flash memory programming....110

Table 41. Flash memory programming with VPP 112

Table 42. Flash memory endurance and data retention....112

Table 43. EMS characteristics 113

Table 44. EMI characteristics for fHSE = 25 MH and fCPU = 168 MHz....114

Table 45. ESD absolute maximum ratings 114
Table 46. Electrical sensitivities 115
Table 47. I/O current injection susceptibility 116
Table 48. I/O static characteristics 116
Table 49. Output voltage characteristics 118
Table 50. I/O AC characteristics....119
Table 51. NRST pin characteristics 121
Table 52. Characteristics of TIMx connected to the APB1 domain 122
Table 53. Characteristics of TIMx connected to the APB2 domain 123
Table 54. I2C analog filter characteristics....123
Table 55. SPI dynamic characteristics 124
Table 56. I2S dynamic characteristics 128
Table 57. USB OTG FS startup time 130
Table 58. USB OTG FS DC electrical characteristics....130
Table 59. USB OTG FS electrical characteristics....131
Table 60. USB HS DC electrical characteristics....131
Table 61. USB HS clock timing parameters 131
Table 62. ULPI timing 132
Table 63. Ethernet DC electrical characteristics....133
Table 64. Dynamic characteristics: Ethernet MAC signals for SMI. 133
Table 65. Dynamic characteristics: Ethernet MAC signals for RMII 134
Table 66. Dynamic characteristics: Ethernet MAC signals for MII 135
Table 67. ADC characteristics 135
Table 68. ADC accuracy at $f_{ADC} = 30$ MHz 137
Table 69. Temperature sensor characteristics 140
Table 70. Temperature sensor calibration values....140
Table 71. $V_{BAT}$ monitoring characteristics ..... 141
Table 72. Embedded internal reference voltage....141
Table 73. Internal reference voltage calibration values .... 141
Table 74. DAC characteristics 141
Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings ..... 145
Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings ..... 146
Table 77. Asynchronous multiplexed PSRAM/NOR read timings. 147
Table 78. Asynchronous multiplexed PSRAM/NOR write timings 148
Table 79. Synchronous multiplexed NOR/PSRAM read timings 150
Table 80. Synchronous multiplexed PSRAM write timings....151
Table 81. Synchronous non-multiplexed NOR/PSRAM read timings 153
Table 82. Synchronous non-multiplexed PSRAM write timings 154
Table 83. Switching characteristics for PC Card/CF read and write cycles in attribute/common space....159
Table 84. Switching characteristics for PC Card/CF read and write cycles in I/O space 160
Table 85. Switching characteristics for NAND flash read cycles .... 161
Table 86. Switching characteristics for NAND flash write cycles ..... 162
Table 87. DCMI characteristics....162
Table 88. Dynamic characteristics: SD/MMC characteristics ..... 164
Table 89. RTC characteristics 164
Table 90. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package mechanical data....167
Table 91. WLCSP90 recommended PCB design rules 168
Table 92. LQFP64 - Mechanical data....170
Table 93. LQFP100 - Mechanical data....173

Table 94. LQFP144 - Mechanical data....176
Table 95. UFBGA(176+25) - Mechanical data 179
Table 96. UFBGA(176+25) - Example of PCB design rules (0.65 mm pitch BGA) ..... 180
Table 97. LQFP176 - Mechanical data....182
Table 98. Package thermal characteristics....185
Table 99. Document revision history .... 193

## List of figures

Figure 1. Compatible board design between STM32F10xx/STM32F40xxx for LQFP64....17

Figure 2. Compatible board design STM32F10xx/STM32F2/STM32F40xxx for LQFP100 package....18

Figure 3. Compatible board design between STM32F10xx/STM32F2/STM32F40xxx for LQFP144 package....18

Figure 4. Compatible board design between STM32F2 and STM32F40xxx for LQFP176 and BGA176 packages 19

Figure 5. STM32F40xxx block diagram....20

Figure 6. Multi-AHB matrix....23

Figure 7. Power supply supervisor interconnection with internal reset OFF .... 27

Figure 8. PDR\_ON and NRST control with internal reset OFF 28

Figure 9. Regulator OFF 29

Figure 10. Startup in regulator OFF mode: slow $V_{DD}$ slope
- power-down reset risen after $V_{CAP}$ 1/ $V_{CAP}$ 2 stabilization ..... 30

Figure 11. Startup in regulator OFF mode: fast $\overline{V}_{DD}$ slope
- power-down reset risen before $V_{CAP\_1}/V_{CAP\_2}$ stabilization ..... 31

Figure 12. STM32F40xxx LQFP64 pinout 43

Figure 13. STM32F40xxx LQFP100 pinout 44

Figure 14. STM32F40xxx LQFP144 pinout 45

Figure 15. STM32F40xxx LQFP176 pinout 46

Figure 16. STM32F40xxx UFBGA176 bailout 47

Figure 17. STM32F40xxx WLCSP90ballout 48

Figure 18. STM32F40xxx memory map....73

Figure 19. Pin loading conditions....78

Figure 20. Pin input voltage 78

Figure 21. Power supply scheme 79

Figure 22. Current consumption measurement scheme .... 80

Figure 23. External capacitor $C_{EXT}$ 84

Figure 24. Typical current consumption versus temperature, Run mode, code with data processing running from flash (ART accelerator ON) or RAM, and peripherals OFF....89

Figure 25. Typical current consumption versus temperature, Run mode, code with data processing running from flash (ART accelerator ON) or RAM, and peripherals ON. . . . . 89

Figure 26. Typical current consumption versus temperature, Run mode, code with data processing running from flash (ART accelerator OFF) or RAM, and peripherals OFF....90

Figure 27. Typical current consumption versus temperature, Run mode, code with data processing running from flash (ART accelerator OFF) or RAM, and peripherals ON....90

Figure 28. Typical $V_{BAT}$ current consumption (LSE and RTC ON/backup RAM OFF) ..... 93

Figure 29. Typical $V_{BAT}$ current consumption (LSE and RTC ON/backup RAM ON) ..... 94

Figure 30. High-speed external clock source AC timing diagram .... 102

Figure 31. Low-speed external clock source AC timing diagram....103

Figure 32. Typical application with an 8 MHz crystal....104

Figure 33. Typical application with a 32.768 kHz crystal....105

Figure 34. ACC $_{LSI}$ versus temperature .... 106

Figure 35. PLL output clock waveforms in center spread mode 109

Figure 36. PLL output clock waveforms in down spread mode 110

Figure 37. I/O AC characteristics definition .... 120

Figure 38. Recommended NRST pin protection 121

Figure 39. SPI timing diagram - slave mode and CPHA = 0 126

Figure 40. SPI timing diagram - slave mode and CPHA = 1 126
Figure 41. SPI timing diagram - master mode 127
Figure 42. I2S slave timing diagram (Philips protocol) 129
Figure 43. I2S master timing diagram (Philips protocol) $^{(1)}$ .... 129
Figure 44. USB OTG FS timings: definition of data signal rise and fall time ..... 131
Figure 45. ULPI timing diagram....132
Figure 46. Ethernet SMI timing diagram 133
Figure 47. Ethernet RMII timing diagram....134
Figure 48. Ethernet MII timing diagram 134
Figure 49. ADC accuracy characteristics....137
Figure 50. Typical connection diagram when using the ADC with FT/TT pins featuring analog switch function 138
Figure 51. Power supply and reference decoupling ( $V_{REF+}$ not connected to $V_{DDA}$ ). 139
Figure 52. Power supply and reference decoupling ( $V_{REF+}$ connected to $V_{DDA}$ ). 140
Figure 53. 12-bit buffered /non-buffered DAC 144
Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms ..... 145
Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms ..... 146
Figure 56. Asynchronous multiplexed PSRAM/NOR read waveforms. 147
Figure 57. Asynchronous multiplexed PSRAM/NOR write waveforms ..... 148
Figure 58. Synchronous multiplexed NOR/PSRAM read timings 149
Figure 59. Synchronous multiplexed PSRAM write timings....151
Figure 60. Synchronous non-multiplexed NOR/PSRAM read timings....152
Figure 61. Synchronous non-multiplexed PSRAM write timings .... 154
Figure 62. PC Card/CompactFlash controller waveforms for common memory read access ..... 155
Figure 63. PC Card/CompactFlash controller waveforms for common memory write access.....156
Figure 64. PC Card/CompactFlash controller waveforms for attribute memory read access. 157
Figure 65. PC Card/CompactFlash controller waveforms for attribute memory write access....158
Figure 66. PC Card/CompactFlash controller waveforms for I/O space read access ..... 158
Figure 67. PC Card/CompactFlash controller waveforms for I/O space write access ..... 159
Figure 68. NAND controller waveforms for read access 161
Figure 69. NAND controller waveforms for write access 161
Figure 70. DCMI timing diagram 162
Figure 71. SDIO high-speed mode 163
Figure 72. SD default mode....164
Figure 73. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package outline. 166
Figure 74. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package recommended footprint 167
Figure 75. WLCSP90 marking example (package top view)....168
Figure 76. LQFP64 - Outline $^{(15)}$ 169
Figure 77. LQFP100 - Outline $^{(15)}$ 172
Figure 78. LQFP100 - Footprint example 174
Figure 79. LQFP144 - Outline $^{(15)}$ 175
Figure 80. LQFP144 - Footprint example 178
Figure 81. UFBGA(176+25) - Outline 179
Figure 82. UFBGA(176+25) - Footprint example....180
Figure 83. LQFP176 - Outline $^{(15)}$ 181
Figure 84. LQFP176 - Footprint example 184
Figure 85. USB controller configured as peripheral-only and used in Full speed mode 187

Figure 86. USB controller configured as host-only and used in full speed mode. 187
Figure 87. USB controller configured in dual mode and used in full speed mode....188
Figure 88. USB controller configured as peripheral, host, or dual-mode and used in high speed mode....189
Figure 89. MII mode using a 25 MHz crystal 190
Figure 90. RMII with a 50 MHz oscillator 190
Figure 91. RMII with a 25 MHz crystal and PHY with PLL....191

## 1 Introduction

This datasheet provides the description of the STM32F405xx and STM32F407xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, refer to Section 2.1: Full compatibility throughout the family.

The STM32F405xx and STM32F407xx datasheet should be read in conjunction with the STM32F4xx reference manual which is available from the STMicroelectronics website www.st.com.

For information on the device errata with respect to the datasheet and reference manual, refer to the STM32F405xx and STM32F407xx errata sheet (ES0182), which is available from the STMicroelectronics website www.st.com.

For information on the Arm $^{\textregistered}$ Cortex $^{\textregistered}$ -M4 core, refer to the Cortex $^{\textregistered}$ -M4 programming manual (PM0214) available from www.st.com.

## arm

Note: Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere.

The Arm word and logo are trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved.

## 2 Description

The STM32F405xx and STM32F407xx family is based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 168 MHz. The Cortex®-M4 core features a floating-point unit (FPU) single precision which supports all Arm single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.

The STM32F405xx and STM32F407xx family incorporates high-speed embedded memories (flash memory up to 1 Mbyte, up to 192 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix.

All devices offer three 12-bit ADCs, two DACs, a low-power RTC, 12 general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. a true random number generator (RNG). They also feature standard and advanced communication interfaces.

- Up to three I²Cs
- Three SPIs, two I²Ss full duplex. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization
• Four USARTs plus two UARTs
- A USB OTG full speed and a USB OTG high speed with full-speed capability (with the ULPI)
- Two CANs
- An SDIO/MMC interface
- Ethernet and the camera interface available on STM32F407xx devices only

New advanced peripherals include an SDIO, an enhanced flexible static memory control (FSMC) interface (for devices offered in packages of 100 pins and more), a camera interface for CMOS sensors. Refer to Table 2: STM32F405xx and STM32F407xx: features and peripheral counts for the list of peripherals available on each part number.

The STM32F405xx and STM32F407xx family operates in the -40 to +105 °C temperature range from a 1.8 to 3.6 V power supply. The supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range using an external power supply supervisor: refer to Section 3.15.2: Internal reset OFF. A comprehensive set of power-saving mode allows the design of low-power applications.

The STM32F405xx and STM32F407xx family offers devices in various packages ranging from 64 pins to 176 pins. The set of included peripherals changes with the device chosen.

These features make the STM32F405xx and STM32F407xx microcontroller family suitable for a wide range of applications:

• Motor drive and application control
• Medical equipment
• Industrial applications: PLC, inverters, circuit breakers
- Printers, and scanners
• Alarm systems, video intercom, and HVAC
• Home audio appliances

Table 2. STM32F405xx and STM32F407xx: features and peripheral counts

<table><tr><td colspan="2">Peripherals</td><td>STM32F405RG</td><td>STM32F405OG</td><td>STM32F405VG</td><td>STM32F405ZG</td><td>STM32F405OE</td><td colspan="2">STM32F407Vx</td><td colspan="2">STM32F407Zx</td><td colspan="2">STM32F407Ix</td></tr><tr><td colspan="2">Flash memory in Kbytes</td><td colspan="4">1024</td><td>512</td><td>512</td><td>1024</td><td>512</td><td>1024</td><td>512</td><td>1024</td></tr><tr><td rowspan="2">SRAM in Kbytes</td><td>System</td><td colspan="11">192(112+16+64)</td></tr><tr><td>Backup</td><td colspan="11">4</td></tr><tr><td colspan="2">FSMC memory controller</td><td>No</td><td colspan="10">Yes(1)</td></tr><tr><td colspan="2">Ethernet</td><td colspan="5">No</td><td colspan="6">Yes</td></tr><tr><td rowspan="6">Timers</td><td>General-purpose</td><td colspan="11">10</td></tr><tr><td>Advanced-control</td><td colspan="11">2</td></tr><tr><td>Basic</td><td colspan="11">2</td></tr><tr><td>IWDG</td><td colspan="11">Yes</td></tr><tr><td>WWDG</td><td colspan="11">Yes</td></tr><tr><td>RTC</td><td colspan="11">Yes</td></tr><tr><td colspan="2">True random number generator</td><td colspan="11">Yes</td></tr></table>

Table 2. STM32F405xx and STM32F407xx: features and peripheral counts (continued)

<table><tr><td colspan="2">Peripherals</td><td>STM32F405RG</td><td>STM32F405OG</td><td>STM32F405VG</td><td>STM32F405ZG</td><td>STM32F405OE</td><td>STM32F407Vx</td><td>STM32F407Zx</td><td>STM32F407Ix</td></tr><tr><td rowspan="7">Communication interfaces</td><td>SPI / I2S</td><td colspan="8">3/2 (full duplex)(2)</td></tr><tr><td>I2C</td><td colspan="8">3</td></tr><tr><td>USART/UART</td><td colspan="8">4/2</td></tr><tr><td>USB OTG FS</td><td colspan="8">Yes</td></tr><tr><td>USB OTG HS</td><td colspan="8">Yes</td></tr><tr><td>CAN</td><td colspan="8">2</td></tr><tr><td>SDIO</td><td colspan="8">Yes</td></tr><tr><td colspan="2">Camera interface</td><td colspan="5">No</td><td colspan="3">Yes</td></tr><tr><td colspan="2">GPIOs</td><td>51</td><td>72</td><td>82</td><td>114</td><td>72</td><td>82</td><td>114</td><td>140</td></tr><tr><td rowspan="2" colspan="2">12-bit ADC Number of channels</td><td colspan="8">3</td></tr><tr><td>16</td><td>13</td><td>16</td><td>24</td><td>13</td><td>16</td><td>24</td><td>24</td></tr><tr><td colspan="2">12-bit DAC Number of channels</td><td colspan="8">Yes2</td></tr><tr><td colspan="2">Maximum CPU frequency</td><td colspan="8">168 MHz</td></tr><tr><td colspan="2">Operating voltage</td><td colspan="8">1.8 to 3.6 V(3)</td></tr><tr><td rowspan="2" colspan="2">Operating temperatures</td><td colspan="8">Ambient temperatures: -40 to +85 °C /-40 to +105 °C</td></tr><tr><td colspan="8">Junction temperature: -40 to +125 °C</td></tr><tr><td colspan="2">Package</td><td>LQFP64</td><td>WLCSP90</td><td>LQFP100</td><td>LQFP144</td><td>WLCSP90</td><td>LQFP100</td><td>LQFP144</td><td>UFBGA176 LQFP176</td></tr></table>

1. For the LQFP100 and WLCSP90 packages, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package.
2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I²S audio mode.
3. $V_{DD}/V_{DDA}$ minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF).

## 2.1 Full compatibility throughout the family

The STM32F405xx and STM32F407xx are part of the STM32F4 family. They are fully pin-to-pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, and performances (FPU, higher frequency) for a greater degree of freedom during the development cycle.

The STM32F405xx and STM32F407xx devices maintain a close compatibility with the whole STM32F10xxx family. All functional pins are pin-to-pin compatible. The STM32F405xx and STM32F407xx, however, are not drop-in replacements for the STM32F10xxx devices: the two families do not have the same power scheme, and so their power pins are different. Nonetheless, transition from the STM32F10xxx to the STM32F40xxx family remains simple as only a few pins are impacted.

Figure 4, Figure 3, Figure 2, and Figure 1 give compatible board designs between the STM32F40xxx, STM32F2, and STM32F10xxx families.

Figure 1. Compatible board design between STM32F10xx/STM32F40xxx for LQFP64
![](images/c079baaf8a430ec866ce3659dda5a3e5885f21a4171a0da32ea610b74104ceee.jpg)

<details>
<summary>text_image</summary>

48
47
33
32
31
64
1
17
16
0 Ω resistor or soldering
present for the STM32F1
configuration, not present
STM32F4xx configuration
VSS
VSS
VSS
</details>

ai18489

Figure 2. Compatible board design STM32F10xx/STM32F2/STM32F40xxx for LQFP100 package
![](images/28e1d4add5ee391901a1601992ea4ad1073de09d20eeb7caee3fd5e833bc0ed2.jpg)

<details>
<summary>text_image</summary>

76
75
51
50
49
99 (VSS)
100
1
19
20
25
26
VSS
VSS
VSS
VSS
0 Ω resistor or soldering bridge
present for the STM32F10xxx
configuration, not present in the
STM32F4xx configuration
Two 0 Ω resistors connected to:
- VSS for the STM32F10xx
- VSS for the STM32F4xx
- VSS or NC for the STM32F2xx
VSS for STM32F10xx
VDD for STM32F4xx
ai18488d
</details>

Figure 3. Compatible board design between STM32F10xx/STM32F2/STM32F40xxx for LQFP144 package
![](images/a84766d35813d32e87aff6b1bceddf17a2e9224771fbb042247e75a7d119b9e4.jpg)

<details>
<summary>text_image</summary>

0 Ω resistor or soldering bridge present for the STM32F10xx configuration, not present in the STM32F4xx configuration
73
108
106
72
109
71
VSS
VSS
VSS
VSS
Signal from external power supply supervisor
143 (PDR_ON)
1
30 31 36
37
VDD VSS
Two 0 Ω resistors connected to:
- VSS for the STM32F10xx
- VSS, VDD or NC for the STM32F2xx
- VDD or signal from external power supply supervisor for the STM32F4xx
VSS
VSS for STM32F10xx
VDD for STM32F4xx
ai18487d
</details>

Figure 4. Compatible board design between STM32F2 and STM32F40xxx for LQFP176 and BGA176 packages
![](images/e3619521a4c2bca1a32dd951d04d94d9b50d51bcfd258f0926b95db6950dfeac.jpg)

<details>
<summary>text_image</summary>

Signal from external
power supply
supervisor
171 (PDR_ON)
176
133
132
89
88
45
1
44
VDD VSS
</details>

Two 0 Ω resistors connected to:
- $V_{SS}$ , $V_{DD}$ or NC for the STM32F2xx
- $V_{DD}$ or signal from external power supply supervisor for the STM32F4xx

MS19919V3

## 3 Functional overview

Figure 5. STM32F40xxx block diagram
![](images/35db44eb1409a690b34b525e961684f9e407ce74a72ceb76854df371ae45d395.jpg)

<details>
<summary>flowchart</summary>

This image displays a system architecture diagram for a 8800 microcontroller (likely an 8800 microcontroller), showing the data flow from input/output to external memory, hardware components, and control signals.
</details>

1. The camera interface and ethernet are available only on STM32F407xx devices.

## 3.1 Arm® Cortex®-M4 core with FPU and embedded flash and SRAM

The Arm Cortex-M4 processor with FPU is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The Arm Cortex-M4 32-bit RISC processor with FPU features exceptional code-efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.

Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation.

The STM32F405xx and STM32F407xx family is compatible with all Arm tools and software.

Figure 5 shows the general block diagram of the STM32F40xxx family.

Note: Cortex-M4 with FPU is binary compatible with Cortex-M3.

## 3.2 Adaptive real-time memory accelerator (ART Accelerator)

The ART Accelerator is a memory accelerator which is optimized for STM32 industry-standard Arm® Cortex®-M4 with FPU processors. It balances the inherent performance advantage of the Arm Cortex-M4 with FPU over flash memory technologies, which normally requires the processor to wait for the flash memory at higher frequencies.

To release the processor full 210 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from flash memory at a CPU frequency up to 168 MHz.

## 3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

## 3.4 Embedded flash memory

The STM32F40xxx devices embed a flash memory of 512 Kbytes or 1 Mbytes available for storing programs and data, plus 512 bytes of OTP memory.

## 3.5 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location.

## 3.6 Embedded SRAM

All STM32F40xxx products embed:

- Up to 192 Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory) data RAM
RAM memory is accessed (read/write) at CPU clock speed with 0 wait states.
• 4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode.

## 3.7 Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS) and the slaves (flash memory, RAM, FSMC, AHB, and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.

Figure 6. Multi-AHB matrix
![](images/7253c5e95cd8d6e6e913ee6e48486d07666ccfc30ee60af8bc095ce702e0d05e.jpg)

<details>
<summary>flowchart</summary>

This diagram illustrates the architecture and data flow of a bus matrix (Bus matrix-S) architecture, showing connections between RAM, ARM, GP, MAC, and USB components with associated memory addresses.
</details>

## 3.8 DMA controller (DMA)

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB).

The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code.

Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals:

- SPI and I²S
• $I^{2}C$
- USART
- General-purpose, basic and advanced-control timers TIMx
• DAC
• SDIO
• Camera interface (DCMI)
- ADC.

## 3.9 Flexible static memory controller (FSMC)

The FSMC is embedded in the STM32F405xx and STM32F407xx family. It has four Chip Select outputs supporting the following modes: PCCard/CompactFlash, SRAM, PSRAM, NOR flash and NAND flash.

Functionality overview:

- Write FIFO
• Maximum FSMC\_CLK frequency for synchronous accesses is 60 MHz.

## 3.9.1 LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-effective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration.

## 3.10 Nested vectored interrupt controller (NVIC)

The STM32F405xx and STM32F407xx embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 82 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M4 with FPU core.

• Closely coupled NVIC gives low-latency interrupt processing
- Interrupt entry vector table address passed directly to the core
- Allows early processing of interrupts
- Processing of late arriving, higher-priority interrupts
- Support tail chaining
- Processor state automatically saved
- Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt latency.

## 3.11 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected to the 16 external interrupt lines.

## 3.12 Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full temperature range. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 168 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails).

Several prescalers allow the configuration of the three AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB buses is 168 MHz while the maximum frequency of the high-speed APB domains is 84 MHz. The maximum allowed frequency of the low-speed APB domain is 42 MHz.

The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class performance. In this case, the I²S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz.

## 3.13 Boot modes

At startup, boot pins are used to select one out of three boot options:

- Boot from user flash
- Boot from system memory
- Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the flash memory by using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade).

## 3.14 Power supply schemes

- $V_{DD} = 1.8$ to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through $V_{DD}$ pins.
- $V_{SSA}$ , $V_{DDA} = 1.8$ to $3.6$ V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. $V_{DDA}$ and $V_{SSA}$ must be connected to $V_{DD}$ and $V_{SS}$ , respectively.
- $V_{BAT} = 1.65$ to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when $V_{DD}$ is not present.

Refer to Figure 21: Power supply scheme for more details.

Note: $V_{DD}/V_{DDA}$ minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF).

Refer to Table 2 in order to identify the packages supporting this option.

## 3.15 Power supply supervisor

## 3.15.1 Internal reset ON

On packages embedding the PDR\_ON pin, the power supply supervisor is enabled by holding PDR\_ON high. On all other packages, the power supply supervisor is always enabled.

The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR threshold levels, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when $V_{DD}$ is below a specified threshold, $V_{POR/PDR}$ or $V_{BOR}$ , without the need for an external reset circuit.

The device also features an embedded programmable voltage detector (PVD) that monitors the $V_{DD}/V_{DDA}$ power supply and compares it to the $V_{PVD}$ threshold. An interrupt can be generated when $V_{DD}/V_{DDA}$ drops below the $V_{PVD}$ threshold and/or when $V_{DD}/V_{DDA}$ is higher than the $V_{PVD}$ threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

## 3.15.2 Internal reset OFF

This feature is available only on packages featuring the PDR\_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled with the PDR\_ON pin.

An external power supply supervisor should monitor $V_{DD}$ and should maintain the device in reset mode as long as $V_{DD}$ is below a specified threshold. PDR\_ON should be connected to this external power supply supervisor. Refer to Figure 7: Power supply supervisor interconnection with internal reset OFF.

Figure 7. Power supply supervisor interconnection with internal reset OFF
![](images/8955e754e005daad8c757bda6f3379fb8080c3752a8b035ae960889479eb14d8.jpg)

<details>
<summary>text_image</summary>

VDD
External VDD power supply supervisor
Ext. reset controller active when
VDD < 1.7 V
NRST
Application reset
signal
VDD
PDR_ON
VSS
</details>

MS31383V4

1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range.

The $V_{DD}$ specified threshold, below which the device must be maintained under reset, is 1.8 V (see Figure 7). This supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range.

A comprehensive set of power-saving mode allows to design low-power applications.

When the internal reset is OFF, the following integrated features are no more supported:

- The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
• The brownout reset (BOR) circuitry is disabled
• The embedded programmable voltage detector (PVD) is disabled
- $V_{BAT}$ functionality is no more available and $V_{BAT}$ pin should be connected to $V_{DD}$

All packages, except for the LQFP64 and LQFP100, allow to disable the internal reset through the PDR\_ON signal.

Figure 8. PDR\_ON and NRST control with internal reset OFF
![](images/edc8f27f1520c6f04d89ae4da5271445a0757c7bed4b5319148b5f6f493729b4.jpg)

<details>
<summary>area</summary>

| Time Phase | VDD (V) | NRST (V) |
| --- | --- | --- |
| Start | 0 | 0 |
| PDR_ON | 1.7 | 0 |
| Reset | 1.7 | 0 |
| Peak | 1.7 | ~0.8 |
| Reset | 1.7 | 0 |
| Peak | 1.7 | ~0.8 |
| Reset | 1.7 | 0 |
| PDR_ON | 1.7 | 0 |
</details>

1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range.

## 3.16 Voltage regulator

The regulator has four operating modes:

\- Regulator ON

\- Main regulator mode (MR)

– Low-power regulator (LPR)

\- Power-down

\- Regulator OFF

## 3.16.1 Regulator ON

On packages embedding the BYPASS\_REG pin, the regulator is enabled by holding BYPASS\_REG low. On all other packages, the regulator is always enabled.

There are three power modes configured by software when regulator is ON:

- MR is used in the nominal regulation mode (With different voltage scaling in Run) In Main regulator mode (MR mode), different voltage scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. Refer to Table 14: General operating conditions.

• LPR is used in the Stop modes
The LP regulator mode is configured by software when entering Stop mode.

• Power-down is used in Standby mode.

The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost)

Two external ceramic capacitors should be connected on $V_{CAP\_1}$ & $V_{CAP\_2}$ pin. Refer to Figure 21: Power supply scheme and Figure 16: VCAP\_1/VCAP\_2 operating conditions.

All packages have regulator ON feature.

## 3.16.2 Regulator OFF

This feature is available only on packages featuring the BYPASS\_REG pin. The regulator is disabled by holding BYPASS\_REG high. The regulator OFF mode allows to supply externally a $V_{12}$ voltage source through $V_{CAP\_1}$ and $V_{CAP\_2}$ pins.

Since the internal voltage scaling is not manage internally, the external voltage value must be aligned with the targeted maximum frequency. Refer to Table 14: General operating conditions.

The two 2.2 $\mu$ F ceramic capacitors should be replaced by two 100 nF decoupling capacitors.

Refer to Figure 21: Power supply scheme

When the regulator is OFF, there is no more internal monitoring on $V_{12}$ . An external power supply supervisor should be used to monitor the $V_{12}$ of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on $V_{12}$ power domain.

In regulator OFF mode the following features are no more supported:

- PA0 cannot be used as a GPIO pin since it allows to reset a part of the $V_{12}$ logic power domain which is not reset by the NRST pin.
- As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required.
• The standby mode is not available

Figure 9. Regulator OFF
![](images/d23ab62c99bf20cf4306e05a9f923ce2bf9a57b73ae2c4d0a3d2127b2e263791.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph LR
  A["External VCAP_1/2 power supply supervisor\nExt. reset controller active when VCAP_1/2 < Min V12"] --> B["PAO"]
  A --> C["NRST"]
  B --> D["BYPASS_REG"]
  B --> E["VCCAP1\nVCCAP2"]
  D --> F["VDD\n1/2/...N"]
  E --> G["VSS\n1/2/...N"]
  F --> H["N x 100 nF\n+ 1 x 4.7 μF"]
  G --> H
  H --> I["(note 1)\n(1 x 100 nF)\n2 x 100 nF"]
```
</details>

The following conditions must be respected:

- $V_{DD}$ should always be higher than $V_{CAP\_1}$ and $V_{CAP\_2}$ to avoid current injection between power domains.
- If the time for $V_{CAP\_1}$ and $V_{CAP\_2}$ to reach $V_{12}$ minimum value is faster than the time for $V_{DD}$ to reach 1.8 V, then PA0 should be kept low to cover both conditions: until $V_{CAP\_1}$ and $V_{CAP\_2}$ reach $V_{12}$ minimum value and until $V_{DD}$ reaches 1.8 V (see Figure 10).
- Otherwise, if the time for $V_{CAP\_1}$ and $V_{CAP\_2}$ to reach $V_{12}$ minimum value is slower than the time for $V_{DD}$ to reach 1.8 V, then PA0 could be asserted low externally (see Figure 11).
- If $V_{CAP\_1}$ and $V_{CAP\_2}$ go below $V_{12}$ minimum value and $V_{DD}$ is higher than 1.8 V, then a reset must be asserted on PA0 pin.

Note: The minimum value of $V_{12}$ depends on the maximum frequency targeted in the application (see Table 14: General operating conditions).

Figure 10. Startup in regulator OFF mode: slow $V_{DD}$ slope - power-down reset risen after $V_{CAP\ 1}/V_{CAP\ 2}$ stabilization
![](images/5eb87cd7d0ca9c99a541801975c2ee8d5f46e73b6445298566d66fb5741cbb55.jpg)

<details>
<summary>line</summary>

| Time Event | VDD (V) | VCAP_1/VCAP_2 (V) | NRST (V) |
| --- | --- | --- | --- |
| Initial Rise | ~0.5 | ~0.5 | 0 |
| PDR Threshold | 1.7 | 1.8 | 0 |
| V12 Level | 1.8 | 1.2 | ~0.5 |
| Min V12 Level | 1.8 | 1.2 | ~0.5 |
| Final Drop | 1.8 | ~0.5 | 0 |
</details>

1. This figure is valid both whatever the internal reset mode (ON or OFF).
2. PDR = 1.7 V for reduced temperature range; PDR = 1.8 V for all temperature ranges.

Figure 11. Startup in regulator OFF mode: fast $V_{DD}$ slope - power-down reset risen before $V_{CAP 1}/V_{CAP 2}$ stabilization
![](images/d4815b1d6469bc748a892dcc4c3e56b258d282c81660be14fed92f7efbe857ed.jpg)

<details>
<summary>line</summary>

| Time Phase | VDD (V) | VCAP_1/VCAP_2 (V) | NRST (V) | PA0 asserted externally (V) |
| --- | --- | --- | --- | --- |
| Initial Rise | ~0 | ~0 | 0 | 0 |
| PDR Point | ~1.7 | ~0.5 | 0 | 0 |
| Mid Rise | ~1.8 | ~0.8 | 0 | 0 |
| PDR Point | ~1.8 | ~1.2 | 0 | 0 |
| Mid Plateau | ~1.8 | ~1.2 | 0 | 0 |
| PDR Point | ~1.8 | ~1.2 | 0 | 0 |
| End Plateau | ~1.8 | ~1.2 | 0 | 0 |
| PDR Point | ~1.8 | ~0.8 | 0 | 0 |
| End Plateau | ~1.8 | ~0.5 | 0 | 0 |
</details>

1. This figure is valid both whatever the internal reset mode (ON or OFF).
2. PDR = 1.7 V for a reduced temperature range; PDR = 1.8 V for all temperature ranges.

## 3.17 Regulator ON/OFF and internal reset ON/OFF availability

Table 3. Regulator ON/OFF and internal reset ON/OFF availability

<table><tr><td></td><td>Regulator ON</td><td>Regulator OFF</td><td>Internal reset ON</td><td>Internal reset OFF</td></tr><tr><td>LQFP64LQFP100</td><td rowspan="2">Yes</td><td rowspan="2">No</td><td>Yes</td><td>No</td></tr><tr><td>LQFP144</td><td rowspan="2">YesPDR_ON set to $V_{DD}$ </td><td rowspan="2">YesPDR_ON connected to an external power supply supervisor</td></tr><tr><td>WLCSP90UFBGA176LQFP176</td><td>YesBYPASS_REG set to  $V_{SS}$ </td><td>YesBYPASS_REG set to  $V_{DD}$ </td></tr></table>

## 3.18 Real-time clock (RTC), backup SRAM and backup registers

The backup domain of the STM32F405xx and STM32F407xx includes:

• The real-time clock (RTC)
• 4 Kbytes of backup SRAM
- 20 backup registers

The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format.

It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 2 to 31. The internal low-speed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation.

Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 $\mu$ s to every 36 hours.

A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.

The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data which need to be retained in $V_{BAT}$ and standby mode. This memory area is disabled by default to minimize power consumption (see Section 3.19: Low-power modes). It can be enabled by software.

The backup registers are 32-bit registers used to store 80 bytes of user application data when $V_{DD}$ power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 3.19: Low-power modes).

Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date.

Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the $V_{DD}$ supply when present or from the $V_{BAT}$ pin.

## 3.19 Low-power modes

The STM32F405xx and STM32F407xx support three low-power modes to achieve the best compromise between low-power consumption, short startup time and available wakeup sources:

## - Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

## - Stop mode

The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the $V_{12}$ domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode.

The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup).

## - Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire $V_{12}$ domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected.

The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs.

The standby mode is not supported when the embedded voltage regulator is bypassed and the $V_{12}$ domain is controlled by an external power.

## 3.20 $V_{BAT}$ operation

The $V_{BAT}$ pin allows to power the device $V_{BAT}$ domain from an external battery, an external supercapacitor, or from $V_{DD}$ when no external battery and an external supercapacitor are present.

$V_{BAT}$ operation is activated when $V_{DD}$ is not present.

The $V_{BAT}$ pin supplies the RTC, the backup registers and the backup SRAM.

Note: When the microcontroller is supplied from $V_{BAT}$ , external interrupts and RTC alarm/events do not exit it from $V_{BAT}$ operation.

When PDR\_ON pin is not connected to $V_{DD}$ (internal reset OFF), the $V_{BAT}$ functionality is no more available and $V_{BAT}$ pin should be connected to $V_{DD}$ .

## 3.21 Timers and watchdogs

The STM32F405xx and STM32F407xx devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers.

All timer counters can be frozen in debug mode.

Table 4 compares the features of the advanced-control, general-purpose and basic timers.

Table 4. Timer feature comparison

<table><tr><td>Timer type</td><td>Timer</td><td>Counter resolution</td><td>Counter type</td><td>Prescaler factor</td><td>DMA request generation</td><td>Capture/compare channels</td><td>Complementary output</td><td>Max interface clock (MHz)</td><td>Max timer clock (MHz)</td></tr><tr><td>Advanced -control</td><td>TIM1, TIM8</td><td>16-bit</td><td>Up, Down, Up/down</td><td>Any integer between 1 and 65536</td><td>Yes</td><td>4</td><td>Yes</td><td>84</td><td>168</td></tr><tr><td rowspan="6">General purpose</td><td>TIM2, TIM5</td><td>32-bit</td><td>Up, Down, Up/down</td><td>Any integer between 1 and 65536</td><td>Yes</td><td>4</td><td>No</td><td>42</td><td>84</td></tr><tr><td>TIM3, TIM4</td><td>16-bit</td><td>Up, Down, Up/down</td><td>Any integer between 1 and 65536</td><td>Yes</td><td>4</td><td>No</td><td>42</td><td>84</td></tr><tr><td>TIM9</td><td>16-bit</td><td>Up</td><td>Any integer between 1 and 65536</td><td>No</td><td>2</td><td>No</td><td>84</td><td>168</td></tr><tr><td>TIM10, TIM11</td><td>16-bit</td><td>Up</td><td>Any integer between 1 and 65536</td><td>No</td><td>1</td><td>No</td><td>84</td><td>168</td></tr><tr><td>TIM12</td><td>16-bit</td><td>Up</td><td>Any integer between 1 and 65536</td><td>No</td><td>2</td><td>No</td><td>42</td><td>84</td></tr><tr><td>TIM13, TIM14</td><td>16-bit</td><td>Up</td><td>Any integer between 1 and 65536</td><td>No</td><td>1</td><td>No</td><td>42</td><td>84</td></tr><tr><td>Basic</td><td>TIM6, TIM7</td><td>16-bit</td><td>Up</td><td>Any integer between 1 and 65536</td><td>Yes</td><td>0</td><td>No</td><td>42</td><td>84</td></tr></table>

## 3.21.1 Advanced-control timers (TIM1, TIM8)

The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for:

- Input capture
- Output compare
• PWM generation (edge- or center-aligned modes)
• One-pulse mode output

If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-100%).

The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

TIM1 and TIM8 support independent DMA request generation.

## 3.21.2 General-purpose timers (TIMx)

There are ten synchronizable general-purpose timers embedded in the STM32F40xxx devices (see Table 4 for differences).

## - TIM2, TIM3, TIM4, TIM5

The STM32F40xxx include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4. The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages.

The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining.

Any of these general-purpose timers can be used to generate PWM outputs.

TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors.

## • TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases.

## 3.21.3 Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base.

TIM6 and TIM7 support independent DMA request generation.

## Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes.

## Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

## SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features:

• A 24-bit downcounter
- Autoreload capability
- Maskable system interrupt generation when the counter reaches 0
- Programmable clock source.

## 3.22 Inter-integrated circuit interface (I²C)

Up to three I²C bus interfaces can operate in multimaster and slave modes. They can support the Standard-mode (up to 100 kHz) and Fast-mode (up to 400 kHz). They support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SMBus 2.0/PMBus.

## 3.23 Universal synchronous/asynchronous receiver transmitters (USART)

The STM32F405xx and STM32F407xx embed four universal synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and USART6) and two universal asynchronous receiver transmitters (UART4 and UART5).

These six interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to communicate at speeds of up to 10.5 Mbit/s. The other available interfaces communicate at up to 5.25 Mbit/s.

USART1, USART2, USART3 and USART6 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller.

Table 5. USART feature comparison

<table><tr><td>USART name</td><td>Standard features</td><td>Modem (RTS/CTS)</td><td>LIN</td><td>SPI master</td><td>irDA</td><td>Smartcard (ISO 7816)</td><td>Max. baud rate in Mbit/s (oversampling by 16)</td><td>Max. baud rate in Mbit/s (oversampling by 8)</td><td>APB mapping</td></tr><tr><td>USART1</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>5.25</td><td>10.5</td><td>APB2 (max. 84 MHz)</td></tr><tr><td>USART2</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>2.62</td><td>5.25</td><td>APB1 (max. 42 MHz)</td></tr><tr><td>USART3</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>2.62</td><td>5.25</td><td>APB1 (max. 42 MHz)</td></tr><tr><td>UART4</td><td>X</td><td>-</td><td>X</td><td>-</td><td>X</td><td>-</td><td>2.62</td><td>5.25</td><td>APB1 (max. 42 MHz)</td></tr><tr><td>UART5</td><td>X</td><td>-</td><td>X</td><td>-</td><td>X</td><td>-</td><td>2.62</td><td>5.25</td><td>APB1 (max. 42 MHz)</td></tr><tr><td>USART6</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>X</td><td>5.25</td><td>10.5</td><td>APB2 (max. 84 MHz)</td></tr></table>

## 3.24 Serial peripheral interface (SPI)

The STM32F40xxx feature up to three SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1 can communicate at up to 42 Mbits/s, SPI2 and SPI3 can communicate at up to 21 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller.

The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode.

## 3.25 Inter-integrated sound (I²S)

Two standard I $^{2}$ S interfaces (multiplexed with SPI2 and SPI3) are available. They can be operated in master or slave mode, in full duplex and half-duplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel.

Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I²S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency.

All I $^{2}$ Sx can be served by the DMA controller.

## 3.26 Audio PLL (PLLI2S)

The devices feature an additional dedicated PLL for audio I $^{2}$ S application. It allows to achieve error-free I $^{2}$ S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals.

The PLLI2S configuration can be modified to manage an I²S sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.

The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz.

In addition to the audio PLL, a master clock input pin can be used to synchronize the I²S flow with an external PLL (or Codec output).

## 3.27 Secure digital input/output interface (SDIO)

An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.

The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory Card Specification Version 2.0.

The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit.

The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous.

In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1.

## 3.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support

Peripheral available only on the STM32F407xx devices.

The STM32F407xx devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard medium-independent interface (MII) or a reduced medium-independent interface (RMII). The STM32F407xx requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F407xx MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the STM32F407xx.

The STM32F407xx includes the following features:

• Supports 10 and 100 Mbit/s rates
- Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F40xxx/41xxx reference manual for details)
• Tagged MAC frame support (VLAN support)
• Half-duplex (CSMA/CD) and full-duplex operation
• MAC control sublayer (control frames) support
• 32-bit CRC generation and removal
- Several address filtering modes for physical and multicast address (multicast and group addresses)
• 32-bit status code for each transmitted or received frame
- Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes.
- Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input
- Triggers interrupt when system time becomes greater than target time

## 3.29 Controller area network (bxCAN)

The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated for each CAN.

## 3.30 Universal serial bus on-the-go full-speed (OTG\_FS)

The STM32F405xx and STM32F407xx embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are:

• Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 4 bidirectional endpoints
• 8 host channels with periodic OUT support
• HNP/SNP/IP inside (no need for any external resistor)
- For OTG/Host modes, a power switch is needed in case bus-powered devices are connected

## 3.31 Universal serial bus on-the-go high-speed (OTG\_HS)

The STM32F405xx and STM32F407xx devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required.

The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator.

The major features are:

• Combined Rx and Tx FIFO size of 1 Kbit × 35 with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 6 bidirectional endpoints
• 12 host channels with periodic OUT support
• Internal FS OTG PHY support
- External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output.
- Internal USB DMA
• HNP/SNP/IP inside (no need for any external resistor)
- for OTG/Host modes, a power switch is needed in case bus-powered devices are connected

## 3.32 Digital camera interface (DCMI)

The camera interface is not available in STM32F405xx devices.

STM32F407xx products embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features:

- Programmable polarity for the input pixel clock and synchronization signals
• Parallel data communication can be 8-, 10-, 12- or 14-bit
- Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG)
• Supports continuous mode or snapshot (a single frame) mode
• Capability to automatically crop the image

## 3.33 True random number generator (RNG)

All STM32F405xx and STM32F407xx products embed a true random number generator (RNG) that provides full entropy outputs to the application as 32-bit samples. It is composed of a live entropy source (analog) and an internal conditioning component.

## 3.34 General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission.

The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers.

Fast I/O handling allowing maximum I/O toggling up to 84 MHz.

## 3.35 Analog-to-digital converters (ADCs)

Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

• Simultaneous sample and hold
• Interleaved sample and hold

The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM5, or TIM8 timer.

## 3.36 Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.8 V and 3.6 V. The temperature sensor is internally connected to the ADC1\_IN16 input channel which is used to convert the sensor output voltage into a digital value.

As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used.

## 3.37 Digital-to-analog converter (DAC)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs.

This dual digital Interface supports the following features:

- two DAC converters: one for each output channel
• 8-bit or 12-bit monotonic output
• left or right data alignment in 12-bit mode
• synchronized update capability
- noise-wave generation
• triangular-wave generation
- dual DAC channel independent or simultaneous conversions
• DMA capability for each channel
• external triggers for conversion
• input voltage reference $V_{REF+}$

Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams.

## 3.38 Serial wire JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

## 3.39 Embedded Trace Macrocell™

The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F40xxx through a small number of ETM pins to an external hardware trace port analyser (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors.

The Embedded Trace Macrocell operates with third party debugger software tools.

## 4 Pinouts and pin description

Figure 12. STM32F40xxx LQFP64 pinout
![](images/cb60f58589f87bc37596a5877dae20bc20e55573e95e98cc92193b13546ebd6b.jpg)

<details>
<summary>text_image</summary>

VDD VSS PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VBAT 1 48 VDD
PC13 2 47 VCAP_2
PC14 3 46 PA13
PC15 4 45 PA12
PH0 5 44 PA11
PH1 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA 12 37 PC6
VDDA 13 36 PB15
PA0_WKUP 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VDD
LQFP64
ai18493b
</details>

1. The above figure shows the package top view.

Figure 13. STM32F40xxx LQFP100 pinout
![](images/3fbf8439f266fb0fbc644bb0f0a547937fa4584df3d6c6509d1a6912cd4ec564.jpg)

<details>
<summary>text_image</summary>

VDD
VSS
PE1
PE0
PB9
PB8
BOOT0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2
1
75
VDD
PE3
2
74
VSS
PE4
3
73
VCAP_2
PE5
4
72
PA13
PE6
5
71
PA12
VBAT
6
70
PA 11
PC13
7
69
PA10
PC14
8
68
PA9
PC15
9
67
PA8
VSS
10
66
PC9
VDD
11
65
PC8
PH0
12
64
PC7
PH1
13
63
PC6
NRST
14
62
PD15
PC0
15
61
PD14
PC1
16
60
PD13
PC2
17
59
PD12
PC3
18
58
PD11
VDD
19
57
PD10
VSSA
20
56
PD9
VREF+
21
55
PD8
VDDA
22
54
PB15
PA0
23
53
PB14
PA1
24
52
PB13
PA2
25
PA3
26
VSS
27
VDD
28
PA4
29
PA5
30
PA6
31
PA7
32
PC4
33
PC5
34
PB0
35
PB1
36
PB2
37
PE7
38
PE8
39
PE9
40
PE10
41
PE11
42
PE12
43
PE13
44
PE14
45
PE15
46
PB10
47
PB11
48
VCAP_1
VDD
50
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
ai18495c
</details>

1. The above figure shows the package top view.

Figure 14. STM32F40xxx LQFP144 pinout
![](images/58ca4a2f5aa485299fa8314bf5909368c100045e2151ac4d1a9ef81a4c28bff3.jpg)

<details>
<summary>wireframe</summary>

| Pin Number | Function |
| --- | --- |
| 1 | VDD |
| 2 | PDR_ON |
| 3 | PE2 |
| 4 | PE3 |
| 5 | PE4 |
| 6 | PE5 |
| 7 | PE6 |
| 8 | VBAT |
| 9 | PC13 |
| 10 | PC14 |
| 11 | PC15 |
| 12 | PF0 |
| 13 | PF1 |
| 14 | PF2 |
| 15 | PF3 |
| 16 | PF4 |
| 17 | PF5 |
| 18 | VSS |
| 19 | VDD |
| 20 | PF6 |
| 21 | PF7 |
| 22 | PF8 |
| 23 | PF9 |
| 24 | PF10 |
| 25 | PH0 |
| 26 | PH1 |
| 27 | NRST |
| 28 | PC0 |
| 29 | PC1 |
| 30 | PC2 |
| 31 | PC3 |
| 32 | VDD |
| 33 | VSSA |
| 34 | VREF+ |
| 35 | VDDA |
| 36 | PA0 |
| 37 | PA1 |
| 38 | PA2 |
| 39 | PA3 |
| 40 | VSS |
| 41 | VDD |
| 42 | PA4 |
| 43 | PA5 |
| 44 | PA6 |
| 45 | PA7 |
| 46 | PC4 |
| 47 | PC5 |
| 48 | PB0 |
| 49 | PB1 |
| 50 | PB2 |
| 51 | PF11 |
| 52 | PF12 |
| 53 | PF13 |
| 54 | PF14 |
| 55 | PF15 |
| 56 | PG0 |
| 57 | PG1 |
| 58 | PE7 |
| 59 | PE8 |
| 60 | PE9 |
| 61 | VSS |
| 62 | VDD |
| 63 | PE10 |
| 64 | PE11 |
| 65 | PE12 |
| 66 | PE13 |
| 67 | PE14 |
| 68 | PE15 |
| 69 | PB10 |
| 70 | PB11 |
| 71 | VCAP_1 |
| 72 | VDD |
</details>

1. The above figure shows the package top view.

Figure 15. STM32F40xxx LQFP176 pinout
![](images/6448fa208433ef9033c5f1724372f47da6ec46ed28aa6e34a297ef6e8b314db6.jpg)

<details>
<summary>text_image</summary>

176 PI7
175 PI6
174 PI5
173 PI4
172 VDD
171 PDR_ON
170 PE1
169 PE0
168 PB9
167 PB8
166 BOOT0
165 PB7
164 PB6
163 PB5
162 PB4
161 PB3
160 PG15
159 VDD
158 VSS
157 PG14
156 PG13
155 PG12
154 PG11
153 PG10
152 PG9
151 PD7
150 PD6
149 VDD
148 VSS
147 PD5
146 PD4
145 PD3
144 PD2
143 PD1
142 PD0
141 PC12
140 PC11
139 PC10
138 PA15
137 PA14
136 VDD
135 VSS
134 PI3
133 PI2
PE2 1
PE3 2
PE4 3
PE5 4
PE6 5
VBAT 6
PI8 7
PC13 8
PC14 9
PC15 10
PI9 11
PI10 12
PI11 13
VSS 14
VDD 15
PF0 16
PF1 17
PF2 18
PF3 19
PF4 20
PF5 21
VSS 22
VDD 23
PF6 24
PF7 25
PF8 26
PF9 27
PF10 28
PH0 29
PH1 30
NRST 31
PC0 32
PC1 33
PC2 34
PC3 35
VDD 36
VSSA 37
VREF+ 38
VDDA 39
PA0 40
PA1 41
PA2 42
PH2 43
PH3 44
PH4 45
PH5 46
PA3 47
BYPASS_REG 48
VDD 49
PA4 50
PA5 51
PA6 52
PA7 53
PC4 54
PC5 55
PB0 56
PB1 57
PB2 58
PF11 59
PF12 60
VSS 61
VDD 62
PF13 63
PF14 64
PF15 65
PG0 66
PG1 67
PE7 68
PE8 69
PE9 70
VSS 71
VDD 72
PE10 73
PE11 74
PE12 75
PE13 76
PE14 77
PE15 78
PB10 79
PB11 80
VCAP-1 81
VDD 82
PH6 83
PH7 84
PH8 85
PH9 86
PH10 87
PH11 88
LQFP176
132 PI1
131 PI0
130 PH15
129 PH14
128 PH13
127 VDD
126 VSS
125 VCAP_2
124 PA13
123 PA12
122 PA11
121 PA10
120 PA9
119 PA8
118 PC9
117 PC8
116 PC7
115 PC6
114 VDD
113 VSS
112 PG8
111 PG7
110 PG6
109 PG5
108 PG4
107 PG3
106 PG2
105 PD15
104 PD14
103 VDD
102 VSS
101 PD13
100 PD12
99 PD11
98 PD10
97 PD9
96 PD8
95 PB15
94 PB14
93 PB13
92 PB12
91 VDD
90 VSS
89 PH12
MS19916V4
</details>

1. The above figure shows the package top view.

Figure 16. STM32F40xxx UFBGA176 bailout

<table><tr><td></td><td>1</td><td>2</td><td>3</td><td>4</td><td>5</td><td>6</td><td>7</td><td>8</td><td>9</td><td>10</td><td>11</td><td>12</td><td>13</td><td>14</td><td>15</td></tr><tr><td>A</td><td>PE3</td><td>PE2</td><td>PE1</td><td>PE0</td><td>PB8</td><td>PB5</td><td>PG14</td><td>PG13</td><td>PB4</td><td>PB3</td><td>PD7</td><td>PC12</td><td>PA15</td><td>PA14</td><td>PA13</td></tr><tr><td>B</td><td>PE4</td><td>PE5</td><td>PE6</td><td>PB9</td><td>PB7</td><td>PB6</td><td>PG15</td><td>PG12</td><td>PG11</td><td>PG10</td><td>PD6</td><td>PD0</td><td>PC11</td><td>PC10</td><td>PA12</td></tr><tr><td>C</td><td>VBAT</td><td>PI7</td><td>PI6</td><td>PI5</td><td>VDD</td><td>PDR_ON</td><td>VDD</td><td>VDD</td><td>VDD</td><td>PG9</td><td>PD5</td><td>PD1</td><td>PI3</td><td>PI2</td><td>PA11</td></tr><tr><td>D</td><td>PC13</td><td>PI8</td><td>PI9</td><td>PI4</td><td>VSS</td><td>BOOT0</td><td>VSS</td><td>VSS</td><td>VSS</td><td>PD4</td><td>PD3</td><td>PD2</td><td>PH15</td><td>PI1</td><td>PA10</td></tr><tr><td>E</td><td>PC14</td><td>PF0</td><td>PI10</td><td>PI11</td><td rowspan="7" colspan="7"></td><td>PH13</td><td>PH14</td><td>PI0</td><td>PA9</td></tr><tr><td>F</td><td>PC15</td><td>VSS</td><td>VDD</td><td>PH2</td><td>VSS</td><td>VCAP_2</td><td>PC9</td><td>PA8</td></tr><tr><td>G</td><td>PH0</td><td>VSS</td><td>VDD</td><td>PH3</td><td>VSS</td><td>VDD</td><td>PC8</td><td>PC7</td></tr><tr><td>H</td><td>PH1</td><td>PF2</td><td>PF1</td><td>PH4</td><td>VSS</td><td>VDD</td><td>PG8</td><td>PC6</td></tr><tr><td>J</td><td>NRST</td><td>PF3</td><td>PF4</td><td>PH5</td><td>VDD</td><td>VDD</td><td>PG7</td><td>PG6</td></tr><tr><td>K</td><td>PF7</td><td>PF6</td><td>PF5</td><td>VDD</td><td>PH12</td><td>PG5</td><td>PG4</td><td>PG3</td></tr><tr><td>L</td><td>PF10</td><td>PF9</td><td>PF8</td><td>BYPASS_REG</td><td>PH11</td><td>PH10</td><td>PD15</td><td>PG2</td></tr><tr><td>M</td><td>VSSA</td><td>PC0</td><td>PC1</td><td>PC2</td><td>PC3</td><td>PB2</td><td>PG1</td><td>VSS</td><td>VSS</td><td>VCAP_1</td><td>PH6</td><td>PH8</td><td>PH9</td><td>PD14</td><td>PD13</td></tr><tr><td>N</td><td>VREF-</td><td>PA1</td><td>PA0</td><td>PA4</td><td>PC4</td><td>PF13</td><td>PG0</td><td>VDD</td><td>VDD</td><td>VDD</td><td>PE13</td><td>PH7</td><td>PD12</td><td>PD11</td><td>PD10</td></tr><tr><td>P</td><td>VREF+</td><td>PA2</td><td>PA6</td><td>PA5</td><td>PC5</td><td>PF12</td><td>PF15</td><td>PE8</td><td>PE9</td><td>PE11</td><td>PE14</td><td>PB12</td><td>PB13</td><td>PD9</td><td>PD8</td></tr><tr><td>R</td><td>VDDA</td><td>PA3</td><td>PA7</td><td>PB1</td><td>PB0</td><td>PF11</td><td>PF14</td><td>PE7</td><td>PE10</td><td>PE12</td><td>PE15</td><td>PB10</td><td>PB11</td><td>PB14</td><td>PB15</td></tr><tr><td colspan="16">ai18497b</td></tr></table>

1. This figure shows the package top view.

Figure 17. STM32F40xxx WLCSP90 bailout
![](images/fdd795683ab945c4cd653805b577b5dd610a39ba91e247133fea6db4504ddca0.jpg)
MS30402V1
1. This figure shows the package bump view.

Table 6. Legend/abbreviations used in the pinout table

<table><tr><td>Name</td><td>Abbreviation</td><td>Definition</td></tr><tr><td>Pin name</td><td colspan="2">Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name</td></tr><tr><td rowspan="3">Pin type</td><td>S</td><td>Supply pin</td></tr><tr><td>I</td><td>Input only pin</td></tr><tr><td>I/O</td><td>Input / output pin</td></tr><tr><td rowspan="4">I/O structure</td><td>FT</td><td>5 V tolerant I/O</td></tr><tr><td>TTa</td><td>3.3 V tolerant I/O directly connected to ADC</td></tr><tr><td>B</td><td>Dedicated BOOT0 pin</td></tr><tr><td>RST</td><td>Bidirectional reset pin with embedded weak pull-up resistor</td></tr><tr><td>Notes</td><td colspan="2">Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset</td></tr><tr><td>Alternate functions</td><td colspan="2">Functions selected through GPIOx_AFR registers</td></tr><tr><td>Additional functions</td><td colspan="2">Functions directly selected/enabled through peripheral registers</td></tr></table>

Table 7. STM32F40xxx pin and ball definitions $^{(1)}$

<table><tr><td colspan="6">Pin number</td><td rowspan="2">Pin name (function after reset)(2)</td><td rowspan="2">Pin type</td><td rowspan="2">I/O structure</td><td rowspan="2">Notes</td><td rowspan="2">Alternate functions</td><td rowspan="2">Additional functions</td></tr><tr><td>LQFP64</td><td>WLCSP90</td><td>LQFP100</td><td>LQFP144</td><td>UFBGA176</td><td>LQFP176</td></tr><tr><td>-</td><td>-</td><td>1</td><td>1</td><td>A2</td><td>1</td><td>PE2</td><td>I/O</td><td>FT</td><td>-</td><td>TRACECLK/ FSMC_A23 / ETH_MII_TXD3 / EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>2</td><td>2</td><td>A1</td><td>2</td><td>PE3</td><td>I/O</td><td>FT</td><td>-</td><td>TRACED0/FSMC_A19 / EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>3</td><td>3</td><td>B1</td><td>3</td><td>PE4</td><td>I/O</td><td>FT</td><td>-</td><td>TRACED1/FSMC_A20 / DCMI_D4/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>4</td><td>4</td><td>B2</td><td>4</td><td>PE5</td><td>I/O</td><td>FT</td><td>-</td><td>TRACED2 / FSMC_A21 / TIM9_CH1 / DCMI_D6 / EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>5</td><td>5</td><td>B3</td><td>5</td><td>PE6</td><td>I/O</td><td>FT</td><td>-</td><td>TRACED3 / FSMC_A22 / TIM9_CH2 / DCMI_D7 / EVENTOUT</td><td>-</td></tr><tr><td>1</td><td>A10</td><td>6</td><td>6</td><td>C1</td><td>6</td><td> $V_{BAT}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>D2</td><td>7</td><td>PI8</td><td>I/O</td><td>FT</td><td>(3)(4)</td><td>-</td><td>RTC_TAMP1, RTC_TAMP2, RTC_TS</td></tr><tr><td>2</td><td>A9</td><td>7</td><td>7</td><td>D1</td><td>8</td><td>PC13</td><td>I/O</td><td>FT</td><td>(3)(4)</td><td>-</td><td>RTC_OUT, RTC_TAMP1, RTC_TS</td></tr><tr><td>3</td><td>B10</td><td>8</td><td>8</td><td>E1</td><td>9</td><td>PC14/OSC32_IN (PC14)</td><td>I/O</td><td>FT</td><td>(3)(4)</td><td>-</td><td>OSC32_IN(5)</td></tr><tr><td>4</td><td>B9</td><td>9</td><td>9</td><td>F1</td><td>10</td><td>PC15/ OSC32_OUT (PC15)</td><td>I/O</td><td>FT</td><td>(3)(4)</td><td>-</td><td>OSC32_OUT(5)</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>D3</td><td>11</td><td>PI9</td><td>I/O</td><td>FT</td><td>-</td><td>CAN1_RX / EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>E3</td><td>12</td><td>PI10</td><td>I/O</td><td>FT</td><td>-</td><td>ETH_MII_RX_ER / EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>E4</td><td>13</td><td>PI11</td><td>I/O</td><td>FT</td><td>-</td><td>OTG_HS_ULPI_DIR / EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>F2</td><td>14</td><td> $V_{SS}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>F3</td><td>15</td><td> $V_{DD}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>10</td><td>E2</td><td>16</td><td>PF0</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_A0 / I2C2_SDA / EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>11</td><td>H3</td><td>17</td><td>PF1</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_A1 / I2C2_SCL / EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>12</td><td>H2</td><td>18</td><td>PF2</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_A2 / I2C2_SMBA / EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>13</td><td>J2</td><td>19</td><td>PF3</td><td>I/O</td><td>FT</td><td>(5)</td><td>FSMC_A3/EVENTOUT</td><td>ADC3_IN9</td></tr><tr><td>-</td><td>-</td><td>-</td><td>14</td><td>J3</td><td>20</td><td>PF4</td><td>I/O</td><td>FT</td><td>(5)</td><td>FSMC_A4/EVENTOUT</td><td>ADC3_IN14</td></tr><tr><td>-</td><td>-</td><td>-</td><td>15</td><td>K3</td><td>21</td><td>PF5</td><td>I/O</td><td>FT</td><td>(5)</td><td>FSMC_A5/EVENTOUT</td><td>ADC3_IN15</td></tr><tr><td>-</td><td>C9</td><td>10</td><td>16</td><td>G2</td><td>22</td><td> $V_{SS}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>B8</td><td>11</td><td>17</td><td>G3</td><td>23</td><td> $V_{DD}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>18</td><td>K2</td><td>24</td><td>PF6</td><td>I/O</td><td>FT</td><td>(5)</td><td>TIM10_CH1 / FSMC_NIORD/ EVENTOUT</td><td>ADC3_IN4</td></tr><tr><td>-</td><td>-</td><td>-</td><td>19</td><td>K1</td><td>25</td><td>PF7</td><td>I/O</td><td>FT</td><td>(5)</td><td>TIM11_CH1/FSMC_NREG/ EVENTOUT</td><td>ADC3_IN5</td></tr><tr><td>-</td><td>-</td><td>-</td><td>20</td><td>L3</td><td>26</td><td>PF8</td><td>I/O</td><td>FT</td><td>(5)</td><td>TIM13_CH1 / FSMC_NIOWR/ EVENTOUT</td><td>ADC3_IN6</td></tr><tr><td>-</td><td>-</td><td>-</td><td>21</td><td>L2</td><td>27</td><td>PF9</td><td>I/O</td><td>FT</td><td>(5)</td><td>TIM14_CH1 / FSMC_CD/ EVENTOUT</td><td>ADC3_IN7</td></tr><tr><td>-</td><td>-</td><td>-</td><td>22</td><td>L1</td><td>28</td><td>PF10</td><td>I/O</td><td>FT</td><td>(5)</td><td>FSMC_INTR/ EVENTOUT</td><td>ADC3_IN8</td></tr><tr><td>5</td><td>F10</td><td>12</td><td>23</td><td>G1</td><td>29</td><td>PH0/OSC_IN (PH0)</td><td>I/O</td><td>FT</td><td>-</td><td>EVENTOUT</td><td> $OSC\_IN^{(5)}$ </td></tr><tr><td>6</td><td>F9</td><td>13</td><td>24</td><td>H1</td><td>30</td><td>PH1/OSC_OUT (PH1)</td><td>I/O</td><td>FT</td><td>-</td><td>EVENTOUT</td><td> $OSC\_OUT^{(5)}$ </td></tr><tr><td>7</td><td>G10</td><td>14</td><td>25</td><td>J1</td><td>31</td><td>NRST</td><td>I/O</td><td>RST</td><td>-</td><td>-</td><td>-</td></tr><tr><td>8</td><td>E10</td><td>15</td><td>26</td><td>M2</td><td>32</td><td>PC0</td><td>I/O</td><td>FT</td><td>(5)</td><td>OTG_HS_ULPI_STP/ EVENTOUT</td><td>ADC123_IN10</td></tr><tr><td>9</td><td>-</td><td>16</td><td>27</td><td>M3</td><td>33</td><td>PC1</td><td>I/O</td><td>FT</td><td>(5)</td><td>ETH_MDC/ EVENTOUT</td><td>ADC123_IN11</td></tr><tr><td>10</td><td>D10</td><td>17</td><td>28</td><td>M4</td><td>34</td><td>PC2</td><td>I/O</td><td>FT</td><td>(5)</td><td>SPI2_MISO / OTG_HS_ULPI_DIR / ETH_MII_TXD2 /I2S2ext_SD/ EVENTOUT</td><td>ADC123_IN12</td></tr><tr><td>11</td><td>E9</td><td>18</td><td>29</td><td>M5</td><td>35</td><td>PC3</td><td>I/O</td><td>FT</td><td>(5)</td><td>SPI2_MOSI / I2S2_SD / OTG_HS_ULPI_NXT / ETH_MII_TX_CLK/ EVENTOUT</td><td>ADC123_IN13</td></tr><tr><td>-</td><td>-</td><td>19</td><td>30</td><td>-</td><td>36</td><td> $V_{DD}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>12</td><td>H10</td><td>20</td><td>31</td><td>M1</td><td>37</td><td> $V_{SSA}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>N1</td><td>-</td><td> $V_{REF-}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>-</td><td>21</td><td>32</td><td>P1</td><td>38</td><td> $V_{REF+}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>13</td><td>G9</td><td>22</td><td>33</td><td>R1</td><td>39</td><td> $V_{DDA}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>14</td><td>C10</td><td>23</td><td>34</td><td>N3</td><td>40</td><td>PA0/WKUP (PA0)</td><td>I/O</td><td>FT</td><td>(6)</td><td>USART2_CTS/ UART4_TX/ ETH_MII_CRS / TIM2_CH1_ETR/ TIM5_CH1 / TIM8_ETR/ EVENTOUT</td><td>ADC123_IN0/WK UP(5)</td></tr><tr><td>15</td><td>F8</td><td>24</td><td>35</td><td>N2</td><td>41</td><td>PA1</td><td>I/O</td><td>FT</td><td>(5)</td><td>USART2_RTS / UART4_RX/ ETH_RMII_REF_CLK / ETH_MII_RX_CLK / TIM5_CH2 / TIM2_CH2/ EVENTOUT</td><td>ADC123_IN1</td></tr><tr><td>16</td><td>J10</td><td>25</td><td>36</td><td>P2</td><td>42</td><td>PA2</td><td>I/O</td><td>FT</td><td>(5)</td><td>USART2_TX/TIM5_CH3 / TIM9_CH1 / TIM2_CH3 / ETH_MDIO/ EVENTOUT</td><td>ADC123_IN2</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>F4</td><td>43</td><td>PH2</td><td>I/O</td><td>FT</td><td>-</td><td>ETH_MII_CRS/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>G4</td><td>44</td><td>PH3</td><td>I/O</td><td>FT</td><td>-</td><td>ETH_MII_COL/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>H4</td><td>45</td><td>PH4</td><td>I/O</td><td>FT</td><td>-</td><td>I2C2_SCL / OTG_HS_ULPI_NXT/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>J4</td><td>46</td><td>PH5</td><td>I/O</td><td>FT</td><td>-</td><td>I2C2_SDA/ EVENTOUT</td><td>-</td></tr><tr><td>17</td><td>H9</td><td>26</td><td>37</td><td>R2</td><td>47</td><td>PA3</td><td>I/O</td><td>FT</td><td>(5)</td><td>USART2_RX/TIM5_CH4 / TIM9_CH2 / TIM2_CH4 / OTG_HS_ULPI_D0 / ETH_MII_COL/ EVENTOUT</td><td>ADC123_IN3</td></tr><tr><td>18</td><td>E5</td><td>27</td><td>38</td><td>-</td><td>-</td><td> $V_{SS}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>D9</td><td>-</td><td>-</td><td>L4</td><td>48</td><td>BYPASS_REG</td><td>I</td><td>FT</td><td>-</td><td>-</td><td>-</td></tr><tr><td>19</td><td>E4</td><td>28</td><td>39</td><td>K4</td><td>49</td><td> $V_{DD}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>20</td><td>J9</td><td>29</td><td>40</td><td>N4</td><td>50</td><td>PA4</td><td>I/O</td><td>TTa</td><td>(5)</td><td>SPI1_NSS / SPI3_NSS / USART2_CK / DCMI_HSYNC / OTG_HS_SOF/ I2S3_WS/ EVENTOUT</td><td>ADC12_IN4 /DAC_OUT1</td></tr><tr><td>21</td><td>G8</td><td>30</td><td>41</td><td>P4</td><td>51</td><td>PA5</td><td>I/O</td><td>TTa</td><td>(5)</td><td>SPI1_SCK/ OTG_HS_ULPI_CK / TIM2_CH1_ETR/ TIM8_CH1N/ EVENTOUT</td><td>ADC12_IN5/DAC_OUT2</td></tr><tr><td>22</td><td>H8</td><td>31</td><td>42</td><td>P3</td><td>52</td><td>PA6</td><td>I/O</td><td>FT</td><td>(5)</td><td>SPI1_MISO / TIM8_BKIN/TIM13_CH1 / DCMI_PIXCLK/TIM3_CH1 / TIM1_BKIN/ EVENTOUT</td><td>ADC12_IN6</td></tr><tr><td>23</td><td>J8</td><td>32</td><td>43</td><td>R3</td><td>53</td><td>PA7</td><td>I/O</td><td>FT</td><td>(5)</td><td>SPI1_MOSI/ TIM8_CH1N / TIM14_CH1/TIM3_CH2/ ETH_MII_RX_DV / TIM1_CH1N / ETH_RMII_CRS_DV/ EVENTOUT</td><td>ADC12_IN7</td></tr><tr><td>24</td><td>-</td><td>33</td><td>44</td><td>N5</td><td>54</td><td>PC4</td><td>I/O</td><td>FT</td><td>(5)</td><td>ETH_RMII_RX_D0 / ETH_MII_RX_D0/ EVENTOUT</td><td>ADC12_IN14</td></tr><tr><td>25</td><td>-</td><td>34</td><td>45</td><td>P5</td><td>55</td><td>PC5</td><td>I/O</td><td>FT</td><td>(5)</td><td>ETH_RMII_RX_D1 / ETH_MII_RX_D1/ EVENTOUT</td><td>ADC12_IN15</td></tr><tr><td>26</td><td>G7</td><td>35</td><td>46</td><td>R5</td><td>56</td><td>PB0</td><td>I/O</td><td>FT</td><td>(5)</td><td>TIM3_CH3 / TIM8_CH2N/ OTG_HS_ULPI_D1/ ETH_MII_RXD2 / TIM1_CH2N/ EVENTOUT</td><td>ADC12_IN8</td></tr><tr><td>27</td><td>H7</td><td>36</td><td>47</td><td>R4</td><td>57</td><td>PB1</td><td>I/O</td><td>FT</td><td>(5)</td><td>TIM3_CH4 / TIM8_CH3N/ OTG_HS_ULPI_D2/ ETH_MII_RXD3 / TIM1_CH3N/ EVENTOUT</td><td>ADC12_IN9</td></tr><tr><td>28-</td><td>J7-</td><td>37-</td><td>4849</td><td>M6R6</td><td>5859</td><td>PB2/BOOT1 (PB2)PF11</td><td>I/OI/O</td><td>FTFT</td><td>--</td><td>EVENTOUTDCMI_D12/ EVENTOUT</td><td>--</td></tr><tr><td>-</td><td>-</td><td>-</td><td>50</td><td>P6</td><td>60</td><td>PF12</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_A6/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>51</td><td>M8</td><td>61</td><td> $V_{SS}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>52</td><td>N8</td><td>62</td><td> $V_{DD}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>53</td><td>N6</td><td>63</td><td>PF13</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_A7/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>54</td><td>R7</td><td>64</td><td>PF14</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_A8/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>55</td><td>P7</td><td>65</td><td>PF15</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_A9/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>56</td><td>N7</td><td>66</td><td>PG0</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_A10/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>57</td><td>M7</td><td>67</td><td>PG1</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_A11/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>G6</td><td>38</td><td>58</td><td>R8</td><td>68</td><td>PE7</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_D4/TIM1_ETR/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>H6</td><td>39</td><td>59</td><td>P8</td><td>69</td><td>PE8</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_D5/ TIM1_CH1N/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>J6</td><td>40</td><td>60</td><td>P9</td><td>70</td><td>PE9</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_D6/TIM1_CH1/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>61</td><td>M9</td><td>71</td><td> $V_{SS}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>62</td><td>N9</td><td>72</td><td> $V_{DD}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>F6</td><td>41</td><td>63</td><td>R9</td><td>73</td><td>PE10</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_D7/TIM1_CH2N/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>J5</td><td>42</td><td>64</td><td>P10</td><td>74</td><td>PE11</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_D8/TIM1_CH2/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>H5</td><td>43</td><td>65</td><td>R10</td><td>75</td><td>PE12</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_D9/TIM1_CH3N/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>G5</td><td>44</td><td>66</td><td>N11</td><td>76</td><td>PE13</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_D10/TIM1_CH3/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>F5</td><td>45</td><td>67</td><td>P11</td><td>77</td><td>PE14</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_D11/TIM1_CH4/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>G4</td><td>46</td><td>68</td><td>R11</td><td>78</td><td>PE15</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_D12/TIM1_BKIN/ EVENTOUT</td><td>-</td></tr><tr><td>29</td><td>H4</td><td>47</td><td>69</td><td>R12</td><td>79</td><td>PB10</td><td>I/O</td><td>FT</td><td>-</td><td>SPI2_SCK / I2S2_CK / I2C2_SCL/ USART3_TX / OTG_HS_ULPI_D3 / ETH_MII_RX_ER / TIM2_CH3/ EVENTOUT</td><td>-</td></tr><tr><td>30</td><td>J4</td><td>48</td><td>70</td><td>R13</td><td>80</td><td>PB11</td><td>I/O</td><td>FT</td><td>-</td><td>I2C2_SDA/USART3_RX/ OTG_HS_ULPI_D4 / ETH_RMII_TX_EN/ ETH_MII_TX_EN / TIM2_CH4/ EVENTOUT</td><td>-</td></tr><tr><td>31</td><td>F4</td><td>49</td><td>71</td><td>M10</td><td>81</td><td> $V_{CAP\_1}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>32</td><td>-</td><td>50</td><td>72</td><td>N10</td><td>82</td><td> $V_{DD}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>M11</td><td>83</td><td>PH6</td><td>I/O</td><td>FT</td><td>-</td><td>I2C2_SMBA / TIM12_CH1 / ETH_MII_RXD2/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>N12</td><td>84</td><td>PH7</td><td>I/O</td><td>FT</td><td>-</td><td>I2C3_SCL / ETH_MII_RXD3/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>M12</td><td>85</td><td>PH8</td><td>I/O</td><td>FT</td><td>-</td><td>I2C3_SDA / DCMI_HSYNC/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>M13</td><td>86</td><td>PH9</td><td>I/O</td><td>FT</td><td>-</td><td>I2C3_SMBA / TIM12_CH2/ DCMI_D0/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>L13</td><td>87</td><td>PH10</td><td>I/O</td><td>FT</td><td>-</td><td>TIM5_CH1 / DCMI_D1/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>L12</td><td>88</td><td>PH11</td><td>I/O</td><td>FT</td><td>-</td><td>TIM5_CH2 / DCMI_D2/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>K12</td><td>89</td><td>PH12</td><td>I/O</td><td>FT</td><td>-</td><td>TIM5_CH3 / DCMI_D3/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>H12</td><td>90</td><td> $V_{SS}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>J12</td><td>91</td><td> $V_{DD}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>33</td><td>J3</td><td>51</td><td>73</td><td>P12</td><td>92</td><td>PB12</td><td>I/O</td><td>FT</td><td>-</td><td>SPI2_NSS / I2S2_WS / I2C2_SMBA/USART3_CK/TIM1_BKIN / CAN2_RX / OTG_HS_ULPI_D5/ETH_RMII_TXD0 / ETH_MII_TXD0/OTG_HS_ID/ EVENTOUT</td><td>-</td></tr><tr><td>34</td><td>J1</td><td>52</td><td>74</td><td>P13</td><td>93</td><td>PB13</td><td>I/O</td><td>FT</td><td>-</td><td>SPI2_SCK / I2S2_CK / USART3_CTS/TIM1_CH1N /CAN2_TX / OTG_HS_ULPI_D6 / ETH_RMII_TXD1 / ETH_MII_TXD1/ EVENTOUT</td><td>OTG_HS_VBUS</td></tr><tr><td>35</td><td>J2</td><td>53</td><td>75</td><td>R14</td><td>94</td><td>PB14</td><td>I/O</td><td>FT</td><td>-</td><td>SPI2_MISO/TIM1_CH2N / TIM12_CH1 / OTG_HS_DM/USART3_RTS / TIM8_CH2N/I2S2ext_SD/ EVENTOUT</td><td>-</td></tr><tr><td>36</td><td>H1</td><td>54</td><td>76</td><td>R15</td><td>95</td><td>PB15</td><td>I/O</td><td>FT</td><td>-</td><td>SPI2_MOSI / I2S2_SD/TIM1_CH3N / TIM8_CH3N / TIM12_CH2 / OTG_HS_DP/ EVENTOUT</td><td>RTC_REFIN</td></tr><tr><td>-</td><td>H2</td><td>55</td><td>77</td><td>P15</td><td>96</td><td>PD8</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_D13/USART3_TX/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>H3</td><td>56</td><td>78</td><td>P14</td><td>97</td><td>PD9</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_D14/USART3_RX/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>G3</td><td>57</td><td>79</td><td>N15</td><td>98</td><td>PD10</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_D15/USART3_CK/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>G1</td><td>58</td><td>80</td><td>N14</td><td>99</td><td>PD11</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_CLE / FSMC_A16/USART3_CTS/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>G2</td><td>59</td><td>81</td><td>N13</td><td>100</td><td>PD12</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_ALE/ FSMC_A17/TIM4_CH1 / USART3_RTS/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>60</td><td>82</td><td>M15</td><td>101</td><td>PD13</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_A18/TIM4_CH2/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>83</td><td>-</td><td>102</td><td> $V_{SS}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>84</td><td>J13</td><td>103</td><td> $V_{DD}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>F2</td><td>61</td><td>85</td><td>M14</td><td>104</td><td>PD14</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_D0/TIM4_CH3/ EVENTOUT/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>F1</td><td>62</td><td>86</td><td>L14</td><td>105</td><td>PD15</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_D1/TIM4_CH4/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>87</td><td>L15</td><td>106</td><td>PG2</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_A12/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>88</td><td>K15</td><td>107</td><td>PG3</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_A13/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>89</td><td>K14</td><td>108</td><td>PG4</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_A14/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>90</td><td>K13</td><td>109</td><td>PG5</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_A15/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>91</td><td>J15</td><td>110</td><td>PG6</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_INT2/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>92</td><td>J14</td><td>111</td><td>PG7</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_INT3/USART6_CK/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>93</td><td>H14</td><td>112</td><td>PG8</td><td>I/O</td><td>FT</td><td>-</td><td>USART6_RTS/ ETH_PPS_OUT/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>94</td><td>G12</td><td>113</td><td> $V_{SS}$ </td><td>S</td><td></td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>95</td><td>H13</td><td>114</td><td> $V_{DD}$ </td><td>S</td><td></td><td>-</td><td>-</td><td>-</td></tr><tr><td>37</td><td>F3</td><td>63</td><td>96</td><td>H15</td><td>115</td><td>PC6</td><td>I/O</td><td>FT</td><td>-</td><td>I2S2_MCK/ TIM8_CH1/SDIO_D6/ USART6_TX/ DCMI_D0/TIM3_CH1/ EVENTOUT</td><td>-</td></tr><tr><td>38</td><td>E1</td><td>64</td><td>97</td><td>G15</td><td>116</td><td>PC7</td><td>I/O</td><td>FT</td><td>-</td><td>I2S3_MCK/ TIM8_CH2/SDIO_D7/ USART6_RX/ DCMI_D1/TIM3_CH2/ EVENTOUT</td><td>-</td></tr><tr><td>39</td><td>E2</td><td>65</td><td>98</td><td>G14</td><td>117</td><td>PC8</td><td>I/O</td><td>FT</td><td>-</td><td>TIM8_CH3/SDIO_D0 /TIM3_CH3/ USART6_CK/ DCMI_D2/ EVENTOUT</td><td>-</td></tr><tr><td>40</td><td>E3</td><td>66</td><td>99</td><td>F14</td><td>118</td><td>PC9</td><td>I/O</td><td>FT</td><td>-</td><td>I2S_CKIN/ MCO2 / TIM8_CH4/SDIO_D1 / /I2C3_SDA / DCMI_D3 / TIM3_CH4/ EVENTOUT</td><td>-</td></tr><tr><td>41</td><td>D1</td><td>67</td><td>100</td><td>F15</td><td>119</td><td>PA8</td><td>I/O</td><td>FT</td><td>-</td><td>MCO1 / USART1_CK/ TIM1_CH1/ I2C3_SCL/ OTG_FS_SOF/ EVENTOUT</td><td>-</td></tr><tr><td>42</td><td>D2</td><td>68</td><td>101</td><td>E15</td><td>120</td><td>PA9</td><td>I/O</td><td>FT</td><td>-</td><td>USART1_TX/ TIM1_CH2 / I2C3_SMBA / DCMI_D0/ EVENTOUT</td><td>OTG_FS_VBUS</td></tr><tr><td>43</td><td>D3</td><td>69</td><td>102</td><td>D15</td><td>121</td><td>PA10</td><td>I/O</td><td>FT</td><td>-</td><td>USART1_RX/ TIM1_CH3/ OTG_FS_ID/DCMI_D1/ EVENTOUT</td><td>-</td></tr><tr><td>44</td><td>C1</td><td>70</td><td>103</td><td>C15</td><td>122</td><td>PA11</td><td>I/O</td><td>FT</td><td>-</td><td>USART1_CTS / CAN1_RX / TIM1_CH4 / OTG_FS_DM/ EVENTOUT</td><td>-</td></tr><tr><td>45</td><td>C2</td><td>71</td><td>104</td><td>B15</td><td>123</td><td>PA12</td><td>I/O</td><td>FT</td><td>-</td><td>USART1_RTS / CAN1_TX/ TIM1_ETR/ OTG_FS_DP/ EVENTOUT</td><td>-</td></tr><tr><td>46</td><td>D4</td><td>72</td><td>105</td><td>A15</td><td>124</td><td>PA13 (JTMS-SWDIO)</td><td>I/O</td><td>FT</td><td>-</td><td>JTMS-SWDIO/ EVENTOUT</td><td>-</td></tr><tr><td>47</td><td>B1</td><td>73</td><td>106</td><td>F13</td><td>125</td><td> $V_{CAP\_2}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>E7</td><td>74</td><td>107</td><td>F12</td><td>126</td><td> $V_{SS}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>48</td><td>E6</td><td>75</td><td>108</td><td>G13</td><td>127</td><td> $V_{DD}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>E12</td><td>128</td><td>PH13</td><td>I/O</td><td>FT</td><td>-</td><td>TIM8_CH1N / CAN1_TX/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>E13</td><td>129</td><td>PH14</td><td>I/O</td><td>FT</td><td>-</td><td>TIM8_CH2N / DCMI_D4/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>D13</td><td>130</td><td>PH15</td><td>I/O</td><td>FT</td><td>-</td><td>TIM8_CH3N / DCMI_D11/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>C3</td><td>-</td><td>-</td><td>E14</td><td>131</td><td>PI0</td><td>I/O</td><td>FT</td><td>-</td><td>TIM5_CH4 / SPI2_NSS / I2S2_WS / DCMI_D13/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>B2</td><td>-</td><td>-</td><td>D14</td><td>132</td><td>PI1</td><td>I/O</td><td>FT</td><td>-</td><td>SPI2_SCK / I2S2_CK / DCMI_D8/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>C14</td><td>133</td><td>PI2</td><td>I/O</td><td>FT</td><td>-</td><td>TIM8_CH4 /SPI2_MISO / DCMI_D9 / I2S2ext_SD/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>C13</td><td>134</td><td>PI3</td><td>I/O</td><td>FT</td><td>-</td><td>TIM8_ETR / SPI2_MOSI / I2S2_SD / DCMI_D10/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>D9</td><td>135</td><td>VSS</td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>C9</td><td>136</td><td>VDD</td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>49</td><td>A2</td><td>76</td><td>109</td><td>A14</td><td>137</td><td>PA14 (JTCK/SWCLK)</td><td>I/O</td><td>FT</td><td>-</td><td>JTCK-SWCLK/ EVENTOUT</td><td>-</td></tr><tr><td>50</td><td>B3</td><td>77</td><td>110</td><td>A13</td><td>138</td><td>PA15 (JTDI)</td><td>I/O</td><td>FT</td><td>-</td><td>JTDI/ SPI3_NSS/ I2S3_WS/TIM2_CH1_ETR / SPI1_NSS / EVENTOUT</td><td>-</td></tr><tr><td>51</td><td>D5</td><td>78</td><td>111</td><td>B14</td><td>139</td><td>PC10</td><td>I/O</td><td>FT</td><td>-</td><td>SPI3_SCK / I2S3_CK/ UART4_TX/SDIO_D2 / DCMI_D8 / USART3_TX/ EVENTOUT</td><td>-</td></tr><tr><td>52</td><td>C4</td><td>79</td><td>112</td><td>B13</td><td>140</td><td>PC11</td><td>I/O</td><td>FT</td><td>-</td><td>UART4_RX/ SPI3_MISO / SDIO_D3 / DCMI_D4/USART3_RX / I2S3ext_SD/ EVENTOUT</td><td>-</td></tr><tr><td>53</td><td>A3</td><td>80</td><td>113</td><td>A12</td><td>141</td><td>PC12</td><td>I/O</td><td>FT</td><td>-</td><td>UART5_TX/SDIO_CK / DCMI_D9 / SPI3_MOSI /I2S3_SD / USART3_CK/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>D6</td><td>81</td><td>114</td><td>B12</td><td>142</td><td>PD0</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_D2/CAN1_RX/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>C5</td><td>82</td><td>115</td><td>C12</td><td>143</td><td>PD1</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_D3 / CAN1_TX/ EVENTOUT</td><td>-</td></tr><tr><td>54</td><td>B4</td><td>83</td><td>116</td><td>D12</td><td>144</td><td>PD2</td><td>I/O</td><td>FT</td><td>-</td><td>TIM3_ETR/UART5_RX/ SDIO_CMD / DCMI_D11/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>84</td><td>117</td><td>D11</td><td>145</td><td>PD3</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_CLK/ USART2_CTS/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>A4</td><td>85</td><td>118</td><td>D10</td><td>146</td><td>PD4</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_NOE/USART2_RTS/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>C6</td><td>86</td><td>119</td><td>C11</td><td>147</td><td>PD5</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_NWE/USART2_TX/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>120</td><td>D8</td><td>148</td><td> $V_{SS}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>121</td><td>C8</td><td>149</td><td> $V_{DD}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>B5</td><td>87</td><td>122</td><td>B11</td><td>150</td><td>PD6</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_NWAIT/USART2_RX/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>A5</td><td>88</td><td>123</td><td>A11</td><td>151</td><td>PD7</td><td>I/O</td><td>FT</td><td>-</td><td>USART2_CK/FSMC_NE1/ FSMC_NCE2/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>124</td><td>C10</td><td>152</td><td>PG9</td><td>I/O</td><td>FT</td><td>-</td><td>USART6_RX / FSMC_NE2/FSMC_NCE3/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>125</td><td>B10</td><td>153</td><td>PG10</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_NCE4_1/ FSMC_NE3/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>126</td><td>B9</td><td>154</td><td>PG11</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_NCE4_2/ ETH_MII_TX_EN/ ETH_RMII_TX_EN/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>127</td><td>B8</td><td>155</td><td>PG12</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_NE4 / USART6_RTS/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>128</td><td>A8</td><td>156</td><td>PG13</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_A24 / USART6_CTS /ETH_MII_TXD0/ ETH_RMII_TXD0/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>129</td><td>A7</td><td>157</td><td>PG14</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_A25 / USART6_TX /ETH_MII_TXD1/ ETH_RMII_TXD1/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>E8</td><td>-</td><td>130</td><td>D7</td><td>158</td><td> $V_{SS}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>F7</td><td>-</td><td>131</td><td>C7</td><td>159</td><td> $V_{DD}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>132</td><td>B7</td><td>160</td><td>PG15</td><td>I/O</td><td>FT</td><td>-</td><td>USART6_CTS / DCMI_D13/ EVENTOUT</td><td>-</td></tr><tr><td>55</td><td>B6</td><td>89</td><td>133</td><td>A10</td><td>161</td><td>PB3 (JTDO/ TRACESWO)</td><td>I/O</td><td>FT</td><td>-</td><td>JTDO/ TRACESWO/ SPI3_SCK / I2S3_CK / TIM2_CH2 / SPI1_SCK/ EVENTOUT</td><td>-</td></tr><tr><td>56</td><td>A6</td><td>90</td><td>134</td><td>A9</td><td>162</td><td>PB4 (NJTRST)</td><td>I/O</td><td>FT</td><td>-</td><td>NJTRST/ SPI3_MISO / TIM3_CH1 / SPI1_MISO / I2S3ext_SD/ EVENTOUT</td><td>-</td></tr><tr><td>57</td><td>D7</td><td>91</td><td>135</td><td>A6</td><td>163</td><td>PB5</td><td>I/O</td><td>FT</td><td>-</td><td>I2C1_SMBA/ CAN2_RX / OTG_HS_ULPI_D7 / ETH_PPS_OUT/TIM3_CH2 / SPI1_MOSI/ SPI3_MOSI / DCMI_D10 / I2S3_SD/ EVENTOUT</td><td>-</td></tr><tr><td>58</td><td>C7</td><td>92</td><td>136</td><td>B6</td><td>164</td><td>PB6</td><td>I/O</td><td>FT</td><td>-</td><td>I2C1_SCL/ TIM4_CH1 / CAN2_TX / DCMI_D5/USART1_TX/ EVENTOUT</td><td>-</td></tr><tr><td>59</td><td>B7</td><td>93</td><td>137</td><td>B5</td><td>165</td><td>PB7</td><td>I/O</td><td>FT</td><td>-</td><td>I2C1_SDA / FSMC_NL / DCMI_VSYNC / USART1_RX/ TIM4_CH2/ EVENTOUT</td><td>-</td></tr><tr><td>60</td><td>A7</td><td>94</td><td>138</td><td>D6</td><td>166</td><td>BOOT0</td><td>I</td><td>B</td><td>-</td><td>-</td><td> $V_{PP}$ </td></tr><tr><td>61</td><td>D8</td><td>95</td><td>139</td><td>A5</td><td>167</td><td>PB8</td><td>I/O</td><td>FT</td><td>-</td><td>TIM4_CH3/SDIO_D4/ TIM10_CH1 / DCMI_D6 / ETH_MII_TXD3 / I2C1_SCL/ CAN1_RX/ EVENTOUT</td><td>-</td></tr><tr><td>62</td><td>C8</td><td>96</td><td>140</td><td>B4</td><td>168</td><td>PB9</td><td>I/O</td><td>FT</td><td>-</td><td>SPI2_NSS/ I2S2_WS / TIM4_CH4/ TIM11_CH1/ SDIO_D5 / DCMI_D7 / I2C1_SDA / CAN1_TX/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>97</td><td>141</td><td>A4</td><td>169</td><td>PE0</td><td>I/O</td><td>FT</td><td>-</td><td>TIM4_ETR / FSMC_NBL0 / DCMI_D2/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>98</td><td>142</td><td>A3</td><td>170</td><td>PE1</td><td>I/O</td><td>FT</td><td>-</td><td>FSMC_NBL1 / DCMI_D3/ EVENTOUT</td><td>-</td></tr><tr><td>63</td><td>-</td><td>99</td><td>-</td><td>D5</td><td>-</td><td> $V_{SS}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>A8</td><td>-</td><td>143</td><td>C6</td><td>171</td><td>PDR_ON</td><td>I</td><td>FT</td><td>-</td><td>-</td><td>-</td></tr><tr><td>64</td><td>A1</td><td>100</td><td>144</td><td>C5</td><td>172</td><td> $V_{DD}$ </td><td>S</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>D4</td><td>173</td><td>PI4</td><td>I/O</td><td>FT</td><td>-</td><td>TIM8_BKIN / DCMI_D5/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>C4</td><td>174</td><td>PI5</td><td>I/O</td><td>FT</td><td>-</td><td>TIM8_CH1 / DCMI_VSYNC/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>C3</td><td>175</td><td>PI6</td><td>I/O</td><td>FT</td><td>-</td><td>TIM8_CH2 / DCMI_D6/ EVENTOUT</td><td>-</td></tr><tr><td>-</td><td>-</td><td>-</td><td>-</td><td>C2</td><td>176</td><td>PI7</td><td>I/O</td><td>FT</td><td>-</td><td>TIM8_CH3 / DCMI_D7/ EVENTOUT</td><td>-</td></tr></table>

1. UFBGA176 F6, F7, F8, F9, F10, G6, G7, G8, G9, G10, H6, H7, H8, H9, H10, J6, J7, J8, J9, J10, K6, K7, K8, K9 and K10 balls are connected to $V_{SS}$ for heat dissipation and package mechanical stability.
2. Function availability depends on the chosen device.
3. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
4. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website: www.st.com.
5. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
6. If the device is delivered in an UFBGA176 or WLCSP90 and the BYPASS\_REG pin is set to VDD (Regulator off/internal reset ON mode), then PA0 is used as an internal Reset (active low).

Table 8. FSMC pin definition

<table><tr><td rowspan="2">Pins(1)</td><td colspan="4">FSMC</td><td rowspan="2">LQFP100(2)</td><td rowspan="2">WLCSP90(2)</td></tr><tr><td>CF</td><td>NOR/PSRAM/SRAM</td><td>NOR/PSRAM Mux</td><td>NAND 16 bit</td></tr><tr><td>PE2</td><td>-</td><td>A23</td><td>A23</td><td>-</td><td>Yes</td><td>-</td></tr><tr><td>PE3</td><td>-</td><td>A19</td><td>A19</td><td>-</td><td>Yes</td><td>-</td></tr><tr><td>PE4</td><td>-</td><td>A20</td><td>A20</td><td>-</td><td>Yes</td><td>-</td></tr><tr><td>PE5</td><td>-</td><td>A21</td><td>A21</td><td>-</td><td>Yes</td><td>-</td></tr><tr><td>PE6</td><td>-</td><td>A22</td><td>A22</td><td>-</td><td>Yes</td><td>-</td></tr><tr><td rowspan="2"> $Pins^{(1)}$ </td><td colspan="4">FSMC</td><td rowspan="2"> $LQFP100^{(2)}$ </td><td rowspan="2">WLCSP90(2)</td></tr><tr><td>CF</td><td>NOR/PSRAM/SRAM</td><td>NOR/PSRAM Mux</td><td>NAND 16 bit</td></tr><tr><td>PF0</td><td>A0</td><td>A0</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PF1</td><td>A1</td><td>A1</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PF2</td><td>A2</td><td>A2</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PF3</td><td>A3</td><td>A3</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PF4</td><td>A4</td><td>A4</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PF5</td><td>A5</td><td>A5</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PF6</td><td>NIORD</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PF7</td><td>NREG</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PF8</td><td>NIOWR</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PF9</td><td>CD</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PF10</td><td>INTR</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PF12</td><td>A6</td><td>A6</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PF13</td><td>A7</td><td>A7</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PF14</td><td>A8</td><td>A8</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PF15</td><td>A9</td><td>A9</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PG0</td><td>A10</td><td>A10</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PG1</td><td>-</td><td>A11</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PE7</td><td>D4</td><td>D4</td><td>DA4</td><td>D4</td><td>Yes</td><td>Yes</td></tr><tr><td>PE8</td><td>D5</td><td>D5</td><td>DA5</td><td>D5</td><td>Yes</td><td>Yes</td></tr><tr><td>PE9</td><td>D6</td><td>D6</td><td>DA6</td><td>D6</td><td>Yes</td><td>Yes</td></tr><tr><td>PE10</td><td>D7</td><td>D7</td><td>DA7</td><td>D7</td><td>Yes</td><td>Yes</td></tr><tr><td>PE11</td><td>D8</td><td>D8</td><td>DA8</td><td>D8</td><td>Yes</td><td>Yes</td></tr><tr><td>PE12</td><td>D9</td><td>D9</td><td>DA9</td><td>D9</td><td>Yes</td><td>Yes</td></tr><tr><td>PE13</td><td>D10</td><td>D10</td><td>DA10</td><td>D10</td><td>Yes</td><td>Yes</td></tr><tr><td>PE14</td><td>D11</td><td>D11</td><td>DA11</td><td>D11</td><td>Yes</td><td>Yes</td></tr><tr><td>PE15</td><td>D12</td><td>D12</td><td>DA12</td><td>D12</td><td>Yes</td><td>Yes</td></tr><tr><td>PD8</td><td>D13</td><td>D13</td><td>DA13</td><td>D13</td><td>Yes</td><td>Yes</td></tr><tr><td>PD9</td><td>D14</td><td>D14</td><td>DA14</td><td>D14</td><td>Yes</td><td>Yes</td></tr><tr><td>PD10</td><td>D15</td><td>D15</td><td>DA15</td><td>D15</td><td>Yes</td><td>Yes</td></tr><tr><td>PD11</td><td>-</td><td>A16</td><td>A16</td><td>CLE</td><td>Yes</td><td>Yes</td></tr><tr><td>PD12</td><td>-</td><td>A17</td><td>A17</td><td>ALE</td><td>Yes</td><td>Yes</td></tr><tr><td>PD13</td><td>-</td><td>A18</td><td>A18</td><td>-</td><td>Yes</td><td>-</td></tr><tr><td>PD14</td><td>D0</td><td>D0</td><td>DA0</td><td>D0</td><td>Yes</td><td>Yes</td></tr><tr><td rowspan="2"> $Pins^{(1)}$ </td><td colspan="4">FSMC</td><td rowspan="2"> $LQFP100^{(2)}$ </td><td rowspan="2"> $WLCSP90^{(2)}$ </td></tr><tr><td>CF</td><td>NOR/PSRAM/SRAM</td><td>NOR/PSRAM Mux</td><td>NAND 16 bit</td></tr><tr><td>PD15</td><td>D1</td><td>D1</td><td>DA1</td><td>D1</td><td>Yes</td><td>Yes</td></tr><tr><td>PG2</td><td>-</td><td>A12</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PG3</td><td>-</td><td>A13</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PG4</td><td>-</td><td>A14</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PG5</td><td>-</td><td>A15</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PG6</td><td>-</td><td>-</td><td>-</td><td>INT2</td><td>-</td><td>-</td></tr><tr><td>PG7</td><td>-</td><td>-</td><td>-</td><td>INT3</td><td>-</td><td>-</td></tr><tr><td>PD0</td><td>D2</td><td>D2</td><td>DA2</td><td>D2</td><td>Yes</td><td>Yes</td></tr><tr><td>PD1</td><td>D3</td><td>D3</td><td>DA3</td><td>D3</td><td>Yes</td><td>Yes</td></tr><tr><td>PD3</td><td>-</td><td>CLK</td><td>CLK</td><td>-</td><td>Yes</td><td>-</td></tr><tr><td>PD4</td><td>NOE</td><td>NOE</td><td>NOE</td><td>NOE</td><td>Yes</td><td>Yes</td></tr><tr><td>PD5</td><td>NWE</td><td>NWE</td><td>NWE</td><td>NWE</td><td>Yes</td><td>Yes</td></tr><tr><td>PD6</td><td>NWAIT</td><td>NWAIT</td><td>NWAIT</td><td>NWAIT</td><td>Yes</td><td>Yes</td></tr><tr><td>PD7</td><td>-</td><td>NE1</td><td>NE1</td><td>NCE2</td><td>Yes</td><td>Yes</td></tr><tr><td>PG9</td><td>-</td><td>NE2</td><td>NE2</td><td>NCE3</td><td>-</td><td>-</td></tr><tr><td>PG10</td><td>NCE4_1</td><td>NE3</td><td>NE3</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PG11</td><td>NCE4_2</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PG12</td><td>-</td><td>NE4</td><td>NE4</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PG13</td><td>-</td><td>A24</td><td>A24</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PG14</td><td>-</td><td>A25</td><td>A25</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PB7</td><td>-</td><td>NADV</td><td>NADV</td><td>-</td><td>Yes</td><td>Yes</td></tr><tr><td>PE0</td><td>-</td><td>NBL0</td><td>NBL0</td><td>-</td><td>Yes</td><td>-</td></tr><tr><td>PE1</td><td>-</td><td>NBL1</td><td>NBL1</td><td>-</td><td>Yes</td><td>-</td></tr></table>

1. Full FSMC features are available on LQFP144, LQFP176, and UFBGA176. The features available on smaller packages are given in the dedicated package column.
2. Ports F and G are not available in devices delivered in 100-pin packages.

Table 9. Alternate function mapping

<table><tr><td rowspan="2" colspan="2">Port</td><td>AF0</td><td>AF1</td><td>AF2</td><td>AF3</td><td>AF4</td><td>AF5</td><td>AF6</td><td>AF7</td><td>AF8</td><td>AF9</td><td>AF10</td><td>AF11</td><td>AF12</td><td>AF13</td><td rowspan="2">AF14</td><td rowspan="2">AF15</td></tr><tr><td>SYS</td><td>TIM1/2</td><td>TIM3/4/5</td><td>TIM8/9/10/11</td><td>I2C1/2/3</td><td>SPI1/SPI2/I2S2/I2S2ext</td><td>SPI3/I2Sext/I2S3</td><td>USART1/2/3/I2S3ext</td><td>UART4/5/USART6</td><td>CAN1/2TIM12/13/14</td><td>OTG_FS/OTG_HS</td><td>ETH</td><td>FSMC/SDIO/OTG_FS</td><td>DCMI</td></tr><tr><td rowspan="16">Port A</td><td>PA0</td><td>-</td><td>TIM2_CH1_ETR</td><td>TIM 5_CH1</td><td>TIM8_ETR</td><td>-</td><td>-</td><td>-</td><td>USART2_CTS</td><td>UART4_TX</td><td>-</td><td>-</td><td>ETH_MII_CRS</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PA1</td><td>-</td><td>TIM2_CH2</td><td>TIM5_CH2</td><td>-</td><td>-</td><td>-</td><td>-</td><td>USART2_RTS</td><td>UART4_RX</td><td>-</td><td>-</td><td>ETH_MII_RX_CLKETH_RMII_REF_CLK</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PA2</td><td>-</td><td>TIM2_CH3</td><td>TIM5_CH3</td><td>TIM9_CH1</td><td>-</td><td>-</td><td>-</td><td>USART2_TX</td><td>-</td><td>-</td><td>-</td><td>ETH_MDIO</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PA3</td><td>-</td><td>TIM2_CH4</td><td>TIM5_CH4</td><td>TIM9_CH2</td><td>-</td><td>-</td><td>-</td><td>USART2_RX</td><td>-</td><td>-</td><td>OTG_HS_ULPI_D0</td><td>ETH_MII_COL</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PA4</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>SPI1_NSS</td><td>SPI3_NSS I2S3_WS</td><td>USART2_CK</td><td>-</td><td>-</td><td>-</td><td>-</td><td>OTG_HS_SOF</td><td>DCMI_HSYNC</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PA5</td><td>-</td><td>TIM2_CH1_ETR</td><td>-</td><td>TIM8_CH1N</td><td>-</td><td>SPI1_SCK</td><td>-</td><td>-</td><td>-</td><td>-</td><td>OTG_HS_ULPI_CK</td><td>-</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PA6</td><td>-</td><td>TIM1_BKIN</td><td>TIM3_CH1</td><td>TIM8_BKIN</td><td>-</td><td>SPI1_MISO</td><td>-</td><td>-</td><td>-</td><td>TIM13_CH1</td><td>-</td><td>-</td><td>-</td><td>DCMI_PIXCLK</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PA7</td><td>-</td><td>TIM1_CH1N</td><td>TIM3_CH2</td><td>TIM8_CH1N</td><td>-</td><td>SPI1_MOSI</td><td>-</td><td>-</td><td>-</td><td>TIM14_CH1</td><td>-</td><td>ETH_MII_RX_DVETH_RMII_CRS_DV</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PA8</td><td>MCO1</td><td>TIM1_CH1</td><td>-</td><td>-</td><td>I2C3_SCL</td><td>-</td><td>-</td><td>USART1_CK</td><td>-</td><td>-</td><td>OTG_FS_SOF</td><td>-</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PA9</td><td>-</td><td>TIM1_CH2</td><td>-</td><td>-</td><td>I2C3_SMBA</td><td>-</td><td>-</td><td>USART1_TX</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>DCMI_D0</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PA10</td><td>-</td><td>TIM1_CH3</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>USART1_RX</td><td>-</td><td>-</td><td>OTG_FS_ID</td><td>-</td><td>-</td><td>DCMI_D1</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PA11</td><td>-</td><td>TIM1_CH4</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>USART1_CTS</td><td>-</td><td>CAN1_RX</td><td>OTG_FS_DM</td><td>-</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PA12</td><td>-</td><td>TIM1_ETR</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>USART1_RTS</td><td>-</td><td>CAN1_TX</td><td>OTG_FS_DP</td><td>-</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PA13</td><td>JTMS-SWDIO</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PA14</td><td>JTCK-SWCLK</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PA15</td><td>JTDI</td><td>TIM 2_CH1TIM 2_ETR</td><td>-</td><td>-</td><td>-</td><td>SPI1_NSS</td><td>SPI3_NSS/I2S3_WS</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr></table>

![](images/e84bb249bf9c387f186025b141ee11205dc78bddfeebb6111e3e54803eeb2be9.jpg)
DS8626 Rev 12

Table 9. Alternate function mapping (continued)

<table><tr><td colspan="2" rowspan="2">Port</td><td>AF0</td><td>AF1</td><td>AF2</td><td>AF3</td><td>AF4</td><td>AF5</td><td>AF6</td><td>AF7</td><td>AF8</td><td>AF9</td><td>AF10</td><td>AF11</td><td>AF12</td><td>AF13</td><td rowspan="2">AF14</td><td rowspan="2">AF15</td></tr><tr><td>SYS</td><td>TIM1/2</td><td>TIM3/4/5</td><td>TIM8/9/10/11</td><td>I2C1/2/3</td><td>SPI1/SPI2/I2S2/I2S2ext</td><td>SPI3/I2Sext/I2S3</td><td>USART1/2/3/I2S3ext</td><td>UART4/5/USART6</td><td>CAN1/2TIM12/13/14</td><td>OTG_FS/OTG_HS</td><td>ETH</td><td>FSMC/SDIO/OTG_FS</td><td>DCMI</td></tr><tr><td rowspan="16">Port B</td><td>PB0</td><td>-</td><td>TIM1_CH2N</td><td>TIM3_CH3</td><td>TIM8_CH2N</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>OTG_HS_ULPI_D1</td><td>ETH_MII_RXD2</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PB1</td><td>-</td><td>TIM1_CH3N</td><td>TIM3_CH4</td><td>TIM8_CH3N</td><td></td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>OTG_HS_ULPI_D2</td><td>ETH_MII_RXD3</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PB2</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PB3</td><td>JTDO/TRACESWO</td><td>TIM2_CH2</td><td>-</td><td>-</td><td>-</td><td>SPI1_SCK</td><td>SPI3_SCKI2S3_CK</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PB4</td><td>NJTRST</td><td>-</td><td>TIM3_CH1</td><td></td><td>-</td><td>SPI1_MISO</td><td>SPI3_MISO</td><td>I2S3ext_SD</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PB5</td><td>-</td><td>-</td><td>TIM3_CH2</td><td></td><td>I2C1_SMBA</td><td>SPI1_MOSI</td><td>SPI3_MOSI I2S3_SD</td><td>-</td><td>-</td><td>CAN2_RX</td><td>OTG_HS_ULPI_D7</td><td>ETH_PPS_OUT</td><td>-</td><td>DCMI_D10</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PB6</td><td>-</td><td>-</td><td>TIM4_CH1</td><td></td><td>I2C1_SCL</td><td>-</td><td>-</td><td>USART1_TX</td><td>-</td><td>CAN2_TX</td><td>-</td><td>-</td><td>-</td><td>DCMI_D5</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PB7</td><td>-</td><td>-</td><td>TIM4_CH2</td><td></td><td>I2C1_SDA</td><td>-</td><td>-</td><td>USART1_RX</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_NL</td><td>DCMI_VSYNC</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PB8</td><td>-</td><td>-</td><td>TIM4_CH3</td><td>TIM10_CH1</td><td>I2C1_SCL</td><td>-</td><td>-</td><td>-</td><td>-</td><td>CAN1_RX</td><td>-</td><td>ETH_MII_TXD3</td><td>SDIO_D4</td><td>DCMI_D6</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PB9</td><td>-</td><td>-</td><td>TIM4_CH4</td><td>TIM11_CH1</td><td>I2C1_SDA</td><td>SPI2_NSS I2S2_WS</td><td>-</td><td>-</td><td>-</td><td>CAN1_TX</td><td>-</td><td>-</td><td>SDIO_D5</td><td>DCMI_D7</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PB10</td><td>-</td><td>TIM2_CH3</td><td>-</td><td>-</td><td>I2C2_SCL</td><td>SPI2_SCK I2S2_CK</td><td>-</td><td>USART3_TX</td><td>-</td><td>-</td><td>OTG_HS_ULPI_D3</td><td>ETH_MII_RX_ER</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PB11</td><td>-</td><td>TIM2_CH4</td><td>-</td><td>-</td><td>I2C2_SDA</td><td>-</td><td>-</td><td>USART3_RX</td><td>-</td><td>-</td><td>OTG_HS_ULPI_D4</td><td>ETH_MII_TX_ENETH_RMII_TX_EN</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PB12</td><td>-</td><td>TIM1_BKIN</td><td>-</td><td>-</td><td>I2C2_SMBA</td><td>SPI2_NSS I2S2_WS</td><td>-</td><td>USART3_CK</td><td>-</td><td>CAN2_RX</td><td>OTG_HS_ULPI_D5</td><td>ETH_MII_TXD0ETH_RMII_TXD0</td><td>OTG_HS_ID</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PB13</td><td>-</td><td>TIM1_CH1N</td><td>-</td><td>-</td><td>-</td><td>SPI2_SCK I2S2_CK</td><td>-</td><td>USART3_CTS</td><td>-</td><td>CAN2_TX</td><td>OTG_HS_ULPI_D6</td><td>ETH_MII_TXD1ETH_RMII_TXD1</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PB14</td><td>-</td><td>TIM1_CH2N</td><td>-</td><td>TIM8_CH2N</td><td>-</td><td>SPI2_MISO</td><td>I2S2ext_SD</td><td>USART3_RTS</td><td>-</td><td>TIM12_CH1</td><td>-</td><td>-</td><td>OTG_HS_DM</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PB15</td><td>RTC_REFIN</td><td>TIM1_CH3N</td><td>-</td><td>TIM8_CH3N</td><td>-</td><td>SPI2_MOSI I2S2_SD</td><td>-</td><td>-</td><td>-</td><td>TIM12_CH2</td><td>-</td><td>-</td><td>OTG_HS_DP</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td rowspan="16">Port C</td><td>PC0</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>OTG_HS_ULPI_STP</td><td>-</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PC1</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>ETH_MDC</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PC2</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>SPI2_MISO</td><td>I2S2ext_SD</td><td>-</td><td>-</td><td>-</td><td>OTG_HS_ULPI_DIR</td><td>ETH_MII_TXD2</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PC3</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>SPI2_MOSI I2S2_SD</td><td>-</td><td>-</td><td>-</td><td>-</td><td>OTG_HS_ULPI_NXT</td><td>ETH_MII_TX_CLK</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PC4</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>ETH_MII_RXD0 ETH_RMII_RXD0</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PC5</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>ETH_MII_RXD1 ETH_RMII_RXD1</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PC6</td><td>-</td><td>-</td><td>TIM3_CH1</td><td>TIM8_CH1</td><td></td><td>I2S2_MCK</td><td></td><td>-</td><td>USART6_TX</td><td>-</td><td>-</td><td>-</td><td>SDIO_D6</td><td>DCMI_D0</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PC7</td><td>-</td><td>-</td><td>TIM3_CH2</td><td>TIM8_CH2</td><td>-</td><td>-</td><td>I2S3_MCK</td><td>-</td><td>USART6_RX</td><td>-</td><td>-</td><td>-</td><td>SDIO_D7</td><td>DCMI_D1</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PC8</td><td>-</td><td>-</td><td>TIM3_CH3</td><td>TIM8_CH3</td><td>-</td><td>-</td><td>-</td><td>-</td><td>USART6_CK</td><td>-</td><td>-</td><td>-</td><td>SDIO_D0</td><td>DCMI_D2</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PC9</td><td>MCO2</td><td>-</td><td>TIM3_CH4</td><td>TIM8_CH4</td><td>I2C3_SDA</td><td>I2S_CKIN</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>SDIO_D1</td><td>DCMI_D3</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PC10</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>SPI3_SCK/I2S3_CK</td><td>USART3_TX/</td><td>UART4_TX</td><td>-</td><td>-</td><td>-</td><td>SDIO_D2</td><td>DCMI_D8</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PC11</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>I2S3ext_SD</td><td>SPI3_MISO/</td><td>USART3_RX</td><td>UART4_RX</td><td>-</td><td>-</td><td>-</td><td>SDIO_D3</td><td>DCMI_D4</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PC12</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>SPI3_MOSI I2S3_SD</td><td>USART3_CK</td><td>UART5_TX</td><td>-</td><td>-</td><td>-</td><td>SDIO_CK</td><td>DCMI_D9</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PC13</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PC14</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PC15</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr></table>

![](images/59ec9210129f2bc1a3a188890403b0b7ece7b70f7f4199527bd2a7f8b826e93a.jpg)

Table 9. Alternate function mapping (continued)

<table><tr><td colspan="2" rowspan="2">Port</td><td>AF0</td><td>AF1</td><td>AF2</td><td>AF3</td><td>AF4</td><td>AF5</td><td>AF6</td><td>AF7</td><td>AF8</td><td>AF9</td><td>AF10</td><td>AF11</td><td>AF12</td><td>AF13</td><td rowspan="2">AF14</td><td rowspan="2">AF15</td></tr><tr><td>SYS</td><td>TIM1/2</td><td>TIM3/4/5</td><td>TIM8/9/10/11</td><td>I2C1/2/3</td><td>SPI1/SPI2/I2S2/I2S2ext</td><td>SPI3/I2Sext/I2S3</td><td>USART1/2/3/I2S3ext</td><td>UART4/5/USART6</td><td>CAN1/2 TIM12/13/14</td><td>OTG_FS/OTG_HS</td><td>ETH</td><td>FSMC/SDIO/OTG_FS</td><td>DCMI</td></tr><tr><td rowspan="16">Port D</td><td>PD0</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>CAN1_RX</td><td>-</td><td>-</td><td>FSMC_D2</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PD1</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>CAN1_TX</td><td>-</td><td>-</td><td>FSMC_D3</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PD2</td><td>-</td><td>-</td><td>TIM3_ETR</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>UART5_RX</td><td>-</td><td>-</td><td>-</td><td>SDIO_CMD</td><td>DCMI_D11</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PD3</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>USART2_CTS</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_CLK</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PD4</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>USART2_RTS</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_NOE</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PD5</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>USART2_TX</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_NWE</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PD6</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>USART2_RX</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_NWAIT</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PD7</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>USART2_CK</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_NE1/FSMC_NCE2</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PD8</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>USART3_TX</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_D13</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PD9</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>USART3_RX</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_D14</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PD10</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>USART3_CK</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_D15</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PD11</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>USART3_CTS</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A16</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PD12</td><td>-</td><td>-</td><td>TIM4_CH1</td><td>-</td><td>-</td><td>-</td><td>-</td><td>USART3_RTS</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A17</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PD13</td><td>-</td><td>-</td><td>TIM4_CH2</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A18</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PD14</td><td>-</td><td>-</td><td>TIM4_CH3</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_D0</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PD15</td><td>-</td><td>-</td><td>TIM4_CH4</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_D1</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td rowspan="16">Port E</td><td>PE0</td><td>-</td><td>-</td><td>TIM4_ETR</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_NBL0</td><td>DCMI_D2</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PE1</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_NBL1</td><td>DCMI_D3</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PE2</td><td>TRACECLK</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>ETH_MII_TXD3</td><td>FSMC_A23</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PE3</td><td>TRACED0</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A19</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PE4</td><td>TRACED1</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A20</td><td>DCMI_D4</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PE5</td><td>TRACED2</td><td>-</td><td>-</td><td>TIM9_CH1</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A21</td><td>DCMI_D6</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PE6</td><td>TRACED3</td><td>-</td><td>-</td><td>TIM9_CH2</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A22</td><td>DCMI_D7</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PE7</td><td>-</td><td>TIM1_ETR</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_D4</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PE8</td><td>-</td><td>TIM1_CH1N</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_D5</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PE9</td><td>-</td><td>TIM1_CH1</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_D6</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PE10</td><td>-</td><td>TIM1_CH2N</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_D7</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PE11</td><td>-</td><td>TIM1_CH2</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_D8</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PE12</td><td>-</td><td>TIM1_CH3N</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_D9</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PE13</td><td>-</td><td>TIM1_CH3</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_D10</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PE14</td><td>-</td><td>TIM1_CH4</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_D11</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PE15</td><td>-</td><td>TIM1_BKIN</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_D12</td><td>-</td><td>-</td><td>EVENTOUT</td></tr></table>

![](images/4bf0aec07360b7ef3b3bc0a0d4ec46835e6d0ec422f6ae0648c1d8c028db625f.jpg)

Table 9. Alternate function mapping (continued)

<table><tr><td colspan="2" rowspan="2">Port</td><td>AF0</td><td>AF1</td><td>AF2</td><td>AF3</td><td>AF4</td><td>AF5</td><td>AF6</td><td>AF7</td><td>AF8</td><td>AF9</td><td>AF10</td><td>AF11</td><td>AF12</td><td>AF13</td><td rowspan="2">AF14</td><td rowspan="2">AF15</td></tr><tr><td>SYS</td><td>TIM1/2</td><td>TIM3/4/5</td><td>TIM8/9/10/11</td><td>I2C1/2/3</td><td>SPI1/SPI2/I2S2/I2S2ext</td><td>SPI3/I2Sext/I2S3</td><td>USART1/2/3/I2S3ext</td><td>UART4/5/USART6</td><td>CAN1/2 TIM12/13/14</td><td>OTG_FS/OTG_HS</td><td>ETH</td><td>FSMC/SDIO/OTG_FS</td><td>DCMI</td></tr><tr><td rowspan="16">Port F</td><td>PF0</td><td>-</td><td>-</td><td>-</td><td>-</td><td>I2C2_SDA</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A0</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PF1</td><td>-</td><td>-</td><td>-</td><td>-</td><td>I2C2_SCL</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A1</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PF2</td><td>-</td><td>-</td><td>-</td><td>-</td><td>I2C2_SMBA</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A2</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PF3</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A3</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PF4</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A4</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PF5</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A5</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PF6</td><td>-</td><td>-</td><td>-</td><td>TIM10_CH1</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_NIORD</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PF7</td><td>-</td><td>-</td><td>-</td><td>TIM11_CH1</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_NREG</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PF8</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>TIM13_CH1</td><td>-</td><td>-</td><td>FSMC_NIOWR</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PF9</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>TIM14_CH1</td><td>-</td><td>-</td><td>FSMC_CD</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PF10</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_INTR</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PF11</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td></td><td>DCMI_D12</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PF12</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A6</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PF13</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A7</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PF14</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A8</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PF15</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A9</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td rowspan="16">Port G</td><td>PG0</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A10</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PG1</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A11</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PG2</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A12</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PG3</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A13</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PG4</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A14</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PG5</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_A15</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PG6</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_INT2</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PG7</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>USART6_CK</td><td>-</td><td>-</td><td>-</td><td>FSMC_INT3</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PG8</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>USART6_RTS</td><td>-</td><td>-</td><td>ETH_PPS_OUT</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PG9</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>USART6_RX</td><td>-</td><td>-</td><td>-</td><td>FSMC_NE2/FSMC_NCE3</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PG10</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>FSMC_NCE4_1/FSMC_NE3</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PG11</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>ETH_MII_TX_ENETH_RMII_TX_EN</td><td>FSMC_NCE4_2</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PG12</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>USART6_RTS</td><td>-</td><td>-</td><td>-</td><td>FSMC_NE4</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PG13</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>UART6_CTS</td><td>-</td><td>-</td><td>ETH_MII_TXD0ETH_RMII_TXD0</td><td>FSMC_A24</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PG14</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>USART6_TX</td><td>-</td><td>-</td><td>ETH_MII_TXD1ETH_RMII_TXD1</td><td>FSMC_A25</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PG15</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>USART6_CTS</td><td>-</td><td>-</td><td>-</td><td>-</td><td>DCMI_D13</td><td>-</td><td>EVENTOUT</td></tr></table>

![](images/67ed5d9a1ae8d62b78ef9770e60757022e547d8f4eaf67292f200d67a790974d.jpg)

Table 9. Alternate function mapping (continued)

<table><tr><td colspan="2" rowspan="2">Port</td><td>AF0</td><td>AF1</td><td>AF2</td><td>AF3</td><td>AF4</td><td>AF5</td><td>AF6</td><td>AF7</td><td>AF8</td><td>AF9</td><td>AF10</td><td>AF11</td><td>AF12</td><td>AF13</td><td rowspan="2">AF14</td><td rowspan="2">AF15</td></tr><tr><td>SYS</td><td>TIM1/2</td><td>TIM3/4/5</td><td>TIM8/9/10/11</td><td>I2C1/2/3</td><td>SPI1/SPI2/I2S2/I2S2ext</td><td>SPI3/I2Sext/I2S3</td><td>USART1/2/3/I2S3ext</td><td>UART4/5/USART6</td><td>CAN1/2 TIM12/13/14</td><td>OTG_FS/OTG_HS</td><td>ETH</td><td>FSMC/SDIO/OTG_FS</td><td>DCMI</td></tr><tr><td rowspan="16">PortH</td><td>PH0</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PH1</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PH2</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>ETH_MII_CRS</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PH3</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>ETH_MII_COL</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PH4</td><td>-</td><td>-</td><td>-</td><td>-</td><td>I2C2_SCL</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>OTG_HS_ULPI_NXT</td><td>-</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PH5</td><td>-</td><td>-</td><td>-</td><td>-</td><td>I2C2_SDA</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PH6</td><td>-</td><td>-</td><td>-</td><td>-</td><td>I2C2_SMBA</td><td>-</td><td>-</td><td>-</td><td>-</td><td>TIM12_CH1</td><td>-</td><td>ETH_MII_RXD2</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PH7</td><td>-</td><td>-</td><td>-</td><td>-</td><td>I2C3_SCL</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>ETH_MII_RXD3</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PH8</td><td>-</td><td>-</td><td>-</td><td>-</td><td>I2C3_SDA</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>DCMI_HSYNC</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PH9</td><td>-</td><td>-</td><td>-</td><td>-</td><td>I2C3_SMBA</td><td>-</td><td>-</td><td>-</td><td>-</td><td>TIM12_CH2</td><td>-</td><td>-</td><td>-</td><td>DCMI_D0</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PH10</td><td>-</td><td>-</td><td>TIM5_CH1</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>DCMI_D1</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PH11</td><td>-</td><td>-</td><td>TIM5_CH2</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>DCMI_D2</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PH12</td><td>-</td><td>-</td><td>TIM5_CH3</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>DCMI_D3</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PH13</td><td>-</td><td>-</td><td>-</td><td>TIM8_CH1N</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>CAN1_TX</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PH14</td><td>-</td><td>-</td><td>-</td><td>TIM8_CH2N</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>DCMI_D4</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PH15</td><td>-</td><td>-</td><td>-</td><td>TIM8_CH3N</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>DCMI_D11</td><td>-</td><td>EVENTOUT</td></tr><tr><td rowspan="12">Port I</td><td>PI0</td><td>-</td><td>-</td><td>TIM5_CH4</td><td>-</td><td>-</td><td>SPI2_NSS I2S2_WS</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>DCMI_D13</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PI1</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>SPI2_SCK I2S2_CK</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>DCMI_D8</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PI2</td><td>-</td><td>-</td><td>-</td><td>TIM8_CH4</td><td>-</td><td>SPI2_MISO</td><td>I2S2ext_SD</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>DCMI_D9</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PI3</td><td>-</td><td>-</td><td>-</td><td>TIM8_ETR</td><td>-</td><td>SPI2_MOSI I2S2_SD</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>DCMI_D10</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PI4</td><td>-</td><td>-</td><td>-</td><td>TIM8_BKIN</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>DCMI_D5</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PI5</td><td>-</td><td>-</td><td>-</td><td>TIM8_CH1</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>DCMI_VSYNC</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PI6</td><td>-</td><td>-</td><td>-</td><td>TIM8_CH2</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>DCMI_D6</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PI7</td><td>-</td><td>-</td><td>-</td><td>TIM8_CH3</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>DCMI_D7</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PI8</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr><tr><td>PI9</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>CAN1_RX</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PI10</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>ETH_MII_RX_ER</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr><tr><td>PI11</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>OTG_HS_ULPI_DIR</td><td>-</td><td>-</td><td>-</td><td>-</td><td>EVENTOUT</td></tr></table>

## 5 Memory mapping

The memory map is shown in Figure 18.

Figure 18. STM32F40xxx memory map
![](images/293353a431e10e808c03b534718e716d83b23754446e5da9a9d428467e2399d0.jpg)

<details>
<summary>flowchart</summary>

This diagram illustrates the data structure and memory allocation for an AI system, showing how various memory addresses are reserved, assigned to specific RAM blocks, and then assigned to specific storage modules.
</details>

Table 10. Register boundary addresses

<table><tr><td>Bus</td><td>Boundary address</td><td>Peripheral</td></tr><tr><td></td><td>0xE00F FFFF - 0xFFFF FFFF</td><td>Reserved</td></tr><tr><td>Cortex-M4</td><td>0xE000 0000 - 0xE00F FFFF</td><td>Cortex-M4 internal peripherals</td></tr><tr><td></td><td>0xA000 1000 - 0xDFFF FFFF</td><td>Reserved</td></tr><tr><td rowspan="5">AHB3</td><td>0xA000 0000 - 0xA000 0FFF</td><td>FSMC control register</td></tr><tr><td>0x9000 0000 - 0x9FFF FFFF</td><td>FSMC bank 4</td></tr><tr><td>0x8000 0000 - 0x8FFF FFFF</td><td>FSMC bank 3</td></tr><tr><td>0x7000 0000 - 0x7FFF FFFF</td><td>FSMC bank 2</td></tr><tr><td>0x6000 0000 - 0x6FFF FFFF</td><td>FSMC bank 1</td></tr><tr><td></td><td>0x5006 0C00- 0x5FFF FFFF</td><td>Reserved</td></tr><tr><td rowspan="3">AHB2</td><td>0x5006 0800 - 0x5006 0BFF</td><td>RNG</td></tr><tr><td>0x5005 0400 - 0x5006 07FF</td><td>Reserved</td></tr><tr><td>0x5005 0000 - 0x5005 03FF</td><td>DCMI</td></tr><tr><td></td><td>0x5004 0000- 0x5004 FFFF</td><td>Reserved</td></tr><tr><td></td><td>0x5000 0000 - 0x5003 FFFF</td><td>USB OTG FS</td></tr><tr><td></td><td>0x4008 0000- 0x4FFF FFFF</td><td>Reserved</td></tr><tr><td rowspan="26">AHB1</td><td>0x4004 0000 - 0x4007 FFFF</td><td>USB OTG HS</td></tr><tr><td>0x4002 9400 - 0x4003 FFFF</td><td>Reserved</td></tr><tr><td>0x4002 9000 - 0x4002 93FF</td><td rowspan="5">ETHERNET MAC</td></tr><tr><td>0x4002 8C00 - 0x4002 8FFF</td></tr><tr><td>0x4002 8800 - 0x4002 8BFF</td></tr><tr><td>0x4002 8400 - 0x4002 87FF</td></tr><tr><td>0x4002 8000 - 0x4002 83FF</td></tr><tr><td>0x4002 6800 - 0x4002 7FFF</td><td>Reserved</td></tr><tr><td>0x4002 6400 - 0x4002 67FF</td><td>DMA2</td></tr><tr><td>0x4002 6000 - 0x4002 63FF</td><td>DMA1</td></tr><tr><td>0x4002 5000 - 0x4002 5FFF</td><td>Reserved</td></tr><tr><td>0x4002 4000 - 0x4002 4FFF</td><td>BKPSRAM</td></tr><tr><td>0x4002 3C00 - 0x4002 3FFF</td><td>Flash interface register</td></tr><tr><td>0x4002 3800 - 0x4002 3BFF</td><td>RCC</td></tr><tr><td>0x4002 3400 - 0x4002 37FF</td><td>Reserved</td></tr><tr><td>0x4002 3000 - 0x4002 33FF</td><td>CRC</td></tr><tr><td>0x4002 2400 - 0x4002 2FFF</td><td>Reserved</td></tr><tr><td>0x4002 2000 - 0x4002 23FF</td><td>GPIOI</td></tr><tr><td>0x4002 1C00 - 0x4002 1FFF</td><td>GPIOH</td></tr><tr><td>0x4002 1800 - 0x4002 1BFF</td><td>GPIOG</td></tr><tr><td>0x4002 1400 - 0x4002 17FF</td><td>GPIOF</td></tr><tr><td>0x4002 1000 - 0x4002 13FF</td><td>GPIOE</td></tr><tr><td>0x4002 0C00 - 0x4002 0FFF</td><td>GPIOD</td></tr><tr><td>0x4002 0800 - 0x4002 0BFF</td><td>GPIOC</td></tr><tr><td>0x4002 0400 - 0x4002 07FF</td><td>GPIOB</td></tr><tr><td>0x4002 0000 - 0x4002 03FF</td><td>GPIOA</td></tr><tr><td></td><td>0x4001 5800- 0x4001 FFFF</td><td>Reserved</td></tr><tr><td rowspan="17">APB2</td><td>0x4001 4C00 - 0x4001 57FF</td><td>Reserved</td></tr><tr><td>0x4001 4800 - 0x4001 4BFF</td><td>TIM11</td></tr><tr><td>0x4001 4400 - 0x4001 47FF</td><td>TIM10</td></tr><tr><td>0x4001 4000 - 0x4001 43FF</td><td>TIM9</td></tr><tr><td>0x4001 3C00 - 0x4001 3FFF</td><td>EXTI</td></tr><tr><td>0x4001 3800 - 0x4001 3BFF</td><td>SYSCFG</td></tr><tr><td>0x4001 3400 - 0x4001 37FF</td><td>Reserved</td></tr><tr><td>0x4001 3000 - 0x4001 33FF</td><td>SPI1</td></tr><tr><td>0x4001 2C00 - 0x4001 2FFF</td><td>SDIO</td></tr><tr><td>0x4001 2400 - 0x4001 2BFF</td><td>Reserved</td></tr><tr><td>0x4001 2000 - 0x4001 23FF</td><td>ADC1 - ADC2 - ADC3</td></tr><tr><td>0x4001 1800 - 0x4001 1FFF</td><td>Reserved</td></tr><tr><td>0x4001 1400 - 0x4001 17FF</td><td>USART6</td></tr><tr><td>0x4001 1000 - 0x4001 13FF</td><td>USART1</td></tr><tr><td>0x4001 0800 - 0x4001 0FFF</td><td>Reserved</td></tr><tr><td>0x4001 0400 - 0x4001 07FF</td><td>TIM8</td></tr><tr><td>0x4001 0000 - 0x4001 03FF</td><td>TIM1</td></tr><tr><td></td><td>0x4000 7800 - 0x4000 FFFF</td><td>Reserved</td></tr><tr><td rowspan="31">APB1</td><td>0x4000 7800 - 0x4000 7FFF</td><td>Reserved</td></tr><tr><td>0x4000 7400 - 0x4000 77FF</td><td>DAC</td></tr><tr><td>0x4000 7000 - 0x4000 73FF</td><td>PWR</td></tr><tr><td>0x4000 6C00 - 0x4000 6FFF</td><td>Reserved</td></tr><tr><td>0x4000 6800 - 0x4000 6BFF</td><td>CAN2</td></tr><tr><td>0x4000 6400 - 0x4000 67FF</td><td>CAN1</td></tr><tr><td>0x4000 6000 - 0x4000 63FF</td><td>Reserved</td></tr><tr><td>0x4000 5C00 - 0x4000 5FFF</td><td>I2C3</td></tr><tr><td>0x4000 5800 - 0x4000 5BFF</td><td>I2C2</td></tr><tr><td>0x4000 5400 - 0x4000 57FF</td><td>I2C1</td></tr><tr><td>0x4000 5000 - 0x4000 53FF</td><td>UART5</td></tr><tr><td>0x4000 4C00 - 0x4000 4FFF</td><td>UART4</td></tr><tr><td>0x4000 4800 - 0x4000 4BFF</td><td>USART3</td></tr><tr><td>0x4000 4400 - 0x4000 47FF</td><td>USART2</td></tr><tr><td>0x4000 4000 - 0x4000 43FF</td><td>I2S3ext</td></tr><tr><td>0x4000 3C00 - 0x4000 3FFF</td><td>SPI3 / I2S3</td></tr><tr><td>0x4000 3800 - 0x4000 3BFF</td><td>SPI2 / I2S2</td></tr><tr><td>0x4000 3400 - 0x4000 37FF</td><td>I2S2ext</td></tr><tr><td>0x4000 3000 - 0x4000 33FF</td><td>IWDG</td></tr><tr><td>0x4000 2C00 - 0x4000 2FFF</td><td>WWDG</td></tr><tr><td>0x4000 2800 - 0x4000 2BFF</td><td>RTC &amp; BKP Registers</td></tr><tr><td>0x4000 2400 - 0x4000 27FF</td><td>Reserved</td></tr><tr><td>0x4000 2000 - 0x4000 23FF</td><td>TIM14</td></tr><tr><td>0x4000 1C00 - 0x4000 1FFF</td><td>TIM13</td></tr><tr><td>0x4000 1800 - 0x4000 1BFF</td><td>TIM12</td></tr><tr><td>0x4000 1400 - 0x4000 17FF</td><td>TIM7</td></tr><tr><td>0x4000 1000 - 0x4000 13FF</td><td>TIM6</td></tr><tr><td>0x4000 0C00 - 0x4000 0FFF</td><td>TIM5</td></tr><tr><td>0x4000 0800 - 0x4000 0BFF</td><td>TIM4</td></tr><tr><td>0x4000 0400 - 0x4000 07FF</td><td>TIM3</td></tr><tr><td>0x4000 0000 - 0x4000 03FF</td><td>TIM2</td></tr></table>

## 6 Electrical characteristics

## 6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to $V_{SS}$ .

## 6.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are evaluated in the worst conditions of ambient temperature, supply voltage, and frequencies by tests in production on 100% of the devices with an ambient temperature at $T_{A} = 25\ ^{\circ}C$ and $T_{A} = T_{A}\max$ (given by the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ).

## 6.1.2 Typical values

Unless otherwise specified, typical data are based on $T_{A} = 25\;^{\circ}C$ , $V_{DD} = 3.3\;V$ (for the $1.8\;V \leq V_{DD} \leq 3.6\;V$ voltage range). They are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ).

## 6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

## 6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 19.

## 6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 20.

Figure 19. Pin loading conditions
![](images/8d917dac4aaf3515077279e152c6616c4c5b06f3f0122d8d00e93fa923c1698c.jpg)

<details>
<summary>text_image</summary>

C = 50 pF
MCU pin
</details>

MS19011V2

Figure 20. Pin input voltage
![](images/3f67a85257d891a4373c8b53a0ac5719cce0b6130d294ef93c9f7ef949c94df4.jpg)

<details>
<summary>text_image</summary>

MCU pin
VIN
</details>

MS19010V2

## 6.1.6 Power supply scheme

Figure 21. Power supply scheme
![](images/dfe61355a98e7b989a32cc536db2841c5aa7b1f3522c24d5c68697cea34c430c.jpg)

<details>
<summary>flowchart</summary>

This diagram illustrates the architecture and signal flow of a voltage regulator system, showing connections between components like VBAT, GPIOs, ADC, and various logic blocks like VDD, VSS, and VREF.
</details>

MS19911V3

1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.
2. To connect BYPASS\_REG and PDR\_ON pins, refer to Section 3.16: Voltage regulator and Table 3.15: Power supply supervisor.
3. The two 2.2 $\mu$ F ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF.
4. The 4.7 $\mu$ F ceramic capacitor must be connected to one of the $V_{DD}$ pin.
5. $V_{DDA}=V_{DD}$ and $V_{SSA}=V_{SS}$ .

## 6.1.7 Current consumption measurement

Figure 22. Current consumption measurement scheme
![](images/5f080a9339081b10008ae6ccb148ea04cec10b18e5b17ef10d07c171ca192978.jpg)

<details>
<summary>text_image</summary>

IDD_VBAT
VBAT
IDD
VDD
VDDA
</details>

ai14126

## 6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

Table 11. Voltage characteristics

<table><tr><td>Symbol</td><td>Ratings</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td> $V_{DD}-V_{SS}$ </td><td>External main supply voltage (including  $V_{DDA}, V_{DD}$ ) $^{(1)}$ </td><td>-0.3</td><td>4.0</td><td rowspan="3">V</td></tr><tr><td rowspan="2"> $V_{IN}$ </td><td>Input voltage on five-volt tolerant pin $^{(2)}$ </td><td> $V_{SS}-0.3$ </td><td> $V_{DD}+4$ </td></tr><tr><td>Input voltage on any other pin</td><td> $V_{SS}-0.3$ </td><td>4.0</td></tr><tr><td> $|\Delta V_{DDx}|$ </td><td>Variations between different  $V_{DD}$  power pins</td><td>-</td><td>50</td><td rowspan="2">mV</td></tr><tr><td> $|V_{SSX}-V_{SS}|$ </td><td>Variations between all the different ground pins including  $V_{REF-}$ </td><td>-</td><td>50</td></tr><tr><td> $V_{ESD(HBM)}$ </td><td>Electrostatic discharge voltage (human body model)</td><td colspan="2">see Section 6.3.14: Absolute maximum ratings (electrical sensitivity)</td><td></td></tr></table>

1. All main power ( $V_{DD}$ , $V_{DDA}$ ) and ground ( $V_{SS}$ , $V_{SSA}$ ) pins must always be connected to the external power supply, in the permitted range.
2. $V_{IN}$ maximum value must always be respected. Refer to Table 12 for the values of the maximum allowed injected current.

Table 12. Current characteristics

<table><tr><td>Symbol</td><td>Ratings</td><td>Max.</td><td>Unit</td></tr><tr><td> $I_{VDD}$ </td><td>Total current into  $V_{DD}$  power lines (source)(1)</td><td>240</td><td rowspan="7">mA</td></tr><tr><td> $I_{VSS}$ </td><td>Total current out of  $V_{SS}$  ground lines (sink)(1)</td><td>240</td></tr><tr><td rowspan="2"> $I_{IO}$ </td><td>Output current sunk by any I/O and control pin</td><td>25</td></tr><tr><td>Output current source by any I/Os and control pin</td><td>25</td></tr><tr><td rowspan="2"> $I_{INJ(PIN)}$ (2)</td><td>Injected current on five-volt tolerant I/O(3)</td><td>-5/+0</td></tr><tr><td>Injected current on any other pin(4)</td><td>±5</td></tr><tr><td> $\Sigma I_{INJ(PIN)}$ (4)</td><td>Total injected current (sum of all I/O and control pins)(5)</td><td>±25</td></tr></table>

1. All main power ( $V_{DD}$ , $V_{DDA}$ ) and ground ( $V_{SS}$ , $V_{SSA}$ ) pins must always be connected to the external power supply, in the permitted range.
2. Negative injection disturbs the analog performance of the device. See note in Section 6.3.21: 12-bit ADC characteristics.
3. Positive injection is not possible on these I/Os. A negative injection is induced by $V_{IN}<V_{SS}$ . $I_{INJ(PIN)}$ must never be exceeded. Refer to Table 11 for the values of the maximum allowed input voltage.
4. A positive injection is induced by $V_{IN}>V_{DD}$ while a negative injection is induced by $V_{IN}<V_{SS}$ . $I_{INJ(PIN)}$ must never be exceeded. Refer to Table 11 for the values of the maximum allowed input voltage.
5. When several inputs are submitted to a current injection, the maximum $\Sigma I_{INJ(PIN)}$ is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 13. Thermal characteristics

<table><tr><td>Symbol</td><td>Ratings</td><td>Value</td><td>Unit</td></tr><tr><td> $T_{STG}$ </td><td>Storage temperature range</td><td>-65 to +150</td><td>°C</td></tr><tr><td> $T_J$ </td><td>Maximum junction temperature</td><td>125</td><td>°C</td></tr></table>

## 6.3 Operating conditions

## 6.3.1 General operating conditions

Table 14. General operating conditions

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td rowspan="2"> $f_{HCLK}$ </td><td rowspan="2">Internal AHB clock frequency</td><td>VOS bit in PWR_CR register = 0(1)</td><td>0</td><td>-</td><td>144</td><td rowspan="4">MHz</td></tr><tr><td>VOS bit in PWR_CR register= 1</td><td>0</td><td>-</td><td>168</td></tr><tr><td> $f_{PCLK1}$ </td><td>Internal APB1 clock frequency</td><td>-</td><td>0</td><td>-</td><td>42</td></tr><tr><td> $f_{PCLK2}$ </td><td>Internal APB2 clock frequency</td><td>-</td><td>0</td><td>-</td><td>84</td></tr><tr><td> $V_{DD}$ </td><td>Standard operating voltage</td><td>-</td><td>1.8(2)</td><td>-</td><td>3.6</td><td>V</td></tr><tr><td rowspan="2"> $V_{DDA}^{(3)(4)}$ </td><td>Analog operating voltage(ADC limited to 1.2 M samples)</td><td rowspan="2">Must be the same potential as $V_{DD}^{(5)}$ </td><td>1.8(2)</td><td>-</td><td>2.4</td><td rowspan="2">V</td></tr><tr><td>Analog operating voltage(ADC limited to 1.4 M samples)</td><td>2.4</td><td>-</td><td>3.6</td></tr><tr><td> $V_{BAT}$ </td><td>Backup operating voltage</td><td>-</td><td>1.65</td><td>-</td><td>3.6</td><td>V</td></tr><tr><td rowspan="4"> $V_{12}$ </td><td rowspan="2">Regulator ON:1.2 V internal voltage on $V_{CAP\_1}/V_{CAP\_2}$  pins</td><td>VOS bit in PWR_CR register = 0(1)Max frequency 144MHz</td><td>1.08</td><td>1.14</td><td>1.20</td><td>V</td></tr><tr><td>VOS bit in PWR_CR register= 1Max frequency 168MHz</td><td>1.20</td><td>1.26</td><td>1.32</td><td>V</td></tr><tr><td rowspan="2">Regulator OFF:1.2 V external voltage must be supplied from external regulator on  $V_{CAP\_1}/V_{CAP\_2}$  pins</td><td>Max frequency 144MHz</td><td>1.10</td><td>1.14</td><td>1.20</td><td>V</td></tr><tr><td>Max frequency 168MHz</td><td>1.20</td><td>1.26</td><td>1.30</td><td>V</td></tr><tr><td rowspan="4"> $V_{IN}$ </td><td rowspan="2">Input voltage on RST and FT pins(6)</td><td>2 V ≤ $V_{DD}$  ≤ 3.6 V</td><td>-0.3</td><td>-</td><td>5.5</td><td rowspan="4">V</td></tr><tr><td> $V_{DD}$  ≤ 2 V</td><td>-0.3</td><td>-</td><td>5.2</td></tr><tr><td>Input voltage on TTa pins</td><td>-</td><td>-0.3</td><td>-</td><td> $V_{DDA}^{+}$ 0.3</td></tr><tr><td>Input voltage on B pin</td><td>-</td><td>-</td><td>-</td><td>5.5</td></tr><tr><td rowspan="6"> $P_{D}$ </td><td rowspan="6">Power dissipation at  $T_{A}$ = 85 °C for suffix 6 or  $T_{A}$ = 105 °C for suffix 7(7)</td><td>LQFP64</td><td>-</td><td>-</td><td>435</td><td rowspan="6">mW</td></tr><tr><td>LQFP100</td><td>-</td><td>-</td><td>465</td></tr><tr><td>LQFP144</td><td>-</td><td>-</td><td>500</td></tr><tr><td>LQFP176</td><td>-</td><td>-</td><td>526</td></tr><tr><td>UFBGA176</td><td>-</td><td>-</td><td>513</td></tr><tr><td>WLCSP90</td><td>-</td><td>-</td><td>543</td></tr><tr><td rowspan="4"> $T_{A}$ </td><td rowspan="2">Ambient temperature for 6 suffix version</td><td>Maximum power dissipation</td><td>-40</td><td>-</td><td>85</td><td rowspan="2">°C</td></tr><tr><td>Low-power dissipation(8)</td><td>-40</td><td>-</td><td>105</td></tr><tr><td rowspan="2">Ambient temperature for 7 suffix version</td><td>Maximum power dissipation</td><td>-40</td><td>-</td><td>105</td><td rowspan="2">°C</td></tr><tr><td>Low-power dissipation(8)</td><td>-40</td><td>-</td><td>125</td></tr><tr><td rowspan="2"> $T_{J}$ </td><td rowspan="2">Junction temperature range</td><td>6 suffix version</td><td>-40</td><td>-</td><td>105</td><td rowspan="2">°C</td></tr><tr><td>7 suffix version</td><td>-40</td><td>-</td><td>125</td></tr></table>

1. The average expected gain in power consumption when VOS = 0 compared to VOS = 1 is around 10% for the whole temperature range, when the system clock frequency is between 30 and 144 MHz.
2. $V_{DD}/V_{DDA}$ minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF).
3. When the ADC is used, refer to Table 67: ADC characteristics.
4. If $V_{REF+}$ pin is present, it must respect the following condition: $V_{DDA}-V_{REF+} < 1.2 V$ .
5. It is recommended to power $V_{DD}$ and $V_{DDA}$ from the same source. A maximum difference of 300 mV between $V_{DD}$ and $V_{DDA}$ can be tolerated during power-up and power-down operation.
6. To sustain a voltage higher than $V_{DD}+0.3$ , the internal pull-up and pull-down resistors must be disabled.
7. If $T_{A}$ is lower, higher $P_{D}$ values are allowed as long as $T_{J}$ does not exceed $T_{Jmax}$ .
8. In low-power dissipation state, $T_{A}$ can be extended to this range as long as $T_{J}$ does not exceed $T_{Jmax}$ .

Table 15. Limitations depending on the operating power supply range

<table><tr><td>Operating power supply range</td><td>ADC operation</td><td>Maximum flash memory access frequency with no wait state (fFlashmax)</td><td>Maximum flash memory access frequency with wait states(1) (2)</td><td>I/O operation</td><td>Clock output Frequency on I/O pins</td><td>Possible flash memory operations</td></tr><tr><td>VDD=1.8 to 2.1 V(3)</td><td>Conversion time up to 1.2 Msps</td><td>20 MHz(4)</td><td>160 MHz with 7 wait states</td><td>- Degraded speed performance- No I/O compensation</td><td>up to 30 MHz</td><td>8-bit erase and program operations only</td></tr><tr><td>VDD=2.1 to 2.4 V</td><td>Conversion time up to 1.2 Msps</td><td>22 MHz</td><td>168 MHz with 7 wait states</td><td>- Degraded speed performance- No I/O compensation</td><td>up to 30 MHz</td><td>16-bit erase and program operations</td></tr><tr><td>VDD=2.4 to 2.7 V</td><td>Conversion time up to 2.4 Msps</td><td>24 MHz</td><td>168 MHz with 6 wait states</td><td>- Degraded speed performance- I/O compensation works</td><td>up to 48 MHz</td><td>16-bit erase and program operations</td></tr><tr><td>VDD=2.7 to 3.6 V(5)</td><td>Conversion time up to 2.4 Msps</td><td>30 MHz</td><td>168 MHz with 5 wait states</td><td>- Full-speed operation- I/O compensation works</td><td>- up to 60 MHz when VDD=3.0 to 3.6 V- up to 48 MHz when VDD=2.7 to 3.0 V</td><td>32-bit erase and program operations</td></tr></table>

1. It applies only when code executed from flash memory access, when code executed from RAM, no wait state is required.
2. Thanks to the ART accelerator and the 128-bit flash memory, the number of wait states given here does not impact the execution speed from flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state program execution.
3. $V_{DD}/VDDA$ minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF).
4. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and power.
5. The voltage range for OTG USB FS can drop down to 2.7 V. However it is degraded between 2.7 and 3 V.

## 6.3.2 $V_{CAP\_1}/V_{CAP\_2}$ external capacitor

Stabilization for the main regulator is achieved by connecting an external capacitor $C_{EXT}$ to the $V_{CAP\_1}/V_{CAP\_2}$ pins. $C_{EXT}$ is specified in Table 16.

Figure 23. External capacitor $C_{EXT}$
![](images/a4622e3d581dbd7dd52900f5ae1f38865dfc2e108b858497527fd96d2625cc36.jpg)
1. Legend: ESR is the equivalent series resistance.

Table 16. $V_{CAP\_1}/V_{CAP\_2}$ operating conditions $^{(1)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td></tr><tr><td>CEXT</td><td>Capacitance of external capacitor</td><td>2.2 μF</td></tr><tr><td>ESR</td><td>ESR of external capacitor</td><td>&lt; 2 Ω</td></tr></table>

1. When bypassing the voltage regulator, the two 2.2 $\mu$ F $V_{CAP}$ capacitors are not required and should be replaced by two 100 nF decoupling capacitors.

## 6.3.3 Operating conditions at power-up / power-down (regulator ON)

Subject to general operating conditions for $T_{A}$ .

Table 17. Operating conditions at power-up / power-down (regulator ON)

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td rowspan="2"> $t_{VDD}$ </td><td> $V_{DD}$  rise time rate</td><td>20</td><td> $\infty$ </td><td rowspan="2"> $\mu s/V$ </td></tr><tr><td> $V_{DD}$  fall time rate</td><td>20</td><td> $\infty$ </td></tr></table>

## 6.3.4 Operating conditions at power-up / power-down (regulator OFF)

Subject to general operating conditions for $T_{A}$ .

Table 18. Operating conditions at power-up / power-down (regulator OFF) $^{(1)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td rowspan="2"> $t_{VDD}$ </td><td> $V_{DD}$  rise time rate</td><td>Power-up</td><td>20</td><td>∞</td><td rowspan="4">μs/V</td></tr><tr><td> $V_{DD}$  fall time rate</td><td>Power-down</td><td>20</td><td>∞</td></tr><tr><td rowspan="2"> $t_{VCAP}$ </td><td> $V_{CAP\_1}$  and  $V_{CAP\_2}$  rise time rate</td><td>Power-up</td><td>20</td><td>∞</td></tr><tr><td> $V_{CAP\_1}$  and  $V_{CAP\_2}$  fall time rate</td><td>Power-down</td><td>20</td><td>∞</td></tr></table>

1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when $V_{DD}$ reach below minimum value of $V_{12}$ .

## 6.3.5 Embedded reset and power control block characteristics

The parameters given in Table 19 are derived from tests performed under ambient temperature and $V_{DD}$ supply voltage conditions summarized in Table 14.

Table 19. Embedded reset and power control block characteristics

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td rowspan="16"> $V_{PVD}$ </td><td rowspan="16">Programmable voltage detector level selection</td><td>PLS[2:0]=000 (rising edge)</td><td>2.09</td><td>2.14</td><td>2.19</td><td>V</td></tr><tr><td>PLS[2:0]=000 (falling edge)</td><td>1.98</td><td>2.04</td><td>2.08</td><td>V</td></tr><tr><td>PLS[2:0]=001 (rising edge)</td><td>2.23</td><td>2.30</td><td>2.37</td><td>V</td></tr><tr><td>PLS[2:0]=001 (falling edge)</td><td>2.13</td><td>2.19</td><td>2.25</td><td>V</td></tr><tr><td>PLS[2:0]=010 (rising edge)</td><td>2.39</td><td>2.45</td><td>2.51</td><td>V</td></tr><tr><td>PLS[2:0]=010 (falling edge)</td><td>2.29</td><td>2.35</td><td>2.39</td><td>V</td></tr><tr><td>PLS[2:0]=011 (rising edge)</td><td>2.54</td><td>2.60</td><td>2.65</td><td>V</td></tr><tr><td>PLS[2:0]=011 (falling edge)</td><td>2.44</td><td>2.51</td><td>2.56</td><td>V</td></tr><tr><td>PLS[2:0]=100 (rising edge)</td><td>2.70</td><td>2.76</td><td>2.82</td><td>V</td></tr><tr><td>PLS[2:0]=100 (falling edge)</td><td>2.59</td><td>2.66</td><td>2.71</td><td>V</td></tr><tr><td>PLS[2:0]=101 (rising edge)</td><td>2.86</td><td>2.93</td><td>2.99</td><td>V</td></tr><tr><td>PLS[2:0]=101 (falling edge)</td><td>2.75</td><td>2.84</td><td>2.92</td><td>V</td></tr><tr><td>PLS[2:0]=110 (rising edge)</td><td>2.96</td><td>3.03</td><td>3.10</td><td>V</td></tr><tr><td>PLS[2:0]=110 (falling edge)</td><td>2.85</td><td>2.93</td><td>2.99</td><td>V</td></tr><tr><td>PLS[2:0]=111 (rising edge)</td><td>3.07</td><td>3.14</td><td>3.21</td><td>V</td></tr><tr><td>PLS[2:0]=111 (falling edge)</td><td>2.95</td><td>3.03</td><td>3.09</td><td>V</td></tr><tr><td> $V_{PVDhyst}^{(1)}$ </td><td>PVD hysteresis</td><td>-</td><td>-</td><td>100</td><td>-</td><td>mV</td></tr><tr><td rowspan="2"> $V_{POR/PDR}$ </td><td rowspan="2">Power-on/power-down reset threshold</td><td>Falling edge</td><td>1.60</td><td>1.68</td><td>1.76</td><td>V</td></tr><tr><td>Rising edge</td><td>1.64</td><td>1.72</td><td>1.80</td><td>V</td></tr><tr><td> $V_{PDRhyst}^{(1)}$ </td><td>PDR hysteresis</td><td>-</td><td>-</td><td>40</td><td>-</td><td>mV</td></tr><tr><td rowspan="2"> $V_{BOR1}$ </td><td rowspan="2">Brownout level 1 threshold</td><td>Falling edge</td><td>2.13</td><td>2.19</td><td>2.24</td><td>V</td></tr><tr><td>Rising edge</td><td>2.23</td><td>2.29</td><td>2.33</td><td>V</td></tr><tr><td rowspan="2"> $V_{BOR2}$ </td><td rowspan="2">Brownout level 2 threshold</td><td>Falling edge</td><td>2.44</td><td>2.50</td><td>2.56</td><td>V</td></tr><tr><td>Rising edge</td><td>2.53</td><td>2.59</td><td>2.63</td><td>V</td></tr><tr><td rowspan="2"> $V_{BOR3}$ </td><td rowspan="2">Brownout level 3 threshold</td><td>Falling edge</td><td>2.75</td><td>2.83</td><td>2.88</td><td>V</td></tr><tr><td>Rising edge</td><td>2.85</td><td>2.92</td><td>2.97</td><td>V</td></tr><tr><td> $V_{BORhyst}^{(1)}$ </td><td>BOR hysteresis</td><td>-</td><td>-</td><td>100</td><td>-</td><td>mV</td></tr><tr><td> $T_{RSTTEMPO}^{(1)(2)}$ </td><td>Reset temporization</td><td>-</td><td>0.5</td><td>1.5</td><td>3.0</td><td>ms</td></tr><tr><td> $I_{RUSH}^{(1)}$ </td><td>InRush current on voltage regulator power-on (POR or wakeup from Standby)</td><td>-</td><td>-</td><td>160</td><td>200</td><td>mA</td></tr><tr><td> $E_{RUSH}^{(1)}$ </td><td>InRush energy on voltage regulator power-on (POR or wakeup from Standby)</td><td> $V_{DD} = 1.8 \text{ V}, T_{A} = 105 \text{ }^{\circ}\text{C}, I_{RUSH} = 171 \text{ mA for } 31 \mu\text{s}$ </td><td>-</td><td>-</td><td>5.4</td><td> $\mu\text{C}$ </td></tr></table>

1. Specified by design.
2. The reset temporization is measured from the power-on (POR reset or wakeup from $V_{BAT}$ ) to the instant when first instruction is read by the user application code.

## 6.3.6 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in Figure 22: Current consumption measurement scheme.

All Run mode current consumption measurements given in this section are performed using a CoreMark-compliant code.

## Typical and maximum current consumption

The MCU is placed under the following conditions:

- At startup, all I/O pins are configured as analog inputs by firmware.
- All peripherals are disabled except if it is explicitly mentioned.
- The flash memory access time is adjusted to $f_{HCLK}$ frequency (0 wait state from 0 to 30 MHz, 1 wait state from 30 to 60 MHz, 2 wait states from 60 to 90 MHz, 3 wait states from 90 to 120 MHz, 4 wait states from 120 to 150 MHz, and 5 wait states from 150 to 168 MHz).
- When the peripherals are enabled HCLK is the system clock, $f_{PCLK1} = f_{HCLK}/4$ , and $f_{PCLK2} = f_{HCLK}/2$ , except is explicitly mentioned.
- The maximum values are obtained for $V_{DD} = 3.6 \, \text{V}$ and maximum ambient temperature ( $T_A$ ), and the typical values for $T_A = 25 \, ^\circ\text{C}$ and $V_{DD} = 3.3 \, \text{V}$ unless otherwise specified.

Table 20. Typical and maximum current consumption in Run mode, code with data processing running from flash memory (ART accelerator enabled) or RAM (1)

<table><tr><td rowspan="2">Symbol</td><td rowspan="2">Parameter</td><td rowspan="2">Conditions</td><td rowspan="2">fHCLK</td><td>Typ</td><td colspan="2">Max(2)</td><td rowspan="2">Unit</td></tr><tr><td>TA=25°C</td><td>TA=85°C</td><td>TA=105°C</td></tr><tr><td rowspan="22">IDD</td><td rowspan="22">Supply current in Run mode</td><td rowspan="11">External clock(3), all peripherals enabled(4)(5)</td><td>168 MHz</td><td>87</td><td>102</td><td>109</td><td rowspan="22">mA</td></tr><tr><td>144 MHz</td><td>67</td><td>80</td><td>86</td></tr><tr><td>120 MHz</td><td>56</td><td>69</td><td>75</td></tr><tr><td>90 MHz</td><td>44</td><td>56</td><td>62</td></tr><tr><td>60 MHz</td><td>30</td><td>42</td><td>49</td></tr><tr><td>30 MHz</td><td>16</td><td>28</td><td>35</td></tr><tr><td>25 MHz</td><td>12</td><td>24</td><td>31</td></tr><tr><td>16 MHz(6)</td><td>9</td><td>20</td><td>28</td></tr><tr><td>8 MHz</td><td>5</td><td>17</td><td>24</td></tr><tr><td>4 MHz</td><td>3</td><td>15</td><td>22</td></tr><tr><td>2 MHz</td><td>2</td><td>14</td><td>21</td></tr><tr><td rowspan="11">External clock(3), all peripherals disabled(4)(5)</td><td>168 MHz</td><td>40</td><td>54</td><td>61</td></tr><tr><td>144 MHz</td><td>31</td><td>43</td><td>50</td></tr><tr><td>120 MHz</td><td>26</td><td>38</td><td>45</td></tr><tr><td>90 MHz</td><td>20</td><td>32</td><td>39</td></tr><tr><td>60 MHz</td><td>14</td><td>26</td><td>33</td></tr><tr><td>30 MHz</td><td>8</td><td>20</td><td>27</td></tr><tr><td>25 MHz</td><td>6</td><td>18</td><td>25</td></tr><tr><td>16 MHz(6)</td><td>5</td><td>16</td><td>24</td></tr><tr><td>8 MHz</td><td>3</td><td>15</td><td>22</td></tr><tr><td>4 MHz</td><td>2</td><td>14</td><td>21</td></tr><tr><td>2 MHz</td><td>2</td><td>14</td><td>21</td></tr></table>

1. Code and data processing running from SRAM1 using boot pins.
2. Evaluated by characterization, tested in production at $V_{DD}$ max and $f_{HCLK}$ max with peripherals enabled.
3. External clock is 4 MHz and PLL is on when $f_{HCLK} > 25$ MHz.
4. When the ADC is ON (ADON bit set in the ADC\_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part.
5. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered.
6. In this case HCLK = system clock/2.

Table 21. Typical and maximum current consumption in Run mode, code with data processing running from flash memory (ART accelerator disabled)

<table><tr><td rowspan="2">Symbol</td><td rowspan="2">Parameter</td><td rowspan="2">Conditions</td><td rowspan="2"> $f_{HCLK}$ </td><td>Typ</td><td colspan="2"> $Max^{(1)}$ </td><td rowspan="2">Unit</td></tr><tr><td> $T_A = 25 °C$ </td><td> $T_A = 85 °C$ </td><td> $T_A = 105 °C$ </td></tr><tr><td rowspan="22"> $I_{DD}$ </td><td rowspan="22">Supply current in Run mode</td><td rowspan="11">External  $clock^{(2)}$ , all peripherals  $enabled^{(3)(4)}$ </td><td>168 MHz</td><td>93</td><td>109</td><td>117</td><td rowspan="22">mA</td></tr><tr><td>144 MHz</td><td>76</td><td>89</td><td>96</td></tr><tr><td>120 MHz</td><td>67</td><td>79</td><td>86</td></tr><tr><td>90 MHz</td><td>53</td><td>65</td><td>73</td></tr><tr><td>60 MHz</td><td>37</td><td>49</td><td>56</td></tr><tr><td>30 MHz</td><td>20</td><td>32</td><td>39</td></tr><tr><td>25 MHz</td><td>16</td><td>27</td><td>35</td></tr><tr><td>16 MHz</td><td>11</td><td>23</td><td>30</td></tr><tr><td>8 MHz</td><td>6</td><td>18</td><td>25</td></tr><tr><td>4 MHz</td><td>4</td><td>16</td><td>23</td></tr><tr><td>2 MHz</td><td>3</td><td>15</td><td>22</td></tr><tr><td rowspan="11">External  $clock^{(2)}$ , all peripherals  $disabled^{(3)(4)}$ </td><td>168 MHz</td><td>46</td><td>61</td><td>69</td></tr><tr><td>144 MHz</td><td>40</td><td>52</td><td>60</td></tr><tr><td>120 MHz</td><td>37</td><td>48</td><td>56</td></tr><tr><td>90 MHz</td><td>30</td><td>42</td><td>50</td></tr><tr><td>60 MHz</td><td>22</td><td>33</td><td>41</td></tr><tr><td>30 MHz</td><td>12</td><td>24</td><td>31</td></tr><tr><td>25 MHz</td><td>10</td><td>21</td><td>29</td></tr><tr><td>16 MHz</td><td>7</td><td>19</td><td>26</td></tr><tr><td>8 MHz</td><td>4</td><td>16</td><td>23</td></tr><tr><td>4 MHz</td><td>3</td><td>15</td><td>22</td></tr><tr><td>2 MHz</td><td>2</td><td>14</td><td>21</td></tr></table>

1. Evaluated by characterization, tested in production at $V_{DD}$ max and $f_{HCLK}$ max with peripherals enabled.
2. External clock is 4 MHz and PLL is on when $f_{HCLK} > 25$ MHz.
3. When analog peripheral blocks such as (ADCs, DACs, HSE, LSE, HSI,LSI) are on, an additional power consumption should be considered.
4. When the ADC is ON (ADON bit set in the ADC\_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part.

Figure 24. Typical current consumption versus temperature, Run mode, code with data processing running from flash (ART accelerator ON) or RAM, and peripherals OFF
![](images/7b7a5734030a0893c56a173fc930224c1af947185637f9e49600ad17387e0706.jpg)

<details>
<summary>line</summary>

| CPU Frequency (MHz) | \(-45{}^{\circ}C (\)mA) | \(0{}^{\circ}C (\)mA) | \(25{}^{\circ}C (\)mA) | \(55{}^{\circ}C (\)mA) | \(85{}^{\circ}C (\)mA) | \(105{}^{\circ}C (\)mA) |
| --- | --- | --- | --- | --- | --- | --- |
| 0 | ~1.5 | ~1.5 | ~1.5 | ~2.0 | ~5.0 | ~8.0 |
| 25 | ~5.5 | ~5.5 | ~5.5 | ~6.0 | ~9.5 | ~12.0 |
| 168 | ~37.5 | ~37.5 | ~37.5 | ~39.0 | ~42.5 | ~45.0 |
</details>

MS19974V1

Figure 25. Typical current consumption versus temperature, Run mode, code with data processing running from flash (ART accelerator ON) or RAM, and peripherals ON
![](images/50bdc2ab03634fe8f7727a793262a082fd450cecab30e89353a69f2d77f314e5.jpg)

<details>
<summary>line</summary>

| CPU Frequency (MHz) | \(-45{}^{\circ}C (mA)\) | \(0{}^{\circ}C (mA)\) | \(25{}^{\circ}C (mA)\) | \(55{}^{\circ}C (mA)\) | \(85{}^{\circ}C (mA)\) | \(105{}^{\circ}C (mA)\) |
| --- | --- | --- | --- | --- | --- | --- |
| 0 | ~2 | ~2 | ~2 | ~5 | ~6 | ~8 |
| 25 | ~11 | ~11 | ~11 | ~14 | ~16 | ~18 |
| 168 | ~82 | ~83 | ~83 | ~87 | ~88 | ~90 |
</details>

MS19975V1

Figure 26. Typical current consumption versus temperature, Run mode, code with data processing running from flash (ART accelerator OFF) or RAM, and peripherals OFF
![](images/a6c1e923a70658fad791464659310f4bebc80ea88dd4f6aa22c7302ecf0c6c6e.jpg)

<details>
<summary>line</summary>

| CPU Frequency (MHz) | \(-45{}^{\circ}C (\)mA) | \(0{}^{\circ}C (\)mA) | \(25{}^{\circ}C (\)mA) | \(55{}^{\circ}C (\)mA) | \(85{}^{\circ}C (\)mA) | \(105{}^{\circ}C (\)mA) |
| --- | --- | --- | --- | --- | --- | --- |
| 0 | ~1.5 | ~1.5 | ~1.5 | ~2.0 | ~5.5 | ~8.0 |
| 25 | ~8.5 | ~8.5 | ~9.0 | ~10.0 | ~13.0 | ~15.5 |
| 50 | ~18.0 | ~18.0 | ~19.0 | ~20.0 | ~23.0 | ~26.0 |
| 75 | ~27.0 | ~27.0 | ~28.0 | ~29.0 | ~32.0 | ~35.0 |
| 100 | ~35.0 | ~35.0 | ~36.0 | ~37.0 | ~40.0 | ~43.0 |
| 125 | ~42.0 | ~42.0 | ~43.0 | ~44.0 | ~47.0 | ~50.0 |
| 150 | ~48.0 | ~48.0 | ~49.0 | ~50.0 | ~53.0 | ~56.0 |
| 170 | ~53.0 | ~53.0 | ~54.0 | ~55.0 | ~59.0 | ~62.0 |
</details>

MS19976V1

Figure 27. Typical current consumption versus temperature, Run mode, code with data processing running from flash (ART accelerator OFF) or RAM, and peripherals ON
![](images/03b58bc2be3335bbafa55fc07420e27f4b3f864cb60bd95695990e91f9f60c23.jpg)

<details>
<summary>line</summary>

| CPU Frequency (MHz) | \(-45{}^{\circ}C (\)mA) | \(0{}^{\circ}C (\)mA) | \(25{}^{\circ}C (\)mA) | \(55{}^{\circ}C (\)mA) | \(85{}^{\circ}C (\)mA) | \(105{}^{\circ}C (\)mA) |
| --- | --- | --- | --- | --- | --- | --- |
| 0 | ~2 | ~3 | ~4 | ~5 | ~6 | ~8 |
| 25 | ~14 | ~15 | ~16 | ~17 | ~18 | ~20 |
| 168 | ~88 | ~89 | ~90 | ~91 | ~95 | ~98 |
</details>

MS19977V1

Table 22. Typical and maximum current consumption in Sleep mode

<table><tr><td rowspan="2">Symbol</td><td rowspan="2">Parameter</td><td rowspan="2">Conditions</td><td rowspan="2"> $f_{HCLK}$ </td><td>Typ</td><td colspan="2"> $Max^{(1)}$ </td><td rowspan="2">Unit</td></tr><tr><td> $T_A = 25 °C$ </td><td> $T_A = 85 °C$ </td><td> $T_A = 105 °C$ </td></tr><tr><td rowspan="22"> $I_{DD}$ </td><td rowspan="22">Supply current in Sleep mode</td><td rowspan="11">External  $clock^{(2)}$ , all peripherals  $enabled^{(3)}$ </td><td>168 MHz</td><td>59</td><td>77</td><td>84</td><td rowspan="22">mA</td></tr><tr><td>144 MHz</td><td>46</td><td>61</td><td>67</td></tr><tr><td>120 MHz</td><td>38</td><td>53</td><td>60</td></tr><tr><td>90 MHz</td><td>30</td><td>44</td><td>51</td></tr><tr><td>60 MHz</td><td>20</td><td>34</td><td>41</td></tr><tr><td>30 MHz</td><td>11</td><td>24</td><td>31</td></tr><tr><td>25 MHz</td><td>8</td><td>21</td><td>28</td></tr><tr><td>16 MHz</td><td>6</td><td>18</td><td>25</td></tr><tr><td>8 MHz</td><td>3</td><td>16</td><td>23</td></tr><tr><td>4 MHz</td><td>2</td><td>15</td><td>22</td></tr><tr><td>2 MHz</td><td>2</td><td>14</td><td>21</td></tr><tr><td rowspan="11">External  $clock^{(2)}$ , all peripherals disabled</td><td>168 MHz</td><td>12</td><td>27</td><td>35</td></tr><tr><td>144 MHz</td><td>9</td><td>22</td><td>29</td></tr><tr><td>120 MHz</td><td>8</td><td>20</td><td>28</td></tr><tr><td>90 MHz</td><td>7</td><td>19</td><td>26</td></tr><tr><td>60 MHz</td><td>5</td><td>17</td><td>24</td></tr><tr><td>30 MHz</td><td>3</td><td>16</td><td>23</td></tr><tr><td>25 MHz</td><td>2</td><td>15</td><td>22</td></tr><tr><td>16 MHz</td><td>2</td><td>14</td><td>21</td></tr><tr><td>8 MHz</td><td>1</td><td>14</td><td>21</td></tr><tr><td>4 MHz</td><td>1</td><td>13</td><td>21</td></tr><tr><td>2 MHz</td><td>1</td><td>13</td><td>21</td></tr></table>

1. Evaluated by characterization, tested in production at $V_{DD}$ max and $f_{HCLK}$ max with peripherals enabled.
2. External clock is 4 MHz and PLL is on when $f_{HCLK} > 25$ MHz.
3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC\_CR2 register).

Table 23. Typical and maximum current consumptions in Stop mode

<table><tr><td rowspan="2">Symbol</td><td rowspan="2">Parameter</td><td rowspan="2">Conditions</td><td>Typ</td><td colspan="3">Max</td><td rowspan="2">Unit</td></tr><tr><td> $T_A$ =25°C</td><td> $T_A$ =25°C</td><td> $T_A$ =85°C</td><td> $T_A$ =105°C</td></tr><tr><td rowspan="4"> $I_{DD\_STOP}$ </td><td rowspan="2">Supply current in Stop mode with main regulator in Run mode</td><td>Flash in Stop mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog)</td><td>0.45</td><td>1.5</td><td>11.00</td><td>20.00</td><td rowspan="4">mA</td></tr><tr><td>Flash in Deep power-down mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog)</td><td>0.40</td><td>1.5</td><td>11.00</td><td>20.00</td></tr><tr><td rowspan="2">Supply current in Stop mode with main regulator in Low-power mode</td><td>Flash in Stop mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog)</td><td>0.31</td><td>1.1</td><td>8.00</td><td>15.00</td></tr><tr><td>Flash in Deep power-down mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog)</td><td>0.28</td><td>1.1</td><td>8.00</td><td>15.00</td></tr></table>

Table 24. Typical and maximum current consumptions in Standby mode

<table><tr><td rowspan="3">Symbol</td><td rowspan="3">Parameter</td><td rowspan="3">Conditions</td><td colspan="3">Typ</td><td colspan="2">Max(1)</td><td rowspan="3">Unit</td></tr><tr><td colspan="3">TA=25°C</td><td>TA=85°C</td><td>TA=105°C</td></tr><tr><td>VDD=1.8 V</td><td>VDD=2.4 V</td><td>VDD=3.3 V</td><td colspan="2">VDD=3.6 V</td></tr><tr><td rowspan="4">IDD_STBY</td><td rowspan="4">Supply current in Standby mode</td><td>Backup SRAM ON, low-speed oscillator and RTC ON</td><td>3.0</td><td>3.4</td><td>4.0</td><td>20</td><td>36</td><td rowspan="4">μA</td></tr><tr><td>Backup SRAM OFF, low-speed oscillator and RTC ON</td><td>2.4</td><td>2.7</td><td>3.3</td><td>16</td><td>32</td></tr><tr><td>Backup SRAM ON, RTC OFF</td><td>2.4</td><td>2.6</td><td>3.0</td><td>12.5</td><td>24.8</td></tr><tr><td>Backup SRAM OFF, RTC OFF</td><td>1.7</td><td>1.9</td><td>2.2</td><td>9.8</td><td>19.2</td></tr></table>

1. Evaluated by characterization - not tested in production.

Table 25. Typical and maximum current consumptions in $V_{BAT}$ mode

<table><tr><td rowspan="3">Symbol</td><td rowspan="3">Parameter</td><td rowspan="3">Conditions</td><td colspan="3">Typ</td><td colspan="2">Max(1)</td><td rowspan="3">Unit</td></tr><tr><td colspan="3">TA=25°C</td><td>TA=85°C</td><td>TA=105°C</td></tr><tr><td>VBAT=1.8 V</td><td>VBAT=2.4 V</td><td>VBAT=3.3 V</td><td colspan="2">VBAT=3.6 V</td></tr><tr><td rowspan="4">IDD_VBAT</td><td rowspan="4">Backup domain supply current</td><td>Backup SRAM ON, low-speed oscillator and RTC ON</td><td>1.29</td><td>1.42</td><td>1.68</td><td>6</td><td>11</td><td rowspan="4">μA</td></tr><tr><td>Backup SRAM OFF, low-speed oscillator and RTC ON</td><td>0.62</td><td>0.73</td><td>0.96</td><td>3</td><td>5</td></tr><tr><td>Backup SRAM ON, RTC OFF</td><td>0.79</td><td>0.81</td><td>0.86</td><td>5</td><td>10</td></tr><tr><td>Backup SRAM OFF, RTC OFF</td><td>0.10</td><td>0.10</td><td>0.10</td><td>2</td><td>4</td></tr></table>

1. Evaluated by characterization - not tested in production.

Figure 28. Typical $V_{BAT}$ current consumption (LSE and RTC ON/backup RAM OFF)
![](images/bfe171d0b0946a9c110fc59f7f16ce347fe5f103a4b6dde182090bfea841c045.jpg)

<details>
<summary>line</summary>

| Temperature \(({}^{\circ}C)\) | 1.65V | 1.8V | 2V | 2.4V | 2.7V | 3V | 3.3V | 3.6V |
| --- | --- | --- | --- | --- | --- | --- | --- | --- |
| 0 | ~0.55 | ~0.62 | ~0.65 | ~0.72 | ~0.85 | ~0.88 | ~0.92 | ~1.05 |
| 25 | ~0.58 | ~0.65 | ~0.68 | ~0.75 | ~0.88 | ~0.92 | ~0.95 | ~1.08 |
| 60 | ~0.75 | ~0.82 | ~0.85 | ~0.92 | ~1.05 | ~1.10 | ~1.18 | ~1.30 |
| 85 | ~1.20 | ~1.28 | ~1.32 | ~1.42 | ~1.55 | ~1.60 | ~1.72 | ~1.88 |
| 105 | ~2.20 | ~2.30 | ~2.35 | ~2.48 | ~2.60 | ~2.70 | ~2.85 | ~3.02 |
</details>

MS19990V1

Figure 29. Typical $V_{BAT}$ current consumption (LSE and RTC ON/backup RAM ON)
![](images/6a7e8547504f197542fe05eff28483b9f1a95ff2d867fe1e9c1d549671ac1aae.jpg)

<details>
<summary>line</summary>

| Temperature \(({}^{\circ}C)\) | 1.65V (µA) | 1.8V (µA) | 2V (µA) | 2.4V (µA) | 2.7V (µA) | 3V (µA) | 3.3V (µA) | 3.6V (µA) |
| --- | --- | --- | --- | --- | --- | --- | --- | --- |
| 0 | ~1.2 | ~1.3 | ~1.3 | ~1.4 | ~1.4 | ~1.5 | ~1.6 | ~1.7 |
| 25 | ~1.25 | ~1.3 | ~1.3 | ~1.4 | ~1.5 | ~1.6 | ~1.7 | ~1.8 |
| 60 | ~1.7 | ~1.75 | ~1.8 | ~1.85 | ~1.9 | ~2.0 | ~2.1 | ~2.2 |
| 85 | ~2.25 | ~2.7 | ~2.8 | ~2.9 | ~3.0 | ~3.1 | ~3.2 | ~3.3 |
| 105 | ~4.7 | ~4.7 | ~4.7 | ~4.8 | ~4.9 | ~5.1 | ~5.4 | ~5.6 |
</details>

MS19991V1

## Additional current consumption

The MCU is placed under the following conditions:

• All I/O pins are configured in analog mode.
- The flash memory access time is adjusted to $f_{HCLK}$ frequency.
- The voltage scaling is adjusted to $f_{HCLK}$ frequency as follows:
- Scale 2 for $f_{HCLK} \leq 144$ MHz
- Scale 1 for 144 MHz < f $_{HCLK}$ ≤ 168 MHz.
• The system clock is HCLK, $f_{PCLK1} = f_{HCLK}/4$ , and $f_{PCLK2} = f_{HCLK}/2$ .
• The HSE crystal clock frequency is 25 MHz.
- $T_{A}=25^{\circ}C.$

Table 26. Typical current consumption in Run mode, code with data processing running from flash memory, regulator ON (ART accelerator enabled except prefetch), $V_{DD} = 1.8 V^{(1)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td> $f_{HCLK}$  (MHz)</td><td>Typ. at  $T_A$ =25 °C</td><td>Unit</td></tr><tr><td rowspan="7">IDD</td><td rowspan="7">Supply current in Run mode</td><td rowspan="7">All peripheral disabled</td><td>160</td><td>36.2</td><td rowspan="7">mA</td></tr><tr><td>144</td><td>29.3</td></tr><tr><td>120</td><td>24.7</td></tr><tr><td>90</td><td>19.3</td></tr><tr><td>60</td><td>13.4</td></tr><tr><td>30</td><td>7.7</td></tr><tr><td>25</td><td>6.0</td></tr></table>

1. When peripherals are enabled, the power consumption corresponding to the analog part of the peripherals (such as ADC or DAC) is not included.

## I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as input with pull-up or pull-down generate current consumption when the pin is externally held to the opposite level. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 48: I/O static characteristics.

For the output pins, any internal or external pull-up or pull-down and external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see Table 28: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load internal and external connected to the pin:

$$
\mathrm{I} _ {\mathrm{SW}} = \mathrm{V} _ {\mathrm{DD}} \times \mathrm{f} _ {\mathrm{SW}} \times \mathrm{C}
$$

where

$I_{SW}$ is the current sunk by a switching I/O to charge/discharge the capacitive load

$V_{DD}$ is the MCU supply voltage

$f_{SW}$ is the I/O switching frequency

C is the total capacitance seen by the I/O pin: $C = C_{INT} + C_{EXT}$

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

Table 27. Switching output I/O current consumption

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions(1)</td><td>I/O toggling frequency (fSW)</td><td>Typ</td><td>Unit</td></tr><tr><td rowspan="25">IDDIO</td><td rowspan="25">I/O switching current</td><td rowspan="5">VDD=3.3 V(2)C=CINT</td><td>2 MHz</td><td>0.02</td><td rowspan="25">mA</td></tr><tr><td>8 MHz</td><td>0.14</td></tr><tr><td>25 MHz</td><td>0.51</td></tr><tr><td>50 MHz</td><td>0.86</td></tr><tr><td>60 MHz</td><td>1.30</td></tr><tr><td rowspan="5">VDD=3.3 VCEXT=0 pFC=CINT+CEXT+CS</td><td>2 MHz</td><td>0.10</td></tr><tr><td>8 MHz</td><td>0.38</td></tr><tr><td>25 MHz</td><td>1.18</td></tr><tr><td>50 MHz</td><td>2.47</td></tr><tr><td>60 MHz</td><td>2.86</td></tr><tr><td rowspan="5">VDD=3.3 VCEXT=10 pFC=CINT+CEXT+CS</td><td>2 MHz</td><td>0.17</td></tr><tr><td>8 MHz</td><td>0.66</td></tr><tr><td>25 MHz</td><td>1.70</td></tr><tr><td>50 MHz</td><td>2.65</td></tr><tr><td>60 MHz</td><td>3.48</td></tr><tr><td rowspan="5">VDD=3.3 VCEXT=22 pFC=CINT+CEXT+CS</td><td>2 MHz</td><td>0.23</td></tr><tr><td>8 MHz</td><td>0.95</td></tr><tr><td>25 MHz</td><td>3.20</td></tr><tr><td>50 MHz</td><td>4.69</td></tr><tr><td>60 MHz</td><td>8.06</td></tr><tr><td rowspan="5">VDD=3.3 VCEXT=33 pFC=CINT+CEXT+CS</td><td>2 MHz</td><td>0.30</td></tr><tr><td>8 MHz</td><td>1.22</td></tr><tr><td>25 MHz</td><td>3.90</td></tr><tr><td>50 MHz</td><td>8.82</td></tr><tr><td>60 MHz</td><td>_(3)</td></tr></table>

1. $C_{S}$ is the PCB board capacitance including the pad pin. $C_{S} = 7$ pF (estimated value).
2. This test is performed by cutting the LQFP package pin (pad removal).
3. At 60 MHz, C maximum load is specified 30 pF.

## On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 28. The MCU is placed under the following conditions:

- At startup, all I/O pins are configured as analog pins by firmware.
• All peripherals are disabled unless otherwise mentioned
- The code is running from flash memory and the flash memory access time is equal to 5 wait states at 168 MHz.
- The code is running from flash memory and the flash memory access time is equal to 4 wait states at 144 MHz, and the power scale mode is set to 2.
• The ART accelerator is ON.
- The given value is calculated by measuring the difference of current consumption
– with all peripherals clocked off
– with one peripheral clocked on (with only the clock applied)
- When the peripherals are enabled: HCLK is the system clock, $f_{PCLK1} = f_{HCLK}/4$ , and $f_{PCLK2} = f_{HCLK}/2$ .
- The typical values are obtained for $V_{DD} = 3.3 \, \text{V}$ and $T_A = 25 \, ^\circ\text{C}$ , unless otherwise specified.

Table 28. Peripheral current consumption

<table><tr><td colspan="2" rowspan="2">Peripheral</td><td colspan="2"> $I_{DD}(Typ)^{(1)}$ </td><td rowspan="2">Unit</td></tr><tr><td>Scale1(up t 168 MHz)</td><td>Scale2(up to 144 MHz)</td></tr><tr><td rowspan="15">AHB1(up to 168 MHz)</td><td>GPIOA</td><td>2.70</td><td>2.40</td><td rowspan="15">μA/MHz</td></tr><tr><td>GPIOB</td><td>2.50</td><td>2.22</td></tr><tr><td>GPIOC</td><td>2.54</td><td>2.28</td></tr><tr><td>GPIOD</td><td>2.55</td><td>2.28</td></tr><tr><td>GPIOE</td><td>2.68</td><td>2.40</td></tr><tr><td>GPIOF</td><td>2.53</td><td>2.28</td></tr><tr><td>GPIOG</td><td>2.51</td><td>2.22</td></tr><tr><td>GPIOH</td><td>2.51</td><td>2.22</td></tr><tr><td>GPIOI</td><td>2.50</td><td>2.22</td></tr><tr><td>OTG_HS+ULPI</td><td>28.33</td><td>25.38</td></tr><tr><td>CRC</td><td>0.41</td><td>0.40</td></tr><tr><td>BKPSRAM</td><td>0.63</td><td>0.58</td></tr><tr><td>DMA1</td><td>37.44</td><td>33.58</td></tr><tr><td>DMA2</td><td>37.69</td><td>33.93</td></tr><tr><td>ETH_MACETH_MAC_TXETH_MAC_RXETH_MAC_PTP</td><td>20.43</td><td>18.39</td></tr><tr><td rowspan="3">AHB2(up to 168 MHz)</td><td>OTG_FS</td><td>26.45</td><td>26.67</td><td rowspan="3">μA/MHz</td></tr><tr><td>DCMI</td><td>5.87</td><td>5.35</td></tr><tr><td>RNG</td><td>1.50</td><td>1.67</td></tr><tr><td>AHB3(up to 168 MHz)</td><td>FSMC</td><td>12.46</td><td>11.31</td><td>μA/MHz</td></tr><tr><td colspan="2">Bus matrix(2)</td><td>13.10</td><td>11.81</td><td>μA/MHz</td></tr><tr><td rowspan="25">APB1(up to 42 MHz)</td><td>TIM2</td><td>16.71</td><td>16.50</td><td rowspan="25">μA/MHz</td></tr><tr><td>TIM3</td><td>12.33</td><td>11.94</td></tr><tr><td>TIM4</td><td>13.45</td><td>12.92</td></tr><tr><td>TIM5</td><td>17.14</td><td>16.58</td></tr><tr><td>TIM6</td><td>2.43</td><td>3.06</td></tr><tr><td>TIM7</td><td>2.43</td><td>2.22</td></tr><tr><td>TIM12</td><td>6.62</td><td>6.83</td></tr><tr><td>TIM13</td><td>5.05</td><td>5.47</td></tr><tr><td>TIM14</td><td>5.26</td><td>5.61</td></tr><tr><td>PWR</td><td>1.00</td><td>0.56</td></tr><tr><td>USART2</td><td>2.69</td><td>2.78</td></tr><tr><td>USART3</td><td>2.74</td><td>2.78</td></tr><tr><td>UART4</td><td>3.24</td><td>3.33</td></tr><tr><td>UART5</td><td>2.69</td><td>2.78</td></tr><tr><td>I2C1</td><td>2.67</td><td>2.50</td></tr><tr><td>I2C2</td><td>2.83</td><td>2.78</td></tr><tr><td>I2C3</td><td>2.81</td><td>2.78</td></tr><tr><td>SPI2</td><td>2.43</td><td>2.22</td></tr><tr><td>SPI3</td><td>2.43</td><td>2.22</td></tr><tr><td> $I2S2^{(3)}$ </td><td>2.43</td><td>2.22</td></tr><tr><td> $I2S3^{(3)}$ </td><td>2.26</td><td>2.22</td></tr><tr><td>CAN1</td><td>5.12</td><td>5.56</td></tr><tr><td>CAN2</td><td>4.81</td><td>5.28</td></tr><tr><td> $DAC^{(4)}$ </td><td>1.67</td><td>1.67</td></tr><tr><td>WWDG</td><td>1.00</td><td>0.83</td></tr><tr><td rowspan="13">APB2(up to 84 MHz)</td><td>SDIO</td><td>7.08</td><td>7.92</td><td rowspan="13">μA/MHz</td></tr><tr><td>TIM1</td><td>16.79</td><td>15.51</td></tr><tr><td>TIM8</td><td>17.88</td><td>16.53</td></tr><tr><td>TIM9</td><td>7.64</td><td>7.28</td></tr><tr><td>TIM10</td><td>4.89</td><td>4.82</td></tr><tr><td>TIM11</td><td>5.19</td><td>4.82</td></tr><tr><td> $ADC1^{(5)}$ </td><td>4.67</td><td>4.58</td></tr><tr><td> $ADC2^{(5)}$ </td><td>4.67</td><td>4.58</td></tr><tr><td> $ADC3^{(5)}$ </td><td>4.43</td><td>4.44</td></tr><tr><td>SPI1</td><td>1.32</td><td>1.39</td></tr><tr><td>USART1</td><td>3.51</td><td>3.72</td></tr><tr><td>USART6</td><td>3.55</td><td>3.75</td></tr><tr><td>SYSCFG</td><td>0.74</td><td>0.56</td></tr></table>

1. When the I/O compensation cell is ON, $I_{DD}$ typical value increases by 0.22 mA.
2. The BusMatrix is automatically active when at least one master is ON.
3. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI\_I2SCFGR register.
4. When the DAC is ON and EN1/2 bits are set in DAC\_CR register, add an additional power consumption of 0.8 mA per DAC channel for the analog part.
5. When the ADC is ON (ADON bit set in the ADC\_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part.

## 6.3.7 Wakeup time from low-power mode

The wakeup times given in Table 29 is measured on a wakeup phase with a 16 MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode:

- Stop or Standby mode: the clock source is the RC oscillator
- Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under ambient temperature and $V_{DD}$ supply voltage conditions summarized in Table 14.

Table 29. Low-power mode wakeup timings

<table><tr><td>Symbol</td><td>Parameter</td><td>Min(1)</td><td>Typ(1)</td><td>Max(1)</td><td>Unit</td></tr><tr><td> $t_{WUSLEEP}^{(2)}$ </td><td>Wakeup from Sleep mode</td><td>-</td><td>5</td><td>-</td><td>CPU clock cycle</td></tr><tr><td rowspan="4"> $t_{WUSTOP}^{(2)}$ </td><td>Wakeup from Stop mode (regulator in Run mode and flash memory in Stop mode)</td><td>-</td><td>13</td><td>-</td><td rowspan="4">μs</td></tr><tr><td>Wakeup from Stop mode (regulator in low-power mode and flash memory in Stop mode)</td><td>-</td><td>17</td><td>40</td></tr><tr><td>Wakeup from Stop mode (regulator in Run mode and flash memory in Deep power-down mode)</td><td>-</td><td>105</td><td>-</td></tr><tr><td>Wakeup from Stop mode (regulator in low-power mode and flash memory in Deep power-down mode)</td><td>-</td><td>110</td><td>-</td></tr><tr><td> $t_{WUSTDBY}^{(2)(3)}$ </td><td>Wakeup from Standby mode</td><td>260</td><td>375</td><td>480</td><td>μs</td></tr></table>

1. Evaluated by characterization - not tested in production.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.
3. $t_{WUSTDBY}$ minimum and maximum values are given at $105\ °C$ and $-45\ °C$ , respectively.

## 6.3.8 External clock source characteristics

## High-speed external user clock generated from an external source

The characteristics given in Table 30 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 14.

Table 30. High-speed external user clock characteristics

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td> $f_{HSE\_ext}$ </td><td>External user clock source frequency(1)</td><td rowspan="5">-</td><td>1</td><td>-</td><td>50</td><td>MHz</td></tr><tr><td> $V_{HSEH}$ </td><td>OSC_IN input pin high level voltage</td><td> $0.7V_{DD}$ </td><td>-</td><td> $V_{DD}$ </td><td rowspan="2">V</td></tr><tr><td> $V_{HSEL}$ </td><td>OSC_IN input pin low level voltage</td><td> $V_{SS}$ </td><td>-</td><td> $0.3V_{DD}$ </td></tr><tr><td> $t_{w(HSE)}$  $t_{w(HSE)}$ </td><td>OSC_IN high or low time(1)</td><td>5</td><td>-</td><td>-</td><td rowspan="2">ns</td></tr><tr><td> $t_{r(HSE)}$  $t_{f(HSE)}$ </td><td>OSC_IN rise or fall time(1)</td><td>-</td><td>-</td><td>10</td></tr><tr><td> $C_{in(HSE)}$ </td><td>OSC_IN input capacitance(1)</td><td>-</td><td>-</td><td>5</td><td>-</td><td>pF</td></tr><tr><td> $DuCy_{(HSE)}$ </td><td>Duty cycle</td><td>-</td><td>45</td><td>-</td><td>55</td><td>%</td></tr><tr><td> $I_L$ </td><td>OSC_IN Input leakage current</td><td> $V_{SS} \leq V_{IN} \leq V_{DD}$ </td><td>-</td><td>-</td><td>±1</td><td>μA</td></tr></table>

1. Specified by design.

## Low-speed external user clock generated from an external source

The characteristics given in Table 31 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 14.

Table 31. Low-speed external user clock characteristics

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td> $f_{LSE\_ext}$ </td><td>User External clock source frequency(1)</td><td rowspan="5">-</td><td>-</td><td>32.768</td><td>1000</td><td>kHz</td></tr><tr><td> $V_{LSEH}$ </td><td>OSC32_IN input pin high level voltage</td><td> $0.7V_{DD}$ </td><td>-</td><td> $V_{DD}$ </td><td rowspan="2">V</td></tr><tr><td> $V_{LSEL}$ </td><td>OSC32_IN input pin low level voltage</td><td> $V_{SS}$ </td><td>-</td><td> $0.3V_{DD}$ </td></tr><tr><td> $t_{w(LSE)}$  $t_{f(LSE)}$ </td><td>OSC32_IN high or low time(1)</td><td>450</td><td>-</td><td>-</td><td rowspan="2">ns</td></tr><tr><td> $t_{r(LSE)}$  $t_{f(LSE)}$ </td><td>OSC32_IN rise or fall time(1)</td><td>-</td><td>-</td><td>50</td></tr><tr><td> $C_{in(LSE)}$ </td><td>OSC32_IN input capacitance(1)</td><td>-</td><td>-</td><td>5</td><td>-</td><td>pF</td></tr><tr><td> $DuCy_{(LSE)}$ </td><td>Duty cycle</td><td>-</td><td>30</td><td>-</td><td>70</td><td>%</td></tr><tr><td> $I_{L}$ </td><td>OSC32_IN Input leakage current</td><td> $V_{SS} \leq V_{IN} \leq V_{DD}$ </td><td>-</td><td>-</td><td>±1</td><td>μA</td></tr></table>

1. Specified by design.

Figure 30. High-speed external clock source AC timing diagram
![](images/1c90f6801749a2310241fbe045787b5019d3af9e867e127df764cbf7e8a449b1.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph LR
  A["External clock source"] --> B["fHSE_ext"]
  B --> C["OSC_IN"]
  C --> D["STM32F"]
  D --> E["t_HSE"]
  E --> F["t_HSE_HSE"]
  F --> G["t_W(HSE)"]
  G --> H["t_W(HSE)"]
  H --> I["t_W(HSE)"]
  I --> J["t_HSE"]
  J --> K["t_HSE_HSE"]
  K --> L["t_HSE_HSE_HSE"]
  L --> M["t_HSE_HSE_HSE_HSE"]
  M --> N["t_HSE_HSE_HSE_HSE_HSE"]
  N --> O["t_HSE_HSE_HSE_HSE_HSE_HSE"]
  O --> P["t_HSE_HSE_HSE_HSE_HSE_HSE_HSE"]
  P --> Q["t_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE"]
  Q --> R["t_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE"]
  R --> S["t_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE"]
  S --> T["t_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE"]
  T --> U["t_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE"]
  U --> V["t_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE"]
  V --> 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_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE
```
</details>

Figure 31. Low-speed external clock source AC timing diagram
![](images/9ca8e529e2cce5d46f4d7e49e855b674ad3097c4838c2bbb1bd1abf3fb488c1c.jpg)

<details>
<summary>flowchart</summary>

This diagram illustrates the timing and signal flow of an external clock source (STM32F) in an oscilloscope system, showing the relationship between the clock signal, switching logic, and external clock output.
</details>

## High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 32. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Table 32. HSE 4-26 MHz oscillator characteristics (1)

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td> $f_{OSC\_IN}$ </td><td>Oscillator frequency</td><td>-</td><td>4</td><td>-</td><td>26</td><td>MHz</td></tr><tr><td> $R_F$ </td><td>Feedback resistor</td><td>-</td><td>-</td><td>200</td><td>-</td><td>kΩ</td></tr><tr><td> $G_m$ </td><td>Oscillator transconductance</td><td rowspan="2">Startup</td><td>5</td><td>-</td><td>-</td><td rowspan="2">mA/V</td></tr><tr><td> $G_{mcritmax}$ </td><td>Maximum critical crystal  $G_m$ </td><td>-</td><td>-</td><td>1</td></tr><tr><td> $t_{SU(HSE)}^{(2)}$ </td><td>Startup time</td><td> $V_{DD}$  is stabilized</td><td>-</td><td>2</td><td>-</td><td>ms</td></tr></table>

1. Specified by design.
2. Evaluated by characterization - not tested in production. $t_{\mathrm{SU(HSE)}}$ is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and can vary significantly with the crystal manufacturer

For $C_{L1}$ and $C_{L2}$ , it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 32). $C_{L1}$ and $C_{L2}$ are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of $C_{L1}$ and $C_{L2}$ . PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing $C_{L1}$ and $C_{L2}$ .

Note: For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 32. Typical application with an 8 MHz crystal
![](images/ad7f51ccef571914524024893120a8fe8ff1d410779b4116241ac59f425e0d97.jpg)

<details>
<summary>text_image</summary>

Resonator with
integrated capacitors
CL1
8 MHz
resonator
CL2
REXT(1)
OSC_IN
RF
OSC_OUT
Bias
controlled
gain
STM32F
fHSE
ai17530
</details>

1. $R_{EXT}$ value depends on the crystal characteristics.

## Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 33. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Table 33. LSE oscillator characteristics ( $f_{LSE} = 32.768$ kHz) (1)

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td>fOSC_IN</td><td>Oscillator frequency</td><td>-</td><td>-</td><td>32.768</td><td>-</td><td>kHz</td></tr><tr><td>RF</td><td>Feedback resistor</td><td>-</td><td>-</td><td>18.4</td><td>-</td><td>MΩ</td></tr><tr><td>IDD</td><td>LSE current consumption</td><td>-</td><td>-</td><td>-</td><td>1</td><td>μA</td></tr><tr><td>Gm</td><td>Oscillator transconductance</td><td rowspan="2">Startup</td><td>2.8</td><td>-</td><td>-</td><td rowspan="2">μA/V</td></tr><tr><td>Gmcritmax</td><td>Maximum critical crystal Gm</td><td>-</td><td>-</td><td>0.56</td></tr><tr><td>tSU(LSE)(2)</td><td>Startup time</td><td>VDD is stabilized</td><td>-</td><td>2</td><td>-</td><td>s</td></tr></table>

1. Specified by design.
2. Evaluated by characterization - not tested in production. $t_{SU(LSE)}$ is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

Note: For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 33. Typical application with a 32.768 kHz crystal
![](images/16fd8cd598b34779f64e9ac8a046af8c7600f1df663d21bd7690ce01510dd125.jpg)

<details>
<summary>text_image</summary>

Resonator with
integrated capacitors
C_L1
32.768 kHz
resonator
C_L2
OSC32_IN
RF
Bias
controlled gain
OSC32_OUT
f_LSE
STM32F
</details>

ai17531

## 6.3.9 Internal clock source characteristics

The parameters given in Table 34 and Table 35 are derived from tests performed under ambient temperature and $V_{DD}$ supply voltage conditions summarized in Table 14.

## High-speed internal (HSI) RC oscillator

Table 34. HSI oscillator characteristics (1)

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td> $f_{HSI}$ </td><td>Frequency</td><td>-</td><td>-</td><td>16</td><td>-</td><td>MHz</td></tr><tr><td rowspan="4"> $ACC_{HSI}$ </td><td>HSI user trimming  $step^{(2)}$ </td><td>-</td><td>-</td><td>-</td><td>1</td><td>%</td></tr><tr><td rowspan="3">Accuracy of the HSI oscillator</td><td> $T_A = -40 to 105 °C^{(3)}$ </td><td>-8</td><td>-</td><td>4.5</td><td>%</td></tr><tr><td> $T_A = -10 to 85 °C^{(3)}$ </td><td>-4</td><td>-</td><td>4</td><td>%</td></tr><tr><td> $T_A = 25 °C^{(4)}$ </td><td>-1</td><td>-</td><td>1</td><td>%</td></tr><tr><td> $t_{su(HSI)}^{(2)}$ </td><td>HSI oscillator startup time</td><td>-</td><td>-</td><td>2.2</td><td>4</td><td>μs</td></tr><tr><td> $I_{DD(HSI)}^{(2)}$ </td><td>HSI oscillator power consumption</td><td>-</td><td>-</td><td>60</td><td>80</td><td>μA</td></tr></table>

1. $V_{DD} = 3.3$ V, PLL OFF, $T_{A} = -40$ to $125 \, ^{\circ}C$ unless otherwise specified.
2. Specified by design.
3. Evaluated by characterization - not tested in production.
4. Factory calibrated, parts not soldered.

## Low-speed internal (LSI) RC oscillator

Table 35. LSI oscillator characteristics (1)

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td> $f_{LSI}^{(2)}$ </td><td>Frequency</td><td>17</td><td>32</td><td>47</td><td>kHz</td></tr><tr><td> $t_{su(LSI)}^{(3)}$ </td><td>LSI oscillator startup time</td><td>-</td><td>15</td><td>40</td><td>μs</td></tr><tr><td> $I_{DD(LSI)}^{(3)}$ </td><td>LSI oscillator power consumption</td><td>-</td><td>0.4</td><td>0.6</td><td>μA</td></tr></table>

1. $V_{DD} = 3 V, T_{A} = -40$ to $105^{\circ}C$ unless otherwise specified.
2. Evaluated by characterization - not tested in production.
3. Specified by design.

Figure 34. ACC $_{LSI}$ versus temperature
![](images/52a29acfb7d710f3f0f439c05e64ac18a6fca292e5e0145bd277d5c3eb97371f.jpg)

<details>
<summary>line</summary>

| Temperature \(({}^{\circ}C)\) | max (%) | avg (%) | min (%) |
| --- | --- | --- | --- |
| -45 | ~39 | ~3 | ~-33 |
| -35 | ~38 | ~3 | ~-32 |
| -25 | ~37 | ~3 | ~-31 |
| -15 | ~36 | ~3 | ~-30 |
| -5 | ~35 | ~3 | ~-29 |
| 5 | ~34 | ~3 | ~-28 |
| 15 | ~33 | ~3 | ~-27 |
| 25 | ~32 | ~3 | ~-26 |
| 35 | ~31 | ~2 | ~-26 |
| 45 | ~30 | ~2 | ~-26 |
| 55 | ~29 | ~1 | ~-26 |
| 65 | ~28 | ~1 | ~-26 |
| 75 | ~27 | ~0 | ~-26 |
| 85 | ~26 | ~0 | ~-26 |
| 95 | ~25 | ~-1 | ~-26 |
| 105 | ~23 | ~-2 | ~-27 |
</details>

MS19013V1

## 6.3.10 PLL characteristics

The parameters given in Table 36 and Table 37 are derived from tests performed under temperature and $V_{DD}$ supply voltage conditions summarized in Table 14.

Table 36. Main PLL characteristics

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td> $f_{PLL\_IN}$ </td><td>PLL input clock(1)</td><td>-</td><td>0.95(2)</td><td>1</td><td>2.10</td><td>MHz</td></tr><tr><td> $f_{PLL\_OUT}$ </td><td>PLL multiplier output clock</td><td>-</td><td>24</td><td>-</td><td>168</td><td>MHz</td></tr><tr><td> $f_{PLL48\_OUT}$ </td><td>48 MHz PLL multiplier output clock</td><td>-</td><td>-</td><td>48</td><td>75</td><td>MHz</td></tr><tr><td> $f_{VCO\_OUT}$ </td><td>PLL VCO output</td><td>-</td><td>100</td><td>-</td><td>432</td><td>MHz</td></tr><tr><td rowspan="2"> $t_{LOCK}$ </td><td rowspan="2">PLL lock time</td><td>VCO freq = 100 MHz</td><td>75</td><td>-</td><td>200</td><td rowspan="2">μs</td></tr><tr><td>VCO freq = 432 MHz</td><td>100</td><td>-</td><td>300</td></tr></table>

Table 36. Main PLL characteristics (continued)

<table><tr><td>Symbol</td><td>Parameter</td><td colspan="2">Conditions</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td rowspan="7">Jitter(3)</td><td rowspan="2">Cycle-to-cycle jitter</td><td rowspan="4">System clock 120 MHz</td><td>RMS</td><td>-</td><td>25</td><td>-</td><td rowspan="7">ps</td></tr><tr><td>peak to peak</td><td>-</td><td>±150</td><td>-</td></tr><tr><td rowspan="2">Period Jitter</td><td>RMS</td><td>-</td><td>15</td><td>-</td></tr><tr><td>peak to peak</td><td>-</td><td>±200</td><td>-</td></tr><tr><td>Main clock output (MCO) for RMII Ethernet</td><td colspan="2">Cycle to cycle at 50 MHz on 1000 samples</td><td>-</td><td>32</td><td>-</td></tr><tr><td>Main clock output (MCO) for MII Ethernet</td><td colspan="2">Cycle to cycle at 25 MHz on 1000 samples</td><td>-</td><td>40</td><td>-</td></tr><tr><td>Bit Time CAN jitter</td><td colspan="2">Cycle to cycle at 1 MHz on 1000 samples</td><td>-</td><td>330</td><td>-</td></tr><tr><td> $I_{DD(PLL)}^{(4)}$ </td><td>PLL power consumption on VDD</td><td colspan="2">VCO freq = 100 MHzVCO freq = 432 MHz</td><td>0.150.45</td><td>-</td><td>0.400.75</td><td>mA</td></tr><tr><td> $I_{DDA(PLL)}^{(4)}$ </td><td>PLL power consumption on VDDA</td><td colspan="2">VCO freq = 100 MHzVCO freq = 432 MHz</td><td>0.300.55</td><td>-</td><td>0.400.85</td><td>mA</td></tr></table>

1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S.
2. Specified by design.
3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
4. Evaluated by characterization - not tested in production.

Table 37. PLLI2S (audio PLL) characteristics

<table><tr><td>Symbol</td><td>Parameter</td><td colspan="2">Conditions</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td> $f_{\text{PLLI2S\_IN}}$ </td><td>PLLI2S input clock(1)</td><td colspan="2">-</td><td> $0.95^{(2)}$ </td><td>1</td><td>2.10</td><td>MHz</td></tr><tr><td> $f_{\text{PLLI2S\_OUT}}$ </td><td>PLLI2S multiplier output clock</td><td colspan="2">-</td><td>-</td><td>-</td><td>216</td><td>MHz</td></tr><tr><td> $f_{\text{VCO\_OUT}}$ </td><td>PLLI2S VCO output</td><td colspan="2">-</td><td>100</td><td>-</td><td>432</td><td>MHz</td></tr><tr><td rowspan="2"> $t_{\text{LOCK}}$ </td><td rowspan="2">PLLI2S lock time</td><td colspan="2">VCO freq = 100 MHz</td><td>75</td><td>-</td><td>200</td><td rowspan="2">μs</td></tr><tr><td colspan="2">VCO freq = 432 MHz</td><td>100</td><td>-</td><td>300</td></tr><tr><td rowspan="4"> $Jitter^{(3)}$ </td><td rowspan="3">Master  $I^2S$  clock jitter</td><td rowspan="2">Cycle to cycle at 12.288 MHz on 48KHz period, N=432, R=5</td><td>RMS</td><td>-</td><td>90</td><td>-</td><td></td></tr><tr><td>peak to peak</td><td>-</td><td>±280</td><td>-</td><td>ps</td></tr><tr><td colspan="2">Average frequency of 12.288 MHz N = 432, R = 5 on 1000 samples</td><td>-</td><td>90</td><td>-</td><td>ps</td></tr><tr><td>WS  $I^2S$  clock jitter</td><td colspan="2">Cycle to cycle at 48 KHz on 1000 samples</td><td>-</td><td>400</td><td>-</td><td>ps</td></tr><tr><td rowspan="2"> $I_{DD(PLL12S)}^{(4)}$ </td><td rowspan="2">PLLI2S power consumption on  $V_{DD}$ </td><td>VCO freq = 100 MHz</td><td>0.15</td><td rowspan="2">-</td><td>0.40</td><td colspan="2" rowspan="2">mA</td></tr><tr><td>VCO freq = 432 MHz</td><td>0.45</td><td colspan="2">0.75</td></tr><tr><td rowspan="2"> $I_{DDA(PLL12S)}^{(4)}$ </td><td rowspan="2">PLLI2S power consumption on  $V_{DDA}$ </td><td>VCO freq = 100 MHz</td><td>0.30</td><td rowspan="2">-</td><td>0.40</td><td colspan="2" rowspan="2">mA</td></tr><tr><td>VCO freq = 432 MHz</td><td>0.55</td><td colspan="2">0.85</td></tr></table>

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Specified by design.
3. Value given with main PLL running.
4. Evaluated by characterization - not tested in production.

## 6.3.11 PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 44: EMI characteristics for fHSE = 25 MH and fCPU = 168 MHz). It is available only on the main PLL.

Table 38. SSCG parameters constraint

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Typ</td><td>Max(1)</td><td>Unit</td></tr><tr><td> $f_{Mod}$ </td><td>Modulation frequency</td><td>-</td><td>-</td><td>10</td><td>KHz</td></tr><tr><td>md</td><td>Peak modulation depth</td><td>0.25</td><td>-</td><td>2</td><td>%</td></tr><tr><td>MODEPER * INCSTEP</td><td>-</td><td>-</td><td>-</td><td> $2^{15}-1$ </td><td>-</td></tr></table>

1. Specified by design.

## Equation 1

The frequency modulation period (MODEPER) is given by the equation below:

$$
\text {MODEPER} = \text {round} \left[ f _ {\text {PLL\_IN}} / \left(4 \times f _ {\text {Mod}}\right) \right]
$$

$f_{PLL\_IN}$ and $f_{Mod}$ must be expressed in Hz.

As an example:

If $f_{PLL\_IN} = 1$ MHz, and $f_{MOD} = 1$ kHz, the modulation depth (MODEPER) is given by equation 1:

$$
\text {MODEPER} = \text {round} \left[ 1 0 ^ {6} / \left(4 \times 1 0 ^ {3}\right) \right] = 2 5 0
$$

## Equation 2

Equation 2 allows to calculate the increment step (INCSTEP):

$$
\text {INCSTEP} = \text {round} \left[ \left(\left(2 ^ {1 5} - 1\right) \times \mathrm{md} \times \text {PLLN}\right) / (1 0 0 \times 5 \times \text {MODEPER}) \right]
$$

$f_{VCO\_OUT}$ must be expressed in MHz.

With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz):

$$
\text {INCSTEP} = \text {round} \left[ \left(\left(2 ^ {1 5} - 1\right) \times 2 \times 2 4 0\right) / (1 0 0 \times 5 \times 2 5 0) \right] = 1 2 6 \mathrm{md} (\text {quantitized})\%
$$

An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula:

$$
\mathrm{md} _ {\text {quantized}} \% = (\text {MODEPER} \times \text {INCSTEP} \times 100 \times 5) / ((2 ^ {15} - 1) \times \text {PLLN})
$$

As a result:

$$
\mathrm{md} _ {\text {quantized}} \% = (250 \times 126 \times 100 \times 5) / ((2 ^ {15} - 1) \times 240) = 2.002 \% (\text {peak})
$$

Figure 35 and Figure 36 show the main PLL output clock waveforms in center spread and down spread modes, where:

F0 is fPLL\_OUT nominal.

$T_{mode}$ is the modulation period.

md is the modulation depth.

Figure 35. PLL output clock waveforms in center spread mode
![](images/78286f73d9b316e0adb29e3c538060c6dccd1d4fe5ee3ee523f725680a73ba5f.jpg)

<details>
<summary>line</summary>

| Time | Frequency (PLL_OUT) |
| --- | --- |
| 0 | F0 |
| tmode | F0 |
| 2xtmode | F0 |
</details>

ai17291

Figure 36. PLL output clock waveforms in down spread mode
![](images/b5f04623f3ac2bb53bbf3bbaa351422730a9517b151d9c2754d6b5f82da1b53b.jpg)

<details>
<summary>line</summary>

| Time | Frequency (PLL_OUT) |
| --- | --- |
| 0 | F0 |
| tmode | F0 |
| 2xmode | F0 |
</details>

## 6.3.12 Memory characteristics

## Flash memory

The characteristics are given at $T_{A} = -40$ to $105\;^{\circ}C$ unless otherwise specified.

The devices are shipped to customers with the flash memory erased.

Table 39. Flash memory characteristics

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td rowspan="3"> $I_{DD}$ </td><td rowspan="3">Supply current</td><td>Write / Erase 8-bit mode,  $V_{DD} = 1.8$  V</td><td>-</td><td>5</td><td>-</td><td rowspan="3">mA</td></tr><tr><td>Write / Erase 16-bit mode,  $V_{DD} = 2.1$  V</td><td>-</td><td>8</td><td>-</td></tr><tr><td>Write / Erase 32-bit mode,  $V_{DD} = 3.3$  V</td><td>-</td><td>12</td><td>-</td></tr></table>

Table 40. Flash memory programming

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td> $Min^{(1)}$ </td><td>Typ</td><td> $Max^{(1)}$ </td><td>Unit</td></tr><tr><td> $t_{prog}$ </td><td>Word programming time</td><td>Program/erase parallelism (PSIZE) = x 8/16/32</td><td>-</td><td>16</td><td> $100^{(2)}$ </td><td>μs</td></tr><tr><td rowspan="3"> $t_{ERASE16KB}$ </td><td rowspan="3">Sector (16 KB) erase time</td><td>Program/erase parallelism (PSIZE) = x 8</td><td>-</td><td>400</td><td>800</td><td rowspan="3">ms</td></tr><tr><td>Program/erase parallelism (PSIZE) = x 16</td><td>-</td><td>300</td><td>600</td></tr><tr><td>Program/erase parallelism (PSIZE) = x 32</td><td>-</td><td>250</td><td>500</td></tr><tr><td rowspan="3"> $t_{ERASE64KB}$ </td><td rowspan="3">Sector (64 KB) erase time</td><td>Program/erase parallelism (PSIZE) = x 8</td><td>-</td><td>1200</td><td>2400</td><td rowspan="3">ms</td></tr><tr><td>Program/erase parallelism (PSIZE) = x 16</td><td>-</td><td>700</td><td>1400</td></tr><tr><td>Program/erase parallelism (PSIZE) = x 32</td><td>-</td><td>550</td><td>1100</td></tr><tr><td rowspan="3"> $t_{ERASE128KB}$ </td><td rowspan="3">Sector (128 KB) erase time</td><td>Program/erase parallelism (PSIZE) = x 8</td><td>-</td><td>2</td><td>4</td><td rowspan="3">s</td></tr><tr><td>Program/erase parallelism (PSIZE) = x 16</td><td>-</td><td>1.3</td><td>2.6</td></tr><tr><td>Program/erase parallelism (PSIZE) = x 32</td><td>-</td><td>1</td><td>2</td></tr><tr><td rowspan="3"> $t_{ME}$ </td><td rowspan="3">Mass erase time</td><td>Program/erase parallelism (PSIZE) = x 8</td><td>-</td><td>16</td><td>32</td><td rowspan="3">s</td></tr><tr><td>Program/erase parallelism (PSIZE) = x 16</td><td>-</td><td>11</td><td>22</td></tr><tr><td>Program/erase parallelism (PSIZE) = x 32</td><td>-</td><td>8</td><td>16</td></tr><tr><td rowspan="3"> $V_{prog}$ </td><td rowspan="3">Programming voltage</td><td>32-bit program operation</td><td>2.7</td><td>-</td><td>3.6</td><td>V</td></tr><tr><td>16-bit program operation</td><td>2.1</td><td>-</td><td>3.6</td><td>V</td></tr><tr><td>8-bit program operation</td><td>1.8</td><td>-</td><td>3.6</td><td>V</td></tr></table>

1. Evaluated by characterization - not tested in production.
2. The maximum programming time is measured after 100K erase operations.

Table 41. Flash memory programming with $V_{PP}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td> $Min^{(1)}$ </td><td>Typ</td><td> $Max^{(1)}$ </td><td>Unit</td></tr><tr><td> $t_{prog}$ </td><td>Double word programming</td><td rowspan="5"> $T_A=0 to +40 °C$  $V_{DD}=3.3 V$  $V_{PP}=8.5 V$ </td><td>-</td><td>16</td><td> $100^{(2)}$ </td><td>μs</td></tr><tr><td> $t_{ERASE16KB}$ </td><td>Sector (16 KB) erase time</td><td>-</td><td>230</td><td>-</td><td rowspan="3">ms</td></tr><tr><td> $t_{ERASE64KB}$ </td><td>Sector (64 KB) erase time</td><td>-</td><td>490</td><td>-</td></tr><tr><td> $t_{ERASE128KB}$ </td><td>Sector (128 KB) erase time</td><td>-</td><td>875</td><td>-</td></tr><tr><td> $t_{ME}$ </td><td>Mass erase time</td><td>-</td><td>6.9</td><td>-</td><td>s</td></tr><tr><td> $V_{prog}$ </td><td>Programming voltage</td><td>-</td><td>2.7</td><td>-</td><td>3.6</td><td>V</td></tr><tr><td> $V_{PP}$ </td><td> $V_{PP}$  voltage range</td><td>-</td><td>7</td><td>-</td><td>9</td><td>V</td></tr><tr><td> $I_{PP}$ </td><td>Minimum current sunk on the  $V_{PP}$  pin</td><td>-</td><td>10</td><td>-</td><td>-</td><td>mA</td></tr><tr><td> $t_{VPP}^{(3)}$ </td><td>Cumulative time during which  $V_{PP}$  is applied</td><td>-</td><td>-</td><td>-</td><td>1</td><td>hour</td></tr></table>

1. Specified by design.
2. The maximum programming time is measured after 100K erase operations.
3. $V_{PP}$ should only be connected during programming/erasing.

Table 42. Flash memory endurance and data retention

<table><tr><td rowspan="2">Symbol</td><td rowspan="2">Parameter</td><td rowspan="2">Conditions</td><td>Value</td><td rowspan="2">Unit</td></tr><tr><td>Min(1)</td></tr><tr><td rowspan="2">NEND</td><td rowspan="2">Endurance</td><td>TA=-40 to +85 °C (6 suffix versions)</td><td rowspan="2">10</td><td rowspan="2">kcycles</td></tr><tr><td>TA=-40 to +105 °C (7 suffix versions)</td></tr><tr><td rowspan="3">tRET</td><td rowspan="3">Data retention</td><td>1 kcycle(2) at TA=85 °C</td><td>30</td><td rowspan="3">Years</td></tr><tr><td>1 kcycle(2) at TA=105 °C</td><td>10</td></tr><tr><td>10 kcycles(2) at TA=55 °C</td><td>20</td></tr></table>

1. Evaluated by characterization - not tested in production.
2. Cycling performed over the whole temperature range.

## 6.3.13 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

## Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports), the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

- Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
- FTB: A burst of fast transient voltage (positive and negative) is applied to $V_{DD}$ and $V_{SS}$ through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 43. They are based on the EMS levels and classes defined in application note AN1709.

Table 43. EMS characteristics

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Level/Class</td></tr><tr><td> $V_{FESD}$ </td><td>Voltage limits to be applied on any I/O pin to induce a functional disturbance</td><td> $V_{DD} = 3.3 \text{ V, LQFP176, } T_{A} = +25 \, ^{\circ}\text{C}, f_{HCLK} = 168 \text{ MHz, conforms to IEC 61000-4-2}$ </td><td>2B</td></tr><tr><td> $V_{EFTB}$ </td><td>Fast transient voltage burst limits to be applied through 100 pF on  $V_{DD}$  and  $V_{SS}$  pins to induce a functional disturbance</td><td> $V_{DD} = 3.3 \text{ V, LQFP176, } T_{A} = +25 \, ^{\circ}\text{C}, f_{HCLK} = 168 \text{ MHz, conforms to IEC 61000-4-2}$ </td><td>4A</td></tr></table>

## Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter
- Unexpected reset
• Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

## Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading.

Table 44. EMI characteristics for $f_{HSE} = 25$ MH and $f_{CPU} = 168$ MHz

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Monitored frequency band</td><td>Value</td><td>Unit</td></tr><tr><td rowspan="8">SEMI</td><td rowspan="3">Peak(1)</td><td rowspan="4">VDD=3.3 V, TA=25 °C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running from flash memory with ART accelerator enabled</td><td>0.1 to 30 MHz</td><td>32</td><td rowspan="3">dBμV</td></tr><tr><td>30 to 130 MHz</td><td>25</td></tr><tr><td>130 MHz to 1GHz</td><td>29</td></tr><tr><td>Level(2)</td><td>0.1 MHz to 2 GHz</td><td>4</td><td>-</td></tr><tr><td rowspan="3">Peak(1)</td><td rowspan="4">VDD=3.3 V, TA=25 °C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running from flash memory with ART accelerator and PLL spread spectrum enabled</td><td>0.1 to 30 MHz</td><td>19</td><td rowspan="3">dBμV</td></tr><tr><td>30 to 130 MHz</td><td>16</td></tr><tr><td>130 MHz to 1GHz</td><td>18</td></tr><tr><td>Level(2)</td><td>0.1 MHz to 2 GHz</td><td>3.5</td><td>-</td></tr></table>

1. Refer to AN1709 "EMI radiated test" chapter.
2. Refer to AN1709 "EMI level classification" chapter.

## 6.3.14 Absolute maximum ratings (electrical sensitivity)

Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

## Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.

Table 45. ESD absolute maximum ratings

<table><tr><td>Symbol</td><td>Ratings</td><td>Conditions</td><td>Class</td><td>Maximum value(1)</td><td>Unit</td></tr><tr><td> $V_{ESD(HBM)}$ </td><td>Electrostatic discharge voltage (human body model)</td><td> $T_A = +25 °C$  conforming to JESD22-A114</td><td>2</td><td>2000(2)</td><td rowspan="2">V</td></tr><tr><td> $V_{ESD(CDM)}$ </td><td>Electrostatic discharge voltage (charge device model)</td><td> $T_A = +25 °C$  conforming to ANSI/ESDA/JEDEC JS-002</td><td>II</td><td>250</td></tr></table>

1. Evaluated by characterization - not tested in production.

2. On $V_{BAT}$ pin, $V_{ESD(HBM)}$ is limited to 1000 V.

## Static latchup

Two complementary static tests are required on six parts to assess the latchup performance:

• A supply overvoltage is applied to each power supply pin
- A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latchup standard.

Table 46. Electrical sensitivities

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Class</td></tr><tr><td>LU</td><td>Static latch-up class</td><td>$ T_{A}=+105\ ^{\circ}C $ conforming to JESD78A</td><td>II level A</td></tr></table>

## 6.3.15 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below $V_{SS}$ or above $V_{DD}$ (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

## Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of 5 $\mu$ A/+0 $\mu$ A range), or other functional failure (for example reset, oscillator frequency deviation).

Negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection.

The test results are given in Table 47.

Table 47. I/O current injection susceptibility

<table><tr><td rowspan="2">Symbol</td><td rowspan="2">Description</td><td colspan="2">Functional susceptibility</td><td rowspan="2">Unit</td></tr><tr><td>Negative injection</td><td>Positive injection</td></tr><tr><td rowspan="5"> $I_{INJ}^{(1)}$ </td><td>Injected current on BOOT0 pin</td><td>-0</td><td>NA</td><td rowspan="5">mA</td></tr><tr><td>Injected current on NRST pin</td><td>-0</td><td>NA</td></tr><tr><td>Injected current on PE2, PE3, PE4, PE5, PE6, PI8, PC13, PC14, PC15, PI9, PI10, PI11, PF0, PF1, PF2, PF3, PF4, PF5, PF10, PH0/OSC_IN, PH1/OSC_OUT, PC0, PC1, PC2, PC3, PB6, PB7, PB8, PB9, PE0, PE1, PI4, PI5, PI6, PI7, PDR_ON, BYPASS_REG</td><td>-0</td><td>NA</td></tr><tr><td>Injected current on all FT pins</td><td>-5</td><td>NA</td></tr><tr><td>Injected current on any other pin</td><td>-5</td><td>+5</td></tr></table>

1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

## 6.3.16 I/O port characteristics

## General input/output characteristics

Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under the conditions summarized in Table 14. All I/Os are CMOS and TTL compliant.

Note: For information on GPIO configuration, refer to application note AN4899 "STM32 GPIO configuration for hardware settings and low-power consumption" available from the ST website www.st.com.

Table 48. I/O static characteristics

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Typ</td><td>Max</td><td colspan="2">Unit</td></tr><tr><td rowspan="4"> $V_{IL}$ </td><td rowspan="2">FT, TTa and NRST I/O input low level voltage</td><td rowspan="2">1.7 V ≤ $V_{DD}$  ≤3.6 V</td><td>-</td><td>-</td><td> $0.3V_{DD}-0.04^{(1)}$ </td><td colspan="2" rowspan="8">V</td></tr><tr><td>-</td><td>-</td><td colspan="2"> $0.3V_{DD}^{(2)}$ </td></tr><tr><td rowspan="2">BOOT0 I/O input low level voltage</td><td>1.75 V ≤ $V_{DD}$  ≤3.6 V-40 °C≤ $T_A$ ≤105 °C</td><td>-</td><td>-</td><td colspan="2" rowspan="2"> $0.1V_{DD}-+0.1^{(1)}$ </td></tr><tr><td>1.7 V ≤ $V_{DD}$  ≤3.6 V0 °C≤ $T_A$ ≤105 °C</td><td>-</td><td colspan="2">-</td></tr><tr><td rowspan="4"> $V_{IH}$ </td><td rowspan="2">FT, TTa and NRST I/O input low level voltage</td><td rowspan="2">1.7 V ≤ $V_{DD}$  ≤3.6 V</td><td> $0.45V_{DD}+0.3^{(1)}$ </td><td>-</td><td colspan="2">-</td></tr><tr><td> $0.7V_{DD}^{(2)}$ </td><td>-</td><td colspan="2">-</td></tr><tr><td rowspan="2">BOOT0 I/O input low level voltage</td><td>1.75 V ≤ $V_{DD}$  ≤3.6 V-40 °C≤ $T_A$ ≤105 °C</td><td rowspan="2"> $0.17V_{DD}+0.7^{(1)}$ </td><td>-</td><td colspan="2">-</td></tr><tr><td>1.7 V ≤ $V_{DD}$  ≤3.6 V0 °C≤ $T_A$ ≤105 °C</td><td>-</td><td colspan="2">-</td></tr><tr><td rowspan="3"> $V_{HYS}$ </td><td colspan="2">FT, TTa and NRST I/O input hysteresis</td><td>1.7 V ≤ $V_{DD}$  ≤3.6 V</td><td> $10\%V_{DD}^{(3)}$ </td><td>-</td><td>-</td><td rowspan="3">V</td></tr><tr><td colspan="2" rowspan="2">BOOT0 I/O input hysteresis</td><td>1.75 V ≤ $V_{DD}$  ≤3.6 V-40 °C≤ $T_A$  ≤105 °C</td><td rowspan="2">0.1</td><td rowspan="2">-</td><td rowspan="2">-</td></tr><tr><td>1.7 V ≤ $V_{DD}$  ≤3.6 V0 °C≤ $T_A$  ≤105 °C</td></tr><tr><td rowspan="2"> $I_{Ikg}$ </td><td colspan="2">I/O input leakage current (4)</td><td> $V_{SS}$  ≤ $V_{IN}$  ≤ $V_{DD}$ </td><td>-</td><td>-</td><td>±1</td><td rowspan="2">μA</td></tr><tr><td colspan="2">I/O FT input leakage current (5)</td><td> $V_{IN}$ = 5 V</td><td>-</td><td>-</td><td>3</td></tr><tr><td rowspan="2"> $R_{PU}$ </td><td rowspan="2">Weak pull-up equivalent resistor(6)</td><td>All pins except for PA10 and PB12 (OTG_FS_ID, OTG_HS_ID)</td><td> $V_{IN}$ =  $V_{SS}$ </td><td>30</td><td>40</td><td>50</td><td rowspan="4">kΩ</td></tr><tr><td>PA10 and PB12 (OTG_FS_ID, OTG_HS_ID)</td><td>-</td><td>7</td><td>10</td><td>14</td></tr><tr><td rowspan="2"> $R_{PD}$ </td><td rowspan="2">Weak pull-down equivalent resistor(7)</td><td>All pins except for PA10 and PB12</td><td> $V_{IN}$ =  $V_{DD}$ </td><td>30</td><td>40</td><td>50</td></tr><tr><td>PA10 and PB12</td><td>-</td><td>7</td><td>10</td><td>14</td></tr><tr><td> $C_{IO}^{(8)}$ </td><td>I/O pin capacitance</td><td>-</td><td>-</td><td>-</td><td>5</td><td>-</td><td>pF</td></tr></table>

1. Specified by design.
2. Tested in production.
3. With a minimum of 200 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 47: I/O current injection susceptibility
5. To sustain a voltage higher than $V_{DD} + 0.3$ V, the internal pull-up/pull-down resistors must be disabled. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 47: I/O current injection susceptibility.
6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimum ( $\sim$ 10% order).
7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the series resistance is minimum (\~10% order).
8. Hysteresis voltage between Schmitt trigger switching levels. Evaluated by characterization - not tested in production.

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters.

## Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed $V_{OL}/V_{OH}$ ) except PC13, PC14 and PC15 which can sink or source up to ±3mA. When using the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2. In particular:

- The sum of the currents sourced by all the I/Os on $V_{DD}$ , plus the maximum Run consumption of the MCU sourced on $V_{DD}$ , cannot exceed the absolute maximum rating $I_{VDD}$ (see Table 12).
- The sum of the currents sunk by all the I/Os on $V_{SS}$ plus the maximum Run consumption of the MCU sunk on $V_{SS}$ cannot exceed the absolute maximum rating $I_{VSS}$ (see Table 12).

## Output voltage levels

Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under ambient temperature and $V_{DD}$ supply voltage conditions summarized in Table 14. All I/Os are CMOS and TTL compliant.

Table 49. Output voltage characteristics $^{(1)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td> $V_{OL}^{(2)}$ </td><td>Output low level voltage</td><td rowspan="2">CMOS port $I_{IO} = +8 mA$  $2.7 V < V_{DD} < 3.6 V$ </td><td>-</td><td>0.4</td><td rowspan="2">V</td></tr><tr><td> $V_{OH}^{(3)}$ </td><td>Output high level voltage</td><td> $V_{DD}-0.4$ </td><td>-</td></tr><tr><td> $V_{OL}^{(2)}$ </td><td>Output low level voltage</td><td rowspan="2">TTL port $I_{IO} = +8 mA$  $2.7 V < V_{DD} < 3.6 V$ </td><td>-</td><td>0.4</td><td rowspan="2">V</td></tr><tr><td> $V_{OH}^{(3)}$ </td><td>Output high level voltage</td><td>2.4</td><td>-</td></tr><tr><td> $V_{OL}^{(2)(4)}$ </td><td>Output low level voltage</td><td rowspan="2"> $I_{IO} = +20 mA$  $2.7 V < V_{DD} < 3.6 V$ </td><td>-</td><td>1.3</td><td rowspan="2">V</td></tr><tr><td> $V_{OH}^{(3)(4)}$ </td><td>Output high level voltage</td><td> $V_{DD}-1.3$ </td><td>-</td></tr><tr><td> $V_{OL}^{(2)(4)}$ </td><td>Output low level voltage</td><td rowspan="2"> $I_{IO} = +6 mA$  $2 V < V_{DD} < 2.7 V$ </td><td>-</td><td>0.4</td><td rowspan="2">V</td></tr><tr><td> $V_{OH}^{(3)(4)}$ </td><td>Output high level voltage</td><td> $V_{DD}-0.4$ </td><td>-</td></tr></table>

1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED).
2. The $I_{IO}$ current sunk by the device must always respect the absolute maximum rating specified in Table 12 and the sum of $I_{IO}$ (I/O ports and control pins) must not exceed $I_{VSS}$ .
3. The $I_{IO}$ current sourced by the device must always respect the absolute maximum rating specified in Table 12 and the sum of $I_{IO}$ (I/O ports and control pins) must not exceed $I_{VDD}$ .
4. Evaluated by characterization - not tested in production.

## Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 37 and Table 50, respectively.

Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under the ambient temperature and $V_{DD}$ supply voltage conditions summarized in Table 14.

Table 50. I/O AC characteristics $^{(1)(2)}$

<table><tr><td>OSPEEDRy [1:0] bit value(1)</td><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td rowspan="5">00</td><td rowspan="4"> $f_{max(IO)out}$ </td><td rowspan="4">Maximum frequency(3)</td><td> $C_L=50 pF, V_{DD}>2.70 V$ </td><td>-</td><td>-</td><td>4</td><td rowspan="4">MHz</td></tr><tr><td> $C_L=50 pF, V_{DD}>1.8 V$ </td><td>-</td><td>-</td><td>2</td></tr><tr><td> $C_L=10 pF, V_{DD}>2.70 V$ </td><td>-</td><td>-</td><td>8</td></tr><tr><td> $C_L=10 pF, V_{DD}>1.8 V$ </td><td>-</td><td>-</td><td>4</td></tr><tr><td> $t_{f(IO)out}/ t_{r(IO)out}$ </td><td>Output high to low level fall time and output low to high level rise time</td><td> $C_L=50 pF, V_{DD}=1.8 V to 3.6 V$ </td><td>-</td><td>-</td><td>100</td><td>ns</td></tr><tr><td rowspan="8">01</td><td rowspan="4"> $f_{max(IO)out}$ </td><td rowspan="4">Maximum frequency(3)</td><td> $C_L=50 pF, V_{DD}>2.70 V$ </td><td>-</td><td>-</td><td>25</td><td rowspan="4">MHz</td></tr><tr><td> $C_L=50 pF, V_{DD}>1.8 V$ </td><td>-</td><td>-</td><td>12.5</td></tr><tr><td> $C_L=10 pF, V_{DD}>2.70 V$ </td><td>-</td><td>-</td><td> $50^{(4)}$ </td></tr><tr><td> $C_L=10 pF, V_{DD}>1.8 V$ </td><td>-</td><td>-</td><td>20</td></tr><tr><td rowspan="4"> $t_{f(IO)out}/ t_{r(IO)out}$ </td><td rowspan="4">Output high to low level fall time and output low to high level rise time</td><td> $C_L=50 pF, V_{DD}>2.7 V$ </td><td>-</td><td>-</td><td>10</td><td rowspan="4">ns</td></tr><tr><td> $C_L=50 pF, V_{DD}>1.8 V$ </td><td>-</td><td>-</td><td>20</td></tr><tr><td> $C_L=10 pF, V_{DD}>2.70 V$ </td><td>-</td><td>-</td><td>6</td></tr><tr><td> $C_L=10 pF, V_{DD}>1.8 V$ </td><td>-</td><td>-</td><td>10</td></tr><tr><td rowspan="8">10</td><td rowspan="4"> $f_{max(IO)out}$ </td><td rowspan="4">Maximum frequency(3)</td><td> $C_L=40 pF, V_{DD}>2.70 V$ </td><td>-</td><td>-</td><td> $50^{(4)}$ </td><td rowspan="4">MHz</td></tr><tr><td> $C_L=40 pF, V_{DD}>1.8 V$ </td><td>-</td><td>-</td><td>25</td></tr><tr><td> $C_L=10 pF, V_{DD}>2.70 V$ </td><td>-</td><td>-</td><td> $100^{(4)}$ </td></tr><tr><td> $C_L=10 pF, V_{DD}>1.8 V$ </td><td>-</td><td>-</td><td> $50^{(4)}$ </td></tr><tr><td rowspan="4"> $t_{f(IO)out}/ t_{r(IO)out}$ </td><td rowspan="4">Output high to low level fall time and output low to high level rise time</td><td> $C_L=40 pF, V_{DD}>2.70 V$ </td><td>-</td><td>-</td><td>6</td><td rowspan="4">ns</td></tr><tr><td> $C_L=40 pF, V_{DD}>1.8 V$ </td><td>-</td><td>-</td><td>10</td></tr><tr><td> $C_L=10 pF, V_{DD}>2.70 V$ </td><td>-</td><td>-</td><td>4</td></tr><tr><td> $C_L=10 pF, V_{DD}>1.8 V$ </td><td>-</td><td>-</td><td>6</td></tr><tr><td rowspan="8">11</td><td rowspan="4"> $F_{max(IO)out}$ </td><td rowspan="4">Maximum frequency(3)</td><td> $C_L = 30 \text{ pF}, V_{DD} > 2.70 \text{ V}$ </td><td>-</td><td>-</td><td>100(4)</td><td rowspan="4">MHz</td></tr><tr><td> $C_L = 30 \text{ pF}, V_{DD} > 1.8 \text{ V}$ </td><td>-</td><td>-</td><td>50(4)</td></tr><tr><td> $C_L = 10 \text{ pF}, V_{DD} > 2.70 \text{ V}$ </td><td>-</td><td>-</td><td>180(4)</td></tr><tr><td> $C_L = 10 \text{ pF}, V_{DD} > 1.8 \text{ V}$ </td><td>-</td><td>-</td><td>100(4)</td></tr><tr><td rowspan="4"> $t_{f(IO)out}/t_{r(IO)out}$ </td><td rowspan="4">Output high to low level fall time and output low to high level rise time</td><td> $C_L = 30 \text{ pF}, V_{DD} > 2.70 \text{ V}$ </td><td>-</td><td>-</td><td>4</td><td rowspan="4">ns</td></tr><tr><td> $C_L = 30 \text{ pF}, V_{DD} > 1.8 \text{ V}$ </td><td>-</td><td>-</td><td>6</td></tr><tr><td> $C_L = 10 \text{ pF}, V_{DD} > 2.70 \text{ V}$ </td><td>-</td><td>-</td><td>2.5</td></tr><tr><td> $C_L = 10 \text{ pF}, V_{DD} > 1.8 \text{ V}$ </td><td>-</td><td>-</td><td>4</td></tr><tr><td>-</td><td> $t_{EXTIpw}$ </td><td>Pulse width of external signals detected by the EXTI controller</td><td>-</td><td>10</td><td>-</td><td>-</td><td>ns</td></tr></table>

1. Evaluated by characterization - not tested in production.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of the GPIOx\_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 37.
4. For maximum frequencies above 50 MHz, the compensation cell should be used.

Figure 37. I/O AC characteristics definition
![](images/9d5c904780c4be8acc13fa3941f5c79ce1c175dc33a49e44b490ebcb51c66f36.jpg)

<details>
<summary>line</summary>

| Parameter | Value |
| --- | --- |
| Peak-to-Peak (10%) | 10% |
| Peak-to-Peak (50%) | 50% |
| Peak-to-Peak (90%) | 90% |
| Peak-to-Peak (10%) | 10% |
| Peak-to-Peak (50%) | 50% |
| Peak-to-Peak (90%) | 90% |
| T (Time Interval) | tr(IO)out |
| T (Time Interval) | tf(IO)out |
</details>

Maximum frequency is achieved with a duty cycle at 45-55% when loaded by the specified capacitance

MSv75936V1

## 6.3.17 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, $R_{PU}$ (see Table 48).

Unless otherwise specified, the parameters given in Table 51 are derived from tests performed under the ambient temperature and $V_{DD}$ supply voltage conditions summarized in Table 14.

Table 51. NRST pin characteristics

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td> $V_{IL(NRST)}^{(1)}$ </td><td>NRST Input low level voltage</td><td rowspan="2">TTL ports $2.7\ V \leq V_{DD} \leq 3.6\ V$ </td><td>-</td><td>-</td><td>0.8</td><td rowspan="4">V</td></tr><tr><td> $V_{IH(NRST)}^{(1)}$ </td><td>NRST Input high level voltage</td><td>2</td><td>-</td><td>-</td></tr><tr><td> $V_{IL(NRST)}^{(1)}$ </td><td>NRST Input low level voltage</td><td rowspan="2">CMOS ports $1.8\ V \leq V_{DD} \leq 3.6\ V$ </td><td>-</td><td>-</td><td> $0.3V_{DD}$ </td></tr><tr><td> $V_{IH(NRST)}^{(1)}$ </td><td>NRST Input high level voltage</td><td> $0.7V_{DD}$ </td><td>-</td><td>-</td></tr><tr><td> $V_{hys(NRST)}$ </td><td>NRST Schmitt trigger voltage hysteresis</td><td>-</td><td>-</td><td>200</td><td>-</td><td>mV</td></tr><tr><td> $R_{PU}$ </td><td>Weak pull-up equivalent resistor $^{(2)}$ </td><td> $V_{IN} = V_{SS}$ </td><td>30</td><td>40</td><td>50</td><td>kΩ</td></tr><tr><td> $V_{F(NRST)}^{(1)}$ </td><td>NRST Input filtered pulse</td><td>-</td><td>-</td><td>-</td><td>100</td><td>ns</td></tr><tr><td> $V_{NF(NRST)}^{(1)}$ </td><td>NRST Input not filtered pulse</td><td> $V_{DD} > 2.7\ V$ </td><td>300</td><td>-</td><td>-</td><td>ns</td></tr><tr><td> $T_{NRST\_OUT}$ </td><td>Generated reset pulse duration</td><td>Internal reset source</td><td>20</td><td>-</td><td>-</td><td>μs</td></tr></table>

1. Specified by design.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (\~10% order).

Figure 38. Recommended NRST pin protection
![](images/393995a1396972f175629d9d89776d67aa05d4ee4e7911e5f04c1e87821a41a6.jpg)

<details>
<summary>text_image</summary>

External
reset circuit(1)
0.1 µF
NRST(2)
VDD
RPU
Filter
Internal Reset
STM32F
ai14132c
</details>

1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the $V_{\mathrm{IL(NRST)}}$ max level specified in Table 51. Otherwise the reset is not taken into account by the device.

## 6.3.18 TIM timer characteristics

The parameters given in Table 52 and Table 53 are specified by design.

Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output).

Table 52. Characteristics of TIMx connected to the APB1 domain $^{(1)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td rowspan="4"> $t_{res(TIM)}$ </td><td rowspan="4">Timer resolution time</td><td rowspan="2">AHB/APB1 prescaler distinct from 1,  $f_{TIMxCLK}=84 MHz$ </td><td>1</td><td>-</td><td> $t_{TIMxCLK}$ </td></tr><tr><td>11.9</td><td>-</td><td>ns</td></tr><tr><td rowspan="2">AHB/APB1 prescaler = 1,  $f_{TIMxCLK}=42 MHz$ </td><td>1</td><td>-</td><td> $t_{TIMxCLK}$ </td></tr><tr><td>23.8</td><td>-</td><td>ns</td></tr><tr><td rowspan="2"> $f_{EXT}$ </td><td rowspan="2">Timer external clock frequency on CH1 to CH4</td><td rowspan="9"> $f_{TIMxCLK}=84 MHz$  APB1= 42 MHz</td><td>0</td><td> $f_{TIMxCLK}/2$ </td><td>MHz</td></tr><tr><td>0</td><td>42</td><td>MHz</td></tr><tr><td> $Res_{TIM}$ </td><td>Timer resolution</td><td>-</td><td>16/32</td><td>bit</td></tr><tr><td rowspan="4"> $t_{COUNTER}$ </td><td rowspan="2">16-bit counter clock period when internal clock is selected</td><td>1</td><td>65536</td><td> $t_{TIMxCLK}$ </td></tr><tr><td>0.0119</td><td>780</td><td>μs</td></tr><tr><td rowspan="2">32-bit counter clock period when internal clock is selected</td><td>1</td><td>-</td><td> $t_{TIMxCLK}$ </td></tr><tr><td>0.0119</td><td>51130563</td><td>μs</td></tr><tr><td rowspan="2"> $t_{MAX\_COUNT}$ </td><td rowspan="2">Maximum possible count</td><td>-</td><td>65536 × 65536</td><td> $t_{TIMxCLK}$ </td></tr><tr><td>-</td><td>51.1</td><td>s</td></tr></table>

1. TIMx is used as a general term to refer to the TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, and TIM12 timers.

Table 53. Characteristics of TIMx connected to the APB2 domain $^{(1)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td rowspan="4"> $t_{res(TIM)}$ </td><td rowspan="4">Timer resolution time</td><td rowspan="2">AHB/APB2 prescaler distinct from 1,  $f_{TIMxCLK}$ = 168 MHz</td><td>1</td><td>-</td><td> $t_{TIMxCLK}$ </td></tr><tr><td>5.95</td><td>-</td><td>ns</td></tr><tr><td rowspan="2">AHB/APB2 prescaler = 1,  $f_{TIMxCLK}$ = 84 MHz</td><td>1</td><td>-</td><td> $t_{TIMxCLK}$ </td></tr><tr><td>11.9</td><td>-</td><td>ns</td></tr><tr><td rowspan="2"> $f_{EXT}$ </td><td rowspan="2">Timer external clock frequency on CH1 to CH4</td><td rowspan="5"> $f_{TIMxCLK}$ = 168 MHz APB2 = 84 MHz</td><td>0</td><td> $f_{TIMxCLK}/2$ </td><td>MHz</td></tr><tr><td>0</td><td>84</td><td>MHz</td></tr><tr><td> $Res_{TIM}$ </td><td>Timer resolution</td><td>-</td><td>16</td><td>bit</td></tr><tr><td> $t_{COUNTER}$ </td><td>16-bit counter clock period when internal clock is selected</td><td>1</td><td>65536</td><td> $t_{TIMxCLK}$ </td></tr><tr><td> $t_{MAX\_COUNT}$ </td><td>Maximum possible count</td><td>-</td><td>32768</td><td> $t_{TIMxCLK}$ </td></tr></table>

1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers.

## 6.3.19 Communications interfaces

## $I^{2}C$ interface characteristics

The I $^{2}$ C interface meets the timings requirements of the I $^{2}$ C-bus specification and user manual rev. 03 for:

• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s.

The I $^{2}$ C timings requirements are specified by design when the I2C peripheral is properly configured (refer to RM0090 reference manual).

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and $V_{DD}$ is disabled, but is still present. Refer to Section 6.3.16: I/O port characteristics for more details on the $I^{2}C$ I/O characteristics.

All I $^{2}$ C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics:

Table 54. I2C analog filter characteristics $^{(1)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td> $t_{AF}$ </td><td>Maximum pulse width of spikes that are suppressed by the analog filter</td><td> $50^{(2)}$ </td><td> $260^{(3)}$ </td><td>ns</td></tr></table>

1. Specified by design.
2. Spikes with widths below $t_{AF(min)}$ are filtered.
3. Spikes with widths above $t_{AF(max)}$ are not filtered

## SPI interface characteristics

Unless otherwise specified, the parameters given in Table 55 for SPI are derived from tests performed under the ambient temperature, $f_{PCLKx}$ frequency and $V_{DD}$ supply voltage conditions summarized in Table 14 with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 V $_{DD}$

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 55. SPI dynamic characteristics $^{(1)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td rowspan="2"> $f_{SCK}$ </td><td rowspan="4">SPI clock frequency</td><td>Master mode, SPI1, 2.7V &lt;  $V_{DD}$  &lt; 3.6V</td><td rowspan="2">-</td><td rowspan="2">-</td><td>42</td><td rowspan="4">MHz</td></tr><tr><td>Slave mode, SPI1, 2.7V &lt;  $V_{DD}$  &lt; 3.6V</td><td>42</td></tr><tr><td rowspan="2"> $1/t_{c(SCK)}$ </td><td>Master mode, SPI1/2/3, 1.7V &lt;  $V_{DD}$  &lt; 3.6V</td><td rowspan="2">-</td><td rowspan="2">-</td><td>21</td></tr><tr><td>Slave mode, SPI1/2/3, 1.7V &lt;  $V_{DD}$  &lt; 3.6V</td><td>21</td></tr><tr><td>Duty(SCK)</td><td>Duty cycle of SPI clock frequency</td><td>Slave mode</td><td>30</td><td>50</td><td>70</td><td>%</td></tr><tr><td> $t_{w(SCKH)}$ </td><td rowspan="2">SCK high and low time</td><td>Master mode, SPI presc = 2, 2.7V &lt;  $V_{DD}$  &lt; 3.6V</td><td> $T_{PCLK}-0.5$ </td><td> $T_{PCLK}$ </td><td> $T_{PCLK}+0.5$ </td><td rowspan="18">ns</td></tr><tr><td> $t_{w(SCKL)}$ </td><td>Master mode, SPI presc = 2, 1.7V &lt;  $V_{DD}$  &lt; 3.6V</td><td> $T_{PCLK}-2$ </td><td> $T_{PCLK}$ </td><td> $T_{PCLK}+2$ </td></tr><tr><td> $t_{su(NSS)}$ </td><td>NSS setup time</td><td>Slave mode, SPI presc = 2</td><td>4 x  $T_{PCLK}$ </td><td rowspan="2">-</td><td rowspan="2">-</td></tr><tr><td> $t_{h(NSS)}$ </td><td>NSS hold time</td><td>Slave mode, SPI presc = 2</td><td>2 x  $T_{PCLK}$ </td></tr><tr><td> $t_{su(MI)}$ </td><td rowspan="2">Data input setup time</td><td>Master mode</td><td>6.5</td><td>-</td><td>-</td></tr><tr><td> $t_{su(SI)}$ </td><td>Slave mode</td><td>2.5</td><td>-</td><td>-</td></tr><tr><td> $t_{h(MI)}$ </td><td rowspan="2">Data input hold time</td><td>Master mode</td><td>2.5</td><td>-</td><td>-</td></tr><tr><td> $t_{h(SI)}$ </td><td>Slave mode</td><td>4</td><td>-</td><td>-</td></tr><tr><td> $t_{a(SO)}^{(2)}$ </td><td>Data output access time</td><td>Slave mode, SPI presc = 2</td><td>0</td><td>-</td><td>4 x  $T_{PCLK}$ </td></tr><tr><td rowspan="2"> $t_{dis(SO)}^{(3)}$ </td><td rowspan="2">Data output disable time</td><td>Slave mode, SPI1, 2.7V &lt;  $V_{DD}$  &lt; 3.6V</td><td>0</td><td>-</td><td>7.5</td></tr><tr><td>Slave mode, SPI1/2/3 1.7V &lt;  $V_{DD}$  &lt; 3.6V</td><td>0</td><td>-</td><td>16.5</td></tr><tr><td rowspan="2"> $t_{v(SO)}$ </td><td rowspan="4">Data output valid/hold time</td><td>Slave mode (after enable edge), SPI1, 2.7V &lt;  $V_{DD}$  &lt; 3.6V</td><td>-</td><td>11</td><td>13</td></tr><tr><td>Slave mode (after enable edge), SPI2/3, 2.7V &lt;  $V_{DD}$  &lt; 3.6V</td><td>-</td><td>12</td><td>16.5</td></tr><tr><td rowspan="2"> $t_{h(SO)}$ </td><td>Slave mode (after enable edge), SPI1, 1.7V &lt;  $V_{DD}$  &lt; 3.6V</td><td>-</td><td>15.5</td><td>19</td></tr><tr><td>Slave mode (after enable edge), SPI2/3, 1.7V &lt;  $V_{DD}$  &lt; 3.6V</td><td>-</td><td>18</td><td>20.5</td></tr><tr><td rowspan="2"> $t_{v(MO)}$ </td><td rowspan="2">Data output valid time</td><td>Master mode (after enable edge), SPI1, 2.7V &lt;  $V_{DD}$  &lt; 3.6V</td><td>-</td><td>-</td><td>2.5</td></tr><tr><td>Master mode (after enable edge), SPI1/2/3, 1.7V &lt;  $V_{DD}$  &lt; 3.6V</td><td>-</td><td>-</td><td>4.5</td></tr><tr><td> $t_{h(MO)}$ </td><td>Data output hold time</td><td>Master mode (after enable edge)</td><td>0</td><td>-</td><td>-</td></tr></table>

1. Evaluated by characterization - not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.

Figure 39. SPI timing diagram - slave mode and CPHA = 0
![](images/60decabd29b97b9afb59054db33b6f366fc1d0f4c0fb005c8e606864105f4bd1.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph LR
  NSS_input["NSS input"] -->|t_cSCK| SCK_input
  SCK_input -->|t_hNSS| NSS_input
  SCK_input -->|t_wSCKH| SCK_input
  SCK_input -->|t_suNSS| SCK_input
  SCK_input -->|t_aSO| MISO_output
  SCK_input -->|t_wSCKL| MISO_output
  SCK_input -->|t_vSO| MISO_output
  SCK_input -->|t_hSO| MISO_output
  SCK_input -->|t_disSO| MISO_output
  MISO_output -->|First bit OUT| MISO_output
  MISO_output -->|Next bits OUT| MISO_output
  MISO_output -->|Last bit OUT| MISO_output
  MOSI_input -->|First bit IN| MOSI_input
  MOSI_input -->|Next bits IN| MOSI_input
  MOSI_input -->|Last bit IN| MOSI_input
```
</details>

Figure 40. SPI timing diagram - slave mode and CPHA = 1
![](images/e83a077a30aedc46244f8418c39e0a1b72d93c86b3a658ce79aeeddf887553dc.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph LR
  NSS_input["NSS input"] -->|t_cSCK| SCK_input
  SCK_input -->|t_aSO| MISO_output
  SCK_input -->|t_hSCKH| SCK_input
  SCK_input -->|t_hNSS| SCK_input
  SCK_input -->|t_hSO| MISO_output
  SCK_input -->|t_disSO| MISO_output
  MISO_output -->|First bit OUT| SCK_input
  MISO_output -->|First bit IN| MOSI_input
  MISO_output -->|Next bits IN| MOSI_input
  MISO_output -->|Last bit IN| MOSI_input
```
</details>

Figure 41. SPI timing diagram - master mode
![](images/d6387dd398773fcf4a7e3d9128c405057996767857a59ef2476ba0072b9d1af4.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph LR
  subgraph High
    NSS_input["NSS input"]
    SCK_output1["SCK output\nCPHA=0, CPOL=0\nCPHA=0, CPOL=1"]
    SCK_output2["SCK output\nCPHA=1, CPOL=0\nCPHA=1, CPOL=1"]
    MISO_input["MISO input"]
    MOSI_output["MOSI output"]
  end

  subgraph Timing Signals
  NSS_input -->|t_cSCK| SCK_output1
  SCK_output1 -->|t_wSCKH| SCK_output2
  SCK_output2 -->|t_wSCKL| SCK_output1
  MISO_input -->|t_suMI| MOSI_output
  MOSI_output -->|t_hMI| MISO_input

    subgraph Timing Signals
  MISO_input -->|First bit IN| NextBitsIn["Next bits_IN"]
  NextBitsIn -->|Next bits IN| LastBitIn["Last bit_IN"]
  NextBitsIn -->|Next bits OUT| MOSI_output
  MOSI_output -->|First bit OUT| NextBitsOut["Next bits_OUT"]
  NextBitsOut -->|Next bits OUT| MOSI_output
  MOSI_output -->|t_vMO| NextBitsOut
  NextBitsOut -->|t_hMO| MOSI_output
  end
```
</details>

## I²S interface characteristics

Unless otherwise specified, the parameters given in Table 56 for the $i^{2}S$ interface are derived from tests performed under the ambient temperature, $f_{PCLKx}$ frequency and $V_{DD}$ supply voltage conditions summarized in Table 14, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 V $_{DD}$

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS).

Table 56. I²S dynamic characteristics(1)

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td> $f_{MCK}$ </td><td> $I^2S$  main clock output</td><td>-</td><td>256 x 8K</td><td> $256 \times F_{S}^{(2)}$ </td><td>MHz</td></tr><tr><td rowspan="2"> $f_{CK}$ </td><td rowspan="2"> $I^2S$  clock frequency</td><td>Master data: 32 bits</td><td>-</td><td> $64 \times F_{S}$ </td><td rowspan="2">MHz</td></tr><tr><td>Slave data: 32 bits</td><td>-</td><td> $64 \times F_{S}$ </td></tr><tr><td> $D_{CK}$ </td><td> $I^2S$  clock frequency duty cycle</td><td>Slave receiver</td><td>30</td><td>70</td><td>%</td></tr><tr><td> $t_{v(WS)}$ </td><td>WS valid time</td><td>Master mode</td><td>0</td><td>6</td><td rowspan="11">ns</td></tr><tr><td> $t_{h(WS)}$ </td><td>WS hold time</td><td>Master mode</td><td>0</td><td>-</td></tr><tr><td> $t_{su(WS)}$ </td><td>WS setup time</td><td>Slave mode</td><td>1</td><td>-</td></tr><tr><td> $t_{h(WS)}$ </td><td>WS hold time</td><td>Slave mode</td><td>0</td><td>-</td></tr><tr><td> $t_{su(SD_MR)}$ </td><td rowspan="2">Data input setup time</td><td>Master receiver</td><td>7.5</td><td>-</td></tr><tr><td> $t_{su(SD_SR)}$ </td><td>Slave receiver</td><td>2</td><td>-</td></tr><tr><td> $t_{h(SD_MR)}$ </td><td rowspan="2">Data input hold time</td><td>Master receiver</td><td>0</td><td>-</td></tr><tr><td> $t_{h(SD_SR)}$ </td><td>Slave receiver</td><td>0</td><td>-</td></tr><tr><td> $t_{v(SD_ST)}$ </td><td rowspan="2">Data output valid time</td><td>Slave transmitter (after enable edge)</td><td>-</td><td>27</td></tr><tr><td> $t_{h(SD_ST)}$ </td><td>Master transmitter (after enable edge)</td><td>-</td><td>20</td></tr><tr><td> $t_{v(SD_MT)}$ </td><td>Data output hold time</td><td>Master transmitter (after enable edge)</td><td>2.5</td><td>-</td></tr></table>

1. Evaluated by characterization - not tested in production.
2. The maximum value of $256 \times F_{S}$ is 42 MHz (APB1 maximum frequency).

Note: Refer to the I²S section of RM0090 reference manual for more details on the sampling frequency ( $F_{S}$ ). $f_{MCK}$ , $f_{CK}$ , and $D_{CK}$ values reflect only the digital peripheral behavior. The value of these parameters might be slightly impacted by the source clock accuracy. $D_{CK}$ depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of I2SDIV / (2 x I2SDIV + ODD) and a maximum value of (I2SDIV + ODD) / (2 x I2SDIV + ODD). $F_{S}$ maximum value is supported for each mode/condition.

Figure 42. I²S slave timing diagram (Philips protocol)
![](images/15bf3eb15d4bfeee862100003c6dbc51dd8861bd5fdddfba6223a2c5ed2c83fe.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph LR
  subgraph CK_Input
    CPOL["CPOL = 0"]
    CPOL2["CPOL = 1"]
  end

  WS_input["WS input"]
  SD_transmit["SD_transmit"]
  SD_receive["SD_receive"]

  CPOL -->|t_cCK| CPOL2
  CPOL2 -->|t_wCKH| CPOL
  CPOL -->|t_wCKL| CPOL2
  CPOL2 -->|t_hWS| WS_input

  WS_input -->|tsuWS| SD_transmit
  SD_transmit -->|tsuSD_SR| SD_receive

  SD_transmit -->|tsuSD_ST| SD_receive
  SD_receive -->|tsuSD_SR| SD_transmit
  SD_receive -->|tsuSD_SR| SD_receive

  SD_transmit -->|MSB_transmit| Bitn_transmit
  SD_transmit -->|MSB receive| Bitn_receive
  SDReceive["SD receive"] -->|MSB receive| BitnReceive["Bitn receive"]
  SDReceive -->|Bitn receive| BSB_receive
```
</details>

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 43. I²S master timing diagram (Philips protocol)(1)
![](images/1cbb15ca401c2190a272fc486a5038ceeab0e1363b0503b0baf921fc0398c362.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph LR
  subgraph CK_output
    CPOL["CPOL = 0"]
    CPOL2["CPOL = 1"]
    WS_output["WS output"]
    SD_transmit["SD_transmit"]
    SD_receive["SD_receive"]
  end

  subgraph Signal Stream
  CPOL -->|tfCK| CPOL2
  CPOL -->|trCK| CPOL2
  CPOL -->|twCKH| CPOL2
  CPOL -->|tvWS| WS_output
  CPOL -->|twCKL| WS_output
  CPOL -->|thWS| WS_output
  WS_output -->|tvSD_MT| SD_transmit
  WS_output -->|thSD_MT| SD_transmit
  WS_output -->|tvWS| SD_receive
  WS_output -->|thWS| SD_receive
  end

  subgraph Signal Stream
  SD_transmit -->|LSB_transmit2| MSB_transmit
  SD_transmit -->|Bitn_transmit| MSB_transmit
  SD_transmit -->|LSB_transmit| SD_receive
  SD_receive -->|tsuSD_MR| MSB_receive
  SD_receive -->|thSD_MR| MSB_receive
  end

  CPOL -->|tfCK| CPOL2
  CPOL -->|trCK| CPOL2
  CPOL -->|twCKH| CPOL2
  CPOL -->|tvWS| WS_output
  CPOL -->|thWS| WS_output
  MSB_transmit -->|tvSD_MT| SD_transmit
  MSB_transmit -->|Bitn_transmit| SD_transmit
  MSB_transmit -->|LSB_transmit| SD_receive
  MSB_receive -->|tsuSD_MR| SD_receive
  MSB_receive -->|thSD_MR| SD_receive
  SD_receive -->|LSB receive| SD_receive
```
</details>

1. Evaluated by characterization - not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

## USB OTG FS characteristics

This interface is present in both the USB OTG HS and USB OTG FS controllers.

Table 57. USB OTG FS startup time

<table><tr><td>Symbol</td><td>Parameter</td><td>Max</td><td>Unit</td></tr><tr><td> $t_{STARTUP}^{(1)}$ </td><td>USB OTG FS transceiver startup time</td><td>1</td><td>μs</td></tr></table>

1. Specified by design.

Table 58. USB OTG FS DC electrical characteristics

<table><tr><td colspan="2">Symbol</td><td>Parameter</td><td>Conditions</td><td>Min.(1)</td><td>Typ.</td><td>Max.(1)</td><td>Unit</td></tr><tr><td rowspan="4">Input levels</td><td> $V_{DD}$ </td><td>USB OTG FS operating voltage</td><td>-</td><td> $3.0^{(2)}$ </td><td>-</td><td>3.6</td><td>V</td></tr><tr><td> $V_{DI}^{(3)}$ </td><td>Differential input sensitivity</td><td>I(USB_FS_DP/DM,USB_HS_DP/DM)</td><td>0.2</td><td>-</td><td>-</td><td rowspan="3">V</td></tr><tr><td> $V_{CM}^{(3)}$ </td><td>Differential common mode range</td><td>Includes  $V_{DI}$  range</td><td>0.8</td><td>-</td><td>2.5</td></tr><tr><td> $V_{SE}^{(3)}$ </td><td>Single ended receiver threshold</td><td>-</td><td>1.3</td><td>-</td><td>2.0</td></tr><tr><td rowspan="2">Output levels</td><td> $V_{OL}$ </td><td>Static output level low</td><td> $R_L$  of 1.5 kΩ to 3.6  $V^{(4)}$ </td><td>-</td><td>-</td><td>0.3</td><td rowspan="2">V</td></tr><tr><td> $V_{OH}$ </td><td>Static output level high</td><td> $R_L$  of 15 kΩ to  $V_{SS}^{(4)}$ </td><td>2.8</td><td>-</td><td>3.6</td></tr><tr><td rowspan="2" colspan="2"> $R_{PD}$ </td><td>PA11, PA12, PB14, PB15(USB_FS_DP/DM,USB_HS_DP/DM)</td><td rowspan="2"> $V_{IN}=V_{DD}$ </td><td>17</td><td>21</td><td>24</td><td rowspan="4">kΩ</td></tr><tr><td>PA9, PB13(OTG_FS_VBUS,OTG_HS_VBUS)</td><td>0.65</td><td>1.1</td><td>2.0</td></tr><tr><td rowspan="2" colspan="2"> $R_{PU}$ </td><td>PA12, PB15 (USB_FS_DP,USB_HS_DP)</td><td> $V_{IN}=V_{SS}$ </td><td>1.5</td><td>1.8</td><td>2.1</td></tr><tr><td>PA9, PB13(OTG_FS_VBUS,OTG_HS_VBUS)</td><td> $V_{IN}=V_{SS}$ </td><td>0.25</td><td>0.37</td><td>0.55</td></tr></table>

1. All the voltages are measured from the local ground potential.
2. The STM32F405xx and STM32F407xx USB OTG FS functionality is ensured down to 2.7 V but not the full USB OTG FS electrical characteristics which are degraded in the 2.7-to-3.0 V $V_{DD}$ voltage range.
3. Specified by design.
4. $R_{L}$ is the load connected on the USB OTG FS drivers

Figure 44. USB OTG FS timings: definition of data signal rise and fall time
![](images/0bd6f6339b7afa77afcaf0829e656575842fb298e620ec3a12460f51e51a4a92.jpg)

<details>
<summary>text_image</summary>

Cross over
points
Differential
data lines
VCRS
Vss
tr
tr
ai14137b
</details>

Table 59. USB OTG FS electrical characteristics $^{(1)}$

<table><tr><td colspan="6">Driver characteristics</td></tr><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td> $t_r$ </td><td>Rise time $^{(2)}$ </td><td> $C_L$ =50 pF</td><td>4</td><td>20</td><td>ns</td></tr><tr><td> $t_f$ </td><td>Fall time $^{(2)}$ </td><td> $C_L$ =50 pF</td><td>4</td><td>20</td><td>ns</td></tr><tr><td> $t_{rfm}$ </td><td>Rise/ fall time matching</td><td> $t_f/t_f$ </td><td>90</td><td>110</td><td>%</td></tr><tr><td> $V_{CRS}$ </td><td>Output signal crossover voltage</td><td>-</td><td>1.3</td><td>2.0</td><td>V</td></tr></table>

1. Specified by design.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0).

## USB HS characteristics

Unless otherwise specified, the parameters given in Table 62 for ULPI are derived from tests performed under the ambient temperature, $f_{HCLK}$ frequency summarized in Table 61 and $V_{DD}$ supply voltage conditions summarized in Table 60, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: $0.5V_{DD}$ .

Refer to Section Section 6.3.16: I/O port characteristics for more details on the input/output characteristics.

Table 60. USB HS DC electrical characteristics

<table><tr><td colspan="2">Symbol</td><td>Parameter</td><td>Min.(1)</td><td>Max.(1)</td><td>Unit</td></tr><tr><td>Input level</td><td> $V_{DD}$ </td><td>USB OTG HS operating voltage</td><td>2.7</td><td>3.6</td><td>V</td></tr></table>

1. All the voltages are measured from the local ground potential.

Table 61. USB HS clock timing parameters $^{(1)}$

<table><tr><td colspan="2">Parameter</td><td>Symbol</td><td>Min</td><td>Nominal</td><td>Max</td><td>Unit</td></tr><tr><td colspan="2"> $f_{HCLK}$  value to guarantee proper operation of USB HS interface</td><td>-</td><td>30</td><td>-</td><td>-</td><td>MHz</td></tr><tr><td>Frequency (first transition)</td><td>8-bit ±10%</td><td> $F_{START\_8BIT}$ </td><td>54</td><td>60</td><td>66</td><td>MHz</td></tr></table>

Table 61. USB HS clock timing parameters $^{(1)}$

<table><tr><td colspan="2">Parameter</td><td>Symbol</td><td>Min</td><td>Nominal</td><td>Max</td><td>Unit</td></tr><tr><td colspan="2">Frequency (steady state) ±500 ppm</td><td> $F_{STEADY}$ </td><td>59.97</td><td>60</td><td>60.03</td><td>MHz</td></tr><tr><td>Duty cycle (first transition)</td><td>8-bit ±10%</td><td> $D_{START\_8BIT}$ </td><td>40</td><td>50</td><td>60</td><td>%</td></tr><tr><td colspan="2">Duty cycle (steady state) ±500 ppm</td><td> $D_{STEADY}$ </td><td>49.975</td><td>50</td><td>50.025</td><td>%</td></tr><tr><td colspan="2">Time to reach the steady state frequency and duty cycle after the first transition</td><td> $T_{STEADY}$ </td><td>-</td><td>-</td><td>1.4</td><td>ms</td></tr><tr><td rowspan="2">Clock startup time after the de-assertion of SuspendM</td><td>Peripheral</td><td> $T_{START\_DEV}$ </td><td>-</td><td>-</td><td>5.6</td><td rowspan="2">ms</td></tr><tr><td>Host</td><td> $T_{START\_HOST}$ </td><td>-</td><td>-</td><td>-</td></tr><tr><td colspan="2">PHY preparation time after the first transition of the input clock</td><td> $T_{PREP}$ </td><td>-</td><td>-</td><td>-</td><td>μs</td></tr></table>

1. Specified by design.

Table 62. ULPI timing

<table><tr><td rowspan="2">Parameter</td><td rowspan="2">Symbol</td><td colspan="2">Value(1)</td><td rowspan="2">Unit</td></tr><tr><td>Min.</td><td>Max.</td></tr><tr><td>Control in (ULPI_DIR) setup time</td><td rowspan="2"> $t_{SC}$ </td><td>-</td><td>2.0</td><td rowspan="7">ns</td></tr><tr><td>Control in (ULPI_NXT) setup time</td><td>-</td><td>1.5</td></tr><tr><td>Control in (ULPI_DIR, ULPI_NXT) hold time</td><td> $t_{HC}$ </td><td>0</td><td>-</td></tr><tr><td>Data in setup time</td><td> $t_{SD}$ </td><td>-</td><td>2.0</td></tr><tr><td>Data in hold time</td><td> $t_{HD}$ </td><td>0</td><td>-</td></tr><tr><td>Control out (ULPI_STP) setup time and hold time</td><td> $t_{DC}$ </td><td>-</td><td>9.2</td></tr><tr><td>Data out available from clock rising edge</td><td> $t_{DD}$ </td><td>-</td><td>10.7</td></tr></table>

1. $V_{DD} = 2.7 V$ to 3.6 V and $T_{A} = -40$ to 85 °C.

Figure 45. ULPI timing diagram
![](images/69dbc50b9c8487de6bf29ef9a575a924ff69cfb4d4bf5875c2cffa3a5091e995.jpg)

<details>
<summary>text_image</summary>

Clock
Control In
(ULPI_DIR,
ULPI_NXT)
data In
(8-bit)
Control out
(ULPI_STP)
data out
(8-bit)
ai17361c
tSC
tHC
tSD
tHD
tDC
tDC
tDD
</details>

## Ethernet characteristics

Unless otherwise specified, the parameters given in Table 64, Table 65 and Table 66 for SMI, RMII and MII are derived from tests performed under the ambient temperature, $f_{HCLK}$ frequency summarized in Table 14 and VDD supply voltage conditions summarized in Table 63, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: $0.5V_{DD}$ .

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output characteristics.

Table 63. Ethernet DC electrical characteristics

<table><tr><td colspan="2">Symbol</td><td>Parameter</td><td>Min.(1)</td><td>Max.(1)</td><td>Unit</td></tr><tr><td>Input level</td><td> $V_{DD}$ </td><td>Ethernet operating voltage</td><td>2.7</td><td>3.6</td><td>V</td></tr></table>

1. All the voltages are measured from the local ground potential.

Table 64 gives the list of Ethernet MAC signals for the SMI (station management interface) and Figure 46 shows the corresponding timing diagram.

Figure 46. Ethernet SMI timing diagram
![](images/cf0072f2e7607e0c12839db38019c18370967cbee8c0302d7ebf80151ce746bf.jpg)

<details>
<summary>text_image</summary>

ETH_MDC
tMDC
td(MDIO)
ETH_MDIO(O)
tsu(MDIO)
th(MDIO)
ETH_MDIO(I)
MS31384V1
</details>

Table 64. Dynamic characteristics: Ethernet MAC signals for SMI $^{(1)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td> $t_{\text{MDC}}$ </td><td>MDC cycle time(2.38 MHz)</td><td>411</td><td>420</td><td>425</td><td rowspan="4">ns</td></tr><tr><td> $T_{\text{d(MDIO)}}$ </td><td>Write data valid time</td><td>6</td><td>10</td><td>13</td></tr><tr><td> $t_{\text{su(MDIO)}}$ </td><td>Read data setup time</td><td>12</td><td>-</td><td>-</td></tr><tr><td> $t_{\text{h(MDIO)}}$ </td><td>Read data hold time</td><td>0</td><td>-</td><td>-</td></tr></table>

1. Evaluated by characterization - not tested in production.

Table 65 gives the list of Ethernet MAC signals for the RMII and Figure 47 shows the corresponding timing diagram.

Figure 47. Ethernet RMII timing diagram
![](images/57dc48c0bbc979974c12c1bfa1b13883f306cc3c76c363af5905c9b9b18ecf28.jpg)

<details>
<summary>text_image</summary>

RMII_REF_CLK
RMII_TX_EN
RMII_TXD[1:0]
RMII_RXD[1:0]
RMII_CRS_DV
td(TXEN)
td(TXD)
tsu(RXD)
tsu(CRS)
tih(RXD)
tih(CRS)
ai15667
</details>

Table 65. Dynamic characteristics: Ethernet MAC signals for RMII

<table><tr><td>Symbol</td><td>Rating</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td> $t_{su(RXD)}$ </td><td>Receive data setup time</td><td>2</td><td>-</td><td>-</td><td>ns</td></tr><tr><td> $t_{ih(RXD)}$ </td><td>Receive data hold time</td><td>1</td><td>-</td><td>-</td><td>ns</td></tr><tr><td> $t_{su(CRS)}$ </td><td>Carrier sense set-up time</td><td>0.5</td><td>-</td><td>-</td><td>ns</td></tr><tr><td> $t_{ih(CRS)}$ </td><td>Carrier sense hold time</td><td>2</td><td>-</td><td>-</td><td>ns</td></tr><tr><td> $t_{d(TXEN)}$ </td><td>Transmit enable valid delay time</td><td>8</td><td>9.5</td><td>11</td><td>ns</td></tr><tr><td> $t_{d(TXD)}$ </td><td>Transmit data valid delay time</td><td>8.5</td><td>10</td><td>11.5</td><td>ns</td></tr></table>

Table 66 gives the list of Ethernet MAC signals for MII and Figure 47 shows the corresponding timing diagram.

Figure 48. Ethernet MII timing diagram
![](images/6fb1bbbd7940f58787ec2ce5341fca05aae817973c3ffa1fe85cd36ffae91e89.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph LR
  subgraph MII_RX_CLK
  A["tsu(RXD)"] --> B["tsu(ER)"]
  B --> C["tsu(DV)"]
  C --> D["tih(RXD)"]
  D --> E["tih(ER)"]
  E --> F["tih(DV)"]
  end

  subgraph MII_RXD[3:0]
  G["&quot;MII_RXD[3:0"]"] --> H["MII_RX_DV"]
  H --> I["MII_RX_ER"]
  end

  subgraph MII_TX_CLK
  J["MII_TX_CLK"] --> K["MII_TX_EN"]
  K --> L["&quot;MII_TXD[3:0"]"]
  L --> M["t_d(TXEN)"]
  M --> N["t_d(TXD)"]
  end

  A -.->|t_d(TXEN)| K
  B -.->|t_d(TXD)| N
  C -.->|t_d(TXEN)| K
  D -.->|t_d(TXD)| N
  E -.->|t_d(TXEN)| K
  F -.->|t_d(TXD)| N
  G -.->|t_d(TXEN)| K
  H -.->|t_d(TXD)| N
  I -.->|t_d(TXD)| K
  J -.->|t_d(TXD)| N
  K -.->|t_d(TXD)| N
  L -.->|t_d(TXD)| N
  M -.->|t_d(TXD)| N
  N -.->|t_d(TXD)| K
```
</details>

Table 66. Dynamic characteristics: Ethernet MAC signals for MII $^{(1)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td> $t_{su(RXD)}$ </td><td>Receive data setup time</td><td>9</td><td>-</td><td>-</td><td rowspan="8">ns</td></tr><tr><td> $t_{ih(RXD)}$ </td><td>Receive data hold time</td><td>10</td><td>-</td><td>-</td></tr><tr><td> $t_{su(DV)}$ </td><td>Data valid setup time</td><td>9</td><td>-</td><td>-</td></tr><tr><td> $t_{ih(DV)}$ </td><td>Data valid hold time</td><td>8</td><td>-</td><td>-</td></tr><tr><td> $t_{su(ER)}$ </td><td>Error setup time</td><td>6</td><td>-</td><td>-</td></tr><tr><td> $t_{ih(ER)}$ </td><td>Error hold time</td><td>8</td><td>-</td><td>-</td></tr><tr><td> $t_{d(TXEN)}$ </td><td>Transmit enable valid delay time</td><td>0</td><td>10</td><td>14</td></tr><tr><td> $t_{d(TXD)}$ </td><td>Transmit data valid delay time</td><td>0</td><td>10</td><td>15</td></tr></table>

1. Evaluated by characterization - not tested in production.

## 6.3.20 CAN (controller area network) interface

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX).

## 6.3.21 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 67 are derived from tests performed under the ambient temperature, $f_{PCLK2}$ frequency and $V_{DDA}$ supply voltage conditions summarized in Table 14.

Table 67. ADC characteristics

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td> $V_{DDA}$ </td><td>Power supply</td><td>-</td><td> $1.8^{(1)}$ </td><td>-</td><td>3.6</td><td rowspan="3">V</td></tr><tr><td> $V_{REF+}$ </td><td>Positive reference voltage</td><td>-</td><td> $1.8^{(1)(2)(3)}$ </td><td>-</td><td> $V_{DDA}$ </td></tr><tr><td> $V_{REF-}$ </td><td>Negative reference voltage</td><td>-</td><td>-</td><td>0</td><td>-</td></tr><tr><td rowspan="2"> $f_{ADC}$ </td><td rowspan="2">ADC clock frequency</td><td> $V_{DDA} = 1.8^{(1)(3)}$  to 2.4 V</td><td>0.6</td><td>15</td><td>18</td><td>MHz</td></tr><tr><td> $V_{DDA} = 2.4$  to  $3.6$  V $^{(3)}$ </td><td>0.6</td><td>30</td><td>36</td><td>MHz</td></tr><tr><td rowspan="2"> $f_{TRIG}^{(4)}$ </td><td rowspan="2">External trigger frequency</td><td> $f_{ADC} = 30$  MHz, 12-bit resolution</td><td>-</td><td>-</td><td>1764</td><td>kHz</td></tr><tr><td>-</td><td>-</td><td>-</td><td>17</td><td> $1/f_{ADC}$ </td></tr><tr><td> $V_{AIN}$ </td><td>Conversion voltage range $^{(5)}$ </td><td>-</td><td> $0$  ( $V_{SSA}$  or  $V_{REF-}$  tied to ground)</td><td>-</td><td> $V_{REF+}$ </td><td>V</td></tr><tr><td> $R_{AIN}^{(4)}$ </td><td>External input impedance</td><td>See Equation 1 for details</td><td>-</td><td>-</td><td>50</td><td> $\kappa\Omega$ </td></tr><tr><td> $R_{ADC}^{(4)(6)}$ </td><td>Sampling switch resistance</td><td>-</td><td>-</td><td>-</td><td>6</td><td> $\kappa\Omega$ </td></tr><tr><td> $C_{ADC}^{(4)}$ </td><td>Internal sample and hold capacitor</td><td>-</td><td>-</td><td>4</td><td>-</td><td>pF</td></tr><tr><td rowspan="2"> $t_{lat}^{(4)}$ </td><td rowspan="2">Injection trigger conversion latency</td><td> $f_{ADC}$ =30 MHz</td><td>-</td><td>-</td><td>0.100</td><td>μs</td></tr><tr><td></td><td>-</td><td>-</td><td> $3^{(7)}$ </td><td> $1/f_{ADC}$ </td></tr><tr><td rowspan="2"> $t_{latr}^{(4)}$ </td><td rowspan="2">Regular trigger conversion latency</td><td> $f_{ADC}$ =30 MHz</td><td>-</td><td>-</td><td>0.067</td><td>μs</td></tr><tr><td></td><td>-</td><td>-</td><td> $2^{(7)}$ </td><td> $1/f_{ADC}$ </td></tr><tr><td rowspan="2"> $t_{S}^{(4)}$ </td><td rowspan="2">Sampling time</td><td> $f_{ADC}$ =30 MHz</td><td>0.100</td><td>-</td><td>16</td><td>μs</td></tr><tr><td>-</td><td>3</td><td>-</td><td>480</td><td> $1/f_{ADC}$ </td></tr><tr><td> $t_{STAB}^{(4)}$ </td><td>Power-up time</td><td>-</td><td>-</td><td>2</td><td>3</td><td>μs</td></tr><tr><td rowspan="5"> $t_{CONV}^{(4)}$ </td><td rowspan="5">Total conversion time (including sampling time)</td><td> $f_{ADC}$ =30 MHz12-bit resolution</td><td>0.50</td><td>-</td><td>16.40</td><td>μs</td></tr><tr><td> $f_{ADC}$ =30 MHz10-bit resolution</td><td>0.43</td><td>-</td><td>16.34</td><td>μs</td></tr><tr><td> $f_{ADC}$ =30 MHz8-bit resolution</td><td>0.37</td><td>-</td><td>16.27</td><td>μs</td></tr><tr><td> $f_{ADC}$ =30 MHz6-bit resolution</td><td>0.30</td><td>-</td><td>16.20</td><td>μs</td></tr><tr><td colspan="4">9 to 492 ( $t_{S}$  for sampling +n-bit resolution for successive approximation)</td><td> $1/f_{ADC}$ </td></tr><tr><td rowspan="3"> $f_{S}^{(4)}$ </td><td rowspan="3">Sampling rate( $f_{ADC}$ =30 MHz, and $t_{S}$ =3 ADC cycles)</td><td>12-bit resolutionSingle ADC</td><td>-</td><td>-</td><td>2</td><td>Msps</td></tr><tr><td>12-bit resolutionInterleave Dual ADC mode</td><td>-</td><td>-</td><td>3.75</td><td>Msps</td></tr><tr><td>12-bit resolutionInterleave Triple ADC mode</td><td>-</td><td>-</td><td>6</td><td>Msps</td></tr><tr><td> $I_{VREF+}^{(4)}$ </td><td>ADC  $V_{REF}$  DC current consumption in conversion mode</td><td>-</td><td>-</td><td>300</td><td>500</td><td>μA</td></tr><tr><td> $I_{VDDA}^{(4)}$ </td><td>ADC  $V_{DDA}$  DC current consumption in conversion mode</td><td>-</td><td>-</td><td>1.6</td><td>1.8</td><td>mA</td></tr></table>

1. $V_{DD}/V_{DDA}$ minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF).
2. It is recommended to maintain the voltage difference between $V_{REF+}$ and $V_{DDA}$ below 1.8 V.
3. $V_{DDA} - V_{REF+} < 1.2 V.$
4. Evaluated by characterization - not tested in production.
5. $V_{REF+}$ is internally connected to $V_{DDA}$ and $V_{REF-}$ is internally connected to $V_{SSA}$ .
6. $R_{ADC}$ maximum value is given for $V_{DD}=1.8$ V, and minimum value for $V_{DD}=3.3$ V.
7. For external triggers, a delay of $1/f_{PCLK2}$ must be added to the latency specified in Table 67.

Equation 1: $R_{AIN}$ max formula

$$
R _ {\mathrm{AIN}} = \frac {(k - 0 . 5)}{f _ {\mathrm{ADC}} \times C _ {\mathrm{ADC}} \times \ln \left(2 ^ {N + 2}\right)} - R _ {\mathrm{ADC}}
$$

The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC\_SMPR1 register.

Table 68. ADC accuracy at $f_{ADC} = 30$ MHz

<table><tr><td>Symbol</td><td>Parameter</td><td>Test conditions</td><td>Typ</td><td>Max(1)</td><td>Unit</td></tr><tr><td>ET</td><td>Total unadjusted error</td><td rowspan="5"> $f_{PCLK2} = 60 MHz,$  $f_{ADC} = 30 MHz, R_{AIN} < 10 k\Omega,$  $V_{DDA} = 1.8^{(2)}$  to 3.6 V</td><td>±2</td><td>±5</td><td rowspan="5">LSB</td></tr><tr><td>EO</td><td>Offset error</td><td>±1.5</td><td>±2.5</td></tr><tr><td>EG</td><td>Gain error</td><td>±1.5</td><td>±3</td></tr><tr><td>ED</td><td>Differential linearity error</td><td>±1</td><td>±2</td></tr><tr><td>EL</td><td>Integral linearity error</td><td>±1.5</td><td>±3</td></tr></table>

1. Evaluated by characterization - not tested in production.
2. $V_{DD}/V_{DDA}$ minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF).

Note:

ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for $I_{INJ(PIN)}$ and $SI_{INJ(PIN)}$ in Section 6.3.16 does not affect the ADC accuracy.

Figure 49. ADC accuracy characteristics
![](images/c8267e6e614998614d7814864bf2a17ffa2d52fee0efcaeaf479cc1c9a6ef589.jpg)

<details>
<summary>line</summary>

| VREF+ (VDDA) | Output code |
| --- | --- |
| (1/2n)*VREF+ | 1 |
| (2/2n)*VREF+ | 2 |
| (3/2n)*VREF+ | 3 |
| (4/2n)*VREF+ | 4 |
| (5/2n)*VREF+ | 5 |
| (6/2n)*VREF+ | 6 |
| (7/2n)*VREF+ | 7 |
| (2n-3/2n)*VREF+ | 8 |
| (2n-2/2n)*VREF+ | 9 |
| (2n-1/2n)*VREF+ | 10 |
</details>

Figure 50. Typical connection diagram when using the ADC with FT/TT pins featuring analog switch function
![](images/4d5dfcd63b6ec0e3468db44c253a4da84adeaedf54ad00d2b1161a545c9f84bc.jpg)

<details>
<summary>text_image</summary>

R_{AIN}^{(1)}
V_{AIN}
C_{parasitic}^{(2)}
I_{Ikg}^{(3)}
V_{SS}
V_{SS}
I/O
analog
switch
V_{DDA}^{(4)}
V_{REF+}^{(4)}
Sampling
switch with
multiplexing
Sample-and-hold ADC converter
R_{ADC}
Converter
C_{ADC}
V_{SSA}
MSv67871V3
</details>

1. Refer to Table 67: ADC characteristics for the values of $R_{AIN}$ , $R_{ADC}$ and $C_{ADC}$ .
2. $C_{parasitic}$ represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (refer to Table 48: I/O static characteristics) A high $C_{parasitic}$ value downgrades conversion accuracy. To remedy this, $f_{ADC}$ should be reduced.
3. Refer to Table 48: I/O static characteristics.
4. Refer to Figure 21: Power supply scheme.

## General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 51 or Figure 52, depending on whether $V_{REF+}$ is connected to $V_{DDA}$ or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 51. Power supply and reference decoupling ( $V_{REF+}$ not connected to $V_{DDA}$ )
![](images/99e1f1e39802d24003d9ead37e2e5068ce9e1d58951bcceaaf1dc3bc1d659392.jpg)

<details>
<summary>text_image</summary>

STM32F
VREF+ (1)
1 µF // 10 nF
VDDA
1 µF // 10 nF
VSSA/VREF- (1)
ai17535b
</details>

1. $V_{REF+}$ and $V_{REF-}$ inputs are both available on UFBGA176. $V_{REF+}$ is also available on LQFP100, LQFP144, and LQFP176. When $V_{REF+}$ and $V_{REF-}$ are not available, they are internally connected to $V_{DDA}$ and $V_{SSA}$ .

Figure 52. Power supply and reference decoupling ( $V_{REF+}$ connected to $V_{DDA}$ )
![](images/65fd04d023fbb9c4d411fe022bb0d919498f19d5bbcdb2606beea87fe3ac7660.jpg)

<details>
<summary>text_image</summary>

STM32F
VREF+/VDDA(1)
1 μF // 10 nF
VREF-/VSSA (1)
ai17536c
</details>

1. $V_{REF+}$ and $V_{REF-}$ inputs are both available on UFBGA176. $V_{REF+}$ is also available on LQFP100, LQFP144, and LQFP176. When $V_{REF+}$ and $V_{REF-}$ are not available, they are internally connected to $V_{DDA}$ and $V_{SSA}$ .

## 6.3.22 Temperature sensor characteristics

Table 69. Temperature sensor characteristics

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td> $T_{L}^{(1)}$ </td><td> $V_{SENSE}$  linearity with temperature</td><td>-</td><td>±1</td><td>±2</td><td>°C</td></tr><tr><td> $Avg\_Slope^{(1)}$ </td><td>Average slope</td><td>-</td><td>2.5</td><td>-</td><td>mV/°C</td></tr><tr><td> $V_{25}^{(1)}$ </td><td>Voltage at 25 °C</td><td>-</td><td>0.76</td><td>-</td><td>V</td></tr><tr><td> $t_{START}^{(2)}$ </td><td>Startup time</td><td>-</td><td>6</td><td>10</td><td>μs</td></tr><tr><td> $T_{S\_temp}^{(2)}$ </td><td>ADC sampling time when reading the temperature (1 °C accuracy)</td><td>10</td><td>-</td><td>-</td><td>μs</td></tr></table>

1. Evaluated by characterization - not tested in production.
2. Specified by design.

Table 70. Temperature sensor calibration values

<table><tr><td>Symbol</td><td>Parameter</td><td>Memory address</td></tr><tr><td>TS_CAL1</td><td>TS ADC raw data acquired at temperature of 30 °C, VDDA=3.3 V</td><td>0x1FFF 7A2C - 0x1FFF 7A2D</td></tr><tr><td>TS_CAL2</td><td>TS ADC raw data acquired at temperature of 110 °C, VDDA=3.3 V</td><td>0x1FFF 7A2E - 0x1FFF 7A2F</td></tr></table>

## 6.3.23 $V_{BAT}$ monitoring characteristics

Table 71. $V_{BAT}$ monitoring characteristics

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td>R</td><td>Resistor bridge for VBAT</td><td>-</td><td>50</td><td>-</td><td>KΩ</td></tr><tr><td>Q</td><td>Ratio on VBAT measurement</td><td>-</td><td>2</td><td>-</td><td>-</td></tr><tr><td>Er(1)</td><td>Error on Q</td><td>-1</td><td>-</td><td>+1</td><td>%</td></tr><tr><td>TS_vbat(2)(2)</td><td>ADC sampling time when reading the VBAT1 mV accuracy</td><td>5</td><td>-</td><td>-</td><td>μs</td></tr></table>

1. Specified by design.
2. Shortest sampling time can be determined in the application by multiple iterations.

## 6.3.24 Embedded reference voltage

The parameters given in Table 72 are derived from tests performed under ambient temperature and $V_{DD}$ supply voltage conditions summarized in Table 14.

Table 72. Embedded internal reference voltage

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td> $V_{REFINT}$ </td><td>Internal reference voltage</td><td> $-40^{\circ}C < T_A < +105^{\circ}C$ </td><td>1.18</td><td>1.21</td><td>1.24</td><td>V</td></tr><tr><td> $T_{S\_vrefint}^{(1)}$ </td><td>ADC sampling time when reading the internal reference voltage</td><td>-</td><td>10</td><td>-</td><td>-</td><td>μs</td></tr><tr><td> $V_{RERINT\_s}^{(2)}$ </td><td>Internal reference voltage spread over the temperature range</td><td> $V_{DD} = 3 V$ </td><td>-</td><td>3</td><td>5</td><td>mV</td></tr><tr><td> $T_{Coeff}^{(2)}$ </td><td>Temperature coefficient</td><td>-</td><td>-</td><td>30</td><td>50</td><td>ppm/°C</td></tr><tr><td> $t_{START}^{(2)}$ </td><td>Startup time</td><td>-</td><td>-</td><td>6</td><td>10</td><td>μs</td></tr></table>

1. Shortest sampling time can be determined in the application by multiple iterations.
2. Specified by design.

Table 73. Internal reference voltage calibration values

<table><tr><td>Symbol</td><td>Parameter</td><td>Memory address</td></tr><tr><td> $V_{REFIN\_CAL}$ </td><td>Raw data acquired at temperature of 30 °C,  $V_{DDA}$ =3.3 V</td><td>0x1FFF 7A2A - 0x1FFF 7A2B</td></tr></table>

## 6.3.25 DAC electrical characteristics

Table 74. DAC characteristics

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td><td>Comments</td></tr><tr><td> $V_{DDA}$ </td><td>Analog supply voltage</td><td> $1.8^{(1)}$ </td><td>-</td><td>3.6</td><td>V</td><td>-</td></tr><tr><td> $V_{REF+}$ </td><td>Reference supply voltage</td><td> $1.8^{(1)}$ </td><td>-</td><td>3.6</td><td>V</td><td> $V_{REF+} \leq V_{DDA}$ </td></tr><tr><td> $V_{SSA}$ </td><td>Ground</td><td>0</td><td>-</td><td>0</td><td>V</td><td>-</td></tr><tr><td> $R_{LOAD}^{(2)}$ </td><td>Resistive load with buffer ON</td><td>5</td><td>-</td><td>-</td><td>kΩ</td><td>-</td></tr><tr><td> $R_{O}^{(2)}$ </td><td>Impedance output with buffer OFF</td><td>-</td><td>-</td><td>15</td><td>kΩ</td><td>When the buffer is OFF, the Minimum resistive load between DAC_OUT and  $V_{SS}$  to have a 1% accuracy is 1.5 MΩ</td></tr><tr><td> $C_{LOAD}^{(2)}$ </td><td>Capacitive load</td><td>-</td><td>-</td><td>50</td><td>pF</td><td>Maximum capacitive load at DAC_OUT pin (when the buffer is ON).</td></tr><tr><td> $DAC\_OUT\ min^{(2)}$ </td><td>Lower DAC_OUT voltage with buffer ON</td><td>0.2</td><td>-</td><td>-</td><td>V</td><td rowspan="2">It gives the maximum output excursion of the DAC.It corresponds to 12-bit input code (0x0E0) to (0xF1C) at  $V_{REF+} = 3.6$  V and (0x1C7) to (0xE38) at  $V_{REF+} = 1.8$  V</td></tr><tr><td> $DAC\_OUT\ max^{(2)}$ </td><td>Higher DAC_OUT voltage with buffer ON</td><td>-</td><td>-</td><td> $V_{DDA} - 0.2$ </td><td>V</td></tr><tr><td> $DAC\_OUT\ min^{(2)}$ </td><td>Lower DAC_OUT voltage with buffer OFF</td><td>-</td><td>0.5</td><td>-</td><td>mV</td><td rowspan="2">It gives the maximum output excursion of the DAC.</td></tr><tr><td> $DAC\_OUT\ max^{(2)}$ </td><td>Higher DAC_OUT voltage with buffer OFF</td><td>-</td><td>-</td><td> $V_{REF+} - 1LSB$ </td><td>V</td></tr><tr><td rowspan="2"> $I_{VREF+}^{(4)}$ </td><td rowspan="2">DAC DC  $V_{REF}$  current consumption in quiescent mode (Standby mode)</td><td>-</td><td>170</td><td>240</td><td rowspan="2">μA</td><td>With no load, worst code (0x800) at  $V_{REF+} = 3.6$  V in terms of DC consumption on the inputs</td></tr><tr><td>-</td><td>50</td><td>75</td><td>With no load, worst code (0xF1C) at  $V_{REF+} = 3.6$  V in terms of DC consumption on the inputs</td></tr><tr><td rowspan="2"> $I_{DDA}^{(4)}$ </td><td rowspan="2">DAC DC VDDA current consumption in quiescent mode(3)</td><td>-</td><td>280</td><td>380</td><td>μA</td><td>With no load, middle code (0x800) on the inputs</td></tr><tr><td>-</td><td>475</td><td>625</td><td>μA</td><td>With no load, worst code (0xF1C) at  $V_{REF+} = 3.6$  V in terms of DC consumption on the inputs</td></tr><tr><td rowspan="2"> $DNL^{(4)}$ </td><td rowspan="2">Differential non linearity Difference between two consecutive code-1LSB)</td><td>-</td><td>-</td><td>±0.5</td><td>LSB</td><td>Given for the DAC in 10-bit configuration.</td></tr><tr><td>-</td><td>-</td><td>±2</td><td>LSB</td><td>Given for the DAC in 12-bit configuration.</td></tr><tr><td rowspan="2"> $INL^{(4)}$ </td><td rowspan="2">Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023)</td><td>-</td><td>-</td><td>±1</td><td>LSB</td><td>Given for the DAC in 10-bit configuration.</td></tr><tr><td>-</td><td>-</td><td>±4</td><td>LSB</td><td>Given for the DAC in 12-bit configuration.</td></tr><tr><td rowspan="3">Offset(4)</td><td rowspan="3">Offset error(difference between measured value at Code (0x800) and the ideal value = VREF+/2)</td><td>-</td><td>-</td><td>±10</td><td>mV</td><td>Given for the DAC in 12-bit configuration</td></tr><tr><td>-</td><td>-</td><td>±3</td><td>LSB</td><td>Given for the DAC in 10-bit at VREF+ = 3.6 V</td></tr><tr><td>-</td><td>-</td><td>±12</td><td>LSB</td><td>Given for the DAC in 12-bit at VREF+ = 3.6 V</td></tr><tr><td>Gain error(4)</td><td>Gain error</td><td>-</td><td>-</td><td>±0.5</td><td>%</td><td>Given for the DAC in 12-bit configuration</td></tr><tr><td>tSETTLING(4)</td><td>Settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when DAC_OUT reaches final value ±4LSB</td><td>-</td><td>3</td><td>6</td><td>μs</td><td>CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ</td></tr><tr><td>THD(4)</td><td>Total Harmonic Distortion Buffer ON</td><td>-</td><td>-</td><td>-</td><td>dB</td><td>CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ</td></tr><tr><td>Update rate(2)</td><td>Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB)</td><td>-</td><td>-</td><td>1</td><td>MS/s</td><td>CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ</td></tr><tr><td>tWAKEUP(4)</td><td>Wakeup time from off state (Setting the ENx bit in the DAC Control register)</td><td>-</td><td>6.5</td><td>10</td><td>μs</td><td>CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones.</td></tr><tr><td>PSRR+ (2)</td><td>Power supply rejection ratio (to VDDA) (static DC measurement)</td><td>-</td><td>-67</td><td>-40</td><td>dB</td><td>No RLOAD, CLOAD = 50 pF</td></tr></table>

1. $V_{DD}/V_{DDA}$ minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF).
2. Specified by design.
3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs.
4. Evaluated by characterization - not tested in production.

Figure 53. 12-bit buffered /non-buffered DAC
![](images/8e01b7a9db6fb916e4189c54388f31e3c6311347071a3206090d4b781d2ec3ea.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph LR
  A["12-bit digital to analog converter"] --> B["Buffer(1)"]
  B --> C["DAC_OUTx"]
  C --> D["RL"]
  D --> E["C_L"]
  E --> F["Ground"]
  F --> G["Output"]
  G --> B
```
</details>

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC\_CR register.

## 6.3.26 FSMC characteristics

Unless otherwise specified, the parameters given in Table 75 to Table 86 for the FSMC interface are derived from tests performed under the ambient temperature, $f_{HCLK}$ frequency and $V_{DD}$ supply voltage conditions summarized in Table 14, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: $0.5V_{DD}$

Refer to Section Section 6.3.16: I/O port characteristics for more details on the input/output characteristics.

## Asynchronous waveforms and timings

Figure 54 through Figure 57 represent asynchronous waveforms and Table 75 through Table 78 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration:

- AddressSetupTime = 1
- AddressHoldTime = 0x1
- DataSetupTime = 0x1
• BusTurnAroundDuration = 0x0

In all timing tables, the $T_{HCLK}$ is the HCLK clock period.

Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
![](images/3e261381fcc31bc0d33973db9c4eb2390a588275925d6438f1bc065e82aef76e.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph LR
  FSMC_NE["FSMC_NE"] -->|twNE| t_w(NE)
  FSMC_NOE["FSMC_NOE"] -->|twNOE| t_w(NOE)
  FSMC_NWE["FSMC_NWE"] -->|tvA_NE| t_v(A_NE)
  FSMC_A["25:0"] -->|Address| t_h(A_NOE)
  FSMC_NBL["1:0"] -->|tvBL_NE| t_h(BL_NOE)
  FSMC_D["15:0"] -->|tsuData_NOE| t_h(Data_NOE)
  FSMC_NADV["1"] -->|tvNADV_NE| t_w(NADV)
  FSMC_NADV -->|twNADV| t_w(NADV)
  t_w(NE)_1["t_w(NE)"] --> t_w(NE)
  t_w(NE)_2["t_w(NOE)"] --> t_h(NE_NOE)
  t_h(NE_NOE)_1["t_h(NE_NOE)"] --> t_h(NE)
  t_h(BL_NE)_1["t_v(BL_NE)"] --> t_h(BL_NOE)_1
  t_h(BL_NOE)_1["t_h(BL_NOE)"] --> t_h(Data_NE)
  t_h(Data_NE)_1["t_h(Data_NOE)"] --> t_h(Data_NOE)
  t_h(Data_NE)_2["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data_NE)_3["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data_NE)_4["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data_NE)_5["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data_NE)_6["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data_NE)_7["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data_NE)_8["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data_NE)_9["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data_NE)_10["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data_NE)_11["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data_NE)_12["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_13["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_14["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_15["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_16["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_17["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_18["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_19["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_20["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_21["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_22["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_23["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_24["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_25["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_26["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_27["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_28["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_29["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_30["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_31["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_32["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_33["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_34["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_35["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_36["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_37["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_38["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_39["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_40["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_41["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_42["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_43["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_44["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_45["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_46["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_47["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_48["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_49["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_50["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_51["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_52["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_53["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_54["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_55["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_56["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_57["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_58["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_59["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_60["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_61["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_62["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_63["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_64["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_65["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_66["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_67["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_68["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_69["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_70["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_71["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_72["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_73["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_74["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_75["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_76["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_77["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_78["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_79["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_80["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_81["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_82["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_83["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_84["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_85["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_86["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_87["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_88["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_89["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_90["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_91["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_92["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_93["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_94["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_95["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_96["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_97["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_98["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_99["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_100["t_h(Data_NOE)"] --> t_h(Data)
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:
```
</details>

1. Mode 2/B, C and D only. In Mode 1, FSMC\_NADV is not used.

Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings $^{(1)(2)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td> $t_{w(NE)}$ </td><td>FSMC_NE low time</td><td> $2T_{HCLK}-0.5$ </td><td> $2T_{HCLK}+1$ </td><td>ns</td></tr><tr><td> $t_{v(NOE_NE)}$ </td><td>FSMC_NEx low to FSMC_NOE low</td><td>0.5</td><td>3</td><td>ns</td></tr><tr><td> $t_{w(NOE)}$ </td><td>FSMC_NOE low time</td><td> $2T_{HCLK}-2$ </td><td> $2T_{HCLK}+2$ </td><td>ns</td></tr><tr><td> $t_{h(NE_NOE)}$ </td><td>FSMC_NOE high to FSMC_NE high hold time</td><td>0</td><td>-</td><td>ns</td></tr><tr><td> $t_{v(A_NE)}$ </td><td>FSMC_NEx low to FSMC_A valid</td><td>-</td><td>4.5</td><td>ns</td></tr><tr><td> $t_{h(A_NOE)}$ </td><td>Address hold time after FSMC_NOE high</td><td>4</td><td>-</td><td>ns</td></tr><tr><td> $t_{v(BL_NE)}$ </td><td>FSMC_NEx low to FSMC_BL valid</td><td>-</td><td>1.5</td><td>ns</td></tr><tr><td> $t_{h(BL_NOE)}$ </td><td>FSMC_BL hold time after FSMC_NOE high</td><td>0</td><td>-</td><td>ns</td></tr><tr><td> $t_{su(Data_NE)}$ </td><td>Data to FSMC_NEx high setup time</td><td> $T_{HCLK}+4$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{su(Data_NOE)}$ </td><td>Data to FSMC_NOEx high setup time</td><td> $T_{HCLK}+4$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{h(Data_NOE)}$ </td><td>Data hold time after FSMC_NOE high</td><td>0</td><td>-</td><td>ns</td></tr><tr><td> $t_{h(Data_NE)}$ </td><td>Data hold time after FSMC_NEx high</td><td>0</td><td>-</td><td>ns</td></tr><tr><td> $t_{v(NADV_NE)}$ </td><td>FSMC_NEx low to FSMC_NADV low</td><td>-</td><td>2</td><td>ns</td></tr><tr><td> $t_{w(NADV)}$ </td><td>FSMC_NADV low time</td><td>-</td><td> $T_{HCLK}$ </td><td>ns</td></tr></table>

1. $C_{L} = 30$ pF.
2. Evaluated by characterization - not tested in production.

Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
![](images/f0f490c2d26b8925e75f90f95652ccfc387fc43065d69360642652bea56c466b.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph LR
  FSMC_NEX["FSMC_NEX"] -->|twNE| FSMC_NEX
  FSMC_NOE["FSMC_NOE"] -->|tvNWE_NE| FSMC_NWE
  FSMC_NWE -->|tvA_NE| FSMC_A["25:0"] |
  FSMC_A["25:0"] -->|Address| FSMC_A
  FSMC_A["25:0"] -->|tvBL_NE| FSMC_NBL["1:0"] |
  FSMC_NBL["1:0"] -->|NBL| FSMC_NBL
  FSMC_D["15:0"] -->|tvData_NE| FSMC_D
  FSMC_D["15:0"] -->|tvNADV_NE| FSMC_NADV(1)
  FSMC_NADV(1) -->|twNADV| FSMC_NADV
  FSMC_NWE -->|thNE_NWE| FSMC_NWE
  FSMC_NWE -->|thA_NWE| FSMC_A
  FSMC_NWE -->|thBL_NWE| FSMC_NBL
  FSMC_NWE -->|thData_NWE| FSMC_D
  FSMC_NWE -->|thNE_NWE| FSMC_NWE
```
</details>

ai14990
1. Mode 2/B, C and D only. In Mode 1, FSMC\_NADV is not used.

Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings $^{(1)(2)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td> $t_{w(NE)}$ </td><td>FSMC_NE low time</td><td> $3T_{HCLK}$ </td><td> $3T_{HCLK}+4$ </td><td>ns</td></tr><tr><td> $t_{v(NWE\_NE)}$ </td><td>FSMC_NEx low to FSMC_NWE low</td><td> $T_{HCLK}-0.5$ </td><td> $T_{HCLK}+0.5$ </td><td>ns</td></tr><tr><td> $t_{w(NWE)}$ </td><td>FSMC_NWE low time</td><td> $T_{HCLK}-1$ </td><td> $T_{HCLK}+2$ </td><td>ns</td></tr><tr><td> $t_{h(NE\_NWE)}$ </td><td>FSMC_NWE high to FSMC_NE high hold time</td><td> $T_{HCLK}-1$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{v(A\_NE)}$ </td><td>FSMC_NEx low to FSMC_A valid</td><td>-</td><td>0</td><td>ns</td></tr><tr><td> $t_{h(A\_NWE)}$ </td><td>Address hold time after FSMC_NWE high</td><td> $T_{HCLK}-2$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{v(BL\_NE)}$ </td><td>FSMC_NEx low to FSMC_BL valid</td><td>-</td><td>1.5</td><td>ns</td></tr><tr><td> $t_{h(BL\_NWE)}$ </td><td>FSMC_BL hold time after FSMC_NWE high</td><td> $T_{HCLK}-1$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{v(Data\_NE)}$ </td><td>Data to FSMC_NEx low to Data valid</td><td>-</td><td> $T_{HCLK}+3$ </td><td>ns</td></tr><tr><td> $t_{h(Data\_NWE)}$ </td><td>Data hold time after FSMC_NWE high</td><td> $T_{HCLK}-1$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{v(NADV\_NE)}$ </td><td>FSMC_NEx low to FSMC_NADV low</td><td>-</td><td>2</td><td>ns</td></tr><tr><td> $t_{w(NADV)}$ </td><td>FSMC_NADV low time</td><td>-</td><td> $T_{HCLK}+0.5$ </td><td>ns</td></tr></table>

1. $C_{L} = 30 \, pF.$
2. Evaluated by characterization - not tested in production.

Figure 56. Asynchronous multiplexed PSRAM/NOR read waveforms
![](images/49a229d47840df23dda2e5a31055eebd8786c9022be15e3a72e9b38dff4a6163.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph LR
  FSMC_NE["FSMC_NE"] -->|twNE| FSMC_NE
  FSMC_NE -->|tvNOE_NE| FSMC_NOE
  FSMC_NOE -->|thNE_NOE| FSMC_NOE
  FSMC_NWE -->|tvA_NE| FSMC_A["25:16"]
  FSMC_A["25:16"] -->|Address| FSMC_A["25:16"]
  FSMC_A["25:16"] -->|tvBL_NE| FSMC_NBL["1:0"]
  FSMC_NBL["1:0"] -->|NBL| FSMC_NBL["1:0"]
  FSMC_NBL["1:0"] -->|tvA_NE| FSMC_AD["15:0"]
  FSMC_AD -->|Address| FSMC_AD["15:0"]
  FSMC_AD -->|tvNADV_NE| FSMC_NADV
  FSMC_NADV -->|thAD_NADV| FSMC_NADV
  FSMC_NADV -->|tvNADV| FSMC_NADV
  FSMC_NNE -->|thA_NOE| FSMC_A["25:16"]
  FSMC_A["25:16"] -->|thBL_NOE| FSMC_NBL["1:0"]
  FSMC_NBL["1:0"] -->|thData_NE| FSMC_NBL["1:0"]
  FSMC_NBL["1:0"] -->|tsuData_NE| FSMC_AD["15:0"]
  FSMC_AD -->|tsuData_NOE| FSMC_AD["15:0"]
  FSMC_AD -->|thData_NOE| FSMC_AD["15:0"]
  FSMC_AD -->|thAD_NADV| FSMC_NADV
```
</details>

Table 77. Asynchronous multiplexed PSRAM/NOR read timings $^{(1)(2)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td> $t_{w(NE)}$ </td><td>FSMC_NE low time</td><td> $3T_{HCLK}-1$ </td><td> $3T_{HCLK}+1$ </td><td>ns</td></tr><tr><td> $t_{v(NOE\_NE)}$ </td><td>FSMC_NEx low to FSMC_NOE low</td><td> $2T_{HCLK}-0.5$ </td><td> $2T_{HCLK}+0.5$ </td><td>ns</td></tr><tr><td> $t_{w(NOE)}$ </td><td>FSMC_NOE low time</td><td> $T_{HCLK}-1$ </td><td> $T_{HCLK}+1$ </td><td>ns</td></tr><tr><td> $t_{h(NE\_NOE)}$ </td><td>FSMC_NOE high to FSMC_NE high hold time</td><td>0</td><td>-</td><td>ns</td></tr><tr><td> $t_{v(A\_NE)}$ </td><td>FSMC_NEx low to FSMC_A valid</td><td>-</td><td>3</td><td>ns</td></tr><tr><td> $t_{v(NADV\_NE)}$ </td><td>FSMC_NEx low to FSMC_NADV low</td><td>1</td><td>2</td><td>ns</td></tr><tr><td> $t_{w(NADV)}$ </td><td>FSMC_NADV low time</td><td> $T_{HCLK}-2$ </td><td> $T_{HCLK}+1$ </td><td>ns</td></tr><tr><td> $t_{h(AD\_NADV)}$ </td><td>FSMC_AD(adress) valid hold time after FSMC_NADV high)</td><td> $T_{HCLK}$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{h(A\_NOE)}$ </td><td>Address hold time after FSMC_NOE high</td><td> $T_{HCLK}-1$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{h(BL\_NOE)}$ </td><td>FSMC_BL time after FSMC_NOE high</td><td>0</td><td>-</td><td>ns</td></tr><tr><td> $t_{v(BL\_NE)}$ </td><td>FSMC_NEx low to FSMC_BL valid</td><td>-</td><td>2</td><td>ns</td></tr><tr><td> $t_{su(Data\_NE)}$ </td><td>Data to FSMC_NEx high setup time</td><td> $T_{HCLK}+4$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{su(Data\_NOE)}$ </td><td>Data to FSMC_NOE high setup time</td><td> $T_{HCLK}+4$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{h(Data\_NE)}$ </td><td>Data hold time after FSMC_NEx high</td><td>0</td><td>-</td><td>ns</td></tr><tr><td> $t_{h(Data\_NOE)}$ </td><td>Data hold time after FSMC_NOE high</td><td>0</td><td>-</td><td>ns</td></tr></table>

1. $C_{L}=30\ pF.$
2. Evaluated by characterization - not tested in production.

Figure 57. Asynchronous multiplexed PSRAM/NOR write waveforms
![](images/5610ba62c658676b9e46683ae3231c04338baf8d9edc4e87d7089bc02de38e73.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph LR
  FSMC_NEX["FSMC_NEx"] -->|twNE| NWE["NWE"]
  FSMC_NOE["FSMC_NOE"] -->|tvNWE_NE| NWE
  FSMC_NWE["FSMC_NWE"] -->|tvA_NE| A["&quot;A[25:16"]"]
  FSMC_A["&quot;FSMC_A[25:16"]"] -->|Address| NBL["NBL"]
  FSMC_NBL["&quot;FSMC_NBL[1:0"]"] -->|tvBL_NE| NBL
  FSMC_AD["&quot;FSMC_AD[15:0"]"] -->|tvA_NE| AD["Address"]
  FSMC_NADV["FSMC_NADV"] -->|tvNADV_NE| AD
  FSMC_NWE -->|thNE_NWE| NWE
  FSMC_A["&quot;FSMC_A[25:16"]"] -->|thA_NWE| NWE
  FSMC_A["&quot;FSMC_A[25:16"]"] -->|thBL_NWE| NBL
  FSMC_NBL["&quot;FSMC_NBL[1:0"]"] -->|NBL| NBL
  FSMC_AD["&quot;FSMC_AD[15:0"]"] -->|tvData_NADV| Data["Data"]
  FSMC_NADV["FSMC_NADV"] -->|thAD_NADV| Data
  FSMC_AD["&quot;FSMC_AD[15:0"]"] -->|tvNADV_NE| AD
  FSMC_NADV["FSMC_NADV"] -->|twNADV| AD
```
</details>

Table 78. Asynchronous multiplexed PSRAM/NOR write timings $^{(1)(2)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td> $t_{w(NE)}$ </td><td>FSMC_NE low time</td><td> $4T_{HCLK}-0.5$ </td><td> $4T_{HCLK}+3$ </td><td>ns</td></tr><tr><td> $t_{v(NWE\_NE)}$ </td><td>FSMC_NEx low to FSMC_NWE low</td><td> $T_{HCLK}-0.5$ </td><td> $T_{HCLK}-0.5$ </td><td>ns</td></tr><tr><td> $t_{w(NWE)}$ </td><td>FSMC_NWE low tim e</td><td> $2T_{HCLK}-0.5$ </td><td> $2T_{HCLK}+3$ </td><td>ns</td></tr><tr><td> $t_{h(NE\_NWE)}$ </td><td>FSMC_NWE high to FSMC_NE high hold time</td><td> $T_{HCLK}$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{v(A\_NE)}$ </td><td>FSMC_NEx low to FSMC_A valid</td><td>-</td><td>0</td><td>ns</td></tr><tr><td> $t_{v(NADV\_NE)}$ </td><td>FSMC_NEx low to FSMC_NADV low</td><td>1</td><td>2</td><td>ns</td></tr><tr><td> $t_{w(NADV)}$ </td><td>FSMC_NADV low time</td><td> $T_{HCLK}-2$ </td><td> $T_{HCLK}+1$ </td><td>ns</td></tr><tr><td> $t_{h(AD\_NADV)}$ </td><td>FSMC_AD(address) valid hold time after FSMC_NADV high)</td><td> $T_{HCLK}-2$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{h(A\_NWE)}$ </td><td>Address hold time after FSMC_NWE high</td><td> $T_{HCLK}$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{h(BL\_NWE)}$ </td><td>FSMC_BL hold time after FSMC_NWE high</td><td> $T_{HCLK}-2$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{v(BL\_NE)}$ </td><td>FSMC_NEx low to FSMC_BL valid</td><td>-</td><td>1.5</td><td>ns</td></tr><tr><td> $t_{v(Data\_NADV)}$ </td><td>FSMC_NADV high to Data valid</td><td>-</td><td> $T_{HCLK}-0.5$ </td><td>ns</td></tr><tr><td> $t_{h(Data\_NWE)}$ </td><td>Data hold time after FSMC_NWE high</td><td> $T_{HCLK}$ </td><td>-</td><td>ns</td></tr></table>

1. $C_{L} = 30$ pF.

2. Evaluated by characterization - not tested in production.

## Synchronous waveforms and timings

Figure 58 through Figure 61 represent synchronous waveforms and Table 80 through Table 82 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration:

- BurstAccessMode = FSMC\_BurstAccessMode\_Enable;
• MemoryType = FSMC\_MemoryType\_CRAM;
• WriteBurst = FSMC\_WriteBurst\_Enable;
- CLKDivision = 1; (0 is not supported, see the STM32F40xxx/41xxx reference manual)
- DataLatency = 1 for NOR flash; DataLatency = 0 for PSRAM

In all timing tables, the $T_{HCLK}$ is the HCLK clock period (with maximum FSMC\_CLK = 60 MHz).

Figure 58. Synchronous multiplexed NOR/PSRAM read timings
![](images/5c39da83d294829aa58838c5cd5f27ea165ca9b047d9fb65f483524cb06ada0e.jpg)

<details>
<summary>flowchart</summary>

This diagram illustrates the timing and signal flow of various FSMC communication signals (CLK, NEX, NADV, A, NOE, AD, NWAIT) during a burst operation, including delay and activation states.
</details>

Table 79. Synchronous multiplexed NOR/PSRAM read timings $^{(1)(2)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td> $t_{w(CLK)}$ </td><td>FSMC_CLK period</td><td> $2T_{HCLK}$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NExL)}$ </td><td>FSMC_CLK low to FSMC_NEx low (x=0..2)</td><td>-</td><td>0</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NExH)}$ </td><td>FSMC_CLK low to FSMC_NEx high (x= 0...2)</td><td>2</td><td>-</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NADVL)}$ </td><td>FSMC_CLK low to FSMC_NADV low</td><td>-</td><td>2</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NADVH)}$ </td><td>FSMC_CLK low to FSMC_NADV high</td><td>2</td><td>-</td><td>ns</td></tr><tr><td> $t_{d(CLKL-AV)}$ </td><td>FSMC_CLK low to FSMC_Ax valid (x=16...25)</td><td>-</td><td>0</td><td>ns</td></tr><tr><td> $t_{d(CLKL-AIV)}$ </td><td>FSMC_CLK low to FSMC_Ax invalid (x=16...25)</td><td>0</td><td>-</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NOEL)}$ </td><td>FSMC_CLK low to FSMC_NOE low</td><td>-</td><td>0</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NOEH)}$ </td><td>FSMC_CLK low to FSMC_NOE high</td><td>2</td><td>-</td><td>ns</td></tr><tr><td> $t_{d(CLKL-ADV)}$ </td><td>FSMC_CLK low to FSMC_AD[15:0] valid</td><td>-</td><td>4.5</td><td>ns</td></tr><tr><td> $t_{d(CLKL-ADIV)}$ </td><td>FSMC_CLK low to FSMC_AD[15:0] invalid</td><td>0</td><td>-</td><td>ns</td></tr><tr><td> $t_{su(ADV-CLKH)}$ </td><td>FSMC_A/D[15:0] valid data before FSMC_CLK high</td><td>6</td><td>-</td><td>ns</td></tr><tr><td> $t_{h(CLKH-ADV)}$ </td><td>FSMC_A/D[15:0] valid data after FSMC_CLK high</td><td>0</td><td>-</td><td>ns</td></tr><tr><td> $t_{su(NWAIT-CLKH)}$ </td><td>FSMC_NWAIT valid before FSMC_CLK high</td><td>4</td><td>-</td><td>ns</td></tr><tr><td> $t_{h(CLKH-NWAIT)}$ </td><td>FSMC_NWAIT valid after FSMC_CLK high</td><td>0</td><td>-</td><td>ns</td></tr></table>

1. $C_{L} = 30$ pF.
2. Evaluated by characterization - not tested in production.

Figure 59. Synchronous multiplexed PSRAM write timings
![](images/7cfcca8edc0abbece58dff3d658d1b394fd83698f10032ef877849317c87f3ad.jpg)

<details>
<summary>flowchart</summary>

This diagram illustrates the timing and signal flow of various FSMC communication signals (CLK, NEx, NADV, A, NWE, AD, NWAIT, NBL) during a data delay event.
</details>

Table 80. Synchronous multiplexed PSRAM write timings $^{(1)(2)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td> $t_{w(CLK)}$ </td><td>FSMC_CLK period</td><td> $2T_{HCLK}$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NExL)}$ </td><td>FSMC_CLK low to FSMC_NEx low (x=0..2)</td><td>-</td><td>1</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NExH)}$ </td><td>FSMC_CLK low to FSMC_NEx high (x= 0...2)</td><td>1</td><td>-</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NADVL)}$ </td><td>FSMC_CLK low to FSMC_NADV low</td><td>-</td><td>0</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NADVH)}$ </td><td>FSMC_CLK low to FSMC_NADV high</td><td>0</td><td>-</td><td>ns</td></tr><tr><td> $t_{d(CLKL-AV)}$ </td><td>FSMC_CLK low to FSMC_Ax valid (x=16...25)</td><td>-</td><td>0</td><td>ns</td></tr><tr><td> $t_{d(CLKL-AIV)}$ </td><td>FSMC_CLK low to FSMC_Ax invalid (x=16...25)</td><td>8</td><td>-</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NWEL)}$ </td><td>FSMC_CLK low to FSMC_NWE low</td><td>-</td><td>0.5</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NWEH)}$ </td><td>FSMC_CLK low to FSMC_NWE high</td><td>0</td><td>-</td><td>ns</td></tr><tr><td> $t_{d(CLKL-ADIV)}$ </td><td>FSMC_CLK low to FSMC_AD[15:0] invalid</td><td>0</td><td>-</td><td>ns</td></tr><tr><td> $t_{d(CLKL-DATA)}$ </td><td>FSMC_A/D[15:0] valid data after FSMC_CLK low</td><td>-</td><td>3</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NBLH)}$ </td><td>FSMC_CLK low to FSMC_NBL high</td><td>0</td><td>-</td><td>ns</td></tr><tr><td> $t_{su(NWAIT-CLKH)}$ </td><td>FSMC_NWAIT valid before FSMC_CLK high</td><td>4</td><td>-</td><td>ns</td></tr><tr><td> $t_{h(CLKH-NWAIT)}$ </td><td>FSMC_NWAIT valid after FSMC_CLK high</td><td>0</td><td>-</td><td>ns</td></tr></table>

1. $C_{L}=30\ pF.$
2. Evaluated by characterization - not tested in production.

Figure 60. Synchronous non-multiplexed NOR/PSRAM read timings
![](images/061e40a389f32c3ca3d31b651c9829fe438f1d153e826f0578d801ea59d34a53.jpg)

<details>
<summary>flowchart</summary>

This diagram illustrates the timing and signal flow of various FSMC communication signals (CLK, NEX, NADV, A, NOE, D, NWAIT) during a burst operation, including delay and timing relationships.
</details>

Table 81. Synchronous non-multiplexed NOR/PSRAM read timings $^{(1)(2)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td> $t_{w(CLK)}$ </td><td>FSMC_CLK period</td><td> $2T_{HCLK}-0.5$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NExL)}$ </td><td>FSMC_CLK low to FSMC_NEx low (x=0..2)</td><td>-</td><td>0.5</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NExH)}$ </td><td>FSMC_CLK low to FSMC_NEx high (x=0..2)</td><td>0</td><td>-</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NADVL)}$ </td><td>FSMC_CLK low to FSMC_NADV low</td><td>-</td><td>2</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NADVH)}$ </td><td>FSMC_CLK low to FSMC_NADV high</td><td>3</td><td>-</td><td>ns</td></tr><tr><td> $t_{d(CLKL-AV)}$ </td><td>FSMC_CLK low to FSMC_Ax valid (x=16..25)</td><td>-</td><td>0</td><td>ns</td></tr><tr><td> $t_{d(CLKL-AIV)}$ </td><td>FSMC_CLK low to FSMC_Ax invalid (x=16..25)</td><td>2</td><td>-</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NOEL)}$ </td><td>FSMC_CLK low to FSMC_NOE low</td><td>-</td><td>0.5</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NOEH)}$ </td><td>FSMC_CLK low to FSMC_NOE high</td><td>1.5</td><td>-</td><td>ns</td></tr><tr><td> $t_{su(DV-CLKH)}$ </td><td>FSMC_D[15:0] valid data before FSMC_CLK high</td><td>6</td><td>-</td><td>ns</td></tr><tr><td> $t_{h(CLKH-DV)}$ </td><td>FSMC_D[15:0] valid data after FSMC_CLK high</td><td>3</td><td>-</td><td>ns</td></tr><tr><td> $t_{su(NWAIT-CLKH)}$ </td><td>FSMC_NWAIT valid before FSMC_CLK high</td><td>4</td><td>-</td><td>ns</td></tr><tr><td> $t_{h(CLKH-NWAIT)}$ </td><td>FSMC_NWAIT valid after FSMC_CLK high</td><td>0</td><td>-</td><td>ns</td></tr></table>

1. $C_{L} = 30$ pF.
2. Evaluated by characterization - not tested in production.

Figure 61. Synchronous non-multiplexed PSRAM write timings
![](images/0f56e52219b0b0572383f87f2b19b1d1b7ec282d15e04974bad4dda36081c67b.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph LR
  subgraph TimeTiming
  t_w(CLK) --> t_d(CLKL-NExL)
  t_d(CLKL-NExL) --> t_d(CLKL-NADVL)
  t_d(CLKL-NADVL) --> t_d(CLKL-NADVH)
  t_d(CLKL-NADVH) --> t_d(CLKL-AIV)
  t_d(CLKL-AIV) --> t_d(CLKL-NWEH)
  t_d(CLKL-AIV) --> t_d(CLKL-AV)
  t_d(CLKL-AV) --> t_d(CLKL-NWEL)
  t_d(CLKL-NWEL) --> t_d(CLKL-Data)
  t_d(CLKL-Data) --> t_d(CLKL-Data)
  t_d(CLKL-Data) --> D1
  D1 --> D2
  D2 --> D2
  D2 --> D1
  D1 --> t_h(CLKH-NWAITV)
  D2 --> t_h(CLKH-NWAITV)
  D1 --> t_su(NWA)TV-CLKH)
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su
```
</details>

Table 82. Synchronous non-multiplexed PSRAM write timings $^{(1)(2)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td> $t_{w(CLK)}$ </td><td>FSMC_CLK period</td><td> $2T_{HCLK}$ </td><td>-</td><td>ns</td></tr><tr><td> $t^{d(CLKL-NExL)}$ </td><td>FSMC_CLK low to FSMC_NEx low (x=0..2)</td><td>-</td><td>1</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NExH)}$ </td><td>FSMC_CLK low to FSMC_NEx high (x= 0...2)</td><td>1</td><td>-</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NADVL)}$ </td><td>FSMC_CLK low to FSMC_NADV low</td><td>-</td><td>7</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NADVH)}$ </td><td>FSMC_CLK low to FSMC_NADV high</td><td>6</td><td>-</td><td>ns</td></tr><tr><td> $t_{d(CLKL-AV)}$ </td><td>FSMC_CLK low to FSMC_Ax valid (x=16...25)</td><td>-</td><td>0</td><td>ns</td></tr><tr><td> $t_{d(CLKL-AIV)}$ </td><td>FSMC_CLK low to FSMC_Ax invalid (x=16...25)</td><td>6</td><td>-</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NWEL)}$ </td><td>FSMC_CLK low to FSMC_NWE low</td><td>-</td><td>1</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NWEH)}$ </td><td>FSMC_CLK low to FSMC_NWE high</td><td>2</td><td>-</td><td>ns</td></tr><tr><td> $t_{d(CLKL-Data)}$ </td><td>FSMC_D[15:0] valid data after FSMC_CLK low</td><td>-</td><td>3</td><td>ns</td></tr><tr><td> $t_{d(CLKL-NBLH)}$ </td><td>FSMC_CLK low to FSMC_NBL high</td><td>3</td><td>-</td><td>ns</td></tr><tr><td> $t_{su(NWAIT-CLKH)}$ </td><td>FSMC_NWAIT valid before FSMC_CLK high</td><td>4</td><td>-</td><td>ns</td></tr><tr><td> $t_{h(CLKH-NWAIT)}$ </td><td>FSMC_NWAIT valid after FSMC_CLK high</td><td>0</td><td>-</td><td>ns</td></tr></table>

1. $C_{L} = 30$ pF.
2. Evaluated by characterization - not tested in production.

## PC Card/CompactFlash controller waveforms and timings

Figure 62 through Figure 67 represent synchronous waveforms, and Table 83 and Table 84 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration:

• COM.FSMC\_SetupTime = 0x04;
• COM.FSMC\_WaitSetupTime = 0x07;
• COM.FSMC\_HoldSetupTime = 0x04;
• COM.FSMC\_HiZSetupTime = 0x00;
- ATT.FSMC\_SetupTime = 0x04;
- ATT.FSMC\_WaitSetupTime = 0x07;
• ATT.FSMC\_HoldSetupTime = 0x04;
• ATT.FSMC\_HiZSetupTime = 0x00;
• IO.FSMC\_SetupTime = 0x04;
• IO.FSMC\_WaitSetupTime = 0x07;
• IO.FSMC\_HoldSetupTime = 0x04;
• IO.FSMC\_HiZSetupTime = 0x00;
- TCLRSetupTime = 0;
- TARSetupTime = 0.

In all timing tables, the $T_{HCLK}$ is the HCLK clock period.

Figure 62. PC Card/CompactFlash controller waveforms for common memory read access
![](images/ca0c351f3789e28eca6575259acf310243ccb30f6fc8284ff6f1014289da67b8.jpg)

<details>
<summary>text_image</summary>

FSMC_NCE4_2(1)
FSMC_NCE4_1
t_v(NCEx-A)
t_h(NCEx-AI)
FSMC_A[10:0]
t_d(NREG-NCEx)
t_d(NIORD-NCEx)
t_h(NCEx-NREG)
t_h(NCEx-NIORD)
t_h(NCEx-NIOWR)
FSMC_NREG
FSMC_NIOWR
FSMC_NIORD
FSMC_NWE
t_d(NCE4_1-NOE)
t_w(NOE)
FSMC_NOE
t_su(D-NOE)
t_h(NOE-D)
FSMC_D[15:0]
ai14895b
</details>

1. FSMC\_NCE4\_2 remains high (inactive during 8-bit access.

Figure 63. PC Card/CompactFlash controller waveforms for common memory write access
![](images/ad673fc50e262191c169bf467152708d98d15e4c3ba1732e1a093eeafc263b3d.jpg)

<details>
<summary>flowchart</summary>

This diagram illustrates the timing relationships and signal transitions between various FSMC and SMC control signals, including High, NREG, NIORD, NWE, and D signals.
</details>

Figure 64. PC Card/CompactFlash controller waveforms for attribute memory read access
![](images/535aeae22c9eb56ee3169591020ae08ea4af261550936277bea2ba31bd83e1b7.jpg)

<details>
<summary>flowchart</summary>

This diagram illustrates the timing relationships and signal transitions between various FSMC communication signals (NCE4, NIOWR, NREG, NWE, NOE, D) over time.
</details>

1. Only data bits 0...7 are read (bits 8...15 are disregarded).

Figure 65. PC Card/CompactFlash controller waveforms for attribute memory write access
![](images/1956b4e2a08375c6792219175941a02ca432c91eb77237e1ffbe8df095d43fd7.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph LR
  FSMC_NCE4_1["FSMC_NCE4_1"] -->|High| FSMC_NCE4_2["FSMC_NCE4_2"]
  FSMC_NCE4_2 -->|High| FSMC_A["10:0"]["FSMC_A["10:0"]"]
  FSMC_NCE4_2 -->|High| FSMC_NIOWR["FSMC_NIOWR\nFSMC_NIORD"]
  FSMC_NCE4_2 -->|High| FSMC_NREG["FSMC_NREG"]
  FSMC_NCE4_2 -->|High| FSMC_NWE["FSMC_NWE"]
  FSMC_NCE4_2 -->|High| FSMC_NOE["FSMC_NOE"]
  FSMC_NCE4_2 -->|High| FSMC_D["7:0"](1)["FSMC_D["7:0"](1)"]
  FSMC_A["10:0"] -->|High| FSMC_A["10:0"] -->|tvNCE4_1-A| FSMC_A["10:0"] -->|thNCE4_1-AI| FSMC_A["10:0"] -->|thNCE4_1-AI| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A[
```
</details>

1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z).

Figure 66. PC Card/CompactFlash controller waveforms for I/O space read access
![](images/c8db99aecc1347a73b679434c9bccc5d2f1c1638a9769c034fcd11cdef9e384d.jpg)

<details>
<summary>text_image</summary>

FSMC_NCE4_1
FSMC_NCE4_2
t_v(NCEx-A)
t_h(NCE4_1-AI)
FSMC_A[10:0]
FSMC_NREG
FSMC_NWE
FSMC_NOE
FSMC_NIOWR
t_d(NIORD-NCE4_1)
t_w(NIORD)
FSMC_NIORD
t_su(D-NIORD)
t_d(NIORD-D)
FSMC_D[15:0]
ai14899B
</details>

Figure 67. PC Card/CompactFlash controller waveforms for I/O space write access
![](images/28d8a0a4a6ae8598b19cebeec654ca8a2b9413627b4ac648911f6333918c7aa7.jpg)

<details>
<summary>text_image</summary>

FSMC_NCE4_1
FSMC_NCE4_2
t_v(NCEx-A)
t_h(NCE4_1-AI)
FSMC_A[10:0]
FSMC_NREG
FSMC_NWE
FSMC_NOE
FSMC_NIORD
t_d(NCE4_1-NIOWR)
t_w(NIOWR)
FSMC_NIOWR
ATTxHIZ =1
t_v(NIOWR-D)
t_h(NIOWR-D)
FSMC_D[15:0]
ai14900c
</details>

Table 83. Switching characteristics for PC Card/CF read and write cycles in attribute/common space $^{(1)(2)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td> $t_{v(NCEx-A)}$ </td><td>FSMC_Ncex low to FSMC_Ay valid</td><td>-</td><td>0</td><td>ns</td></tr><tr><td> $t_{h(NCEx_AI)}$ </td><td>FSMC_NCEx high to FSMC_Ax invalid</td><td>4</td><td>-</td><td>ns</td></tr><tr><td> $t_{d(NREG-NCEx)}$ </td><td>FSMC_NCEx low to FSMC_NREG valid</td><td>-</td><td>3.5</td><td>ns</td></tr><tr><td> $t_{h(NCEx-NREG)}$ </td><td>FSMC_NCEx high to FSMC_NREG invalid</td><td> $T_{HCLK}+4$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{d(NCEx-NWE)}$ </td><td>FSMC_NCEx low to FSMC_NWE low</td><td>-</td><td> $5T_{HCLK}+0.5$ </td><td>ns</td></tr><tr><td> $t_{d(NCEx-NOE)}$ </td><td>FSMC_NCEx low to FSMC_NOE low</td><td>-</td><td> $5T_{HCLK}+0.5$ </td><td>ns</td></tr><tr><td> $t_{w(NOE)}$ </td><td>FSMC_NOE low width</td><td> $8T_{HCLK}-1$ </td><td> $8T_{HCLK}+1$ </td><td>ns</td></tr><tr><td> $t_{d(NOE_NCEx)}$ </td><td>FSMC_NOE high to FSMC_NCEx high</td><td> $5T_{HCLK}+2.5$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{su(D-NOE)}$ </td><td>FSMC_D[15:0] valid data before FSMC_NOE high</td><td>4.5</td><td>-</td><td>ns</td></tr><tr><td> $t_{h(NOE-D)}$ </td><td>FSMC_NOE high to FSMC_D[15:0] invalid</td><td>3</td><td>-</td><td>ns</td></tr><tr><td> $t_{w(NWE)}$ </td><td>FSMC_NWE low width</td><td> $8T_{HCLK}-0.5$ </td><td> $8T_{HCLK}+3$ </td><td>ns</td></tr><tr><td> $t_{d(NWE_NCEx)}$ </td><td>FSMC_NWE high to FSMC_NCEx high</td><td> $5T_{HCLK}-1$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{d(NCEx-NWE)}$ </td><td>FSMC_NCEx low to FSMC_NWE low</td><td>-</td><td> $5T_{HCLK}+1$ </td><td>ns</td></tr><tr><td> $t_{v(NWE-D)}$ </td><td>FSMC_NWE low to FSMC_D[15:0] valid</td><td>-</td><td>0</td><td>ns</td></tr><tr><td> $t_{h(NWE-D)}$ </td><td>FSMC_NWE high to FSMC_D[15:0] invalid</td><td> $8T_{HCLK}-1$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{d(D-NWE)}$ </td><td>FSMC_D[15:0] valid before FSMC_NWE high</td><td> $13T_{HCLK}-1$ </td><td>-</td><td>ns</td></tr></table>

1. $C_{L}=30\ pF.$
2. Evaluated by characterization - not tested in production.

Table 84. Switching characteristics for PC Card/CF read and write cycles in I/O space $^{(1)(2)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td> $t_{w(NIOWR)}$ </td><td>FSMC_NIOWR low width</td><td> $8T_{HCLK}-1$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{v(NIOWR-D)}$ </td><td>FSMC_NIOWR low to FSMC_D[15:0] valid</td><td>-</td><td> $5T_{HCLK}-1$ </td><td>ns</td></tr><tr><td> $t_{h(NIOWR-D)}$ </td><td>FSMC_NIOWR high to FSMC_D[15:0] invalid</td><td> $8T_{HCLK}-2$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{d(NCE4_1-NIOWR)}$ </td><td>FSMC_NCE4_1 low to FSMC_NIOWR valid</td><td>-</td><td> $5T_{HCLK}+2.5$ </td><td>ns</td></tr><tr><td> $t_{h(NCEx-NIOWR)}$ </td><td>FSMC_NCEx high to FSMC_NIOWR invalid</td><td> $5T_{HCLK}-1.5$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{d(NIORD-NCEx)}$ </td><td>FSMC_NCEx low to FSMC_NIORD valid</td><td>-</td><td> $5T_{HCLK}+2$ </td><td>ns</td></tr><tr><td> $t_{h(NCEx-NIORD)}$ </td><td>FSMC_NCEx high to FSMC_NIORD) valid</td><td> $5T_{HCLK}-1.5$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{w(NIORD)}$ </td><td>FSMC_NIORD low width</td><td> $8T_{HCLK}-0.5$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{su(D-NIORD)}$ </td><td>FSMC_D[15:0] valid before FSMC_NIORD high</td><td>9</td><td>-</td><td>ns</td></tr><tr><td> $t_{d(NIORD-D)}$ </td><td>FSMC_D[15:0] valid after FSMC_NIORD high</td><td>0</td><td>-</td><td>ns</td></tr></table>

1. $C_{L}=30\ pF.$
2. Evaluated by characterization - not tested in production.

## NAND controller waveforms and timings

Figure 68 and Figure 69 represent synchronous waveforms, and Table 85 and Table 86 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration:

• COM.FSMC\_SetupTime = 0x01;
• COM.FSMC\_WaitSetupTime = 0x03;
• COM.FSMC\_HoldSetupTime = 0x02;
• COM.FSMC\_HiZSetupTime = 0x01;
- ATT.FSMC\_SetupTime = 0x01;
• ATT.FSMC\_WaitSetupTime = 0x03;
• ATT.FSMC\_HoldSetupTime = 0x02;
• ATT.FSMC\_HiZSetupTime = 0x01;
• Bank = FSMC\_Bank\_NAND;
• MemoryDataWidth = FSMC\_MemoryDataWidth\_16b;
- ECC = FSMC\_ECC\_Enable;
- ECCPageSize = FSMC\_ECCPageSize\_512Bytes;
- TCLRSetupTime = 0;
- TARSetupTime = 0.

In all timing tables, the $T_{HCLK}$ is the HCLK clock period.

Figure 68. NAND controller waveforms for read access
![](images/f23d8a3afa7084ff789e50faa5e4cb2d6d78b4e152c66a07c686b058a52c2979.jpg)

<details>
<summary>text_image</summary>

FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
FMC_NOE (NRE)
FMC_D[y:0]
MSv73150V1
td(ALE-NOE)
tw(NOE)
tsu(D-NOE)
th(NOE-ALE)
th(D-NOE-D)
</details>

1. y = 7 or 15 depending on the NAND flash memory interface.

Figure 69. NAND controller waveforms for write access
![](images/db35c3636e7482ac099e821614450e0df97d24478942e6f29282a48331b4a5e3.jpg)

<details>
<summary>text_image</summary>

FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
FMC_NOE (NRE)
FMC_D[y:0]
MSv73151V1
td(ALE-NWE)
tw(NWE)
th(NWE-ALE)
td(D-NWE)
tv(NWE-D)
th(NWE-D)
</details>

1. y = 7 or 15 depending on the NAND flash memory interface.

Table 85. Switching characteristics for NAND flash read cycles $^{(1)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td> $t_{w(NOE)}$ </td><td>FSMC_NOE low width</td><td> $4T_{HCLK-0.5}$ </td><td> $4T_{HCLK+3}$ </td><td>ns</td></tr><tr><td> $t_{su(D-NOE)}$ </td><td>FSMC_D[15-0] valid data before FSMC_NOE high</td><td>10</td><td>-</td><td>ns</td></tr><tr><td> $t_{h(NOE-D)}$ </td><td>FSMC_D[15-0] valid data after FSMC_NOE high</td><td>0</td><td>-</td><td>ns</td></tr><tr><td> $t_{d(ALE-NOE)}$ </td><td>FSMC_ALE valid before FSMC_NOE low</td><td>-</td><td> $3T_{HCLK}$ </td><td>ns</td></tr><tr><td> $t_{h(NOE-ALE)}$ </td><td>FSMC_NWE high to FSMC_ALE invalid</td><td> $3T_{HCLK-2}$ </td><td>-</td><td>ns</td></tr></table>

1. $C_{L}=30\ pF.$

Table 86. Switching characteristics for NAND flash write cycles $^{(1)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td> $t_{w(NWE)}$ </td><td>FSMC_NWE low width</td><td> $4T_{HCLK}-1$ </td><td> $4T_{HCLK}+3$ </td><td>ns</td></tr><tr><td> $t_{v(NWE-D)}$ </td><td>FSMC_NWE low to FSMC_D[15-0] valid</td><td>-</td><td>0</td><td>ns</td></tr><tr><td> $t_{h(NWE-D)}$ </td><td>FSMC_NWE high to FSMC_D[15-0] invalid</td><td> $3T_{HCLK}-2$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{d(D-NWE)}$ </td><td>FSMC_D[15-0] valid before FSMC_NWE high</td><td> $5T_{HCLK}-3$ </td><td>-</td><td>ns</td></tr><tr><td> $t_{d(ALE-NWE)}$ </td><td>FSMC_ALE valid before FSMC_NWE low</td><td>-</td><td> $3T_{HCLK}$ </td><td>ns</td></tr><tr><td> $t_{h(NWE-ALE)}$ </td><td>FSMC_NWE high to FSMC_ALE invalid</td><td> $3T_{HCLK}-2$ </td><td>-</td><td>ns</td></tr></table>

1. $C_{L} = 30$ pF.

## 6.3.27 Camera interface (DCMI) timing specifications

Unless otherwise specified, the parameters given in Table 87 for DCMI are derived from tests performed under the ambient temperature, $f_{HCLK}$ frequency and $V_{DD}$ supply voltage summarized in Table 13, with the following configuration:

- PCK polarity: falling
• VSYNC and HSYNC polarity: high
• Data format: 14 bits

Figure 70. DCMI timing diagram
![](images/99663c43a379a7a794d6119297ad0bb3d49d278b0102685d72381e91e28d67ae.jpg)

<details>
<summary>text_image</summary>

1/DCMI_PIXCLK
DCMI_PIXCLK
DCMI_HSYNC
DCMI_VSYNC
DATA[0:13]
tsu(HSYNC)
th(HSYNC)
tsu(VSYNC)
th(HSYNC)
tsu(DATA)
th(DATA)
MS32414V2
</details>

Table 87. DCMI characteristics $^{(1)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td>-</td><td>Frequency ratio DCMI_PIXCLK/ $f_{HCLK}$ </td><td>-</td><td>0.4</td><td>-</td></tr><tr><td>DCMI_PIXCLK</td><td>Pixel clock input</td><td>-</td><td>54</td><td>MHz</td></tr><tr><td> $D_{pixel}$ </td><td>Pixel clock input duty cycle</td><td>30</td><td>70</td><td>%</td></tr><tr><td> $t_{su(DATA)}$ </td><td>Data input setup time</td><td>2.5</td><td>-</td><td rowspan="4">ns</td></tr><tr><td> $t_{h(DATA)}$ </td><td>Data hold time</td><td>1</td><td>-</td></tr><tr><td> $t_{su(HSYNC)}, t_{su(VSYNC)}$ </td><td>HSYNC/VSYNC input setup time</td><td>2</td><td>-</td></tr><tr><td> $t_{h(HSYNC)}, t_{h(VSYNC)}$ </td><td>HSYNC/VSYNC input hold time</td><td>0.5</td><td>-</td></tr></table>

1. Evaluated by characterization - not tested in production.

## 6.3.28 SD/SDIO MMC card host interface (SDIO) characteristics

Unless otherwise specified, the parameters given in Table 88 are derived from tests performed under ambient temperature, $f_{PCLKx}$ frequency and $V_{DD}$ supply voltage conditions summarized in Table 14 with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: $0.5V_{DD}$

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output characteristics.

Figure 71. SDIO high-speed mode
![](images/280a4f24c2bba91de6ba196494044fadde9da62e2e141a03bf51a6ea0830e527.jpg)

<details>
<summary>text_image</summary>

tf
tr
tC
tW(CKH)
tW(CKL)
CK
tOV
tOH
D, CMD
(output)
tISU
tIH
D, CMD
(input)
</details>

ai14887

Figure 72. SD default mode
![](images/1d2e30c59794905cacff8be2632293ba0c463114cd0a1595472dd5a8a63b0e34.jpg)

<details>
<summary>text_image</summary>

CK
D, CMD
(output)
tOVD
tOHD
</details>

ai14888

Table 88. Dynamic characteristics: SD/MMC characteristics $^{(1)}$

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td> $f_{PP}$ </td><td>Clock frequency in data transfer mode</td><td>-</td><td>0</td><td>-</td><td>48</td><td>MHz</td></tr><tr><td></td><td>SDIO_CK/ $f_{PCLK2}$  frequency ratio</td><td>-</td><td>-</td><td>-</td><td>8/3</td><td>-</td></tr><tr><td> $t_{W(CKL)}$ </td><td>Clock low time</td><td> $f_{PP}=48 MHz$ </td><td>8.5</td><td>9</td><td>-</td><td rowspan="2">ns</td></tr><tr><td> $t_{W(CKH)}$ </td><td>Clock high time</td><td> $f_{PP}=48 MHz$ </td><td>8.3</td><td>10</td><td>-</td></tr><tr><td colspan="7">CMD, D inputs (referenced to CK) in MMC and SD HS mode</td></tr><tr><td> $t_{ISU}$ </td><td>Input setup time HS</td><td> $f_{PP}=48 MHz$ </td><td>3</td><td>-</td><td>-</td><td rowspan="2">ns</td></tr><tr><td> $t_{IH}$ </td><td>Input hold time HS</td><td> $f_{PP}=48 MHz$ </td><td>0</td><td>-</td><td>-</td></tr><tr><td colspan="7">CMD, D outputs (referenced to CK) in MMC and SD HS mode</td></tr><tr><td> $t_{OV}$ </td><td>Output valid time HS</td><td> $f_{PP}=48 MHz$ </td><td>-</td><td>4.5</td><td>6</td><td rowspan="2">ns</td></tr><tr><td> $t_{OH}$ </td><td>Output hold time HS</td><td> $f_{PP}=48 MHz$ </td><td>1</td><td>-</td><td>-</td></tr><tr><td colspan="7">CMD, D inputs (referenced to CK) in SD default mode</td></tr><tr><td> $t_{ISUD}$ </td><td>Input setup time SD</td><td> $f_{PP}=24 MHz$ </td><td>1.5</td><td>-</td><td>-</td><td rowspan="2">ns</td></tr><tr><td> $t_{IHD}$ </td><td>Input hold time SD</td><td> $f_{PP}=24 MHz$ </td><td>0.5</td><td>-</td><td>-</td></tr><tr><td colspan="7">CMD, D outputs (referenced to CK) in SD default mode</td></tr><tr><td> $t_{OVD}$ </td><td>Output valid default time SD</td><td> $f_{PP}=24 MHz$ </td><td>-</td><td>4.5</td><td>7</td><td rowspan="2">ns</td></tr><tr><td> $t_{OHD}$ </td><td>Output hold default time SD</td><td> $f_{PP}=24 MHz$ </td><td>0.5</td><td>-</td><td>-</td></tr></table>

1. Evaluated by characterization - not tested in production.

## 6.3.29 RTC characteristics

Table 89. RTC characteristics

<table><tr><td>Symbol</td><td>Parameter</td><td>Conditions</td><td>Min</td><td>Max</td></tr><tr><td>-</td><td> $f_{PCLK1}$ /RTCCLK frequency ratio</td><td>Any read/write operation from/to an RTC register</td><td>4</td><td>-</td></tr></table>

## 7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

## 7.1 Device marking

Refer to technical note “Reference device marking schematics for STM32 microcontrollers and microprocessors” (TN1433), available on www.st.com, for the location of pin 1 / ball A1 as well as the location and orientation of the marking areas versus pin 1 / ball A1.

Parts marked as “ES”, “E”, or accompanied by an engineering sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

A WLCSP simplified marking example (if any) is provided in the corresponding package information subsection.

## 7.2 WLCSP90 package information

Figure 73. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package outline
![](images/7ae644e951340baa15d24be02bedc19fc28ebe055cafbf4f6b9439f133f20f2b.jpg)

<details>
<summary>text_image</summary>

e1
A1 ball location
10
e
1
A
e
e2
J
G
F
</details>

BOTTOM VIEW
BUMP SIDE

![](images/68e8bc61db5423c94a26b1eef35e173fa3f4b8ea9f4691159a0c821da7c78937.jpg)

<details>
<summary>text_image</summary>

//bbb Z
Detail A
A3
A2
A
</details>

SIDE VIEW

![](images/815dba851dd57d873ec59d1233017da7eec95c56cb8fe7845689799b2c08d936.jpg)

<details>
<summary>text_image</summary>

A
A2
A3
</details>

FRONT VIEW

![](images/3ca3d2fcd92c1b395d48adeb0110075be1856cb42f575ffa0ae50fe6b1a82d2d.jpg)

<details>
<summary>text_image</summary>

D
A1 orientation
reference
E
aaa
(4X)
</details>

TOP VIEW
WAFER BACK SIDE

![](images/eacc88b98db99ccbad610d5e55cbca136fedd43b03dbd4a20a7c5727c19e6d25.jpg)

<details>
<summary>text_image</summary>

Bump
eee
A1
b
Seating plane
Z
a
X
φ
φccc
φddd
Detail A
(Rotated 90°)
</details>

A0JW\_ME\_V4
1. Drawing is not to scale.

Table 90. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package mechanical data

<table><tr><td rowspan="2">Symbol</td><td colspan="3">millimeters</td><td colspan="3">inches(1)</td></tr><tr><td>Min</td><td>Typ</td><td>Max</td><td>Min</td><td>Typ</td><td>Max</td></tr><tr><td>A</td><td>0.540</td><td>0.570</td><td>0.600</td><td>0.0213</td><td>0.0224</td><td>0.0236</td></tr><tr><td>A1</td><td>-</td><td>0.190</td><td>-</td><td>-</td><td>0.0075</td><td>-</td></tr><tr><td>A2</td><td>-</td><td>0.380</td><td>-</td><td>-</td><td>0.0150</td><td>-</td></tr><tr><td>A3(2)</td><td>-</td><td>0.025</td><td>-</td><td>-</td><td>0.0010</td><td>-</td></tr><tr><td>b(3)</td><td>0.240</td><td>0.270</td><td>0.300</td><td>0.0094</td><td>0.0106</td><td>0.0118</td></tr><tr><td>D</td><td>4.188</td><td>4.223</td><td>4.258</td><td>0.1649</td><td>0.1663</td><td>0.1676</td></tr><tr><td>E</td><td>3.934</td><td>3.969</td><td>4.004</td><td>0.1549</td><td>0.1563</td><td>0.1576</td></tr><tr><td>e</td><td>-</td><td>0.400</td><td>-</td><td>-</td><td>0.0157</td><td>-</td></tr><tr><td>e1</td><td>-</td><td>3.600</td><td>-</td><td>-</td><td>0.1417</td><td>-</td></tr><tr><td>e2</td><td>-</td><td>3.200</td><td>-</td><td>-</td><td>0.1260</td><td>-</td></tr><tr><td>F</td><td>-</td><td>0.3115</td><td>-</td><td>-</td><td>0.0123</td><td>-</td></tr><tr><td>G</td><td>-</td><td>0.3845</td><td>-</td><td>-</td><td>0.0151</td><td>-</td></tr><tr><td>aaa</td><td>-</td><td>0.100</td><td>-</td><td>-</td><td>0.0039</td><td>-</td></tr><tr><td>bbb</td><td>-</td><td>0.100</td><td>-</td><td>-</td><td>0.0039</td><td>-</td></tr><tr><td>ccc</td><td>-</td><td>0.100</td><td>-</td><td>-</td><td>0.0039</td><td>-</td></tr><tr><td>ddd</td><td>-</td><td>0.050</td><td>-</td><td>-</td><td>0.0020</td><td>-</td></tr><tr><td>eee</td><td>-</td><td>0.050</td><td>-</td><td>-</td><td>0.0020</td><td>-</td></tr></table>

1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Back side coating.
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

Figure 74. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package recommended footprint
![](images/794902aba32af466e37183ebc18bdc0567a0e4592507a68cbfad20eb371adb8d.jpg)

<details>
<summary>text_image</summary>

Dpad
Dsm
</details>

MS18965V2

Table 91. WLCSP90 recommended PCB design rules

<table><tr><td>Dimension</td><td>Recommended values</td></tr><tr><td>Pitch</td><td>0.4 mm</td></tr><tr><td>Dpad</td><td>260 μm max. (circular)220 μm recommended</td></tr><tr><td>Dsm</td><td>300 μm min. (for 260 μm diameter pad)</td></tr><tr><td>PCB pad design</td><td>Non-solder mask defined via underbump allowed</td></tr></table>

## Device marking for WLCSP90

The following figure gives an example of topside marking and ball A1 position identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

Figure 75. WLCSP90 marking example (package top view)
![](images/402f91e81866d7b8d0e61f625a0748c39e77fc67c88c743f25417c3b74c7837c.jpg)
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity.

## 7.3 LQFP64 package information (5W)

This LQFP is 64-pin, 10 x 10 mm low-profile quad flat package.

Figure 76. LQFP64 - Outline $^{(15)}$
![](images/b201b10df84708366c6caef2e0f4adb0f7d8ee665370418e227210336725f617.jpg)

<details>
<summary>text_image</summary>

BOTTOM VIEW
4x N/4 TIPS
aaa C A-B
D 1/4
(6)
E 1/4
bbb H A-B D 4x
SECTION A-A
θ2
(2)
θ1
R1
R2
SECTION B-B
B
0.25
θ
S
L
L1
(1) (11)
θ3
(13) (N - 4)x
A
A2 A1 (12)
b
ddd C A-B D
ccc C
(0.05)
C
D
(4)
(5) (2)
D1
(10)
N
E 1/4
D 1/4
(6)
(3) A
A
(Section A-A)
B (3)
(5) (2)
E1
E
(9) (11)
WITH PLATING
(11)
c
c1
b1 (11)
BASE METAL
SECTION B-B
TOP VIEW
5W_LQFP64_ME_V1
</details>

Table 92. LQFP64 - Mechanical data

<table><tr><td rowspan="2">Symbol</td><td colspan="3">millimeters</td><td colspan="3">inches(14)</td></tr><tr><td>Min</td><td>Typ</td><td>Max</td><td>Min</td><td>Typ</td><td>Max</td></tr><tr><td>A</td><td>-</td><td>-</td><td>1.60</td><td>-</td><td>-</td><td>0.0630</td></tr><tr><td>A1(12)</td><td>0.05</td><td>-</td><td>0.15</td><td>0.0020</td><td>-</td><td>0.0059</td></tr><tr><td>A2</td><td>1.35</td><td>1.40</td><td>1.45</td><td>0.0531</td><td>0.0551</td><td>0.0570</td></tr><tr><td>b(9)(11)</td><td>0.17</td><td>0.22</td><td>0.27</td><td>0.0067</td><td>0.0087</td><td>0.0106</td></tr><tr><td>b1(11)</td><td>0.17</td><td>0.20</td><td>0.23</td><td>0.0067</td><td>0.0079</td><td>0.0091</td></tr><tr><td>c(11)</td><td>0.09</td><td>-</td><td>0.20</td><td>0.0035</td><td>-</td><td>0.0079</td></tr><tr><td>c1(11)</td><td>0.09</td><td>-</td><td>0.16</td><td>0.0035</td><td>-</td><td>0.0063</td></tr><tr><td>D(4)</td><td colspan="3">12.00 BSC</td><td colspan="3">0.4724 BSC</td></tr><tr><td>D1(2)(5)</td><td colspan="3">10.00 BSC</td><td colspan="3">0.3937 BSC</td></tr><tr><td>E(4)</td><td colspan="3">12.00 BSC</td><td colspan="3">0.4724 BSC</td></tr><tr><td>E1(2)(5)</td><td colspan="3">10.00 BSC</td><td colspan="3">0.3937 BSC</td></tr><tr><td>e</td><td colspan="3">0.50 BSC</td><td colspan="3">0.1970 BSC</td></tr><tr><td>L</td><td>0.45</td><td>0.60</td><td>0.75</td><td>0.0177</td><td>0.0236</td><td>0.0295</td></tr><tr><td>L1</td><td colspan="3">1.00 REF</td><td colspan="3">0.0394 REF</td></tr><tr><td>N(13)</td><td colspan="6">64</td></tr><tr><td>θ</td><td>0°</td><td>3.5°</td><td>7°</td><td>0°</td><td>3.5°</td><td>7°</td></tr><tr><td>θ1</td><td>0°</td><td>-</td><td>-</td><td>0°</td><td>-</td><td>-</td></tr><tr><td>θ2</td><td>10°</td><td>12°</td><td>14°</td><td>10°</td><td>12°</td><td>14°</td></tr><tr><td>θ3</td><td>10°</td><td>12°</td><td>14°</td><td>10°</td><td>12°</td><td>14°</td></tr><tr><td>R1</td><td>0.08</td><td>-</td><td>-</td><td>0.0031</td><td>-</td><td>-</td></tr><tr><td>R2</td><td>0.08</td><td>-</td><td>0.20</td><td>0.0031</td><td>-</td><td>0.0079</td></tr><tr><td>S</td><td>0.20</td><td>-</td><td>-</td><td>0.0079</td><td>-</td><td>-</td></tr><tr><td>aaa(1)</td><td colspan="3">0.20</td><td colspan="3">0.0079</td></tr><tr><td>bbb(1)</td><td colspan="3">0.20</td><td colspan="3">0.0079</td></tr><tr><td>ccc(1)</td><td colspan="3">0.08</td><td colspan="3">0.0031</td></tr><tr><td>ddd(1)</td><td colspan="3">0.08</td><td colspan="3">0.0031</td></tr></table>

## Notes:

1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum "b" dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

## 7.4 LQFP100 package information (1L)

This LQFP is a 100-pin, 14 x 14 mm low-profile quad flat package.

Note: See list of notes in the notes section.

Figure 77. LQFP100 - Outline $^{(15)}$
![](images/21c3def3fe44322c4459a0cc41ab8be3533c699504796c257ccfe99ec62348ab.jpg)

<details>
<summary>text_image</summary>

4x N/4 TIPS
aaa C A-B D
D1/4
(6)
E1/4
4x
bbb H A-B D
</details>

BOTTOM VIEW

![](images/db885cad95b69a71a9485694c362df93a65e0393fdfcc468db98876ab2a010eb.jpg)

<details>
<summary>text_image</summary>

H
θ2
(2)
θ1
R1
R2
SECTION B-B
B
Gauge PLANE
θ
S
L
θ3
L1
</details>

(1) (11)
SECTION A-A

![](images/749e1e631abaf450abe0419c6ca4e24ec6719fb48e79b28a45a5310e960dfecd.jpg)

<details>
<summary>text_image</summary>

(N-4) x e
(13)
A
0.05
A2
A1
(12)
b
φ aaa③C A-BD
C
ccc|C
</details>

SIDE VIEW

![](images/a8035baa59a0aa9dd7e8072f1c9cbd9a688c96b12a8e780524be91027d74b120.jpg)

<details>
<summary>text_image</summary>

(9) (11)
b
WITH PLATING
(11) c
c1 (11)
b1 (11)
BASE METAL
</details>

SECTION B-B

![](images/89bf64ca1c93931c9f35e7f61abb6d36360a7518e6997e705a4e9858b3ce702a.jpg)

<details>
<summary>text_image</summary>

(2) (5)
(10)
N
D
D1
D (3)
E1/4
E1
E
(6)
A
SECTION A-A
A
B
(4)
(2)
(5)
E
</details>

TOP VIEW
1L\_LQFP100\_ME\_V3

Table 93. LQFP100 - Mechanical data

<table><tr><td rowspan="2">Symbol</td><td colspan="3">millimeters</td><td colspan="3">inches(14)</td></tr><tr><td>Min</td><td>Typ</td><td>Max</td><td>Min</td><td>Typ</td><td>Max</td></tr><tr><td>A</td><td>-</td><td>1.50</td><td>1.60</td><td>-</td><td>0.0590</td><td>0.0630</td></tr><tr><td>A1(12)</td><td>0.05</td><td>-</td><td>0.15</td><td>0.0019</td><td>-</td><td>0.0059</td></tr><tr><td>A2</td><td>1.35</td><td>1.40</td><td>1.45</td><td>0.0531</td><td>0.0551</td><td>0.0570</td></tr><tr><td>b(9)(11)</td><td>0.17</td><td>0.22</td><td>0.27</td><td>0.0067</td><td>0.0087</td><td>0.0106</td></tr><tr><td>b1(11)</td><td>0.17</td><td>0.20</td><td>0.23</td><td>0.0067</td><td>0.0079</td><td>0.0090</td></tr><tr><td>c(11)</td><td>0.09</td><td>-</td><td>0.20</td><td>0.0035</td><td>-</td><td>0.0079</td></tr><tr><td>c1(11)</td><td>0.09</td><td>-</td><td>0.16</td><td>0.0035</td><td>-</td><td>0.0063</td></tr><tr><td>D(4)</td><td colspan="3">16.00 BSC</td><td colspan="3">0.6299 BSC</td></tr><tr><td>D1(2)(5)</td><td colspan="3">14.00 BSC</td><td colspan="3">0.5512 BSC</td></tr><tr><td>E(4)</td><td colspan="3">16.00 BSC</td><td colspan="3">0.6299 BSC</td></tr><tr><td>E1(2)(5)</td><td colspan="3">14.00 BSC</td><td colspan="3">0.5512 BSC</td></tr><tr><td>e</td><td colspan="3">0.50 BSC</td><td colspan="3">0.0197 BSC</td></tr><tr><td>L</td><td>0.45</td><td>0.60</td><td>0.75</td><td>0.177</td><td>0.0236</td><td>0.0295</td></tr><tr><td>L1(1)(11)</td><td colspan="3">1.00</td><td>-</td><td>0.0394</td><td>-</td></tr><tr><td>N(13)</td><td colspan="6">100</td></tr><tr><td>θ</td><td>0°</td><td>3.5°</td><td>7°</td><td>0°</td><td>3.5°</td><td>7°</td></tr><tr><td>θ1</td><td>0°</td><td>-</td><td>-</td><td>0°</td><td>-</td><td>-</td></tr><tr><td>θ2</td><td>10°</td><td>12°</td><td>14°</td><td>10°</td><td>12°</td><td>14°</td></tr><tr><td>θ3</td><td>10°</td><td>12°</td><td>14°</td><td>10°</td><td>12°</td><td>14°</td></tr><tr><td>R1</td><td>0.08</td><td>-</td><td>-</td><td>0.0031</td><td>-</td><td>-</td></tr><tr><td>R2</td><td>0.08</td><td>-</td><td>0.20</td><td>0.0031</td><td>-</td><td>0.0079</td></tr><tr><td>S</td><td>0.20</td><td>-</td><td>-</td><td>0.0079</td><td>-</td><td>-</td></tr><tr><td>aaa(1)</td><td colspan="3">0.20</td><td colspan="3">0.0079</td></tr><tr><td>bbb(1)</td><td colspan="3">0.20</td><td colspan="3">0.0079</td></tr><tr><td>ccc(1)</td><td colspan="3">0.08</td><td colspan="3">0.0031</td></tr><tr><td>ddd(1)</td><td colspan="3">0.08</td><td colspan="3">0.0031</td></tr></table>

## Notes:

1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at the seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All dimensions are in millimeters.
8. No intrusion is allowed inwards the leads.
9. Dimension b does not include a dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. The dambar cannot be located on the lower radius or the foot. The minimum space between the protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. The exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead that is between 0.10 mm and 0.25 mm from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package body.
13. N is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to four decimal digits.
15. Drawing is not to scale.

Figure 78. LQFP100 - Footprint example
![](images/d9eb9c817dfb473474ae761ced338a79218c89bca021bf373094693bedcb4562.jpg)

<details>
<summary>text_image</summary>

75
51
76
0.5
0.3
16.7
14.3
100
26
1
25
1.2
12.3
16.7
</details>

1L\_LQFP100\_FP\_V1
1. Dimensions are expressed in millimeters.

## 7.5 LQFP144 package information (1A)

This LQFP is a 144-pin, 20 x 20 mm low-profile quad flat package.

Note: See list of notes in the notes section.

Figure 79. LQFP144 - Outline $^{(15)}$
![](images/e1d4d72598833ca2251f07ebe0fe976ac25a9584d225009831716f198a3fb653.jpg)

<details>
<summary>text_image</summary>

BOTTOM VIEW
4x N/4 TIPS
aaa C A-B D
D 1/4
(6)
E 1/4
bbb H A-B D 4x
SECTION A-A
θ2
(2)
θ1
R1
R2
SECTION B-B
B
0.25
θ
S
L
θ3
(L1)
(1) (11)
N-4)x e
A
0.05 A2 A1 (12)
b
ddd C A-B D
ccc C
D
D1
(4)
(2)(5)
(10)
N
(3)
D
E 1/4
(6)
(3) A
D 1/4
B (3)
(2)
(5)
E1 E
(Section A-A)
A
A
(Section A-A)
B
WITH PLATING
WITH PLATING
(11) c
c1 (11)
BASE METAL
SECTION B-B
TOP VIEW
1A_LQFP144_ME_V2
</details>

Table 94. LQFP144 - Mechanical data

<table><tr><td rowspan="2">Symbol</td><td colspan="3">millimeters</td><td colspan="3">inches(14)</td></tr><tr><td>Min</td><td>Typ</td><td>Max</td><td>Min</td><td>Typ</td><td>Max</td></tr><tr><td>A</td><td>-</td><td>-</td><td>1.60</td><td>-</td><td>-</td><td>0.0630</td></tr><tr><td>A1(12)</td><td>0.05</td><td>-</td><td>0.15</td><td>0.0020</td><td>-</td><td>0.0059</td></tr><tr><td>A2</td><td>1.35</td><td>1.40</td><td>1.45</td><td>0.0531</td><td>0.0551</td><td>0.0571</td></tr><tr><td>b(9)(11)</td><td>0.17</td><td>0.22</td><td>0.27</td><td>0.0067</td><td>0.0087</td><td>0.0106</td></tr><tr><td>b1(11)</td><td>0.17</td><td>0.20</td><td>0.23</td><td>0.0067</td><td>0.0079</td><td>0.0090</td></tr><tr><td>c(11)</td><td>0.09</td><td>-</td><td>0.20</td><td>0.0035</td><td>-</td><td>0.0079</td></tr><tr><td>c1(11)</td><td>0.09</td><td>-</td><td>0.16</td><td>0.0035</td><td>-</td><td>0.0063</td></tr><tr><td>D(4)</td><td colspan="3">22.00 BSC</td><td colspan="3">0.8661 BSC</td></tr><tr><td>D1(2)(5)</td><td colspan="3">20.00 BSC</td><td colspan="3">0.7874 BSC</td></tr><tr><td>E(4)</td><td colspan="3">22.00 BSC</td><td colspan="3">0.8661 BSC</td></tr><tr><td>E1(2)(5)</td><td colspan="3">20.00 BSC</td><td colspan="3">0.7874 BSC</td></tr><tr><td>e</td><td colspan="3">0.50 BSC</td><td colspan="3">0.0197 BSC</td></tr><tr><td>L</td><td>0.45</td><td>0.60</td><td>0.75</td><td>0.0177</td><td>0.0236</td><td>0.0295</td></tr><tr><td>L1</td><td colspan="3">1.00 REF</td><td colspan="3">0.0394 REF</td></tr><tr><td>N(13)</td><td colspan="6">144</td></tr><tr><td>θ</td><td>0°</td><td>3.5°</td><td>7°</td><td>0°</td><td>3.5°</td><td>7°</td></tr><tr><td>θ1</td><td>0°</td><td>-</td><td>-</td><td>0°</td><td>-</td><td>-</td></tr><tr><td>θ2</td><td>10°</td><td>12°</td><td>14°</td><td>10°</td><td>12°</td><td>14°</td></tr><tr><td>θ3</td><td>10°</td><td>12°</td><td>14°</td><td>10°</td><td>12°</td><td>14°</td></tr><tr><td>R1</td><td>0.08</td><td>-</td><td>-</td><td>0.0031</td><td>-</td><td>-</td></tr><tr><td>R2</td><td>0.08</td><td>-</td><td>0.20</td><td>0.0031</td><td>-</td><td>0.0079</td></tr><tr><td>S</td><td>0.20</td><td>-</td><td>-</td><td>0.0079</td><td>-</td><td>-</td></tr><tr><td>aaa</td><td colspan="3">0.20</td><td colspan="3">0.0079</td></tr><tr><td>bbb</td><td colspan="3">0.20</td><td colspan="3">0.0079</td></tr><tr><td>ccc</td><td colspan="3">0.08</td><td colspan="3">0.0031</td></tr><tr><td>ddd</td><td colspan="3">0.08</td><td colspan="3">0.0031</td></tr></table>

## Notes:

1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at the seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All dimensions are in millimeters.
8. No intrusion is allowed inwards the leads.
9. Dimension b does not include a dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. The dambar cannot be located on the lower radius or the foot. The minimum space between the protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. The exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead that is between 0.10 mm and 0.25 mm from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package body.
13. N is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to four decimal digits.
15. Drawing is not to scale.

Figure 80. LQFP144 - Footprint example
![](images/8af32403a3ba9a5ec07dade1a4af7c2f21bc12e9e18ceaa6d5b89f49fad5e12d.jpg)

<details>
<summary>text_image</summary>

108
109
0.35
0.50
144
1
19.90
36
22.60
73
1.35
72
17.85
37
22.60
</details>

1A\_LQFP144\_FP
1. Dimensions are expressed in millimeters.

## 7.6 UFBGA(176+25) package information (A0E7)

This UFBGA is a 176+25-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package.

Figure 81. UFBGA(176+25) - Outline
![](images/521c91db9d5e96ce9276b4169fb452aed36c402517d62be5dc590644f1c96fd6.jpg)

<details>
<summary>text_image</summary>

Seating plane
C A4
A2 A3 b A1 A
ddd C
A1 ball
identifier
E1
F
A
D1
e
e
R
15 1
BOTTOM VIEW
Øb (176 + 25 balls)
Ø eee M C A B
Ø fff M C
A1 ball
index
area
E
D
B
TOP VIEW
A0E7_ME_V10
</details>

1. Drawing is not to scale.

Table 95. UFBGA(176+25) - Mechanical data

<table><tr><td rowspan="2">Symbol</td><td colspan="3">millimeters</td><td colspan="3">inches(1)</td></tr><tr><td>Min.</td><td>Typ.</td><td>Max.</td><td>Min.</td><td>Typ.</td><td>Max.</td></tr><tr><td>A</td><td>-</td><td>-</td><td>0.600</td><td>-</td><td>-</td><td>0.0236</td></tr><tr><td>A1</td><td>0.050</td><td>0.080</td><td>0.110</td><td>0.0020</td><td>0.0031</td><td>0.0043</td></tr><tr><td>A2</td><td>-</td><td>0.450</td><td>-</td><td>-</td><td>0.0177</td><td>-</td></tr><tr><td>A3</td><td>-</td><td>0.130</td><td>-</td><td>-</td><td>0.0051</td><td>-</td></tr><tr><td>A4</td><td>-</td><td>0.320</td><td>-</td><td>-</td><td>0.0126</td><td>-</td></tr><tr><td>b</td><td>0.240</td><td>0.290</td><td>0.340</td><td>0.0094</td><td>0.0114</td><td>0.0134</td></tr><tr><td>D</td><td>9.850</td><td>10.000</td><td>10.150</td><td>0.3878</td><td>0.3937</td><td>0.3996</td></tr><tr><td>D1</td><td>-</td><td>9.100</td><td>-</td><td>-</td><td>0.3583</td><td>-</td></tr><tr><td>E</td><td>9.850</td><td>10.000</td><td>10.150</td><td>0.3878</td><td>0.3937</td><td>0.3996</td></tr><tr><td>E1</td><td>-</td><td>9.100</td><td>-</td><td>-</td><td>0.3583</td><td>-</td></tr><tr><td>e</td><td>-</td><td>0.650</td><td>-</td><td>-</td><td>0.0256</td><td>-</td></tr><tr><td>F</td><td>-</td><td>0.450</td><td>-</td><td>-</td><td>0.0177</td><td>-</td></tr><tr><td>ddd</td><td>-</td><td>-</td><td>0.080</td><td>-</td><td>-</td><td>0.0031</td></tr><tr><td>eee</td><td>-</td><td>-</td><td>0.150</td><td>-</td><td>-</td><td>0.0059</td></tr><tr><td>fff</td><td>-</td><td>-</td><td>0.050</td><td>-</td><td>-</td><td>0.0020</td></tr></table>

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 82. UFBGA(176+25) - Footprint example
![](images/b6bec8fdd6621f5dcd5269c8bc9670692ef317a81ab3b698861974317c43836b.jpg)

<details>
<summary>text_image</summary>

Dpad
Dsm
</details>

BGA\_WLCSP\_FT\_V1

Table 96. UFBGA(176+25) - Example of PCB design rules (0.65 mm pitch BGA)

<table><tr><td>Dimension</td><td>Values</td></tr><tr><td>Pitch</td><td>0.65 mm</td></tr><tr><td>Dpad</td><td>0.300 mm</td></tr><tr><td>Dsm</td><td>0.400 mm typ. (depends on the soldermask registration tolerance)</td></tr><tr><td>Stencil opening</td><td>0.300 mm</td></tr><tr><td>Stencil thickness</td><td>Between 0.100 mm and 0.125 mm</td></tr><tr><td>Pad trace width</td><td>0.100 mm</td></tr></table>

## 7.7 LQFP176 package information (1T)

This LQFP is a 176-pin, 24 x 24 mm, 0.5 mm pitch, low profile quad flat package.

Note: See list of notes in the notes section.

Figure 83. LQFP176 - Outline $^{(15)}$
![](images/65c2c2d54666dcdf3d5ad1b4ff48d27a64832b4b03594fd50f516891923b9afa.jpg)

<details>
<summary>text_image</summary>

4x N/4 TIPS
aaa C A-B D
D1/4
(6)
E1/4
4x
bbb H A-B D
</details>

BOTTOM VIEW

![](images/7cdd6a799ced32f613a93512dab4b9b6b35500a921eea1b1ecc256807b1bf1b8.jpg)

<details>
<summary>text_image</summary>

θ2
(2)
R1
R2
B(See SECTION B-B)
GAUGE PLANE
0.25
θ
S
L
θ3
(L1)
(1) (11)
</details>

SECTION A-A

![](images/d5416f5cc43dbe8491b845312f107eb635f335a18cac515a49527da264b854ce.jpg)

<details>
<summary>text_image</summary>

A2 0.05
(N-4) x e (13)
A
A1 (12)
b
φ dddM C A-BD
C
ccc C
</details>

SIDE VIEW

![](images/74261157a42be5ea33584e0110d3b997c3472a2cbaaf9c117e4f6f75022cc4b8.jpg)

<details>
<summary>text_image</summary>

(2) (5)
(10)
N
E1/4
D1
D
(3)
D1/4
(6)
A
B
(3)
(5)
(2)
E1 E
SECTION A-A
A
A
</details>

TOP VIEW

![](images/fad043c0f441a829b6e7631806482dafd1c246110652571b474640695c861a1c.jpg)

<details>
<summary>text_image</summary>

(9) (11)
WITH PLATING
(11) c
c1 (11)
b1 (11)
BASE METAL
</details>

SECTION B-B

1T\_LQFP176\_ME\_V2

Table 97. LQFP176 - Mechanical data

<table><tr><td rowspan="2">Symbol</td><td colspan="3">millimeters</td><td colspan="3">inches(14)</td></tr><tr><td>Min</td><td>Typ</td><td>Max</td><td>Min</td><td>Typ</td><td>Max</td></tr><tr><td>A</td><td>-</td><td>-</td><td>1.600</td><td>-</td><td>-</td><td>0.0630</td></tr><tr><td>A1(12)</td><td>0.050</td><td>-</td><td>0.150</td><td>0.0020</td><td>-</td><td>0.0059</td></tr><tr><td>A2</td><td>1.350</td><td>1.400</td><td>1.450</td><td>0.0531</td><td>0.0551</td><td>0.0571</td></tr><tr><td>b(9)(11)</td><td>0.170</td><td>0.220</td><td>0.270</td><td>0.0067</td><td>0.0087</td><td>0.0106</td></tr><tr><td>b1(11)</td><td>0.170</td><td>0.200</td><td>0.230</td><td>0.0067</td><td>0.0079</td><td>0.0091</td></tr><tr><td>c(11)</td><td>0.090</td><td>-</td><td>0.200</td><td>0.0035</td><td>-</td><td>0.0079</td></tr><tr><td>c1(11)</td><td>0.090</td><td>-</td><td>0.160</td><td>0.0035</td><td>-</td><td>0.063</td></tr><tr><td>D(4)</td><td colspan="3">26.000</td><td colspan="3">1.0236</td></tr><tr><td>D1(2)(5)</td><td colspan="3">24.000</td><td colspan="3">0.9449</td></tr><tr><td>E(4)</td><td colspan="3">26.000</td><td colspan="3">0.0197</td></tr><tr><td>E1(2)(5)</td><td colspan="3">24.000</td><td colspan="3">0.9449</td></tr><tr><td>e</td><td colspan="3">0.500</td><td colspan="3">0.1970</td></tr><tr><td>L</td><td>0.450</td><td>0.600</td><td>0.750</td><td>0.0177</td><td>0.0236</td><td>0.0295</td></tr><tr><td>L1(1)(11)</td><td colspan="3">1</td><td colspan="3">0.0394 REF</td></tr><tr><td>N(13)</td><td colspan="6">176</td></tr><tr><td>θ</td><td>0°</td><td>3.5°</td><td>7°</td><td>0°</td><td>3.5°</td><td>7°</td></tr><tr><td>θ1</td><td>0°</td><td>-</td><td>-</td><td>0°</td><td>-</td><td>-</td></tr><tr><td>θ2</td><td>10°</td><td>12°</td><td>14°</td><td>10°</td><td>12°</td><td>14°</td></tr><tr><td>θ3</td><td>10°</td><td>12°</td><td>14°</td><td>10°</td><td>12°</td><td>14°</td></tr><tr><td>R1</td><td>0.080</td><td>-</td><td>-</td><td>0.0031</td><td>-</td><td>-</td></tr><tr><td>R2</td><td>0.080</td><td>-</td><td>0.200</td><td>0.0031</td><td>-</td><td>0.0079</td></tr><tr><td>S</td><td>0.200</td><td>-</td><td>-</td><td>0.0079</td><td>-</td><td>-</td></tr><tr><td>aaa(1)</td><td colspan="3">0.200</td><td colspan="3">0.0079</td></tr><tr><td>bbb(1)</td><td colspan="3">0.200</td><td colspan="3">0.0079</td></tr><tr><td>ccc(1)</td><td colspan="3">0.080</td><td colspan="3">0.0031</td></tr><tr><td>ddd(1)</td><td colspan="3">0.080</td><td colspan="3">0.0031</td></tr></table>

## Notes:

1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at the seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All dimensions are in millimeters.
8. No intrusion is allowed inwards the leads.
9. Dimension b does not include a dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. The dambar cannot be located on the lower radius or the foot. The minimum space between the protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. The exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead that is between 0.10 mm and 0.25 mm from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package body.
13. N is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to four decimal digits.
15. Drawing is not to scale.

Figure 84. LQFP176 - Footprint example
![](images/25338432a12398f110ced7303a8330022b9c549c91e6d655311024eb233a6211.jpg)

<details>
<summary>text_image</summary>

176
1
0.5
133
132
0.3
26.7
21.8
44
45
89
88
1.2
21.8
26.7
1T_FP_V1
</details>

1. Dimensions are expressed in millimeters.

## 7.8 Thermal characteristics

The maximum chip-junction temperature, $T_{J}$ max, in degrees Celsius, may be calculated using the following equation:

$$
T _ {J} \max = T _ {A} \max + (P _ {D} \max \times \Theta_ {J A})
$$

Where:

- $T_{A}$ max is the maximum ambient temperature in $^{\circ}C$ ,
- $\Theta_{JA}$ is the package junction-to-ambient thermal resistance, in $^\circ C/W$ ,
- $P_{D}$ max is the sum of $P_{INT}$ max and $P_{I/O}$ max ( $P_{D}$ max = $P_{INT}$ max + $P_{I/O}$ max),
- $P_{INT}$ max is the product of $I_{DD}$ and $V_{DD}$ , expressed in Watts. This is the maximum chip internal power.

$P_{I/O}$ max represents the maximum power dissipation on output pins where:

$$
P _ {I / O} \max = \Sigma (V _ {O L} \times I _ {O L}) + \Sigma ((V _ {D D} - V _ {O H}) \times I _ {O H}),
$$

taking into account the actual $V_{OL} / I_{OL}$ and $V_{OH} / I_{OH}$ of the I/Os at low and high level in the application.

Table 98. Package thermal characteristics

<table><tr><td>Symbol</td><td>Parameter</td><td>Value</td><td>Unit</td></tr><tr><td rowspan="6"> $\Theta_{JA}$ </td><td>Thermal resistance junction-ambientLQFP64 - 10 × 10 mm / 0.5 mm pitch</td><td>46</td><td rowspan="6">°C/W</td></tr><tr><td>Thermal resistance junction-ambientLQFP100 - 14 × 14 mm / 0.5 mm pitch</td><td>43</td></tr><tr><td>Thermal resistance junction-ambientLQFP144 - 20 × 20 mm / 0.5 mm pitch</td><td>40</td></tr><tr><td>Thermal resistance junction-ambientLQFP176 - 24 × 24 mm / 0.5 mm pitch</td><td>38</td></tr><tr><td>Thermal resistance junction-ambientUFBGA176 - 10× 10 mm / 0.65 mm pitch</td><td>39</td></tr><tr><td>Thermal resistance junction-ambientWLCSP90 - 0.400 mm pitch</td><td>38.1</td></tr></table>

## Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org.

## 8 Ordering information

![](images/f7e1bb4f4c0eacd89b36ceabb933fcdc83364ab45d6981bfc0c3434934e62c89.jpg)

For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.

## Appendix A Application block diagrams

## A.1 USB OTG full speed (FS) interface solutions

Figure 85. USB controller configured as peripheral-only and used in Full speed mode
![](images/ff18b01365baec3b3959827cb892b0cbb12ab28d7b703ca74e101a4240a027a6.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph LR
  VDD["VDD"] -->|Input| STM32F4xx
  STM32F4xx -->|OSC_IN| OSC_IN
  STM32F4xx -->|OSC_OUT| OSC_OUT
  OSC_IN -->|PA11//PB14| USBStdBConnector
  OSC_OUT -->|PA12/PB15| USBStdBConnector
  USBStdBconnector["USB Std-B connector"] -->|VBUS| n5VToVdd["5V to VDD"]
  USBStdBconnector -->|DM| n5VToVdd
  USBStdBconnector -->|DP| n5VToVdd
  USBStdBconnector -->|Vss| VSS["VSS"]
```
</details>

1. External voltage regulator only needed when building a $V_{BUS}$ powered device.
2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.

Figure 86. USB controller configured as host-only and used in full speed mode
![](images/44507c8686d0bfa4a00e93b242ba27d5e5a047b1fc872fc9367ebd4a7940c577.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph LR
  Input["Input"] -->|OSC_IN| STM32F4xx
  Input -->|OSC_OUT| STM32F4xx
  STM32F4xx -->|GPIO| CurrentLimiter["Current limiter power switch(1)"]
  STM32F4xx -->|GPIO+IRQ| CurrentLimiter
  CurrentLimiter -->|EN| CurrentLimiter
  CurrentLimiter -->|Overcurrent| CurrentLimiter
  CurrentLimiter -->|5 V Pwr| USBStdA["USB Std-A connector"]
  CurrentLimiter -->|VBUS| USBStdA
  CurrentLimiter -->|DM| USBStdA
  CurrentLimiter -->|DP| USBStdA
  CurrentLimiter -->|VSS| USBStdA
  USBStdA -->|VSS| Output["Output"]
```
</details>

1. The current limiter is required only if the application has to support a $V_{BUS}$ powered device. A basic power switch can be used if 5 V are available on the application board.
2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.

Figure 87. USB controller configured in dual mode and used in full speed mode
![](images/0de551f602e085c1a4a577a1402cdf644e1651c790825d57e9422d236b59c9ac.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph LR
  VDD["VDD"] --> GPIO["GPIO"]
  GPIO -->|EN| CurrentLimiter["Current limiter power switch(2)"]
  CurrentLimiter -->|5 V Pwr| VDD
  CurrentLimiter -->|Overcurrent| GPIO
  VDD --> VDDRegulator["5 V to VDD voltage regulator(1)"]
  VDDRegulator --> VDDRegulator
  VDDRegulator --> USBMicro["USBmicro-AB connector"]
  USBMicro -->|VBUS| PA9/PB13["PA9/PB13"]
  USBMicro -->|DM| PA11/PB14["PA11/PB14"]
  USBMicro -->|DP| PA12/PB15["PA12/PB15"]
  USBMicro -->|ID3| PA10/PB12["PA10/PB12"]
  PA9Pb13["PA9/PB13"] --> USBMicro
  PA11Pb14["PA11/PB14"] --> USBMicro
  PA12Pb15["PA12/PB15"] --> USBMicro
  PA10Pb12["PA10/PB12"] --> USBMicro
  VSS["Vss"] --> USBMicro
```
</details>

1. External voltage regulator only needed when building a $V_{BUS}$ powered device.
2. The current limiter is required only if the application has to support a $V_{BUS}$ powered device. A basic power switch can be used if 5 V are available on the application board.
3. The ID pin is required in dual role only.
4. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.

## A.2 USB OTG high speed (HS) interface solutions

Figure 88. USB controller configured as peripheral, host, or dual-mode and used in high speed mode
![](images/38ca1b32ee113fde58e85d15138277e7ea5bc7cc43be55759144bf06855d95c3.jpg)

<details>
<summary>flowchart</summary>

```mermaid
graph LR
  subgraph STM32F4xx
  A["USB HS\nOTG Ctrl"] -->|DP not connected| B["FS PHY"]
  B -->|DM not connected| A
  B -->|DP not connected| C["High speed\nOTG PHY"]
  D["ULPI_CLK"] --> C
  E["&quot;ULPI_D[7:0"]"] --> C
  F["ULPI_DIR"] --> C
  G["ULPI_STP"] --> C
  H["ULPI_NXT"] --> C
  I["PLL"] --> J["PLL"]
  J --> K["24 or 26 MHz XT(1)"]
  K --> L["XT1"]
  L --> M["MCO1 or MCO2"]
  M --> N["XI"]
  end
  subgraph USBconnector
    O["USB connector"]
  end
  C --> O
  C --> O
  C --> P["DP"]
  C --> Q["DM"]
  C --> R["ID(2)"]
  C --> S["VBUS"]
  C --> T["VSS"]
```
</details>

1. It is possible to use MCO1 or MCO2 to save a crystal. It is however not mandatory to clock the STM32F40xxx with a 24 or 26 MHz crystal when using USB HS. The above figure only shows an example of a possible connection.
2. The ID pin is required in dual role only.

## A.3 Ethernet interface solutions

Figure 89. MII mode using a 25 MHz crystal
![](images/81b4801d4e59d2f95f4db12a8ac0db5bf74c70d210e25458888679f7b56b7603.jpg)

<details>
<summary>flowchart</summary>

This diagram illustrates the architecture and signal flow of an STM32 microcontroller, showing the interaction between the MCU, Ethernet, PTP, and MT2 components with associated data streams and control signals.
</details>

1. $f_{HCLK}$ must be greater than 25 MHz.
2. Pulse per second when using IEEE1588 PTP optional signal.

Figure 90. RMII with a 50 MHz oscillator
![](images/7802e22cffbb991efc52c0968efaad40507a32beb7a91f42576b000ce8b25d93.jpg)

<details>
<summary>flowchart</summary>

This diagram illustrates the architecture and signal flow of an STM32 microcontroller, showing the interaction between the MCU, Ethernet MAC, and LTE (XT1) via clock and timer input, and the corresponding data flow between the two.
</details>

1. $f_{HCLK}$ must be greater than 25 MHz.

Figure 91. RMII with a 25 MHz crystal and PHY with PLL
![](images/85c073900cd2a2e7bf9269876dad2dd37c08deb495f5f9566a425f1aba0536c4.jpg)

<details>
<summary>flowchart</summary>

This diagram illustrates the architecture and signal flow of an STM32F microcontroller, showing the interaction between the MCU, Ethernet, and PHY components with associated data streams and timing parameters.
</details>

1. $f_{HCLK}$ must be greater than 25 MHz.
2. The 25 MHz (PHY\_CLK) must be derived directly from the HSE oscillator, before the PLL block.

## 9 Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST product(s) identified in this documentation may be certified by various security certification bodies and/or may implement our own security measures as set forth herein. However, no level of security certification and/or built-in security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the customer needs both in relation to the ST product alone, as well as when combined with other components and/or software for the customer end product or application. In particular, take note that:

- ST products may have been certified by one or more security certification bodies, such as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received security certification along with the level and current status of such certification, either visit the relevant certification standards website or go to the relevant product page on www.st.com for the most up to date information. As the status and/or level of security certification for an ST product can change from time to time, customers should re-check security certification status/level as needed. If an ST product is not shown to be certified under a particular security standard, customers should not assume it is certified.
- Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST products. These certification bodies are therefore independently responsible for granting or revoking security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations, assessments, testing, or other activity carried out by the certification body with respect to any ST product.
- Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard technologies which may be used in conjunction with an ST product are based on standards which were not developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open technologies or for any methods which have been or may be developed to bypass, decrypt or crack such algorithms or technologies.
- While robust security testing may be done, no level of certification can absolutely guarantee protections against all attacks, including, for example, against advanced attacks which have not been tested for, against new or unidentified forms of attack, or against any form of attack when using an ST product outside of its specification or intended use, or in conjunction with other components or software which are used by customer to create their end product or application. ST is not responsible for resistance against such attacks. As such, regardless of the incorporated security features and/or any information or support that may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for meets their needs, both in relation to the ST product alone and when incorporated into a customer end product or application.
- All security features of ST products (inclusive of any hardware, software, documentation, and the like), including but not limited to any enhanced security features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the applicable written and signed contract terms specifically provide otherwise.

## 10 Revision history

Table 99. Document revision history

<table><tr><td>Date</td><td>Revision</td><td>Changes</td></tr><tr><td>15-Sep-2011</td><td>1</td><td>Initial release.</td></tr><tr><td>24-Jan-2012</td><td>2</td><td>Added WLCSP90 package on cover page.Renamed USART4 and USART5 into UART4 and UART5, respectively.Updated number of USB OTG HS and FS in Table 3: STM32F405xx and STM32F407xx: features and peripheral counts.Updated Figure 3: Compatible board design between STM32F10xx/STM32F2/STM32F40xxx for LQFP144 package and Figure 4: Compatible board design between STM32F2 and STM32F40xxx for LQFP176 and BGA176 packages, and removed note 1 and 2.Updated Section 3.0.9: Flexible static memory controller (FSMC).Modified I/Os used to reprogram the flash memory for CAN2 and USB OTG FS in Section 3.0.13: Boot modes.Updated note in Section 3.0.14: Power supply schemes.PDR_ON no more available on LQFP100 package. Updated Section 3.0.16: Voltage regulator. Updated condition to obtain a minimum supply voltage of 1.7 V in the whole document.Renamed USART4/5 to UART4/5 and added LIN and IrDA feature for UART4 and UART5 in Table 6: USART feature comparison.Removed support of I2C for OTG PHY in Section 3.0.30: Universal serial bus on-the-go full-speed (OTG_FS).Added Table 7: Legend/abbreviations used in the pinout table.Table 8: STM32F40xxx pin and ball definitions: replaced VSS_3, VSS_4, and VSS_8 by VSS; reformatted Table 8: STM32F40xxx pin and ball definitions to better highlight I/O structure, and alternate functions versus additional functions; signal corresponding to LQFP100 pin 99 changed from PDR_ON to VSS; EVENTOUT added in the list of alternate functions for all I/Os; ADC3_IN8 added as alternate function for PF10; FSMC_CLE and FSMC_ALE added as alternate functions for PD11 and PD12, respectively; PH10 alternate function TIM15_CH1_ETR renamed TIM5_CH1; updated PA4 and PA5 I/O structure to TTa.Removed OTG_HS_SCL, OTG_HS_SDA, OTG_FS_INTN in Table 8: STM32F40xxx pin and ball definitions and Table 10: Alternate function mapping.Changed TCM data RAM to CCM data RAM in Figure 18: STM32F40xxx memory map.Added IVDD and IVSS maximum values in Table 14: Current characteristics.Added Note 1 related to fHCLK, updated Note 2 in Table 16: General operating conditions, and added maximum power dissipation values.Updated Table 17: Limitations depending on the operating power supply range.</td></tr><tr><td>24-Jan-2012</td><td>2(continued)</td><td>Added V12 in Table 21: Embedded reset and power control block characteristics.Updated Table 23: Typical and maximum current consumption in Run mode, code with data processing running from flash memory (ART accelerator disabled) and Table 22: Typical and maximum current consumption in Run mode, code with data processing running from flash memory (ART accelerator enabled) or RAM. Added Figure , Figure 25, Figure 26, and Figure 27.Updated Table 24: Typical and maximum current consumption in Sleep mode and removed Note 1.Updated Table 25: Typical and maximum current consumptions in Stop mode and Table 26: Typical and maximum current consumptions in Standby mode, Table 27: Typical and maximum current consumptions in VBAT mode, and Table 29: Switching output I/O current consumption.Section : On-chip peripheral current consumption: modified conditions, and updated Table 30: Peripheral current consumption and Note 2.Changed fHSE_ext to 50 MHz and tr(HSE)/tf(HSE) maximum value in Table 32: High-speed external user clock characteristics.Added Cin(LSE) in Table 33: Low-speed external user clock characteristics.Updated maximum PLL input clock frequency, removed related note, and deleted jitter for MCO for RMII Ethernet typical value in Table 38: Main PLL characteristics. Updated maximum PLLI2S input clock frequency and removed related note in Table 39: PLLI2S (audio PLL) characteristics.Updated Section : Flash memory to specify that the devices are shipped to customers with the flash memory erased. Updated Table 41: Flash memory characteristics, and added tME in Table 42: Flash memory programming.Updated Table 45: EMS characteristics, and Table 46: EMI characteristics.Updated Table 58: I2S dynamic characteristicsUpdated Figure 45: ULPI timing diagram and Table 64: ULPI timing.Added tCOUNTER and tMAX_COUNT in Table 54: Characteristics of TIMx connected to the APB1 domain and Table 55: Characteristics of TIMx connected to the APB2 domain. Updated Table 67: Dynamic characteristics: Ethernet MAC signals for RMII.Removed USB-IF certification in Section : USB OTG FS characteristics.</td></tr><tr><td>24-Jan-2012</td><td>2(continued)</td><td>Updated Table 63: USB HS clock timing parametersUpdated Table 69: ADC characteristics.Updated Table 70: ADC accuracy at fADC = 30 MHz.Updated Note 1 in Table 76: DAC characteristics.Section 6.3.26: FSMC characteristics: updated Table 77 toTable 88, changed CL value to 30 pF, and modified FSMC configuration for asynchronous timings and waveforms. Updated Figure 59: Synchronous multiplexed PSRAM write timings.Updated Table 100: Package thermal characteristics.Appendix A.1: USB OTG full speed (FS) interface solutions: modified Figure 93: USB controller configured as peripheral-only and used in Full speed mode added Note 2, updated Figure 94: USB controller configured as host-only and used in full speed mode and added Note 2, changed Figure 95: USB controller configured in dual mode and used in full speed mode and added Note 3.Appendix A.2: USB OTG high speed (HS) interface solutions: removed figures USB OTG HS device-only connection in FS mode and USB OTG HS host-only connection in FS mode, and updated Figure 96: USB controller configured as peripheral, host, or dual-mode and used in high speed mode and added Note 2.Added Appendix A.3: Ethernet interface solutions.</td></tr><tr><td>31-May-2012</td><td>3</td><td>Updated Figure 5: STM32F40xxx block diagram and Figure 7: Power supply supervisor interconnection with internal reset OFFAdded SDIO, added notes related to FSMC and SPI/I2S in Table 3: STM32F405xx and STM32F407xx: features and peripheral counts.Starting from Silicon revision Z, USB OTG full-speed interface is now available for all STM32F405xx devices.Added full information on WLCSP90 package together with corresponding part numbers.Changed number of AHB buses to 3.Modified available flash memory sizes in Section 3.0.4: Embedded flash memory.Modified number of maskable interrupt channels in Section 3.0.10: Nested vectored interrupt controller (NVIC).Updated case of Regulator ON/internal reset ON, Regulator ON/internal reset OFF, and Regulator OFF/internal reset ON in Section 3.0.16: Voltage regulator.Updated standby mode description in Section 3.0.19: Low-power modes.Added Note 1 below Figure 16: STM32F40xxx UFBGA176 bailout.Added Note 1 below Figure 17: STM32F40xxx WLCSP90 bailout.Updated Table 8: STM32F40xxx pin and ball definitions.Added Table 9: FSMC pin definition.Removed OTG_HS_INTN alternate function in Table 8: STM32F40xxx pin and ball definitions and Table 10: Alternate function mapping.Removed I2S2_WS on PB6/AF5 in Table 10: Alternate function mapping.Replaced JTRST by NJTRST, removed ETH_RMII _TX_CLK, and modified I2S3ext_SD on PC11 in Table 10: Alternate function mapping.Added Table 12: register boundary addresses.Updated Figure 18: STM32F40xxx memory map.Updated VDDA and VREF+ decoupling capacitor in Figure 21: Power supply scheme.Added power dissipation maximum value for WLCSP90 in Table 16: General operating conditions.Updated VPOR/PDR in Table 21: Embedded reset and power control block characteristics.Updated notes in Table 23: Typical and maximum current consumption in Run mode, code with data processing running from flash memory (ART accelerator disabled), Table 22: Typical and maximum current consumption in Run mode, code with data processing running from flash memory (ART accelerator enabled) or RAM, and Table 24: Typical and maximum current consumption in Sleep mode.Updated maximum current consumption at TA = 25 °n Table 25: Typical and maximum current consumptions in Stop mode.</td></tr><tr><td>31-May-2012</td><td>3(continued)</td><td>Removed fHSE_ext typical value in Table 32: High-speed external user clock characteristics. Updated Table 34: HSE 4-26 MHz oscillator characteristics and Table 35: LSE oscillator characteristics (fLSE = 32.768 kHz).Added fPLL48_OUT maximum value in Table 38: Main PLL characteristics.Modified equation 1 and 2 in Section 6.3.11: PLL spread spectrum clock generation (SSCG) characteristics.Updated Table 41: Flash memory characteristics, Table 42: Flash memory programming, and Table 43: Flash memory programming with VPP.Updated Section : Output driving current.Table 56: I2C characteristics: Note 4 updated and applied to th(SDA) in Fast mode, and removed note 4 related to th(SDA) minimum value.Updated Table 69: ADC characteristics. Updated note concerning ADC accuracy vs. negative injection current below Table 70: ADC accuracy at fADC = 30 MHz.Added WLCSP90 thermal resistance in Table 100: Package thermal characteristics.Updated Table 92: WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package mechanical data.Updated Figure 87: UFBGA176+25 ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outline and Table 97: UFBGA176+25 ball, 10 x 10 x 0.65 mm pitch, ultra thin fine pitch ball grid array mechanical data.Added Figure 91: LQFP176 - 176-pin, 24 x 24 mm low profile quad flat recommended footprint.Removed 256 and 768 Kbyte flash memory density from Table : .</td></tr><tr><td>04-Jun-2013</td><td>4</td><td>Modified Note 1 below Table 3: STM32F405xx and STM32F407xx: features and peripheral counts.Updated Figure 4 title.Updated Note 3 below Figure 21: Power supply scheme.Changed simplex mode into half-duplex mode in Section 3.0.25: Inter-integrated sound (I2S).Replaced DAC1_OUT and DAC2_OUT by DAC_OUT1 and DAC_OUT2, respectively.Updated pin 36 signal in Figure 15: STM32F40xxx LQFP176 pinout.Changed pin number from F8 to D4 for PA13 pin in Table 8: STM32F40xxx pin and ball definitions.Replaced TIM2_CH1/TIM2_ETR by TIM2_CH1_ETR for PA0 and PA5 pins in Table 10: Alternate function mapping.Changed system memory into System memory + OTP in Figure 18: STM32F40xxx memory map.Added Note 1 below Table 18: VCAP_1/VCAP_2 operating conditions.Updated IDDA description in Table 76: DAC characteristics.Removed PA9/PB13 connection to VBUS in Figure 93: USB controller configured as peripheral-only and used in Full speed mode and Figure 94: USB controller configured as host-only and used in full speed mode.Updated SPI throughput on front page and Section 3.0.24: Serial peripheral interface (SPI)Updated operating voltages in Table 3: STM32F405xx and STM32F407xx: features and peripheral counts.Updated note in Section 3.0.14: Power supply schemesUpdated Section 3.0.15: Power supply supervisorUpdated “Regulator ON” paragraph in Section 3.0.16: Voltage regulatorRemoved note in Section 3.0.19: Low-power modesCorrected wrong reference manual in Section 3.0.28: Ethernet MAC interface with dedicated DMA and IEEE 1588 supportUpdated Table 17: Limitations depending on the operating power supply rangeUpdated Table 26: Typical and maximum current consumptions in Standby modeUpdated Table 27: Typical and maximum current consumptions in VBAT modeUpdated Table 39: PLLI2S (audio PLL) characteristicsUpdated Table 46: EMI characteristicsUpdated Table 51: Output voltage characteristicsUpdated Table 53: NRST pin characteristicsUpdated Table 57: SPI dynamic characteristicsUpdated Table 58: I2S dynamic characteristicsDeleted Table 59Updated Table 64: ULPI timingUpdated Figure 46: Ethernet SMI timing diagram</td></tr><tr><td>04-Jun-2013</td><td>4(continued)</td><td>Updated Figure 87: UFBGA176+25 ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outlineUpdated Table 97: UFBGA176+25 ball, 10 x 10 x 0.65 mm pitch, ultra thin fine pitch ball grid array mechanical dataUpdated Figure 5: STM32F40xxx block diagramUpdated Section 2: DescriptionUpdated footnote (3) in Table 3: STM32F405xx and STM32F407xx: features and peripheral counts.Updated Figure 3: Compatible board design between STM32F10xx/STM32F2/STM32F40xxx for LQFP144 packageUpdated Figure 4: Compatible board design between STM32F2 and STM32F40xxx for LQFP176 and BGA176 packagesUpdated Section 3.0.14: Power supply schemesUpdated Section 3.0.15: Power supply supervisorUpdated Section 3.0.16: Voltage regulator, including figures.Updated Table 16: General operating conditions, including footnote (2).Updated Table 17: Limitations depending on the operating power supply range, including footnote (3).Updated footnote (1) in Table 69: ADC characteristics.Updated footnote (2) in Table 70: ADC accuracy at fADC = 30 MHz.Updated footnote (1) in Table 76: DAC characteristics.Updated Figure 9: Regulator OFF.Updated Figure 7: Power supply supervisor interconnection with internal reset OFF.Added Section 3.0.17: Regulator ON/OFF and internal reset ON/OFF availability.Updated footnote (2) of Figure 21: Power supply scheme.Replaced respectively “I2S3S_WS” by “I2S3_WS”, “I2S3S_CK” by “I2S3_CK” and “FSMC_BLN1” by “FSMC_NBL1” in Table 10: Alternate function mapping.Added “EVENTOUT” as alternate function “AF15” for pin PC13, PC14, PC15, PH0, PH1, PI8 in Table 10: Alternate function mappingReplaced “DCMI_12” by “DCMI_D12” in Table 8: STM32F40xxx pin and ball definitions.Removed the following sentence from Section : I2C interface characteristics: ”Unless otherwise specified, the parameters given in Table 56 are derived from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 16.”.In Table 8: STM32F40xxx pin and ball definitions on page 53:- For pin PC13, replaced “RTC_AF1” by “RTC_OUT, RTC_TAMP1, RTC_TS”- for pin PI8, replaced “RTC_AF2” by “RTC_TAMP1, RTC_TAMP2, RTC_TS”.- for pin PB15, added RTC_REFIN in Alternate functions column.In Table 10: Alternate function mapping on page 70, for port PB15, replaced “RTC_50Hz” by “RTC_REFIN”.</td></tr><tr><td>04-Jun-2013</td><td>4(continued)</td><td>Updated Figure 6: Multi-AHB matrix.Updated Figure 7: Power supply supervisor interconnection with internal reset OFFChanged 1.2 V to V12 in Section : Regulator OFFUpdated LQFP176 pin 48.Updated Section 1: Introduction.Updated Section 2: Description.Updated operating voltage in Table 3: STM32F405xx and STM32F407xx: features and peripheral counts.Updated Note 1.Updated Section 3.0.15: Power supply supervisor.Updated Section 3.0.16: Voltage regulator.Updated Figure 9: Regulator OFF.Updated Table 4: Regulator ON/OFF and internal reset ON/OFF availability.Updated Section 3.0.19: Low-power modes.Updated Section 3.0.20: VBAT operation.Updated Section 3.0.22: Inter-integrated circuit interface (I2C).Updated pin 48 in Figure 15: STM32F40xxx LQFP176 pinout.Updated Table 7: Legend/abbreviations used in the pinout table.Updated Table 8: STM32F40xxx pin and ball definitions.Updated Table 16: General operating conditions.Updated Table 17: Limitations depending on the operating power supply range.Updated Section 6.3.7: Wakeup time from low-power mode.Updated Table 36: HSI oscillator characteristics.Updated Section 6.3.15: I/O current injection characteristics.Updated Table 50: I/O static characteristics.Updated Table 53: NRST pin characteristics.Updated Table 56: I2C characteristics.Updated Figure 39: I2C bus AC waveforms and measurement circuit.Updated Section 6.3.19: Communications interfaces.Updated Table 69: ADC characteristics.Added Table 72: Temperature sensor calibration values.Added Table 75: Internal reference voltage calibration values.Updated Section 6.3.26: FSMC characteristics.Updated Section 6.3.28: SD/SDIO MMC card host interface (SDIO) characteristics.Updated Table 25: Typical and maximum current consumptions in Stop mode.Updated Section : SPI interface characteristics included Table 57.Updated Section : I2S interface characteristics included Table 58.Updated Table 66: Dynamic characteristics: Ethernet MAC signals for SMI.Updated Table 68: Dynamic characteristics: Ethernet MAC signals for MII.</td></tr><tr><td>04-Jun-2013</td><td>4(continued)</td><td>Updated Table 66: Dynamic characteristics: Ethernet MAC signals for SMI.Updated Table 68: Dynamic characteristics: Ethernet MAC signals for MII.Updated Table 81: Synchronous multiplexed NOR/PSRAM read timings.Updated Table 82: Synchronous multiplexed PSRAM write timings.Updated Table 83: Synchronous non-multiplexed NOR/PSRAM read timings.Updated Table 84: Synchronous non-multiplexed PSRAM write timings.Updated Section 6.3.27: Camera interface (DCMI) timing specifications including Table 89: DCMI characteristics and addition of Figure 72: DCMI timing diagram.Updated Section 6.3.28: SD/SDIO MMC card host interface (SDIO) characteristics including Table 90.Updated Chapter Figure 9.</td></tr><tr><td>06-Mar-2015</td><td>5</td><td>Replace Cortex-M4F by Cortex-M4 with FPU throughout the document.Updated Section : Regulator OFF and Table 4: Regulator ON/OFF and internal reset ON/OFF availability for LQFP176.Updated Figure 15: STM32F40xxx LQFP176 pinout and Table 8: STM32F40xxx pin and ball definitions.Updated Figure 6: Multi-AHB matrix.Added note 1 below Figure 12: STM32F40xxx LQFP64 pinout, Figure 13: STM32F40xxx LQFP100 pinout, Figure 14: STM32F40xxx LQFP144 pinout and Figure 15: STM32F40xxx LQFP176 pinout.Updated IVDD and IVSS in Table 14: Current characteristics.Updated PLS[2:0]=101 (falling edge) configuration in Table 21: Embedded reset and power control block characteristics.Added Section : Additional current consumption. Updated Section : On-chip peripheral current consumption.Updated Table 31: Low-power mode wakeup timings.Updated Table 34: HSE 4-26 MHz oscillator characteristics and Table 35: LSE oscillator characteristics (fLSE = 32.768 kHz).Changed condition related to VESD(CDM) in Table 47: ESD absolute maximum ratings.Updated Table 49: I/O current injection susceptibility, Table 50: I/O static characteristics, Table 51: Output voltage characteristics conditions, Table 52: I/O AC characteristics and Figure 37: I/O AC characteristics definition.Updated Section : I2C interface characteristics.Remove note 3 in Table 71: Temperature sensor characteristics.Updated Figure 72: DCMI timing diagram.Modified Figure 75: WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package outline and Table 92: WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package mechanical data. Added Figure 76: WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale recommended footprint and Table 93: WLCSP90 recommended PCB design rules. /Modified Figure 78: LQFP64 – 64-pin, 10 x 10 mm low-profile quad flat package outline and Table 94: LQFP64 – 64-pin 10 x 10 mm low-profile quad flat package mechanical data.Updated Figure 87: UFBGA176+25 ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outline and Table 97: UFBGA176+25 ball, 10 x 10 x 0.65 mm pitch, ultra thin fine pitch ball grid array mechanical data. Added Figure 88: UFBGA176+25 - 201- ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array recommended footprint and Table 98: UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA).Updated Figure 90: LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package outline.Added Section : Device marking for WLCSP90, Section : Device marking for LQFP64, Section : Device marking for LFP100, Section : Device marking for LQFP144, Section : Device marking for UFBGA176+25 and Section : Device marking for LQFP176.</td></tr><tr><td>22-Oct-2015</td><td>6</td><td>In the whole document, updated notes related to values specified by design or by characterization.Updated Table 36: HSI oscillator characteristics.Changed fVCO_OUT minimum value and VCO freq to 100 MHz in Table 38: Main PLL characteristics and Table 39: PLLI2S (audio PLL) characteristics.Updated Figure 39: SPI timing diagram - slave mode and CPHA = 0.Updated Figure 53: 12-bit buffered /non-buffered DAC.Removed note 1 related to better performance using a restricted VDD range in Table 70: ADC accuracy at fADC = 30 MHz.Upated Figure 84: LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline.Updated Figure 87: UFBGA176+25 ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outline and Table 97: UFBGA176+25 ball, 10 x 10 x 0.65 mm pitch, ultra thin fine pitch ball grid array mechanical data.</td></tr><tr><td>16-Mar-2016</td><td>7</td><td>Updated Figure 2: Compatible board designSTM32F10xx/STM32F2/STM32F40xxx for LQFP100 package.Updated |VSSX- VSS| in Table 13: Voltage characteristics to add VREF-.Added VREF- in Table 69: ADC characteristics.Updated Table 92: WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package mechanical data.</td></tr><tr><td>09-Sep-2016</td><td>8</td><td>Removed note 1 below Figure 5: STM32F40xxx block diagram.Updated definition of stresses above maximum ratings in Section 6.2: Absolute maximum ratings.Updated th(NSS) in Figure 39: SPI timing diagram - slave mode and CPHA = 0 and Figure 40: SPI timing diagram - slave mode and CPHA = 1.Added note related to optional marking and inset/upset marks in all package marking sections.Updated Figure 87: UFBGA176+25 ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outline and Table 97: UFBGA176+25 ball, 10 x 10 x 0.65 mm pitch, ultra thin fine pitch ball grid array mechanical data.</td></tr><tr><td>14-Aug-2020</td><td>9</td><td>Renamed Section 3 and Section 8 into Functional overview and Ordering information, respectively.Added Arm logo and legal notice in Section 1: Introduction and updated Arm wordmark in the whole document. Removed USB certified logos.Updated camera interfaces for STM32F405OE in Table 3: STM32F405xx and STM32F407xx: features and peripheral counts.Added OTP memory in Features and Section 3.0.4: Embedded flash memory.Changed random number generator to true random number generator in the whole document and updated Section 3.0.34: True random number generator (RNG).Added Note 1 related to UFBGA176 in Table 8: STM32F40xxx pin and ball definitions.Updated Section 6.2: Absolute maximum ratings introduction.Updated VPVD minimum value for PLS[2:0]=101 (falling edge) in Table 21: Embedded reset and power control block characteristics.Updated Note 1 in Table 36: HSI oscillator characteristics.Added reference to application note AN4899 in Section 6.3.16: I/O port characteristics.Replaced DCMI_PIXCK by DCMI_PIXCLK in Table 10: Alternate function mapping.Renamed Section 8 into Ordering information.Updated D1 in Figure 87: UFBGA176+25 ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outline.</td></tr><tr><td>08-Nov-2024</td><td>10</td><td>Updated:– Cover page– Section 1: Introduction– Figure 5: STM32F40xxx block diagram– Section 3.18: Real-time clock (RTC), backup SRAM and backup registers– Table 7: STM32F40xxx pin and ball definitions– Table 9: Alternate function mapping– I/O system current consumption– Note 1 in Table 34: HSI oscillator characteristics.– Table 33: LSE oscillator characteristics ( $f_{LSE} = 32.768$  kHz)– Figure 37: I/O AC characteristics definition– Figure 39: SPI timing diagram - slave mode and CPHA = 0, Figure 40: SPI timing diagram - slave mode and CPHA = 1, and Figure 41: SPI timing diagram - master mode– Table 44: EMI characteristics for fHSE = 25 MH and fCPU = 168 MHz– Figure 49: ADC accuracy characteristics and Figure 50: Typical connection diagram when using the ADC with FT/TT pins featuring analog switch function– Figure 68: NAND controller waveforms for read access and Figure 69: NAND controller waveforms for write access– Table 96: UFBGA(176+25) - Example of PCB design rules (0.65 mm pitch BGA) title– Section 7: Package informationAdded Section 9: Important security notice</td></tr><tr><td>04-Feb-2026</td><td>11</td><td>Updated Figure 7: Power supply supervisor interconnection with internal reset OFF.Updated Figure 8: PDR_ON and NRST control with internal reset OFF.Updated Figure 9: Regulator OFF.Updated Figure 18: STM32F40xxx memory map.Updated Figure 20: Pin input voltage.Updated Table 45: ESD absolute maximum ratings.Updated Section 7.3: LQFP64 package information (5W).</td></tr><tr><td>18-Mar-2026</td><td>12</td><td>Re-numbering of Section 3: Functional overview sub-sections.</td></tr></table>

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