STM32F4-Base/docs/芯片手册/stm32f405rg.md

Arm® Cortex®-M4 32b MCU+FPU, 210DMIPS, up to 1MB flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces, and camera

Datasheet - production data

Features

• Includes ST state-of-the-art patented technology

• Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions

• Memories

• Up to 1 Mbyte of flash memory

• Up to 192+4 Kbytes of SRAM including 64-Kbyte of CCM (core coupled memory) data RAM

• 512 bytes of OTP memory

• Flexible static memory controller supporting CompactFlash™, SRAM, PSRAM, NOR and NAND memories

• LCD parallel interface, 8080/6800 modes

• Clock, reset, and supply management

– 1.8 V to 3.6 V application supply and I/Os

• POR, PDR, PVD and BOR – 4-to-26 MHz crystal oscillator
• Internal 16 MHz factory-trimmed RC (1% accuracy) – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration

- Low-power operation

– Sleep, Stop, and Standby modes

• V_{BAT} supply for RTC, 20×32-bit backup registers + optional 4 KB backup SRAM

• 3×12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode

• 2 \times 12 -bit D/A converters

• General-purpose DMA: 16-stream DMA controller with FIFOs and burst support

LQFP64 (10 × 10 mm)

LQFP100 (14 × 14 mm)

LQFP144 (20 × 20 mm)

LQFP176 (24 × 24 mm)

UFBGA176

(10 × 10 mm)

WLCSP90

(4.223×3.969 mm)

• Up to 17 timers: up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input

• Debug mode

• Serial wire debug (SWD) & JTAG interfaces – Cortex-M4 Embedded Trace Macrocell™

- Up to 140 I/O ports with interrupt capability

– Up to 136 fast I/Os up to 84 MHz – Up to 138 5 V-tolerant I/Os

- Up to 15 communication interfaces

• Up to 3 \times \mathrm{I}^{2}\mathrm{C} interfaces (SMBus/PMBus)

• Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control)

• Up to 3 SPIs (42 Mbits/s), 2 with muxed full-duplex I²S to achieve audio class accuracy via internal audio PLL or external clock

• 2 \times CAN interfaces (2.0B Active)

• SDIO interface

- Advanced connectivity

• USB 2.0 full-speed device/host/OTG controller with on-chip PHY

• USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI

• 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII

• 8- to 14-bit parallel camera interface up to 54 Mbytes/s

• True random number generator

• CRC calculation unit

• 96-bit unique ID

• RTC: subsecond accuracy, hardware calendar

• All packages are ECOPACK2 compliant

Table 1. Device summary

Reference	Part number
STM32F405xx	STM32F405RG, STM32F405VG, STM32F405ZG, STM32F405OG, STM32F405OE
STM32F407xx	STM32F407VG, STM32F407IG, STM32F407ZG, STM32F407VE, STM32F407ZE, STM32F407IE

Contents

1 Introduction 13

2 Description....14

2.1 Full compatibility throughout the family .... 17

3 Functional overview 20

3.1 Arm® Cortex®-M4 core with FPU and embedded flash and SRAM . . . . 21

3.2 Adaptive real-time memory accelerator (ART Accelerator) ..... 21

3.3 Memory protection unit 21

3.4 Embedded flash memory 22

3.5 CRC (cyclic redundancy check) calculation unit 22

3.6 Embedded SRAM 22

3.7 Multi-AHB bus matrix 22

3.8 DMA controller (DMA) 23

3.9 Flexible static memory controller (FSMC) 24

3.9.1 LCD parallel interface 24

3.10 Nested vectored interrupt controller (NVIC) 24

3.11 External interrupt/event controller (EXTI) 25

3.12 Clocks and startup 25

3.13 Boot modes 25

3.14 Power supply schemes 25

3.15 Power supply supervisor 26

3.15.1 Internal reset ON 26

3.15.2 Internal reset OFF 26

3.16 Voltage regulator 28

3.16.1 Regulator ON 28

3.16.2 Regulator OFF 29

3.17 Regulator ON/OFF and internal reset ON/OFF availability .... 31

3.18 Real-time clock (RTC), backup SRAM and backup registers ..... 31

3.19 Low-power modes 32

3.20 V_{BAT} operation 33

3.21 Timers and watchdogs 33

3.21.1 Advanced-control timers (TIM1, TIM8) 34 3.21.2 General-purpose timers (TIMx) 35 3.21.3 Basic timers TIM6 and TIM7 35

3.22 Inter-integrated circuit interface (I²C) 36 3.23 Universal synchronous/asynchronous receiver transmitters (USART) .. 36 3.24 Serial peripheral interface (SPI) 37 3.25 Inter-integrated sound (I2S) 37 3.26 Audio PLL (PLLI2S) 38 3.27 Secure digital input/output interface (SDIO) 38 3.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 38 3.29 Controller area network (bxCAN) 39 3.30 Universal serial bus on-the-go full-speed (OTG_FS) 39 3.31 Universal serial bus on-the-go high-speed (OTG_HS) 40 3.32 Digital camera interface (DCMI) 40 3.33 True random number generator (RNG) 40 3.34 General-purpose input/outputs (GPIOs) 41 3.35 Analog-to-digital converters (ADCs) 41 3.36 Temperature sensor 41 3.37 Digital-to-analog converter (DAC) 41 3.38 Serial wire JTAG debug port (SWJ-DP) 42 3.39 Embedded Trace Macrocell™ 42

4 Pinouts and pin description 43 5 Memory mapping 73 6 Electrical characteristics 78

6.1 Parameter conditions 78

6.1.1 Minimum and maximum values .... 78 6.1.2 Typical values 78 6.1.3 Typical curves 78 6.1.4 Loading capacitor 78 6.1.5 Pin input voltage 78 6.1.6 Power supply scheme 79 6.1.7 Current consumption measurement ....80

6.2 Absolute maximum ratings .... 80

6.3 Operating conditions 81

6.3.1 General operating conditions 81

6.3.2 VCAP_1/VCAP_2 external capacitor 84

6.3.3 Operating conditions at power-up / power-down (regulator ON) ..... 84

6.3.4 Operating conditions at power-up / power-down (regulator OFF) ..... 84

6.3.5 Embedded reset and power control block characteristics ..... 85

6.3.6 Supply current characteristics 86

6.3.7 Wakeup time from low-power mode 100

6.3.8 External clock source characteristics ..... 101

6.3.9 Internal clock source characteristics 105

6.3.10 PLL characteristics 106

6.3.11 PLL spread spectrum clock generation (SSCG) characteristics ..... 108

6.3.12 Memory characteristics 110

6.3.13 EMC characteristics 112

6.3.14 Absolute maximum ratings (electrical sensitivity) 114

6.3.15 I/O current injection characteristics 115

6.3.16 I/O port characteristics 116

6.3.17 NRST pin characteristics 121

6.3.18 TIM timer characteristics 121

6.3.19 Communications interfaces 123

6.3.20 CAN (controller area network) interface .... 135

6.3.21 12-bit ADC characteristics 135

6.3.22 Temperature sensor characteristics 140

6.3.23 V_{BAT} monitoring characteristics ..... 141

6.3.24 Embedded reference voltage 141

6.3.25 DAC electrical characteristics 141

6.3.26 FSMC characteristics 144

6.3.27 Camera interface (DCMI) timing specifications .... 162

6.3.28 SD/SDIO MMC card host interface (SDIO) characteristics ..... 163

6.3.29 RTC characteristics 164

7 Package information 165

7.1 Device marking 165

7.2 WLCSP90 package information 166

7.3 LQFP64 package information (5W) 169

7.4 LQFP100 package information (1L) 172 7.5 LQFP144 package information (1A) 175 7.6 UFBGA(176+25) package information (A0E7) 179 7.7 LQFP176 package information (1T) 181 7.8 Thermal characteristics 185

8 Ordering information 186

Appendix A Application block diagrams 187

A.1 USB OTG full speed (FS) interface solutions ..... 187 A.2 USB OTG high speed (HS) interface solutions....189 A.3 Ethernet interface solutions.... 190

9 Important security notice .... 192

10 Revision history 193

List of tables

Table 1. Device summary....2

Table 2. STM32F405xx and STM32F407xx: features and peripheral counts. 15

Table 3. Regulator ON/OFF and internal reset ON/OFF availability....31

Table 4. Timer feature comparison....33

Table 5. USART feature comparison 37

Table 6. Legend/abbreviations used in the pinout table 48

Table 7. STM32F40xxx pin and ball definitions 49

Table 8. FSMC pin definition 61

Table 9. Alternate function mapping 64

Table 10. Register boundary addresses....74

Table 11. Voltage characteristics 80

Table 12. Current characteristics 81

Table 13. Thermal characteristics....81

Table 14. General operating conditions 81

Table 15. Limitations depending on the operating power supply range ..... 83

Table 16. VCAP_1/VCAP_2 operating conditions 84

Table 17. Operating conditions at power-up / power-down (regulator ON) 84

Table 18. Operating conditions at power-up / power-down (regulator OFF). 84

Table 19. Embedded reset and power control block characteristics. 85

Table 20. Typical and maximum current consumption in Run mode, code with data processing running from flash memory (ART accelerator enabled) or RAM 87

Table 21. Typical and maximum current consumption in Run mode, code with data processing running from flash memory (ART accelerator disabled) 88

Table 22. Typical and maximum current consumption in Sleep mode 91

Table 23. Typical and maximum current consumptions in Stop mode 92

Table 24. Typical and maximum current consumptions in Standby mode ..... 92

Table 25. Typical and maximum current consumptions in V_{BAT} mode.....93

Table 26. Typical current consumption in Run mode, code with data processing running from flash memory, regulator ON (ART accelerator enabled except prefetch), V_{DD} = 1.8 V ..... 95

Table 27. Switching output I/O current consumption 97

Table 28. Peripheral current consumption 98

Table 29. Low-power mode wakeup timings 101

Table 30. High-speed external user clock characteristics....101

Table 31. Low-speed external user clock characteristics 102

Table 32. HSE 4-26 MHz oscillator characteristics 103

Table 33. LSE oscillator characteristics ( f_{LSE} = 32.768 kHz) 104

Table 34. HSI oscillator characteristics 105

Table 35. LSI oscillator characteristics 105

Table 36. Main PLL characteristics....106

Table 37. PLLI2S (audio PLL) characteristics 107

Table 38. SSCG parameters constraint 108

Table 39. Flash memory characteristics....110

Table 40. Flash memory programming....110

Table 41. Flash memory programming with VPP 112

Table 42. Flash memory endurance and data retention....112

Table 43. EMS characteristics 113

Table 44. EMI characteristics for fHSE = 25 MH and fCPU = 168 MHz....114

Table 45. ESD absolute maximum ratings 114 Table 46. Electrical sensitivities 115 Table 47. I/O current injection susceptibility 116 Table 48. I/O static characteristics 116 Table 49. Output voltage characteristics 118 Table 50. I/O AC characteristics....119 Table 51. NRST pin characteristics 121 Table 52. Characteristics of TIMx connected to the APB1 domain 122 Table 53. Characteristics of TIMx connected to the APB2 domain 123 Table 54. I2C analog filter characteristics....123 Table 55. SPI dynamic characteristics 124 Table 56. I2S dynamic characteristics 128 Table 57. USB OTG FS startup time 130 Table 58. USB OTG FS DC electrical characteristics....130 Table 59. USB OTG FS electrical characteristics....131 Table 60. USB HS DC electrical characteristics....131 Table 61. USB HS clock timing parameters 131 Table 62. ULPI timing 132 Table 63. Ethernet DC electrical characteristics....133 Table 64. Dynamic characteristics: Ethernet MAC signals for SMI. 133 Table 65. Dynamic characteristics: Ethernet MAC signals for RMII 134 Table 66. Dynamic characteristics: Ethernet MAC signals for MII 135 Table 67. ADC characteristics 135 Table 68. ADC accuracy at f_{ADC} = 30 MHz 137 Table 69. Temperature sensor characteristics 140 Table 70. Temperature sensor calibration values....140 Table 71. V_{BAT} monitoring characteristics ..... 141 Table 72. Embedded internal reference voltage....141 Table 73. Internal reference voltage calibration values .... 141 Table 74. DAC characteristics 141 Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings ..... 145 Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings ..... 146 Table 77. Asynchronous multiplexed PSRAM/NOR read timings. 147 Table 78. Asynchronous multiplexed PSRAM/NOR write timings 148 Table 79. Synchronous multiplexed NOR/PSRAM read timings 150 Table 80. Synchronous multiplexed PSRAM write timings....151 Table 81. Synchronous non-multiplexed NOR/PSRAM read timings 153 Table 82. Synchronous non-multiplexed PSRAM write timings 154 Table 83. Switching characteristics for PC Card/CF read and write cycles in attribute/common space....159 Table 84. Switching characteristics for PC Card/CF read and write cycles in I/O space 160 Table 85. Switching characteristics for NAND flash read cycles .... 161 Table 86. Switching characteristics for NAND flash write cycles ..... 162 Table 87. DCMI characteristics....162 Table 88. Dynamic characteristics: SD/MMC characteristics ..... 164 Table 89. RTC characteristics 164 Table 90. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package mechanical data....167 Table 91. WLCSP90 recommended PCB design rules 168 Table 92. LQFP64 - Mechanical data....170 Table 93. LQFP100 - Mechanical data....173

Table 94. LQFP144 - Mechanical data....176 Table 95. UFBGA(176+25) - Mechanical data 179 Table 96. UFBGA(176+25) - Example of PCB design rules (0.65 mm pitch BGA) ..... 180 Table 97. LQFP176 - Mechanical data....182 Table 98. Package thermal characteristics....185 Table 99. Document revision history .... 193

List of figures

Figure 1. Compatible board design between STM32F10xx/STM32F40xxx for LQFP64....17

Figure 2. Compatible board design STM32F10xx/STM32F2/STM32F40xxx for LQFP100 package....18

Figure 3. Compatible board design between STM32F10xx/STM32F2/STM32F40xxx for LQFP144 package....18

Figure 4. Compatible board design between STM32F2 and STM32F40xxx for LQFP176 and BGA176 packages 19

Figure 5. STM32F40xxx block diagram....20

Figure 6. Multi-AHB matrix....23

Figure 7. Power supply supervisor interconnection with internal reset OFF .... 27

Figure 8. PDR_ON and NRST control with internal reset OFF 28

Figure 9. Regulator OFF 29

Figure 10. Startup in regulator OFF mode: slow V_{DD} slope

• power-down reset risen after V_{CAP} 1/ V_{CAP} 2 stabilization ..... 30

Figure 11. Startup in regulator OFF mode: fast \overline{V}_{DD} slope

• power-down reset risen before V_{CAP\_1}/V_{CAP\_2} stabilization ..... 31

Figure 12. STM32F40xxx LQFP64 pinout 43

Figure 13. STM32F40xxx LQFP100 pinout 44

Figure 14. STM32F40xxx LQFP144 pinout 45

Figure 15. STM32F40xxx LQFP176 pinout 46

Figure 16. STM32F40xxx UFBGA176 bailout 47

Figure 17. STM32F40xxx WLCSP90ballout 48

Figure 18. STM32F40xxx memory map....73

Figure 19. Pin loading conditions....78

Figure 20. Pin input voltage 78

Figure 21. Power supply scheme 79

Figure 22. Current consumption measurement scheme .... 80

Figure 23. External capacitor C_{EXT} 84

Figure 24. Typical current consumption versus temperature, Run mode, code with data processing running from flash (ART accelerator ON) or RAM, and peripherals OFF....89

Figure 25. Typical current consumption versus temperature, Run mode, code with data processing running from flash (ART accelerator ON) or RAM, and peripherals ON. . . . . 89

Figure 26. Typical current consumption versus temperature, Run mode, code with data processing running from flash (ART accelerator OFF) or RAM, and peripherals OFF....90

Figure 27. Typical current consumption versus temperature, Run mode, code with data processing running from flash (ART accelerator OFF) or RAM, and peripherals ON....90

Figure 28. Typical V_{BAT} current consumption (LSE and RTC ON/backup RAM OFF) ..... 93

Figure 29. Typical V_{BAT} current consumption (LSE and RTC ON/backup RAM ON) ..... 94

Figure 30. High-speed external clock source AC timing diagram .... 102

Figure 31. Low-speed external clock source AC timing diagram....103

Figure 32. Typical application with an 8 MHz crystal....104

Figure 33. Typical application with a 32.768 kHz crystal....105

Figure 34. ACC _{LSI} versus temperature .... 106

Figure 35. PLL output clock waveforms in center spread mode 109

Figure 36. PLL output clock waveforms in down spread mode 110

Figure 37. I/O AC characteristics definition .... 120

Figure 38. Recommended NRST pin protection 121

Figure 39. SPI timing diagram - slave mode and CPHA = 0 126

Figure 40. SPI timing diagram - slave mode and CPHA = 1 126 Figure 41. SPI timing diagram - master mode 127 Figure 42. I2S slave timing diagram (Philips protocol) 129 Figure 43. I2S master timing diagram (Philips protocol) ^{(1)} .... 129 Figure 44. USB OTG FS timings: definition of data signal rise and fall time ..... 131 Figure 45. ULPI timing diagram....132 Figure 46. Ethernet SMI timing diagram 133 Figure 47. Ethernet RMII timing diagram....134 Figure 48. Ethernet MII timing diagram 134 Figure 49. ADC accuracy characteristics....137 Figure 50. Typical connection diagram when using the ADC with FT/TT pins featuring analog switch function 138 Figure 51. Power supply and reference decoupling ( V_{REF+} not connected to V_{DDA} ). 139 Figure 52. Power supply and reference decoupling ( V_{REF+} connected to V_{DDA} ). 140 Figure 53. 12-bit buffered /non-buffered DAC 144 Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms ..... 145 Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms ..... 146 Figure 56. Asynchronous multiplexed PSRAM/NOR read waveforms. 147 Figure 57. Asynchronous multiplexed PSRAM/NOR write waveforms ..... 148 Figure 58. Synchronous multiplexed NOR/PSRAM read timings 149 Figure 59. Synchronous multiplexed PSRAM write timings....151 Figure 60. Synchronous non-multiplexed NOR/PSRAM read timings....152 Figure 61. Synchronous non-multiplexed PSRAM write timings .... 154 Figure 62. PC Card/CompactFlash controller waveforms for common memory read access ..... 155 Figure 63. PC Card/CompactFlash controller waveforms for common memory write access.....156 Figure 64. PC Card/CompactFlash controller waveforms for attribute memory read access. 157 Figure 65. PC Card/CompactFlash controller waveforms for attribute memory write access....158 Figure 66. PC Card/CompactFlash controller waveforms for I/O space read access ..... 158 Figure 67. PC Card/CompactFlash controller waveforms for I/O space write access ..... 159 Figure 68. NAND controller waveforms for read access 161 Figure 69. NAND controller waveforms for write access 161 Figure 70. DCMI timing diagram 162 Figure 71. SDIO high-speed mode 163 Figure 72. SD default mode....164 Figure 73. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package outline. 166 Figure 74. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package recommended footprint 167 Figure 75. WLCSP90 marking example (package top view)....168 Figure 76. LQFP64 - Outline ^{(15)} 169 Figure 77. LQFP100 - Outline ^{(15)} 172 Figure 78. LQFP100 - Footprint example 174 Figure 79. LQFP144 - Outline ^{(15)} 175 Figure 80. LQFP144 - Footprint example 178 Figure 81. UFBGA(176+25) - Outline 179 Figure 82. UFBGA(176+25) - Footprint example....180 Figure 83. LQFP176 - Outline ^{(15)} 181 Figure 84. LQFP176 - Footprint example 184 Figure 85. USB controller configured as peripheral-only and used in Full speed mode 187

Figure 86. USB controller configured as host-only and used in full speed mode. 187 Figure 87. USB controller configured in dual mode and used in full speed mode....188 Figure 88. USB controller configured as peripheral, host, or dual-mode and used in high speed mode....189 Figure 89. MII mode using a 25 MHz crystal 190 Figure 90. RMII with a 50 MHz oscillator 190 Figure 91. RMII with a 25 MHz crystal and PHY with PLL....191

1 Introduction

This datasheet provides the description of the STM32F405xx and STM32F407xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, refer to Section 2.1: Full compatibility throughout the family.

The STM32F405xx and STM32F407xx datasheet should be read in conjunction with the STM32F4xx reference manual which is available from the STMicroelectronics website www.st.com.

For information on the device errata with respect to the datasheet and reference manual, refer to the STM32F405xx and STM32F407xx errata sheet (ES0182), which is available from the STMicroelectronics website www.st.com.

For information on the Arm ^{\textregistered} Cortex ^{\textregistered} -M4 core, refer to the Cortex ^{\textregistered} -M4 programming manual (PM0214) available from www.st.com.

arm

Note: Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere.

The Arm word and logo are trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved.

2 Description

The STM32F405xx and STM32F407xx family is based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 168 MHz. The Cortex®-M4 core features a floating-point unit (FPU) single precision which supports all Arm single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.

The STM32F405xx and STM32F407xx family incorporates high-speed embedded memories (flash memory up to 1 Mbyte, up to 192 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix.

All devices offer three 12-bit ADCs, two DACs, a low-power RTC, 12 general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. a true random number generator (RNG). They also feature standard and advanced communication interfaces.

• Up to three I²Cs
• Three SPIs, two I²Ss full duplex. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization • Four USARTs plus two UARTs
• A USB OTG full speed and a USB OTG high speed with full-speed capability (with the ULPI)
• Two CANs
• An SDIO/MMC interface
• Ethernet and the camera interface available on STM32F407xx devices only

New advanced peripherals include an SDIO, an enhanced flexible static memory control (FSMC) interface (for devices offered in packages of 100 pins and more), a camera interface for CMOS sensors. Refer to Table 2: STM32F405xx and STM32F407xx: features and peripheral counts for the list of peripherals available on each part number.

The STM32F405xx and STM32F407xx family operates in the -40 to +105 °C temperature range from a 1.8 to 3.6 V power supply. The supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range using an external power supply supervisor: refer to Section 3.15.2: Internal reset OFF. A comprehensive set of power-saving mode allows the design of low-power applications.

The STM32F405xx and STM32F407xx family offers devices in various packages ranging from 64 pins to 176 pins. The set of included peripherals changes with the device chosen.

These features make the STM32F405xx and STM32F407xx microcontroller family suitable for a wide range of applications:

• Motor drive and application control • Medical equipment • Industrial applications: PLC, inverters, circuit breakers

• Printers, and scanners • Alarm systems, video intercom, and HVAC • Home audio appliances

Table 2. STM32F405xx and STM32F407xx: features and peripheral counts

Peripherals

STM32F405RG

STM32F405OG

STM32F405VG

STM32F405ZG

STM32F405OE

STM32F407Vx

STM32F407Zx

STM32F407Ix

Flash memory in Kbytes

1024

512

512

1024

512

1024

512

1024

SRAM in Kbytes

System

192(112+16+64)

Backup

4

FSMC memory controller

No

Yes(1)

Ethernet

No

Yes

Timers

General-purpose

10

Advanced-control

2

Basic

2

IWDG

Yes

WWDG

Yes

RTC

Yes

True random number generator

Yes

Table 2. STM32F405xx and STM32F407xx: features and peripheral counts (continued)

Peripherals		STM32F405RG	STM32F405OG	STM32F405VG	STM32F405ZG	STM32F405OE	STM32F407Vx	STM32F407Zx	STM32F407Ix
Communication interfaces	SPI / I2S	3/2 (full duplex)(2)
	I2C	3
	USART/UART	4/2
	USB OTG FS	Yes
	USB OTG HS	Yes
	CAN	2
	SDIO	Yes
Camera interface		No					Yes
GPIOs		51	72	82	114	72	82	114	140
12-bit ADC Number of channels		3
		16	13	16	24	13	16	24	24
12-bit DAC Number of channels		Yes2
Maximum CPU frequency		168 MHz
Operating voltage		1.8 to 3.6 V(3)
Operating temperatures		Ambient temperatures: -40 to +85 °C /-40 to +105 °C
		Junction temperature: -40 to +125 °C
Package		LQFP64	WLCSP90	LQFP100	LQFP144	WLCSP90	LQFP100	LQFP144	UFBGA176 LQFP176

1. For the LQFP100 and WLCSP90 packages, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package.
2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I²S audio mode.
3. V_{DD}/V_{DDA} minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF).

2.1 Full compatibility throughout the family

The STM32F405xx and STM32F407xx are part of the STM32F4 family. They are fully pin-to-pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, and performances (FPU, higher frequency) for a greater degree of freedom during the development cycle.

The STM32F405xx and STM32F407xx devices maintain a close compatibility with the whole STM32F10xxx family. All functional pins are pin-to-pin compatible. The STM32F405xx and STM32F407xx, however, are not drop-in replacements for the STM32F10xxx devices: the two families do not have the same power scheme, and so their power pins are different. Nonetheless, transition from the STM32F10xxx to the STM32F40xxx family remains simple as only a few pins are impacted.

Figure 4, Figure 3, Figure 2, and Figure 1 give compatible board designs between the STM32F40xxx, STM32F2, and STM32F10xxx families.

Figure 1. Compatible board design between STM32F10xx/STM32F40xxx for LQFP64

text_image

48 47 33 32 31 64 1 17 16 0 Ω resistor or soldering present for the STM32F1 configuration, not present STM32F4xx configuration VSS VSS VSS

ai18489

Figure 2. Compatible board design STM32F10xx/STM32F2/STM32F40xxx for LQFP100 package

text_image

76 75 51 50 49 99 (VSS) 100 1 19 20 25 26 VSS VSS VSS VSS 0 Ω resistor or soldering bridge present for the STM32F10xxx configuration, not present in the STM32F4xx configuration Two 0 Ω resistors connected to:

• VSS for the STM32F10xx
• VSS for the STM32F4xx
• VSS or NC for the STM32F2xx VSS for STM32F10xx VDD for STM32F4xx ai18488d

Figure 3. Compatible board design between STM32F10xx/STM32F2/STM32F40xxx for LQFP144 package

text_image

0 Ω resistor or soldering bridge present for the STM32F10xx configuration, not present in the STM32F4xx configuration 73 108 106 72 109 71 VSS VSS VSS VSS Signal from external power supply supervisor 143 (PDR_ON) 1 30 31 36 37 VDD VSS Two 0 Ω resistors connected to:

• VSS for the STM32F10xx
• VSS, VDD or NC for the STM32F2xx
• VDD or signal from external power supply supervisor for the STM32F4xx VSS VSS for STM32F10xx VDD for STM32F4xx ai18487d

Figure 4. Compatible board design between STM32F2 and STM32F40xxx for LQFP176 and BGA176 packages

text_image

Signal from external power supply supervisor 171 (PDR_ON) 176 133 132 89 88 45 1 44 VDD VSS

Two 0 Ω resistors connected to:

• V_{SS} , V_{DD} or NC for the STM32F2xx
• V_{DD} or signal from external power supply supervisor for the STM32F4xx

MS19919V3

3 Functional overview

Figure 5. STM32F40xxx block diagram

flowchart

This image displays a system architecture diagram for a 8800 microcontroller (likely an 8800 microcontroller), showing the data flow from input/output to external memory, hardware components, and control signals.

1. The camera interface and ethernet are available only on STM32F407xx devices.

3.1 Arm® Cortex®-M4 core with FPU and embedded flash and SRAM

The Arm Cortex-M4 processor with FPU is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.

The Arm Cortex-M4 32-bit RISC processor with FPU features exceptional code-efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices.

The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.

Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation.

The STM32F405xx and STM32F407xx family is compatible with all Arm tools and software.

Figure 5 shows the general block diagram of the STM32F40xxx family.

Note: Cortex-M4 with FPU is binary compatible with Cortex-M3.

3.2 Adaptive real-time memory accelerator (ART Accelerator)

The ART Accelerator is a memory accelerator which is optimized for STM32 industry-standard Arm® Cortex®-M4 with FPU processors. It balances the inherent performance advantage of the Arm Cortex-M4 with FPU over flash memory technologies, which normally requires the processor to wait for the flash memory at higher frequencies.

To release the processor full 210 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from flash memory at a CPU frequency up to 168 MHz.

3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.

The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.

The MPU is optional and can be bypassed for applications that do not need it.

3.4 Embedded flash memory

The STM32F40xxx devices embed a flash memory of 512 Kbytes or 1 Mbytes available for storing programs and data, plus 512 bytes of OTP memory.

3.5 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location.

3.6 Embedded SRAM

All STM32F40xxx products embed:

• Up to 192 Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory) data RAM RAM memory is accessed (read/write) at CPU clock speed with 0 wait states. • 4 Kbytes of backup SRAM This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode.

3.7 Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS) and the slaves (flash memory, RAM, FSMC, AHB, and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.

Figure 6. Multi-AHB matrix

flowchart

This diagram illustrates the architecture and data flow of a bus matrix (Bus matrix-S) architecture, showing connections between RAM, ARM, GP, MAC, and USB components with associated memory addresses.

3.8 DMA controller (DMA)

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB).

The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code.

Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent.

The DMA can be used with the main peripherals:

• SPI and I²S • I^{2}C
• USART
• General-purpose, basic and advanced-control timers TIMx • DAC • SDIO • Camera interface (DCMI)
• ADC.

3.9 Flexible static memory controller (FSMC)

The FSMC is embedded in the STM32F405xx and STM32F407xx family. It has four Chip Select outputs supporting the following modes: PCCard/CompactFlash, SRAM, PSRAM, NOR flash and NAND flash.

Functionality overview:

• Write FIFO • Maximum FSMC_CLK frequency for synchronous accesses is 60 MHz.

3.9.1 LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-effective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration.

3.10 Nested vectored interrupt controller (NVIC)

The STM32F405xx and STM32F407xx embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 82 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M4 with FPU core.

• Closely coupled NVIC gives low-latency interrupt processing

• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving, higher-priority interrupts
• Support tail chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt latency.

3.11 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected to the 16 external interrupt lines.

3.12 Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full temperature range. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 168 MHz. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails).

Several prescalers allow the configuration of the three AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB buses is 168 MHz while the maximum frequency of the high-speed APB domains is 84 MHz. The maximum allowed frequency of the low-speed APB domain is 42 MHz.

The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class performance. In this case, the I²S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz.

3.13 Boot modes

At startup, boot pins are used to select one out of three boot options:

• Boot from user flash
• Boot from system memory
• Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the flash memory by using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade).

3.14 Power supply schemes

• V_{DD} = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through V_{DD} pins.
• V_{SSA} , V_{DDA} = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. V_{DDA} and V_{SSA} must be connected to V_{DD} and V_{SS} , respectively.
• V_{BAT} = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V_{DD} is not present.

Refer to Figure 21: Power supply scheme for more details.

Note: V_{DD}/V_{DDA} minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF).

Refer to Table 2 in order to identify the packages supporting this option.

3.15 Power supply supervisor

3.15.1 Internal reset ON

On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On all other packages, the power supply supervisor is always enabled.

The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR threshold levels, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when V_{DD} is below a specified threshold, V_{POR/PDR} or V_{BOR} , without the need for an external reset circuit.

The device also features an embedded programmable voltage detector (PVD) that monitors the V_{DD}/V_{DDA} power supply and compares it to the V_{PVD} threshold. An interrupt can be generated when V_{DD}/V_{DDA} drops below the V_{PVD} threshold and/or when V_{DD}/V_{DDA} is higher than the V_{PVD} threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

3.15.2 Internal reset OFF

This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled with the PDR_ON pin.

An external power supply supervisor should monitor V_{DD} and should maintain the device in reset mode as long as V_{DD} is below a specified threshold. PDR_ON should be connected to this external power supply supervisor. Refer to Figure 7: Power supply supervisor interconnection with internal reset OFF.

Figure 7. Power supply supervisor interconnection with internal reset OFF

text_image

VDD External VDD power supply supervisor Ext. reset controller active when VDD < 1.7 V NRST Application reset signal VDD PDR_ON VSS

MS31383V4

1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range.

The V_{DD} specified threshold, below which the device must be maintained under reset, is 1.8 V (see Figure 7). This supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range.

A comprehensive set of power-saving mode allows to design low-power applications.

When the internal reset is OFF, the following integrated features are no more supported:

• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled • The brownout reset (BOR) circuitry is disabled • The embedded programmable voltage detector (PVD) is disabled
• V_{BAT} functionality is no more available and V_{BAT} pin should be connected to V_{DD}

All packages, except for the LQFP64 and LQFP100, allow to disable the internal reset through the PDR_ON signal.

Figure 8. PDR_ON and NRST control with internal reset OFF

area

Time Phase	VDD (V)	NRST (V)
Start	0	0
PDR_ON	1.7	0
Reset	1.7	0
Peak	1.7	~0.8
Reset	1.7	0
Peak	1.7	~0.8
Reset	1.7	0
PDR_ON	1.7	0

1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range.

3.16 Voltage regulator

The regulator has four operating modes:

- Regulator ON

- Main regulator mode (MR)

– Low-power regulator (LPR)

- Power-down

- Regulator OFF

3.16.1 Regulator ON

On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low. On all other packages, the regulator is always enabled.

There are three power modes configured by software when regulator is ON:

• MR is used in the nominal regulation mode (With different voltage scaling in Run) In Main regulator mode (MR mode), different voltage scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. Refer to Table 14: General operating conditions.

• LPR is used in the Stop modes The LP regulator mode is configured by software when entering Stop mode.

• Power-down is used in Standby mode.

The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost)

Two external ceramic capacitors should be connected on V_{CAP\_1} & V_{CAP\_2} pin. Refer to Figure 21: Power supply scheme and Figure 16: VCAP_1/VCAP_2 operating conditions.

All packages have regulator ON feature.

3.16.2 Regulator OFF

This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V_{12} voltage source through V_{CAP\_1} and V_{CAP\_2} pins.

Since the internal voltage scaling is not manage internally, the external voltage value must be aligned with the targeted maximum frequency. Refer to Table 14: General operating conditions.

The two 2.2 \mu F ceramic capacitors should be replaced by two 100 nF decoupling capacitors.

Refer to Figure 21: Power supply scheme

When the regulator is OFF, there is no more internal monitoring on V_{12} . An external power supply supervisor should be used to monitor the V_{12} of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V_{12} power domain.

In regulator OFF mode the following features are no more supported:

• PA0 cannot be used as a GPIO pin since it allows to reset a part of the V_{12} logic power domain which is not reset by the NRST pin.
• As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required. • The standby mode is not available

Figure 9. Regulator OFF

flowchart

graph LR
  A["External VCAP_1/2 power supply supervisor\nExt. reset controller active when VCAP_1/2 < Min V12"] --> B["PAO"]
  A --> C["NRST"]
  B --> D["BYPASS_REG"]
  B --> E["VCCAP1\nVCCAP2"]
  D --> F["VDD\n1/2/...N"]
  E --> G["VSS\n1/2/...N"]
  F --> H["N x 100 nF\n+ 1 x 4.7 μF"]
  G --> H
  H --> I["(note 1)\n(1 x 100 nF)\n2 x 100 nF"]

The following conditions must be respected:

• V_{DD} should always be higher than V_{CAP\_1} and V_{CAP\_2} to avoid current injection between power domains.
• If the time for V_{CAP\_1} and V_{CAP\_2} to reach V_{12} minimum value is faster than the time for V_{DD} to reach 1.8 V, then PA0 should be kept low to cover both conditions: until V_{CAP\_1} and V_{CAP\_2} reach V_{12} minimum value and until V_{DD} reaches 1.8 V (see Figure 10).
• Otherwise, if the time for V_{CAP\_1} and V_{CAP\_2} to reach V_{12} minimum value is slower than the time for V_{DD} to reach 1.8 V, then PA0 could be asserted low externally (see Figure 11).
• If V_{CAP\_1} and V_{CAP\_2} go below V_{12} minimum value and V_{DD} is higher than 1.8 V, then a reset must be asserted on PA0 pin.

Note: The minimum value of V_{12} depends on the maximum frequency targeted in the application (see Table 14: General operating conditions).

Figure 10. Startup in regulator OFF mode: slow V_{DD} slope - power-down reset risen after V_{CAP\ 1}/V_{CAP\ 2} stabilization

line

Time Event	VDD (V)	VCAP_1/VCAP_2 (V)	NRST (V)
Initial Rise	~0.5	~0.5	0
PDR Threshold	1.7	1.8	0
V12 Level	1.8	1.2	~0.5
Min V12 Level	1.8	1.2	~0.5
Final Drop	1.8	~0.5	0

1. This figure is valid both whatever the internal reset mode (ON or OFF).
2. PDR = 1.7 V for reduced temperature range; PDR = 1.8 V for all temperature ranges.

Figure 11. Startup in regulator OFF mode: fast V_{DD} slope - power-down reset risen before V_{CAP 1}/V_{CAP 2} stabilization

line

Time Phase	VDD (V)	VCAP_1/VCAP_2 (V)	NRST (V)	PA0 asserted externally (V)
Initial Rise	~0	~0	0	0
PDR Point	~1.7	~0.5	0	0
Mid Rise	~1.8	~0.8	0	0
PDR Point	~1.8	~1.2	0	0
Mid Plateau	~1.8	~1.2	0	0
PDR Point	~1.8	~1.2	0	0
End Plateau	~1.8	~1.2	0	0
PDR Point	~1.8	~0.8	0	0
End Plateau	~1.8	~0.5	0	0

1. This figure is valid both whatever the internal reset mode (ON or OFF).
2. PDR = 1.7 V for a reduced temperature range; PDR = 1.8 V for all temperature ranges.

3.17 Regulator ON/OFF and internal reset ON/OFF availability

Table 3. Regulator ON/OFF and internal reset ON/OFF availability

	Regulator ON	Regulator OFF	Internal reset ON	Internal reset OFF
LQFP64LQFP100	Yes	No	Yes	No
LQFP144			YesPDR_ON set to $V_{DD}$	YesPDR_ON connected to an external power supply supervisor
WLCSP90UFBGA176LQFP176	YesBYPASS_REG set to $V_{SS}$	YesBYPASS_REG set to $V_{DD}$

3.18 Real-time clock (RTC), backup SRAM and backup registers

The backup domain of the STM32F405xx and STM32F407xx includes:

• The real-time clock (RTC) • 4 Kbytes of backup SRAM

• 20 backup registers

The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format.

It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 2 to 31. The internal low-speed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation.

Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 \mu s to every 36 hours.

A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz.

The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data which need to be retained in V_{BAT} and standby mode. This memory area is disabled by default to minimize power consumption (see Section 3.19: Low-power modes). It can be enabled by software.

The backup registers are 32-bit registers used to store 80 bytes of user application data when V_{DD} power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 3.19: Low-power modes).

Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date.

Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the V_{DD} supply when present or from the V_{BAT} pin.

3.19 Low-power modes

The STM32F405xx and STM32F407xx support three low-power modes to achieve the best compromise between low-power consumption, short startup time and available wakeup sources:

- Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.

- Stop mode

The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the V_{12} domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode.

The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup).

- Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire V_{12} domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected.

The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs.

The standby mode is not supported when the embedded voltage regulator is bypassed and the V_{12} domain is controlled by an external power.

3.20 V_{BAT} operation

The V_{BAT} pin allows to power the device V_{BAT} domain from an external battery, an external supercapacitor, or from V_{DD} when no external battery and an external supercapacitor are present.

V_{BAT} operation is activated when V_{DD} is not present.

The V_{BAT} pin supplies the RTC, the backup registers and the backup SRAM.

Note: When the microcontroller is supplied from V_{BAT} , external interrupts and RTC alarm/events do not exit it from V_{BAT} operation.

When PDR_ON pin is not connected to V_{DD} (internal reset OFF), the V_{BAT} functionality is no more available and V_{BAT} pin should be connected to V_{DD} .

3.21 Timers and watchdogs

The STM32F405xx and STM32F407xx devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers.

All timer counters can be frozen in debug mode.

Table 4 compares the features of the advanced-control, general-purpose and basic timers.

Table 4. Timer feature comparison

Timer type	Timer	Counter resolution	Counter type	Prescaler factor	DMA request generation	Capture/compare channels	Complementary output	Max interface clock (MHz)	Max timer clock (MHz)
Advanced -control	TIM1, TIM8	16-bit	Up, Down, Up/down	Any integer between 1 and 65536	Yes	4	Yes	84	168
General purpose	TIM2, TIM5	32-bit	Up, Down, Up/down	Any integer between 1 and 65536	Yes	4	No	42	84
	TIM3, TIM4	16-bit	Up, Down, Up/down	Any integer between 1 and 65536	Yes	4	No	42	84
	TIM9	16-bit	Up	Any integer between 1 and 65536	No	2	No	84	168
	TIM10, TIM11	16-bit	Up	Any integer between 1 and 65536	No	1	No	84	168
	TIM12	16-bit	Up	Any integer between 1 and 65536	No	2	No	42	84
	TIM13, TIM14	16-bit	Up	Any integer between 1 and 65536	No	1	No	42	84
Basic	TIM6, TIM7	16-bit	Up	Any integer between 1 and 65536	Yes	0	No	42	84

3.21.1 Advanced-control timers (TIM1, TIM8)

The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for:

• Input capture
• Output compare • PWM generation (edge- or center-aligned modes) • One-pulse mode output

If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-100%).

The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining.

TIM1 and TIM8 support independent DMA request generation.

3.21.2 General-purpose timers (TIMx)

There are ten synchronizable general-purpose timers embedded in the STM32F40xxx devices (see Table 4 for differences).

- TIM2, TIM3, TIM4, TIM5

The STM32F40xxx include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4. The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages.

The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining.

Any of these general-purpose timers can be used to generate PWM outputs.

TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors.

• TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases.

3.21.3 Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base.

TIM6 and TIM7 support independent DMA request generation.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features:

• A 24-bit downcounter

• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source.

3.22 Inter-integrated circuit interface (I²C)

Up to three I²C bus interfaces can operate in multimaster and slave modes. They can support the Standard-mode (up to 100 kHz) and Fast-mode (up to 400 kHz). They support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded.

They can be served by DMA and they support SMBus 2.0/PMBus.

3.23 Universal synchronous/asynchronous receiver transmitters (USART)

The STM32F405xx and STM32F407xx embed four universal synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and USART6) and two universal asynchronous receiver transmitters (UART4 and UART5).

These six interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to communicate at speeds of up to 10.5 Mbit/s. The other available interfaces communicate at up to 5.25 Mbit/s.

USART1, USART2, USART3 and USART6 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller.

Table 5. USART feature comparison

USART name	Standard features	Modem (RTS/CTS)	LIN	SPI master	irDA	Smartcard (ISO 7816)	Max. baud rate in Mbit/s (oversampling by 16)	Max. baud rate in Mbit/s (oversampling by 8)	APB mapping
USART1	X	X	X	X	X	X	5.25	10.5	APB2 (max. 84 MHz)
USART2	X	X	X	X	X	X	2.62	5.25	APB1 (max. 42 MHz)
USART3	X	X	X	X	X	X	2.62	5.25	APB1 (max. 42 MHz)
UART4	X	-	X	-	X	-	2.62	5.25	APB1 (max. 42 MHz)
UART5	X	-	X	-	X	-	2.62	5.25	APB1 (max. 42 MHz)
USART6	X	X	X	X	X	X	5.25	10.5	APB2 (max. 84 MHz)

3.24 Serial peripheral interface (SPI)

The STM32F40xxx feature up to three SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1 can communicate at up to 42 Mbits/s, SPI2 and SPI3 can communicate at up to 21 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller.

The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode.

3.25 Inter-integrated sound (I²S)

Two standard I ^{2} S interfaces (multiplexed with SPI2 and SPI3) are available. They can be operated in master or slave mode, in full duplex and half-duplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel.

Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I²S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency.

All I ^{2} Sx can be served by the DMA controller.

3.26 Audio PLL (PLLI2S)

The devices feature an additional dedicated PLL for audio I ^{2} S application. It allows to achieve error-free I ^{2} S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals.

The PLLI2S configuration can be modified to manage an I²S sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.

The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz.

In addition to the audio PLL, a master clock input pin can be used to synchronize the I²S flow with an external PLL (or Codec output).

3.27 Secure digital input/output interface (SDIO)

An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.

The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory Card Specification Version 2.0.

The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit.

The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous.

In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1.

3.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support

Peripheral available only on the STM32F407xx devices.

The STM32F407xx devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard medium-independent interface (MII) or a reduced medium-independent interface (RMII). The STM32F407xx requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F407xx MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the STM32F407xx.

The STM32F407xx includes the following features:

• Supports 10 and 100 Mbit/s rates

• Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F40xxx/41xxx reference manual for details) • Tagged MAC frame support (VLAN support) • Half-duplex (CSMA/CD) and full-duplex operation • MAC control sublayer (control frames) support • 32-bit CRC generation and removal
• Several address filtering modes for physical and multicast address (multicast and group addresses) • 32-bit status code for each transmitted or received frame
• Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes.
• Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input
• Triggers interrupt when system time becomes greater than target time

3.29 Controller area network (bxCAN)

The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated for each CAN.

3.30 Universal serial bus on-the-go full-speed (OTG_FS)

The STM32F405xx and STM32F407xx embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are:

• Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 4 bidirectional endpoints • 8 host channels with periodic OUT support • HNP/SNP/IP inside (no need for any external resistor)

• For OTG/Host modes, a power switch is needed in case bus-powered devices are connected

3.31 Universal serial bus on-the-go high-speed (OTG_HS)

The STM32F405xx and STM32F407xx devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required.

The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator.

The major features are:

• Combined Rx and Tx FIFO size of 1 Kbit × 35 with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 6 bidirectional endpoints • 12 host channels with periodic OUT support • Internal FS OTG PHY support

• External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output.
• Internal USB DMA • HNP/SNP/IP inside (no need for any external resistor)
• for OTG/Host modes, a power switch is needed in case bus-powered devices are connected

3.32 Digital camera interface (DCMI)

The camera interface is not available in STM32F405xx devices.

STM32F407xx products embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features:

• Programmable polarity for the input pixel clock and synchronization signals • Parallel data communication can be 8-, 10-, 12- or 14-bit
• Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) • Supports continuous mode or snapshot (a single frame) mode • Capability to automatically crop the image

3.33 True random number generator (RNG)

All STM32F405xx and STM32F407xx products embed a true random number generator (RNG) that provides full entropy outputs to the application as 32-bit samples. It is composed of a live entropy source (analog) and an internal conditioning component.

3.34 General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission.

The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers.

Fast I/O handling allowing maximum I/O toggling up to 84 MHz.

3.35 Analog-to-digital converters (ADCs)

Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

• Simultaneous sample and hold • Interleaved sample and hold

The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM5, or TIM8 timer.

3.36 Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.8 V and 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value.

As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used.

3.37 Digital-to-analog converter (DAC)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs.

This dual digital Interface supports the following features:

• two DAC converters: one for each output channel • 8-bit or 12-bit monotonic output • left or right data alignment in 12-bit mode • synchronized update capability
• noise-wave generation • triangular-wave generation
• dual DAC channel independent or simultaneous conversions • DMA capability for each channel • external triggers for conversion • input voltage reference V_{REF+}

Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams.

3.38 Serial wire JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.

3.39 Embedded Trace Macrocell™

The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F40xxx through a small number of ETM pins to an external hardware trace port analyser (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors.

The Embedded Trace Macrocell operates with third party debugger software tools.

4 Pinouts and pin description

Figure 12. STM32F40xxx LQFP64 pinout

text_image

VDD VSS PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VBAT 1 48 VDD PC13 2 47 VCAP_2 PC14 3 46 PA13 PC15 4 45 PA12 PH0 5 44 PA11 PH1 6 43 PA10 NRST 7 42 PA9 PC0 8 41 PA8 PC1 9 40 PC9 PC2 10 39 PC8 PC3 11 38 PC7 VSSA 12 37 PC6 VDDA 13 36 PB15 PA0_WKUP 14 35 PB14 PA1 15 34 PB13 PA2 16 33 PB12 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VDD LQFP64 ai18493b

1. The above figure shows the package top view.

Figure 13. STM32F40xxx LQFP100 pinout

text_image

VDD VSS PE1 PE0 PB9 PB8 BOOT0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PE2 1 75 VDD PE3 2 74 VSS PE4 3 73 VCAP_2 PE5 4 72 PA13 PE6 5 71 PA12 VBAT 6 70 PA 11 PC13 7 69 PA10 PC14 8 68 PA9 PC15 9 67 PA8 VSS 10 66 PC9 VDD 11 65 PC8 PH0 12 64 PC7 PH1 13 63 PC6 NRST 14 62 PD15 PC0 15 61 PD14 PC1 16 60 PD13 PC2 17 59 PD12 PC3 18 58 PD11 VDD 19 57 PD10 VSSA 20 56 PD9 VREF+ 21 55 PD8 VDDA 22 54 PB15 PA0 23 53 PB14 PA1 24 52 PB13 PA2 25 PA3 26 VSS 27 VDD 28 PA4 29 PA5 30 PA6 31 PA7 32 PC4 33 PC5 34 PB0 35 PB1 36 PB2 37 PE7 38 PE8 39 PE9 40 PE10 41 PE11 42 PE12 43 PE13 44 PE14 45 PE15 46 PB10 47 PB11 48 VCAP_1 VDD 50 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ai18495c

1. The above figure shows the package top view.

Figure 14. STM32F40xxx LQFP144 pinout

wireframe

Pin Number	Function
1	VDD
2	PDR_ON
3	PE2
4	PE3
5	PE4
6	PE5
7	PE6
8	VBAT
9	PC13
10	PC14
11	PC15
12	PF0
13	PF1
14	PF2
15	PF3
16	PF4
17	PF5
18	VSS
19	VDD
20	PF6
21	PF7
22	PF8
23	PF9
24	PF10
25	PH0
26	PH1
27	NRST
28	PC0
29	PC1
30	PC2
31	PC3
32	VDD
33	VSSA
34	VREF+
35	VDDA
36	PA0
37	PA1
38	PA2
39	PA3
40	VSS
41	VDD
42	PA4
43	PA5
44	PA6
45	PA7
46	PC4
47	PC5
48	PB0
49	PB1
50	PB2
51	PF11
52	PF12
53	PF13
54	PF14
55	PF15
56	PG0
57	PG1
58	PE7
59	PE8
60	PE9
61	VSS
62	VDD
63	PE10
64	PE11
65	PE12
66	PE13
67	PE14
68	PE15
69	PB10
70	PB11
71	VCAP_1
72	VDD

1. The above figure shows the package top view.

Figure 15. STM32F40xxx LQFP176 pinout

text_image

176 PI7 175 PI6 174 PI5 173 PI4 172 VDD 171 PDR_ON 170 PE1 169 PE0 168 PB9 167 PB8 166 BOOT0 165 PB7 164 PB6 163 PB5 162 PB4 161 PB3 160 PG15 159 VDD 158 VSS 157 PG14 156 PG13 155 PG12 154 PG11 153 PG10 152 PG9 151 PD7 150 PD6 149 VDD 148 VSS 147 PD5 146 PD4 145 PD3 144 PD2 143 PD1 142 PD0 141 PC12 140 PC11 139 PC10 138 PA15 137 PA14 136 VDD 135 VSS 134 PI3 133 PI2 PE2 1 PE3 2 PE4 3 PE5 4 PE6 5 VBAT 6 PI8 7 PC13 8 PC14 9 PC15 10 PI9 11 PI10 12 PI11 13 VSS 14 VDD 15 PF0 16 PF1 17 PF2 18 PF3 19 PF4 20 PF5 21 VSS 22 VDD 23 PF6 24 PF7 25 PF8 26 PF9 27 PF10 28 PH0 29 PH1 30 NRST 31 PC0 32 PC1 33 PC2 34 PC3 35 VDD 36 VSSA 37 VREF+ 38 VDDA 39 PA0 40 PA1 41 PA2 42 PH2 43 PH3 44 PH4 45 PH5 46 PA3 47 BYPASS_REG 48 VDD 49 PA4 50 PA5 51 PA6 52 PA7 53 PC4 54 PC5 55 PB0 56 PB1 57 PB2 58 PF11 59 PF12 60 VSS 61 VDD 62 PF13 63 PF14 64 PF15 65 PG0 66 PG1 67 PE7 68 PE8 69 PE9 70 VSS 71 VDD 72 PE10 73 PE11 74 PE12 75 PE13 76 PE14 77 PE15 78 PB10 79 PB11 80 VCAP-1 81 VDD 82 PH6 83 PH7 84 PH8 85 PH9 86 PH10 87 PH11 88 LQFP176 132 PI1 131 PI0 130 PH15 129 PH14 128 PH13 127 VDD 126 VSS 125 VCAP_2 124 PA13 123 PA12 122 PA11 121 PA10 120 PA9 119 PA8 118 PC9 117 PC8 116 PC7 115 PC6 114 VDD 113 VSS 112 PG8 111 PG7 110 PG6 109 PG5 108 PG4 107 PG3 106 PG2 105 PD15 104 PD14 103 VDD 102 VSS 101 PD13 100 PD12 99 PD11 98 PD10 97 PD9 96 PD8 95 PB15 94 PB14 93 PB13 92 PB12 91 VDD 90 VSS 89 PH12 MS19916V4

1. The above figure shows the package top view.

Figure 16. STM32F40xxx UFBGA176 bailout

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

A

PE3

PE2

PE1

PE0

PB8

PB5

PG14

PG13

PB4

PB3

PD7

PC12

PA15

PA14

PA13

B

PE4

PE5

PE6

PB9

PB7

PB6

PG15

PG12

PG11

PG10

PD6

PD0

PC11

PC10

PA12

C

VBAT

PI7

PI6

PI5

VDD

PDR_ON

VDD

VDD

VDD

PG9

PD5

PD1

PI3

PI2

PA11

D

PC13

PI8

PI9

PI4

VSS

BOOT0

VSS

VSS

VSS

PD4

PD3

PD2

PH15

PI1

PA10

E

PC14

PF0

PI10

PI11

PH13

PH14

PI0

PA9

F

PC15

VSS

VDD

PH2

VSS

VCAP_2

PC9

PA8

G

PH0

VSS

VDD

PH3

VSS

VDD

PC8

PC7

H

PH1

PF2

PF1

PH4

VSS

VDD

PG8

PC6

J

NRST

PF3

PF4

PH5

VDD

VDD

PG7

PG6

K

PF7

PF6

PF5

VDD

PH12

PG5

PG4

PG3

L

PF10

PF9

PF8

BYPASS_REG

PH11

PH10

PD15

PG2

M

VSSA

PC0

PC1

PC2

PC3

PB2

PG1

VSS

VSS

VCAP_1

PH6

PH8

PH9

PD14

PD13

N

VREF-

PA1

PA0

PA4

PC4

PF13

PG0

VDD

VDD

VDD

PE13

PH7

PD12

PD11

PD10

P

VREF+

PA2

PA6

PA5

PC5

PF12

PF15

PE8

PE9

PE11

PE14

PB12

PB13

PD9

PD8

R

VDDA

PA3

PA7

PB1

PB0

PF11

PF14

PE7

PE10

PE12

PE15

PB10

PB11

PB14

PB15

ai18497b

1. This figure shows the package top view.

Figure 17. STM32F40xxx WLCSP90 bailout MS30402V1

1. This figure shows the package bump view.

Table 6. Legend/abbreviations used in the pinout table

Name	Abbreviation	Definition
Pin name	Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
Pin type	S	Supply pin
	I	Input only pin
	I/O	Input / output pin
I/O structure	FT	5 V tolerant I/O
	TTa	3.3 V tolerant I/O directly connected to ADC
	B	Dedicated BOOT0 pin
	RST	Bidirectional reset pin with embedded weak pull-up resistor
Notes	Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate functions	Functions selected through GPIOx_AFR registers
Additional functions	Functions directly selected/enabled through peripheral registers

Table 7. STM32F40xxx pin and ball definitions ^{(1)}

Pin number						Pin name (function after reset)(2)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
LQFP64	WLCSP90	LQFP100	LQFP144	UFBGA176	LQFP176
-	-	1	1	A2	1	PE2	I/O	FT	-	TRACECLK/ FSMC_A23 / ETH_MII_TXD3 / EVENTOUT	-
-	-	2	2	A1	2	PE3	I/O	FT	-	TRACED0/FSMC_A19 / EVENTOUT	-
-	-	3	3	B1	3	PE4	I/O	FT	-	TRACED1/FSMC_A20 / DCMI_D4/ EVENTOUT	-
-	-	4	4	B2	4	PE5	I/O	FT	-	TRACED2 / FSMC_A21 / TIM9_CH1 / DCMI_D6 / EVENTOUT	-
-	-	5	5	B3	5	PE6	I/O	FT	-	TRACED3 / FSMC_A22 / TIM9_CH2 / DCMI_D7 / EVENTOUT	-
1	A10	6	6	C1	6	$V_{BAT}$	S	-	-	-	-
-	-	-	-	D2	7	PI8	I/O	FT	(3)(4)	-	RTC_TAMP1, RTC_TAMP2, RTC_TS
2	A9	7	7	D1	8	PC13	I/O	FT	(3)(4)	-	RTC_OUT, RTC_TAMP1, RTC_TS
3	B10	8	8	E1	9	PC14/OSC32_IN (PC14)	I/O	FT	(3)(4)	-	OSC32_IN(5)
4	B9	9	9	F1	10	PC15/ OSC32_OUT (PC15)	I/O	FT	(3)(4)	-	OSC32_OUT(5)
-	-	-	-	D3	11	PI9	I/O	FT	-	CAN1_RX / EVENTOUT	-
-	-	-	-	E3	12	PI10	I/O	FT	-	ETH_MII_RX_ER / EVENTOUT	-
-	-	-	-	E4	13	PI11	I/O	FT	-	OTG_HS_ULPI_DIR / EVENTOUT	-
-	-	-	-	F2	14	$V_{SS}$	S	-	-	-	-
-	-	-	-	F3	15	$V_{DD}$	S	-	-	-	-
-	-	-	10	E2	16	PF0	I/O	FT	-	FSMC_A0 / I2C2_SDA / EVENTOUT	-
-	-	-	11	H3	17	PF1	I/O	FT	-	FSMC_A1 / I2C2_SCL / EVENTOUT	-
-	-	-	12	H2	18	PF2	I/O	FT	-	FSMC_A2 / I2C2_SMBA / EVENTOUT	-
-	-	-	13	J2	19	PF3	I/O	FT	(5)	FSMC_A3/EVENTOUT	ADC3_IN9
-	-	-	14	J3	20	PF4	I/O	FT	(5)	FSMC_A4/EVENTOUT	ADC3_IN14
-	-	-	15	K3	21	PF5	I/O	FT	(5)	FSMC_A5/EVENTOUT	ADC3_IN15
-	C9	10	16	G2	22	$V_{SS}$	S	-	-	-	-
-	B8	11	17	G3	23	$V_{DD}$	S	-	-	-	-
-	-	-	18	K2	24	PF6	I/O	FT	(5)	TIM10_CH1 / FSMC_NIORD/ EVENTOUT	ADC3_IN4
-	-	-	19	K1	25	PF7	I/O	FT	(5)	TIM11_CH1/FSMC_NREG/ EVENTOUT	ADC3_IN5
-	-	-	20	L3	26	PF8	I/O	FT	(5)	TIM13_CH1 / FSMC_NIOWR/ EVENTOUT	ADC3_IN6
-	-	-	21	L2	27	PF9	I/O	FT	(5)	TIM14_CH1 / FSMC_CD/ EVENTOUT	ADC3_IN7
-	-	-	22	L1	28	PF10	I/O	FT	(5)	FSMC_INTR/ EVENTOUT	ADC3_IN8
5	F10	12	23	G1	29	PH0/OSC_IN (PH0)	I/O	FT	-	EVENTOUT	$OSC\_IN^{(5)}$
6	F9	13	24	H1	30	PH1/OSC_OUT (PH1)	I/O	FT	-	EVENTOUT	$OSC\_OUT^{(5)}$
7	G10	14	25	J1	31	NRST	I/O	RST	-	-	-
8	E10	15	26	M2	32	PC0	I/O	FT	(5)	OTG_HS_ULPI_STP/ EVENTOUT	ADC123_IN10
9	-	16	27	M3	33	PC1	I/O	FT	(5)	ETH_MDC/ EVENTOUT	ADC123_IN11
10	D10	17	28	M4	34	PC2	I/O	FT	(5)	SPI2_MISO / OTG_HS_ULPI_DIR / ETH_MII_TXD2 /I2S2ext_SD/ EVENTOUT	ADC123_IN12
11	E9	18	29	M5	35	PC3	I/O	FT	(5)	SPI2_MOSI / I2S2_SD / OTG_HS_ULPI_NXT / ETH_MII_TX_CLK/ EVENTOUT	ADC123_IN13
-	-	19	30	-	36	$V_{DD}$	S	-	-	-	-
12	H10	20	31	M1	37	$V_{SSA}$	S	-	-	-	-
-	-	-	-	N1	-	$V_{REF-}$	S	-	-	-	-
-	-	21	32	P1	38	$V_{REF+}$	S	-	-	-	-
13	G9	22	33	R1	39	$V_{DDA}$	S	-	-	-	-
14	C10	23	34	N3	40	PA0/WKUP (PA0)	I/O	FT	(6)	USART2_CTS/ UART4_TX/ ETH_MII_CRS / TIM2_CH1_ETR/ TIM5_CH1 / TIM8_ETR/ EVENTOUT	ADC123_IN0/WK UP(5)
15	F8	24	35	N2	41	PA1	I/O	FT	(5)	USART2_RTS / UART4_RX/ ETH_RMII_REF_CLK / ETH_MII_RX_CLK / TIM5_CH2 / TIM2_CH2/ EVENTOUT	ADC123_IN1
16	J10	25	36	P2	42	PA2	I/O	FT	(5)	USART2_TX/TIM5_CH3 / TIM9_CH1 / TIM2_CH3 / ETH_MDIO/ EVENTOUT	ADC123_IN2
-	-	-	-	F4	43	PH2	I/O	FT	-	ETH_MII_CRS/ EVENTOUT	-
-	-	-	-	G4	44	PH3	I/O	FT	-	ETH_MII_COL/ EVENTOUT	-
-	-	-	-	H4	45	PH4	I/O	FT	-	I2C2_SCL / OTG_HS_ULPI_NXT/ EVENTOUT	-
-	-	-	-	J4	46	PH5	I/O	FT	-	I2C2_SDA/ EVENTOUT	-
17	H9	26	37	R2	47	PA3	I/O	FT	(5)	USART2_RX/TIM5_CH4 / TIM9_CH2 / TIM2_CH4 / OTG_HS_ULPI_D0 / ETH_MII_COL/ EVENTOUT	ADC123_IN3
18	E5	27	38	-	-	$V_{SS}$	S	-	-	-	-
-	D9	-	-	L4	48	BYPASS_REG	I	FT	-	-	-
19	E4	28	39	K4	49	$V_{DD}$	S	-	-	-	-
20	J9	29	40	N4	50	PA4	I/O	TTa	(5)	SPI1_NSS / SPI3_NSS / USART2_CK / DCMI_HSYNC / OTG_HS_SOF/ I2S3_WS/ EVENTOUT	ADC12_IN4 /DAC_OUT1
21	G8	30	41	P4	51	PA5	I/O	TTa	(5)	SPI1_SCK/ OTG_HS_ULPI_CK / TIM2_CH1_ETR/ TIM8_CH1N/ EVENTOUT	ADC12_IN5/DAC_OUT2
22	H8	31	42	P3	52	PA6	I/O	FT	(5)	SPI1_MISO / TIM8_BKIN/TIM13_CH1 / DCMI_PIXCLK/TIM3_CH1 / TIM1_BKIN/ EVENTOUT	ADC12_IN6
23	J8	32	43	R3	53	PA7	I/O	FT	(5)	SPI1_MOSI/ TIM8_CH1N / TIM14_CH1/TIM3_CH2/ ETH_MII_RX_DV / TIM1_CH1N / ETH_RMII_CRS_DV/ EVENTOUT	ADC12_IN7
24	-	33	44	N5	54	PC4	I/O	FT	(5)	ETH_RMII_RX_D0 / ETH_MII_RX_D0/ EVENTOUT	ADC12_IN14
25	-	34	45	P5	55	PC5	I/O	FT	(5)	ETH_RMII_RX_D1 / ETH_MII_RX_D1/ EVENTOUT	ADC12_IN15
26	G7	35	46	R5	56	PB0	I/O	FT	(5)	TIM3_CH3 / TIM8_CH2N/ OTG_HS_ULPI_D1/ ETH_MII_RXD2 / TIM1_CH2N/ EVENTOUT	ADC12_IN8
27	H7	36	47	R4	57	PB1	I/O	FT	(5)	TIM3_CH4 / TIM8_CH3N/ OTG_HS_ULPI_D2/ ETH_MII_RXD3 / TIM1_CH3N/ EVENTOUT	ADC12_IN9
28-	J7-	37-	4849	M6R6	5859	PB2/BOOT1 (PB2)PF11	I/OI/O	FTFT	--	EVENTOUTDCMI_D12/ EVENTOUT	--
-	-	-	50	P6	60	PF12	I/O	FT	-	FSMC_A6/ EVENTOUT	-
-	-	-	51	M8	61	$V_{SS}$	S	-	-	-	-
-	-	-	52	N8	62	$V_{DD}$	S	-	-	-	-
-	-	-	53	N6	63	PF13	I/O	FT	-	FSMC_A7/ EVENTOUT	-
-	-	-	54	R7	64	PF14	I/O	FT	-	FSMC_A8/ EVENTOUT	-
-	-	-	55	P7	65	PF15	I/O	FT	-	FSMC_A9/ EVENTOUT	-
-	-	-	56	N7	66	PG0	I/O	FT	-	FSMC_A10/ EVENTOUT	-
-	-	-	57	M7	67	PG1	I/O	FT	-	FSMC_A11/ EVENTOUT	-
-	G6	38	58	R8	68	PE7	I/O	FT	-	FSMC_D4/TIM1_ETR/ EVENTOUT	-
-	H6	39	59	P8	69	PE8	I/O	FT	-	FSMC_D5/ TIM1_CH1N/ EVENTOUT	-
-	J6	40	60	P9	70	PE9	I/O	FT	-	FSMC_D6/TIM1_CH1/ EVENTOUT	-
-	-	-	61	M9	71	$V_{SS}$	S	-	-	-	-
-	-	-	62	N9	72	$V_{DD}$	S	-	-	-	-
-	F6	41	63	R9	73	PE10	I/O	FT	-	FSMC_D7/TIM1_CH2N/ EVENTOUT	-
-	J5	42	64	P10	74	PE11	I/O	FT	-	FSMC_D8/TIM1_CH2/ EVENTOUT	-
-	H5	43	65	R10	75	PE12	I/O	FT	-	FSMC_D9/TIM1_CH3N/ EVENTOUT	-
-	G5	44	66	N11	76	PE13	I/O	FT	-	FSMC_D10/TIM1_CH3/ EVENTOUT	-
-	F5	45	67	P11	77	PE14	I/O	FT	-	FSMC_D11/TIM1_CH4/ EVENTOUT	-
-	G4	46	68	R11	78	PE15	I/O	FT	-	FSMC_D12/TIM1_BKIN/ EVENTOUT	-
29	H4	47	69	R12	79	PB10	I/O	FT	-	SPI2_SCK / I2S2_CK / I2C2_SCL/ USART3_TX / OTG_HS_ULPI_D3 / ETH_MII_RX_ER / TIM2_CH3/ EVENTOUT	-
30	J4	48	70	R13	80	PB11	I/O	FT	-	I2C2_SDA/USART3_RX/ OTG_HS_ULPI_D4 / ETH_RMII_TX_EN/ ETH_MII_TX_EN / TIM2_CH4/ EVENTOUT	-
31	F4	49	71	M10	81	$V_{CAP\_1}$	S	-	-	-	-
32	-	50	72	N10	82	$V_{DD}$	S	-	-	-	-
-	-	-	-	M11	83	PH6	I/O	FT	-	I2C2_SMBA / TIM12_CH1 / ETH_MII_RXD2/ EVENTOUT	-
-	-	-	-	N12	84	PH7	I/O	FT	-	I2C3_SCL / ETH_MII_RXD3/ EVENTOUT	-
-	-	-	-	M12	85	PH8	I/O	FT	-	I2C3_SDA / DCMI_HSYNC/ EVENTOUT	-
-	-	-	-	M13	86	PH9	I/O	FT	-	I2C3_SMBA / TIM12_CH2/ DCMI_D0/ EVENTOUT	-
-	-	-	-	L13	87	PH10	I/O	FT	-	TIM5_CH1 / DCMI_D1/ EVENTOUT	-
-	-	-	-	L12	88	PH11	I/O	FT	-	TIM5_CH2 / DCMI_D2/ EVENTOUT	-
-	-	-	-	K12	89	PH12	I/O	FT	-	TIM5_CH3 / DCMI_D3/ EVENTOUT	-
-	-	-	-	H12	90	$V_{SS}$	S	-	-	-	-
-	-	-	-	J12	91	$V_{DD}$	S	-	-	-	-
33	J3	51	73	P12	92	PB12	I/O	FT	-	SPI2_NSS / I2S2_WS / I2C2_SMBA/USART3_CK/TIM1_BKIN / CAN2_RX / OTG_HS_ULPI_D5/ETH_RMII_TXD0 / ETH_MII_TXD0/OTG_HS_ID/ EVENTOUT	-
34	J1	52	74	P13	93	PB13	I/O	FT	-	SPI2_SCK / I2S2_CK / USART3_CTS/TIM1_CH1N /CAN2_TX / OTG_HS_ULPI_D6 / ETH_RMII_TXD1 / ETH_MII_TXD1/ EVENTOUT	OTG_HS_VBUS
35	J2	53	75	R14	94	PB14	I/O	FT	-	SPI2_MISO/TIM1_CH2N / TIM12_CH1 / OTG_HS_DM/USART3_RTS / TIM8_CH2N/I2S2ext_SD/ EVENTOUT	-
36	H1	54	76	R15	95	PB15	I/O	FT	-	SPI2_MOSI / I2S2_SD/TIM1_CH3N / TIM8_CH3N / TIM12_CH2 / OTG_HS_DP/ EVENTOUT	RTC_REFIN
-	H2	55	77	P15	96	PD8	I/O	FT	-	FSMC_D13/USART3_TX/ EVENTOUT	-
-	H3	56	78	P14	97	PD9	I/O	FT	-	FSMC_D14/USART3_RX/ EVENTOUT	-
-	G3	57	79	N15	98	PD10	I/O	FT	-	FSMC_D15/USART3_CK/ EVENTOUT	-
-	G1	58	80	N14	99	PD11	I/O	FT	-	FSMC_CLE / FSMC_A16/USART3_CTS/ EVENTOUT	-
-	G2	59	81	N13	100	PD12	I/O	FT	-	FSMC_ALE/ FSMC_A17/TIM4_CH1 / USART3_RTS/ EVENTOUT	-
-	-	60	82	M15	101	PD13	I/O	FT	-	FSMC_A18/TIM4_CH2/ EVENTOUT	-
-	-	-	83	-	102	$V_{SS}$	S	-	-	-	-
-	-	-	84	J13	103	$V_{DD}$	S	-	-	-	-
-	F2	61	85	M14	104	PD14	I/O	FT	-	FSMC_D0/TIM4_CH3/ EVENTOUT/ EVENTOUT	-
-	F1	62	86	L14	105	PD15	I/O	FT	-	FSMC_D1/TIM4_CH4/ EVENTOUT	-
-	-	-	87	L15	106	PG2	I/O	FT	-	FSMC_A12/ EVENTOUT	-
-	-	-	88	K15	107	PG3	I/O	FT	-	FSMC_A13/ EVENTOUT	-
-	-	-	89	K14	108	PG4	I/O	FT	-	FSMC_A14/ EVENTOUT	-
-	-	-	90	K13	109	PG5	I/O	FT	-	FSMC_A15/ EVENTOUT	-
-	-	-	91	J15	110	PG6	I/O	FT	-	FSMC_INT2/ EVENTOUT	-
-	-	-	92	J14	111	PG7	I/O	FT	-	FSMC_INT3/USART6_CK/ EVENTOUT	-
-	-	-	93	H14	112	PG8	I/O	FT	-	USART6_RTS/ ETH_PPS_OUT/ EVENTOUT	-
-	-	-	94	G12	113	$V_{SS}$	S		-	-	-
-	-	-	95	H13	114	$V_{DD}$	S		-	-	-
37	F3	63	96	H15	115	PC6	I/O	FT	-	I2S2_MCK/ TIM8_CH1/SDIO_D6/ USART6_TX/ DCMI_D0/TIM3_CH1/ EVENTOUT	-
38	E1	64	97	G15	116	PC7	I/O	FT	-	I2S3_MCK/ TIM8_CH2/SDIO_D7/ USART6_RX/ DCMI_D1/TIM3_CH2/ EVENTOUT	-
39	E2	65	98	G14	117	PC8	I/O	FT	-	TIM8_CH3/SDIO_D0 /TIM3_CH3/ USART6_CK/ DCMI_D2/ EVENTOUT	-
40	E3	66	99	F14	118	PC9	I/O	FT	-	I2S_CKIN/ MCO2 / TIM8_CH4/SDIO_D1 / /I2C3_SDA / DCMI_D3 / TIM3_CH4/ EVENTOUT	-
41	D1	67	100	F15	119	PA8	I/O	FT	-	MCO1 / USART1_CK/ TIM1_CH1/ I2C3_SCL/ OTG_FS_SOF/ EVENTOUT	-
42	D2	68	101	E15	120	PA9	I/O	FT	-	USART1_TX/ TIM1_CH2 / I2C3_SMBA / DCMI_D0/ EVENTOUT	OTG_FS_VBUS
43	D3	69	102	D15	121	PA10	I/O	FT	-	USART1_RX/ TIM1_CH3/ OTG_FS_ID/DCMI_D1/ EVENTOUT	-
44	C1	70	103	C15	122	PA11	I/O	FT	-	USART1_CTS / CAN1_RX / TIM1_CH4 / OTG_FS_DM/ EVENTOUT	-
45	C2	71	104	B15	123	PA12	I/O	FT	-	USART1_RTS / CAN1_TX/ TIM1_ETR/ OTG_FS_DP/ EVENTOUT	-
46	D4	72	105	A15	124	PA13 (JTMS-SWDIO)	I/O	FT	-	JTMS-SWDIO/ EVENTOUT	-
47	B1	73	106	F13	125	$V_{CAP\_2}$	S	-	-	-	-
-	E7	74	107	F12	126	$V_{SS}$	S	-	-	-	-
48	E6	75	108	G13	127	$V_{DD}$	S	-	-	-	-
-	-	-	-	E12	128	PH13	I/O	FT	-	TIM8_CH1N / CAN1_TX/ EVENTOUT	-
-	-	-	-	E13	129	PH14	I/O	FT	-	TIM8_CH2N / DCMI_D4/ EVENTOUT	-
-	-	-	-	D13	130	PH15	I/O	FT	-	TIM8_CH3N / DCMI_D11/ EVENTOUT	-
-	C3	-	-	E14	131	PI0	I/O	FT	-	TIM5_CH4 / SPI2_NSS / I2S2_WS / DCMI_D13/ EVENTOUT	-
-	B2	-	-	D14	132	PI1	I/O	FT	-	SPI2_SCK / I2S2_CK / DCMI_D8/ EVENTOUT	-
-	-	-	-	C14	133	PI2	I/O	FT	-	TIM8_CH4 /SPI2_MISO / DCMI_D9 / I2S2ext_SD/ EVENTOUT	-
-	-	-	-	C13	134	PI3	I/O	FT	-	TIM8_ETR / SPI2_MOSI / I2S2_SD / DCMI_D10/ EVENTOUT	-
-	-	-	-	D9	135	VSS	S	-	-	-	-
-	-	-	-	C9	136	VDD	S	-	-	-	-
49	A2	76	109	A14	137	PA14 (JTCK/SWCLK)	I/O	FT	-	JTCK-SWCLK/ EVENTOUT	-
50	B3	77	110	A13	138	PA15 (JTDI)	I/O	FT	-	JTDI/ SPI3_NSS/ I2S3_WS/TIM2_CH1_ETR / SPI1_NSS / EVENTOUT	-
51	D5	78	111	B14	139	PC10	I/O	FT	-	SPI3_SCK / I2S3_CK/ UART4_TX/SDIO_D2 / DCMI_D8 / USART3_TX/ EVENTOUT	-
52	C4	79	112	B13	140	PC11	I/O	FT	-	UART4_RX/ SPI3_MISO / SDIO_D3 / DCMI_D4/USART3_RX / I2S3ext_SD/ EVENTOUT	-
53	A3	80	113	A12	141	PC12	I/O	FT	-	UART5_TX/SDIO_CK / DCMI_D9 / SPI3_MOSI /I2S3_SD / USART3_CK/ EVENTOUT	-
-	D6	81	114	B12	142	PD0	I/O	FT	-	FSMC_D2/CAN1_RX/ EVENTOUT	-
-	C5	82	115	C12	143	PD1	I/O	FT	-	FSMC_D3 / CAN1_TX/ EVENTOUT	-
54	B4	83	116	D12	144	PD2	I/O	FT	-	TIM3_ETR/UART5_RX/ SDIO_CMD / DCMI_D11/ EVENTOUT	-
-	-	84	117	D11	145	PD3	I/O	FT	-	FSMC_CLK/ USART2_CTS/ EVENTOUT	-
-	A4	85	118	D10	146	PD4	I/O	FT	-	FSMC_NOE/USART2_RTS/ EVENTOUT	-
-	C6	86	119	C11	147	PD5	I/O	FT	-	FSMC_NWE/USART2_TX/ EVENTOUT	-
-	-	-	120	D8	148	$V_{SS}$	S	-	-	-	-
-	-	-	121	C8	149	$V_{DD}$	S	-	-	-	-
-	B5	87	122	B11	150	PD6	I/O	FT	-	FSMC_NWAIT/USART2_RX/ EVENTOUT	-
-	A5	88	123	A11	151	PD7	I/O	FT	-	USART2_CK/FSMC_NE1/ FSMC_NCE2/ EVENTOUT	-
-	-	-	124	C10	152	PG9	I/O	FT	-	USART6_RX / FSMC_NE2/FSMC_NCE3/ EVENTOUT	-
-	-	-	125	B10	153	PG10	I/O	FT	-	FSMC_NCE4_1/ FSMC_NE3/ EVENTOUT	-
-	-	-	126	B9	154	PG11	I/O	FT	-	FSMC_NCE4_2/ ETH_MII_TX_EN/ ETH_RMII_TX_EN/ EVENTOUT	-
-	-	-	127	B8	155	PG12	I/O	FT	-	FSMC_NE4 / USART6_RTS/ EVENTOUT	-
-	-	-	128	A8	156	PG13	I/O	FT	-	FSMC_A24 / USART6_CTS /ETH_MII_TXD0/ ETH_RMII_TXD0/ EVENTOUT	-
-	-	-	129	A7	157	PG14	I/O	FT	-	FSMC_A25 / USART6_TX /ETH_MII_TXD1/ ETH_RMII_TXD1/ EVENTOUT	-
-	E8	-	130	D7	158	$V_{SS}$	S	-	-	-	-
-	F7	-	131	C7	159	$V_{DD}$	S	-	-	-	-
-	-	-	132	B7	160	PG15	I/O	FT	-	USART6_CTS / DCMI_D13/ EVENTOUT	-
55	B6	89	133	A10	161	PB3 (JTDO/ TRACESWO)	I/O	FT	-	JTDO/ TRACESWO/ SPI3_SCK / I2S3_CK / TIM2_CH2 / SPI1_SCK/ EVENTOUT	-
56	A6	90	134	A9	162	PB4 (NJTRST)	I/O	FT	-	NJTRST/ SPI3_MISO / TIM3_CH1 / SPI1_MISO / I2S3ext_SD/ EVENTOUT	-
57	D7	91	135	A6	163	PB5	I/O	FT	-	I2C1_SMBA/ CAN2_RX / OTG_HS_ULPI_D7 / ETH_PPS_OUT/TIM3_CH2 / SPI1_MOSI/ SPI3_MOSI / DCMI_D10 / I2S3_SD/ EVENTOUT	-
58	C7	92	136	B6	164	PB6	I/O	FT	-	I2C1_SCL/ TIM4_CH1 / CAN2_TX / DCMI_D5/USART1_TX/ EVENTOUT	-
59	B7	93	137	B5	165	PB7	I/O	FT	-	I2C1_SDA / FSMC_NL / DCMI_VSYNC / USART1_RX/ TIM4_CH2/ EVENTOUT	-
60	A7	94	138	D6	166	BOOT0	I	B	-	-	$V_{PP}$
61	D8	95	139	A5	167	PB8	I/O	FT	-	TIM4_CH3/SDIO_D4/ TIM10_CH1 / DCMI_D6 / ETH_MII_TXD3 / I2C1_SCL/ CAN1_RX/ EVENTOUT	-
62	C8	96	140	B4	168	PB9	I/O	FT	-	SPI2_NSS/ I2S2_WS / TIM4_CH4/ TIM11_CH1/ SDIO_D5 / DCMI_D7 / I2C1_SDA / CAN1_TX/ EVENTOUT	-
-	-	97	141	A4	169	PE0	I/O	FT	-	TIM4_ETR / FSMC_NBL0 / DCMI_D2/ EVENTOUT	-
-	-	98	142	A3	170	PE1	I/O	FT	-	FSMC_NBL1 / DCMI_D3/ EVENTOUT	-
63	-	99	-	D5	-	$V_{SS}$	S	-	-	-	-
-	A8	-	143	C6	171	PDR_ON	I	FT	-	-	-
64	A1	100	144	C5	172	$V_{DD}$	S	-	-	-	-
-	-	-	-	D4	173	PI4	I/O	FT	-	TIM8_BKIN / DCMI_D5/ EVENTOUT	-
-	-	-	-	C4	174	PI5	I/O	FT	-	TIM8_CH1 / DCMI_VSYNC/ EVENTOUT	-
-	-	-	-	C3	175	PI6	I/O	FT	-	TIM8_CH2 / DCMI_D6/ EVENTOUT	-
-	-	-	-	C2	176	PI7	I/O	FT	-	TIM8_CH3 / DCMI_D7/ EVENTOUT	-

1. UFBGA176 F6, F7, F8, F9, F10, G6, G7, G8, G9, G10, H6, H7, H8, H9, H10, J6, J7, J8, J9, J10, K6, K7, K8, K9 and K10 balls are connected to V_{SS} for heat dissipation and package mechanical stability.
2. Function availability depends on the chosen device.
3. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited:

• The speed should not exceed 2 MHz with a maximum load of 30 pF.
• These I/Os must not be used as a current source (e.g. to drive an LED).

4. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website: www.st.com.
5. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
6. If the device is delivered in an UFBGA176 or WLCSP90 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset ON mode), then PA0 is used as an internal Reset (active low).

Table 8. FSMC pin definition

Pins(1)	FSMC				LQFP100(2)	WLCSP90(2)
	CF	NOR/PSRAM/SRAM	NOR/PSRAM Mux	NAND 16 bit
PE2	-	A23	A23	-	Yes	-
PE3	-	A19	A19	-	Yes	-
PE4	-	A20	A20	-	Yes	-
PE5	-	A21	A21	-	Yes	-
PE6	-	A22	A22	-	Yes	-
$Pins^{(1)}$	FSMC				$LQFP100^{(2)}$	WLCSP90(2)
	CF	NOR/PSRAM/SRAM	NOR/PSRAM Mux	NAND 16 bit
PF0	A0	A0	-	-	-	-
PF1	A1	A1	-	-	-	-
PF2	A2	A2	-	-	-	-
PF3	A3	A3	-	-	-	-
PF4	A4	A4	-	-	-	-
PF5	A5	A5	-	-	-	-
PF6	NIORD	-	-	-	-	-
PF7	NREG	-	-	-	-	-
PF8	NIOWR	-	-	-	-	-
PF9	CD	-	-	-	-	-
PF10	INTR	-	-	-	-	-
PF12	A6	A6	-	-	-	-
PF13	A7	A7	-	-	-	-
PF14	A8	A8	-	-	-	-
PF15	A9	A9	-	-	-	-
PG0	A10	A10	-	-	-	-
PG1	-	A11	-	-	-	-
PE7	D4	D4	DA4	D4	Yes	Yes
PE8	D5	D5	DA5	D5	Yes	Yes
PE9	D6	D6	DA6	D6	Yes	Yes
PE10	D7	D7	DA7	D7	Yes	Yes
PE11	D8	D8	DA8	D8	Yes	Yes
PE12	D9	D9	DA9	D9	Yes	Yes
PE13	D10	D10	DA10	D10	Yes	Yes
PE14	D11	D11	DA11	D11	Yes	Yes
PE15	D12	D12	DA12	D12	Yes	Yes
PD8	D13	D13	DA13	D13	Yes	Yes
PD9	D14	D14	DA14	D14	Yes	Yes
PD10	D15	D15	DA15	D15	Yes	Yes
PD11	-	A16	A16	CLE	Yes	Yes
PD12	-	A17	A17	ALE	Yes	Yes
PD13	-	A18	A18	-	Yes	-
PD14	D0	D0	DA0	D0	Yes	Yes
$Pins^{(1)}$	FSMC				$LQFP100^{(2)}$	$WLCSP90^{(2)}$
	CF	NOR/PSRAM/SRAM	NOR/PSRAM Mux	NAND 16 bit
PD15	D1	D1	DA1	D1	Yes	Yes
PG2	-	A12	-	-	-	-
PG3	-	A13	-	-	-	-
PG4	-	A14	-	-	-	-
PG5	-	A15	-	-	-	-
PG6	-	-	-	INT2	-	-
PG7	-	-	-	INT3	-	-
PD0	D2	D2	DA2	D2	Yes	Yes
PD1	D3	D3	DA3	D3	Yes	Yes
PD3	-	CLK	CLK	-	Yes	-
PD4	NOE	NOE	NOE	NOE	Yes	Yes
PD5	NWE	NWE	NWE	NWE	Yes	Yes
PD6	NWAIT	NWAIT	NWAIT	NWAIT	Yes	Yes
PD7	-	NE1	NE1	NCE2	Yes	Yes
PG9	-	NE2	NE2	NCE3	-	-
PG10	NCE4_1	NE3	NE3	-	-	-
PG11	NCE4_2	-	-	-	-	-
PG12	-	NE4	NE4	-	-	-
PG13	-	A24	A24	-	-	-
PG14	-	A25	A25	-	-	-
PB7	-	NADV	NADV	-	Yes	Yes
PE0	-	NBL0	NBL0	-	Yes	-
PE1	-	NBL1	NBL1	-	Yes	-

1. Full FSMC features are available on LQFP144, LQFP176, and UFBGA176. The features available on smaller packages are given in the dedicated package column.
2. Ports F and G are not available in devices delivered in 100-pin packages.

Table 9. Alternate function mapping

Port

AF0

AF1

AF2

AF3

AF4

AF5

AF6

AF7

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

SYS

TIM1/2

TIM3/4/5

TIM8/9/10/11

I2C1/2/3

SPI1/SPI2/I2S2/I2S2ext

SPI3/I2Sext/I2S3

USART1/2/3/I2S3ext

UART4/5/USART6

CAN1/2TIM12/13/14

OTG_FS/OTG_HS

ETH

FSMC/SDIO/OTG_FS

DCMI

Port A

PA0

-

TIM2_CH1_ETR

TIM 5_CH1

TIM8_ETR

-

-

-

USART2_CTS

UART4_TX

-

-

ETH_MII_CRS

-

-

-

EVENTOUT

PA1

-

TIM2_CH2

TIM5_CH2

-

-

-

-

USART2_RTS

UART4_RX

-

-

ETH_MII_RX_CLKETH_RMII_REF_CLK

-

-

-

EVENTOUT

PA2

-

TIM2_CH3

TIM5_CH3

TIM9_CH1

-

-

-

USART2_TX

-

-

-

ETH_MDIO

-

-

-

EVENTOUT

PA3

-

TIM2_CH4

TIM5_CH4

TIM9_CH2

-

-

-

USART2_RX

-

-

OTG_HS_ULPI_D0

ETH_MII_COL

-

-

-

EVENTOUT

PA4

-

-

-

-

-

SPI1_NSS

SPI3_NSS I2S3_WS

USART2_CK

-

-

-

-

OTG_HS_SOF

DCMI_HSYNC

-

EVENTOUT

PA5

-

TIM2_CH1_ETR

-

TIM8_CH1N

-

SPI1_SCK

-

-

-

-

OTG_HS_ULPI_CK

-

-

-

-

EVENTOUT

PA6

-

TIM1_BKIN

TIM3_CH1

TIM8_BKIN

-

SPI1_MISO

-

-

-

TIM13_CH1

-

-

-

DCMI_PIXCLK

-

EVENTOUT

PA7

-

TIM1_CH1N

TIM3_CH2

TIM8_CH1N

-

SPI1_MOSI

-

-

-

TIM14_CH1

-

ETH_MII_RX_DVETH_RMII_CRS_DV

-

-

-

EVENTOUT

PA8

MCO1

TIM1_CH1

-

-

I2C3_SCL

-

-

USART1_CK

-

-

OTG_FS_SOF

-

-

-

-

EVENTOUT

PA9

-

TIM1_CH2

-

-

I2C3_SMBA

-

-

USART1_TX

-

-

-

-

-

DCMI_D0

-

EVENTOUT

PA10

-

TIM1_CH3

-

-

-

-

-

USART1_RX

-

-

OTG_FS_ID

-

-

DCMI_D1

-

EVENTOUT

PA11

-

TIM1_CH4

-

-

-

-

-

USART1_CTS

-

CAN1_RX

OTG_FS_DM

-

-

-

-

EVENTOUT

PA12

-

TIM1_ETR

-

-

-

-

-

USART1_RTS

-

CAN1_TX

OTG_FS_DP

-

-

-

-

EVENTOUT

PA13

JTMS-SWDIO

-

-

-

-

-

-

-

-

-

-

-

-

-

-

EVENTOUT

PA14

JTCK-SWCLK

-

-

-

-

-

-

-

-

-

-

-

-

-

-

EVENTOUT

PA15

JTDI

TIM 2_CH1TIM 2_ETR

-

-

-

SPI1_NSS

SPI3_NSS/I2S3_WS

-

-

-

-

-

-

-

-

EVENTOUT

DS8626 Rev 12

Table 9. Alternate function mapping (continued)

Port

AF0

AF1

AF2

AF3

AF4

AF5

AF6

AF7

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

SYS

TIM1/2

TIM3/4/5

TIM8/9/10/11

I2C1/2/3

SPI1/SPI2/I2S2/I2S2ext

SPI3/I2Sext/I2S3

USART1/2/3/I2S3ext

UART4/5/USART6

CAN1/2TIM12/13/14

OTG_FS/OTG_HS

ETH

FSMC/SDIO/OTG_FS

DCMI

Port B

PB0

-

TIM1_CH2N

TIM3_CH3

TIM8_CH2N

-

-

-

-

-

-

OTG_HS_ULPI_D1

ETH_MII_RXD2

-

-

-

EVENTOUT

PB1

-

TIM1_CH3N

TIM3_CH4

TIM8_CH3N

-

-

-

-

-

OTG_HS_ULPI_D2

ETH_MII_RXD3

-

-

-

EVENTOUT

PB2

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

EVENTOUT

PB3

JTDO/TRACESWO

TIM2_CH2

-

-

-

SPI1_SCK

SPI3_SCKI2S3_CK

-

-

-

-

-

-

-

-

EVENTOUT

PB4

NJTRST

-

TIM3_CH1

-

SPI1_MISO

SPI3_MISO

I2S3ext_SD

-

-

-

-

-

-

-

EVENTOUT

PB5

-

-

TIM3_CH2

I2C1_SMBA

SPI1_MOSI

SPI3_MOSI I2S3_SD

-

-

CAN2_RX

OTG_HS_ULPI_D7

ETH_PPS_OUT

-

DCMI_D10

-

EVENTOUT

PB6

-

-

TIM4_CH1

I2C1_SCL

-

-

USART1_TX

-

CAN2_TX

-

-

-

DCMI_D5

-

EVENTOUT

PB7

-

-

TIM4_CH2

I2C1_SDA

-

-

USART1_RX

-

-

-

-

FSMC_NL

DCMI_VSYNC

-

EVENTOUT

PB8

-

-

TIM4_CH3

TIM10_CH1

I2C1_SCL

-

-

-

-

CAN1_RX

-

ETH_MII_TXD3

SDIO_D4

DCMI_D6

-

EVENTOUT

PB9

-

-

TIM4_CH4

TIM11_CH1

I2C1_SDA

SPI2_NSS I2S2_WS

-

-

-

CAN1_TX

-

-

SDIO_D5

DCMI_D7

-

EVENTOUT

PB10

-

TIM2_CH3

-

-

I2C2_SCL

SPI2_SCK I2S2_CK

-

USART3_TX

-

-

OTG_HS_ULPI_D3

ETH_MII_RX_ER

-

-

-

EVENTOUT

PB11

-

TIM2_CH4

-

-

I2C2_SDA

-

-

USART3_RX

-

-

OTG_HS_ULPI_D4

ETH_MII_TX_ENETH_RMII_TX_EN

-

-

-

EVENTOUT

PB12

-

TIM1_BKIN

-

-

I2C2_SMBA

SPI2_NSS I2S2_WS

-

USART3_CK

-

CAN2_RX

OTG_HS_ULPI_D5

ETH_MII_TXD0ETH_RMII_TXD0

OTG_HS_ID

-

-

EVENTOUT

PB13

-

TIM1_CH1N

-

-

-

SPI2_SCK I2S2_CK

-

USART3_CTS

-

CAN2_TX

OTG_HS_ULPI_D6

ETH_MII_TXD1ETH_RMII_TXD1

-

-

-

EVENTOUT

PB14

-

TIM1_CH2N

-

TIM8_CH2N

-

SPI2_MISO

I2S2ext_SD

USART3_RTS

-

TIM12_CH1

-

-

OTG_HS_DM

-

-

EVENTOUT

PB15

RTC_REFIN

TIM1_CH3N

-

TIM8_CH3N

-

SPI2_MOSI I2S2_SD

-

-

-

TIM12_CH2

-

-

OTG_HS_DP

-

-

EVENTOUT

Port C

PC0

-

-

-

-

-

-

-

-

-

-

OTG_HS_ULPI_STP

-

-

-

-

EVENTOUT

PC1

-

-

-

-

-

-

-

-

-

-

-

ETH_MDC

-

-

-

EVENTOUT

PC2

-

-

-

-

-

SPI2_MISO

I2S2ext_SD

-

-

-

OTG_HS_ULPI_DIR

ETH_MII_TXD2

-

-

-

EVENTOUT

PC3

-

-

-

-

-

SPI2_MOSI I2S2_SD

-

-

-

-

OTG_HS_ULPI_NXT

ETH_MII_TX_CLK

-

-

-

EVENTOUT

PC4

-

-

-

-

-

-

-

-

-

-

-

ETH_MII_RXD0 ETH_RMII_RXD0

-

-

-

EVENTOUT

PC5

-

-

-

-

-

-

-

-

-

-

-

ETH_MII_RXD1 ETH_RMII_RXD1

-

-

-

EVENTOUT

PC6

-

-

TIM3_CH1

TIM8_CH1

I2S2_MCK

-

USART6_TX

-

-

-

SDIO_D6

DCMI_D0

-

EVENTOUT

PC7

-

-

TIM3_CH2

TIM8_CH2

-

-

I2S3_MCK

-

USART6_RX

-

-

-

SDIO_D7

DCMI_D1

-

EVENTOUT

PC8

-

-

TIM3_CH3

TIM8_CH3

-

-

-

-

USART6_CK

-

-

-

SDIO_D0

DCMI_D2

-

EVENTOUT

PC9

MCO2

-

TIM3_CH4

TIM8_CH4

I2C3_SDA

I2S_CKIN

-

-

-

-

-

-

SDIO_D1

DCMI_D3

-

EVENTOUT

PC10

-

-

-

-

-

-

SPI3_SCK/I2S3_CK

USART3_TX/

UART4_TX

-

-

-

SDIO_D2

DCMI_D8

-

EVENTOUT

PC11

-

-

-

-

-

I2S3ext_SD

SPI3_MISO/

USART3_RX

UART4_RX

-

-

-

SDIO_D3

DCMI_D4

-

EVENTOUT

PC12

-

-

-

-

-

-

SPI3_MOSI I2S3_SD

USART3_CK

UART5_TX

-

-

-

SDIO_CK

DCMI_D9

-

EVENTOUT

PC13

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

PC14

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

PC15

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Table 9. Alternate function mapping (continued)

Port

AF0

AF1

AF2

AF3

AF4

AF5

AF6

AF7

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

SYS

TIM1/2

TIM3/4/5

TIM8/9/10/11

I2C1/2/3

SPI1/SPI2/I2S2/I2S2ext

SPI3/I2Sext/I2S3

USART1/2/3/I2S3ext

UART4/5/USART6

CAN1/2 TIM12/13/14

OTG_FS/OTG_HS

ETH

FSMC/SDIO/OTG_FS

DCMI

Port D

PD0

-

-

-

-

-

-

-

-

-

CAN1_RX

-

-

FSMC_D2

-

-

EVENTOUT

PD1

-

-

-

-

-

-

-

-

-

CAN1_TX

-

-

FSMC_D3

-

-

EVENTOUT

PD2

-

-

TIM3_ETR

-

-

-

-

-

UART5_RX

-

-

-

SDIO_CMD

DCMI_D11

-

EVENTOUT

PD3

-

-

-

-

-

-

-

USART2_CTS

-

-

-

-

FSMC_CLK

-

-

EVENTOUT

PD4

-

-

-

-

-

-

-

USART2_RTS

-

-

-

-

FSMC_NOE

-

-

EVENTOUT

PD5

-

-

-

-

-

-

-

USART2_TX

-

-

-

-

FSMC_NWE

-

-

EVENTOUT

PD6

-

-

-

-

-

-

-

USART2_RX

-

-

-

-

FSMC_NWAIT

-

-

EVENTOUT

PD7

-

-

-

-

-

-

-

USART2_CK

-

-

-

-

FSMC_NE1/FSMC_NCE2

-

-

EVENTOUT

PD8

-

-

-

-

-

-

-

USART3_TX

-

-

-

-

FSMC_D13

-

-

EVENTOUT

PD9

-

-

-

-

-

-

-

USART3_RX

-

-

-

-

FSMC_D14

-

-

EVENTOUT

PD10

-

-

-

-

-

-

-

USART3_CK

-

-

-

-

FSMC_D15

-

-

EVENTOUT

PD11

-

-

-

-

-

-

-

USART3_CTS

-

-

-

-

FSMC_A16

-

-

EVENTOUT

PD12

-

-

TIM4_CH1

-

-

-

-

USART3_RTS

-

-

-

-

FSMC_A17

-

-

EVENTOUT

PD13

-

-

TIM4_CH2

-

-

-

-

-

-

-

-

-

FSMC_A18

-

-

EVENTOUT

PD14

-

-

TIM4_CH3

-

-

-

-

-

-

-

-

-

FSMC_D0

-

-

EVENTOUT

PD15

-

-

TIM4_CH4

-

-

-

-

-

-

-

-

-

FSMC_D1

-

-

EVENTOUT

Port E

PE0

-

-

TIM4_ETR

-

-

-

-

-

-

-

-

-

FSMC_NBL0

DCMI_D2

-

EVENTOUT

PE1

-

-

-

-

-

-

-

-

-

-

-

-

FSMC_NBL1

DCMI_D3

-

EVENTOUT

PE2

TRACECLK

-

-

-

-

-

-

-

-

-

-

ETH_MII_TXD3

FSMC_A23

-

-

EVENTOUT

PE3

TRACED0

-

-

-

-

-

-

-

-

-

-

-

FSMC_A19

-

-

EVENTOUT

PE4

TRACED1

-

-

-

-

-

-

-

-

-

-

-

FSMC_A20

DCMI_D4

-

EVENTOUT

PE5

TRACED2

-

-

TIM9_CH1

-

-

-

-

-

-

-

-

FSMC_A21

DCMI_D6

-

EVENTOUT

PE6

TRACED3

-

-

TIM9_CH2

-

-

-

-

-

-

-

-

FSMC_A22

DCMI_D7

-

EVENTOUT

PE7

-

TIM1_ETR

-

-

-

-

-

-

-

-

-

-

FSMC_D4

-

-

EVENTOUT

PE8

-

TIM1_CH1N

-

-

-

-

-

-

-

-

-

-

FSMC_D5

-

-

EVENTOUT

PE9

-

TIM1_CH1

-

-

-

-

-

-

-

-

-

-

FSMC_D6

-

-

EVENTOUT

PE10

-

TIM1_CH2N

-

-

-

-

-

-

-

-

-

-

FSMC_D7

-

-

EVENTOUT

PE11

-

TIM1_CH2

-

-

-

-

-

-

-

-

-

-

FSMC_D8

-

-

EVENTOUT

PE12

-

TIM1_CH3N

-

-

-

-

-

-

-

-

-

-

FSMC_D9

-

-

EVENTOUT

PE13

-

TIM1_CH3

-

-

-

-

-

-

-

-

-

-

FSMC_D10

-

-

EVENTOUT

PE14

-

TIM1_CH4

-

-

-

-

-

-

-

-

-

-

FSMC_D11

-

-

EVENTOUT

PE15

-

TIM1_BKIN

-

-

-

-

-

-

-

-

-

-

FSMC_D12

-

-

EVENTOUT

Table 9. Alternate function mapping (continued)

Port

AF0

AF1

AF2

AF3

AF4

AF5

AF6

AF7

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

SYS

TIM1/2

TIM3/4/5

TIM8/9/10/11

I2C1/2/3

SPI1/SPI2/I2S2/I2S2ext

SPI3/I2Sext/I2S3

USART1/2/3/I2S3ext

UART4/5/USART6

CAN1/2 TIM12/13/14

OTG_FS/OTG_HS

ETH

FSMC/SDIO/OTG_FS

DCMI

Port F

PF0

-

-

-

-

I2C2_SDA

-

-

-

-

-

-

-

FSMC_A0

-

-

EVENTOUT

PF1

-

-

-

-

I2C2_SCL

-

-

-

-

-

-

-

FSMC_A1

-

-

EVENTOUT

PF2

-

-

-

-

I2C2_SMBA

-

-

-

-

-

-

-

FSMC_A2

-

-

EVENTOUT

PF3

-

-

-

-

-

-

-

-

-

-

-

-

FSMC_A3

-

-

EVENTOUT

PF4

-

-

-

-

-

-

-

-

-

-

-

-

FSMC_A4

-

-

EVENTOUT

PF5

-

-

-

-

-

-

-

-

-

-

-

-

FSMC_A5

-

-

EVENTOUT

PF6

-

-

-

TIM10_CH1

-

-

-

-

-

-

-

-

FSMC_NIORD

-

-

EVENTOUT

PF7

-

-

-

TIM11_CH1

-

-

-

-

-

-

-

-

FSMC_NREG

-

-

EVENTOUT

PF8

-

-

-

-

-

-

-

-

-

TIM13_CH1

-

-

FSMC_NIOWR

-

-

EVENTOUT

PF9

-

-

-

-

-

-

-

-

-

TIM14_CH1

-

-

FSMC_CD

-

-

EVENTOUT

PF10

-

-

-

-

-

-

-

-

-

-

-

-

FSMC_INTR

-

-

EVENTOUT

PF11

-

-

-

-

-

-

-

-

-

-

-

-

DCMI_D12

-

EVENTOUT

PF12

-

-

-

-

-

-

-

-

-

-

-

-

FSMC_A6

-

-

EVENTOUT

PF13

-

-

-

-

-

-

-

-

-

-

-

-

FSMC_A7

-

-

EVENTOUT

PF14

-

-

-

-

-

-

-

-

-

-

-

-

FSMC_A8

-

-

EVENTOUT

PF15

-

-

-

-

-

-

-

-

-

-

-

-

FSMC_A9

-

-

EVENTOUT

Port G

PG0

-

-

-

-

-

-

-

-

-

-

-

-

FSMC_A10

-

-

EVENTOUT

PG1

-

-

-

-

-

-

-

-

-

-

-

-

FSMC_A11

-

-

EVENTOUT

PG2

-

-

-

-

-

-

-

-

-

-

-

-

FSMC_A12

-

-

EVENTOUT

PG3

-

-

-

-

-

-

-

-

-

-

-

-

FSMC_A13

-

-

EVENTOUT

PG4

-

-

-

-

-

-

-

-

-

-

-

-

FSMC_A14

-

-

EVENTOUT

PG5

-

-

-

-

-

-

-

-

-

-

-

-

FSMC_A15

-

-

EVENTOUT

PG6

-

-

-

-

-

-

-

-

-

-

-

-

FSMC_INT2

-

-

EVENTOUT

PG7

-

-

-

-

-

-

-

-

USART6_CK

-

-

-

FSMC_INT3

-

-

EVENTOUT

PG8

-

-

-

-

-

-

-

-

USART6_RTS

-

-

ETH_PPS_OUT

-

-

-

EVENTOUT

PG9

-

-

-

-

-

-

-

-

USART6_RX

-

-

-

FSMC_NE2/FSMC_NCE3

-

-

EVENTOUT

PG10

-

-

-

-

-

-

-

-

-

-

-

-

FSMC_NCE4_1/FSMC_NE3

-

-

EVENTOUT

PG11

-

-

-

-

-

-

-

-

-

-

-

ETH_MII_TX_ENETH_RMII_TX_EN

FSMC_NCE4_2

-

-

EVENTOUT

PG12

-

-

-

-

-

-

-

-

USART6_RTS

-

-

-

FSMC_NE4

-

-

EVENTOUT

PG13

-

-

-

-

-

-

-

-

UART6_CTS

-

-

ETH_MII_TXD0ETH_RMII_TXD0

FSMC_A24

-

-

EVENTOUT

PG14

-

-

-

-

-

-

-

-

USART6_TX

-

-

ETH_MII_TXD1ETH_RMII_TXD1

FSMC_A25

-

-

EVENTOUT

PG15

-

-

-

-

-

-

-

-

USART6_CTS

-

-

-

-

DCMI_D13

-

EVENTOUT

Table 9. Alternate function mapping (continued)

Port

AF0

AF1

AF2

AF3

AF4

AF5

AF6

AF7

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

SYS

TIM1/2

TIM3/4/5

TIM8/9/10/11

I2C1/2/3

SPI1/SPI2/I2S2/I2S2ext

SPI3/I2Sext/I2S3

USART1/2/3/I2S3ext

UART4/5/USART6

CAN1/2 TIM12/13/14

OTG_FS/OTG_HS

ETH

FSMC/SDIO/OTG_FS

DCMI

PortH

PH0

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

EVENTOUT

PH1

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

EVENTOUT

PH2

-

-

-

-

-

-

-

-

-

-

-

ETH_MII_CRS

-

-

-

EVENTOUT

PH3

-

-

-

-

-

-

-

-

-

-

-

ETH_MII_COL

-

-

-

EVENTOUT

PH4

-

-

-

-

I2C2_SCL

-

-

-

-

-

OTG_HS_ULPI_NXT

-

-

-

-

EVENTOUT

PH5

-

-

-

-

I2C2_SDA

-

-

-

-

-

-

-

-

-

-

EVENTOUT

PH6

-

-

-

-

I2C2_SMBA

-

-

-

-

TIM12_CH1

-

ETH_MII_RXD2

-

-

-

EVENTOUT

PH7

-

-

-

-

I2C3_SCL

-

-

-

-

-

-

ETH_MII_RXD3

-

-

-

EVENTOUT

PH8

-

-

-

-

I2C3_SDA

-

-

-

-

-

-

-

-

DCMI_HSYNC

-

EVENTOUT

PH9

-

-

-

-

I2C3_SMBA

-

-

-

-

TIM12_CH2

-

-

-

DCMI_D0

-

EVENTOUT

PH10

-

-

TIM5_CH1

-

-

-

-

-

-

-

-

-

-

DCMI_D1

-

EVENTOUT

PH11

-

-

TIM5_CH2

-

-

-

-

-

-

-

-

-

-

DCMI_D2

-

EVENTOUT

PH12

-

-

TIM5_CH3

-

-

-

-

-

-

-

-

-

-

DCMI_D3

-

EVENTOUT

PH13

-

-

-

TIM8_CH1N

-

-

-

-

-

CAN1_TX

-

-

-

-

-

EVENTOUT

PH14

-

-

-

TIM8_CH2N

-

-

-

-

-

-

-

-

-

DCMI_D4

-

EVENTOUT

PH15

-

-

-

TIM8_CH3N

-

-

-

-

-

-

-

-

-

DCMI_D11

-

EVENTOUT

Port I

PI0

-

-

TIM5_CH4

-

-

SPI2_NSS I2S2_WS

-

-

-

-

-

-

-

DCMI_D13

-

EVENTOUT

PI1

-

-

-

-

-

SPI2_SCK I2S2_CK

-

-

-

-

-

-

-

DCMI_D8

-

EVENTOUT

PI2

-

-

-

TIM8_CH4

-

SPI2_MISO

I2S2ext_SD

-

-

-

-

-

-

DCMI_D9

-

EVENTOUT

PI3

-

-

-

TIM8_ETR

-

SPI2_MOSI I2S2_SD

-

-

-

-

-

-

-

DCMI_D10

-

EVENTOUT

PI4

-

-

-

TIM8_BKIN

-

-

-

-

-

-

-

-

-

DCMI_D5

-

EVENTOUT

PI5

-

-

-

TIM8_CH1

-

-

-

-

-

-

-

-

-

DCMI_VSYNC

-

EVENTOUT

PI6

-

-

-

TIM8_CH2

-

-

-

-

-

-

-

-

-

DCMI_D6

-

EVENTOUT

PI7

-

-

-

TIM8_CH3

-

-

-

-

-

-

-

-

-

DCMI_D7

-

EVENTOUT

PI8

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

PI9

-

-

-

-

-

-

-

-

-

CAN1_RX

-

-

-

-

-

EVENTOUT

PI10

-

-

-

-

-

-

-

-

-

-

-

ETH_MII_RX_ER

-

-

-

EVENTOUT

PI11

-

-

-

-

-

-

-

-

-

-

OTG_HS_ULPI_DIR

-

-

-

-

EVENTOUT

5 Memory mapping

The memory map is shown in Figure 18.

Figure 18. STM32F40xxx memory map

flowchart

This diagram illustrates the data structure and memory allocation for an AI system, showing how various memory addresses are reserved, assigned to specific RAM blocks, and then assigned to specific storage modules.

Table 10. Register boundary addresses

Bus	Boundary address	Peripheral
	0xE00F FFFF - 0xFFFF FFFF	Reserved
Cortex-M4	0xE000 0000 - 0xE00F FFFF	Cortex-M4 internal peripherals
	0xA000 1000 - 0xDFFF FFFF	Reserved
AHB3	0xA000 0000 - 0xA000 0FFF	FSMC control register
	0x9000 0000 - 0x9FFF FFFF	FSMC bank 4
	0x8000 0000 - 0x8FFF FFFF	FSMC bank 3
	0x7000 0000 - 0x7FFF FFFF	FSMC bank 2
	0x6000 0000 - 0x6FFF FFFF	FSMC bank 1
	0x5006 0C00- 0x5FFF FFFF	Reserved
AHB2	0x5006 0800 - 0x5006 0BFF	RNG
	0x5005 0400 - 0x5006 07FF	Reserved
	0x5005 0000 - 0x5005 03FF	DCMI
	0x5004 0000- 0x5004 FFFF	Reserved
	0x5000 0000 - 0x5003 FFFF	USB OTG FS
	0x4008 0000- 0x4FFF FFFF	Reserved
AHB1	0x4004 0000 - 0x4007 FFFF	USB OTG HS
	0x4002 9400 - 0x4003 FFFF	Reserved
	0x4002 9000 - 0x4002 93FF	ETHERNET MAC
	0x4002 8C00 - 0x4002 8FFF
	0x4002 8800 - 0x4002 8BFF
	0x4002 8400 - 0x4002 87FF
	0x4002 8000 - 0x4002 83FF
	0x4002 6800 - 0x4002 7FFF	Reserved
	0x4002 6400 - 0x4002 67FF	DMA2
	0x4002 6000 - 0x4002 63FF	DMA1
	0x4002 5000 - 0x4002 5FFF	Reserved
	0x4002 4000 - 0x4002 4FFF	BKPSRAM
	0x4002 3C00 - 0x4002 3FFF	Flash interface register
	0x4002 3800 - 0x4002 3BFF	RCC
	0x4002 3400 - 0x4002 37FF	Reserved
	0x4002 3000 - 0x4002 33FF	CRC
	0x4002 2400 - 0x4002 2FFF	Reserved
	0x4002 2000 - 0x4002 23FF	GPIOI
	0x4002 1C00 - 0x4002 1FFF	GPIOH
	0x4002 1800 - 0x4002 1BFF	GPIOG
	0x4002 1400 - 0x4002 17FF	GPIOF
	0x4002 1000 - 0x4002 13FF	GPIOE
	0x4002 0C00 - 0x4002 0FFF	GPIOD
	0x4002 0800 - 0x4002 0BFF	GPIOC
	0x4002 0400 - 0x4002 07FF	GPIOB
	0x4002 0000 - 0x4002 03FF	GPIOA
	0x4001 5800- 0x4001 FFFF	Reserved
APB2	0x4001 4C00 - 0x4001 57FF	Reserved
	0x4001 4800 - 0x4001 4BFF	TIM11
	0x4001 4400 - 0x4001 47FF	TIM10
	0x4001 4000 - 0x4001 43FF	TIM9
	0x4001 3C00 - 0x4001 3FFF	EXTI
	0x4001 3800 - 0x4001 3BFF	SYSCFG
	0x4001 3400 - 0x4001 37FF	Reserved
	0x4001 3000 - 0x4001 33FF	SPI1
	0x4001 2C00 - 0x4001 2FFF	SDIO
	0x4001 2400 - 0x4001 2BFF	Reserved
	0x4001 2000 - 0x4001 23FF	ADC1 - ADC2 - ADC3
	0x4001 1800 - 0x4001 1FFF	Reserved
	0x4001 1400 - 0x4001 17FF	USART6
	0x4001 1000 - 0x4001 13FF	USART1
	0x4001 0800 - 0x4001 0FFF	Reserved
	0x4001 0400 - 0x4001 07FF	TIM8
	0x4001 0000 - 0x4001 03FF	TIM1
	0x4000 7800 - 0x4000 FFFF	Reserved
APB1	0x4000 7800 - 0x4000 7FFF	Reserved
	0x4000 7400 - 0x4000 77FF	DAC
	0x4000 7000 - 0x4000 73FF	PWR
	0x4000 6C00 - 0x4000 6FFF	Reserved
	0x4000 6800 - 0x4000 6BFF	CAN2
	0x4000 6400 - 0x4000 67FF	CAN1
	0x4000 6000 - 0x4000 63FF	Reserved
	0x4000 5C00 - 0x4000 5FFF	I2C3
	0x4000 5800 - 0x4000 5BFF	I2C2
	0x4000 5400 - 0x4000 57FF	I2C1
	0x4000 5000 - 0x4000 53FF	UART5
	0x4000 4C00 - 0x4000 4FFF	UART4
	0x4000 4800 - 0x4000 4BFF	USART3
	0x4000 4400 - 0x4000 47FF	USART2
	0x4000 4000 - 0x4000 43FF	I2S3ext
	0x4000 3C00 - 0x4000 3FFF	SPI3 / I2S3
	0x4000 3800 - 0x4000 3BFF	SPI2 / I2S2
	0x4000 3400 - 0x4000 37FF	I2S2ext
	0x4000 3000 - 0x4000 33FF	IWDG
	0x4000 2C00 - 0x4000 2FFF	WWDG
	0x4000 2800 - 0x4000 2BFF	RTC & BKP Registers
	0x4000 2400 - 0x4000 27FF	Reserved
	0x4000 2000 - 0x4000 23FF	TIM14
	0x4000 1C00 - 0x4000 1FFF	TIM13
	0x4000 1800 - 0x4000 1BFF	TIM12
	0x4000 1400 - 0x4000 17FF	TIM7
	0x4000 1000 - 0x4000 13FF	TIM6
	0x4000 0C00 - 0x4000 0FFF	TIM5
	0x4000 0800 - 0x4000 0BFF	TIM4
	0x4000 0400 - 0x4000 07FF	TIM3
	0x4000 0000 - 0x4000 03FF	TIM2

6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to V_{SS} .

6.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are evaluated in the worst conditions of ambient temperature, supply voltage, and frequencies by tests in production on 100% of the devices with an ambient temperature at T_{A} = 25\ ^{\circ}C and T_{A} = T_{A}\max (given by the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on T_{A} = 25\;^{\circ}C , V_{DD} = 3.3\;V (for the 1.8\;V \leq V_{DD} \leq 3.6\;V voltage range). They are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 19.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 20.

Figure 19. Pin loading conditions

text_image

C = 50 pF MCU pin

MS19011V2

Figure 20. Pin input voltage

text_image

MCU pin VIN

MS19010V2

6.1.6 Power supply scheme

Figure 21. Power supply scheme

flowchart

This diagram illustrates the architecture and signal flow of a voltage regulator system, showing connections between components like VBAT, GPIOs, ADC, and various logic blocks like VDD, VSS, and VREF.

MS19911V3

1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device.
2. To connect BYPASS_REG and PDR_ON pins, refer to Section 3.16: Voltage regulator and Table 3.15: Power supply supervisor.
3. The two 2.2 \mu F ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF.
4. The 4.7 \mu F ceramic capacitor must be connected to one of the V_{DD} pin.
5. V_{DDA}=V_{DD} and V_{SSA}=V_{SS} .

6.1.7 Current consumption measurement

Figure 22. Current consumption measurement scheme

text_image

IDD_VBAT VBAT IDD VDD VDDA

ai14126

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

Table 11. Voltage characteristics

Symbol	Ratings	Min	Max	Unit
$V_{DD}-V_{SS}$	External main supply voltage (including $V_{DDA}, V_{DD}$ ) $^{(1)}$	-0.3	4.0	V
$V_{IN}$	Input voltage on five-volt tolerant pin $^{(2)}$	$V_{SS}-0.3$	$V_{DD}+4$
	Input voltage on any other pin	$V_{SS}-0.3$	4.0
$|\Delta V_{DDx}|$	Variations between different $V_{DD}$ power pins	-	50	mV
$|V_{SSX}-V_{SS}|$	Variations between all the different ground pins including $V_{REF-}$	-	50
$V_{ESD(HBM)}$	Electrostatic discharge voltage (human body model)	see Section 6.3.14: Absolute maximum ratings (electrical sensitivity)

1. All main power ( V_{DD} , V_{DDA} ) and ground ( V_{SS} , V_{SSA} ) pins must always be connected to the external power supply, in the permitted range.
2. V_{IN} maximum value must always be respected. Refer to Table 12 for the values of the maximum allowed injected current.

Table 12. Current characteristics

Symbol	Ratings	Max.	Unit
$I_{VDD}$	Total current into $V_{DD}$ power lines (source)(1)	240	mA
$I_{VSS}$	Total current out of $V_{SS}$ ground lines (sink)(1)	240
$I_{IO}$	Output current sunk by any I/O and control pin	25
	Output current source by any I/Os and control pin	25
$I_{INJ(PIN)}$ (2)	Injected current on five-volt tolerant I/O(3)	-5/+0
	Injected current on any other pin(4)	±5
$\Sigma I_{INJ(PIN)}$ (4)	Total injected current (sum of all I/O and control pins)(5)	±25

1. All main power ( V_{DD} , V_{DDA} ) and ground ( V_{SS} , V_{SSA} ) pins must always be connected to the external power supply, in the permitted range.
2. Negative injection disturbs the analog performance of the device. See note in Section 6.3.21: 12-bit ADC characteristics.
3. Positive injection is not possible on these I/Os. A negative injection is induced by V_{IN}<V_{SS} . I_{INJ(PIN)} must never be exceeded. Refer to Table 11 for the values of the maximum allowed input voltage.
4. A positive injection is induced by V_{IN}>V_{DD} while a negative injection is induced by V_{IN}<V_{SS} . I_{INJ(PIN)} must never be exceeded. Refer to Table 11 for the values of the maximum allowed input voltage.
5. When several inputs are submitted to a current injection, the maximum \Sigma I_{INJ(PIN)} is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 13. Thermal characteristics

Symbol	Ratings	Value	Unit
$T_{STG}$	Storage temperature range	-65 to +150	°C
$T_J$	Maximum junction temperature	125	°C

6.3 Operating conditions

6.3.1 General operating conditions

Table 14. General operating conditions

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
$f_{HCLK}$	Internal AHB clock frequency	VOS bit in PWR_CR register = 0(1)	0	-	144	MHz
		VOS bit in PWR_CR register= 1	0	-	168
$f_{PCLK1}$	Internal APB1 clock frequency	-	0	-	42
$f_{PCLK2}$	Internal APB2 clock frequency	-	0	-	84
$V_{DD}$	Standard operating voltage	-	1.8(2)	-	3.6	V
$V_{DDA}^{(3)(4)}$	Analog operating voltage(ADC limited to 1.2 M samples)	Must be the same potential as $V_{DD}^{(5)}$	1.8(2)	-	2.4	V
	Analog operating voltage(ADC limited to 1.4 M samples)		2.4	-	3.6
$V_{BAT}$	Backup operating voltage	-	1.65	-	3.6	V
$V_{12}$	Regulator ON:1.2 V internal voltage on $V_{CAP\_1}/V_{CAP\_2}$ pins	VOS bit in PWR_CR register = 0(1)Max frequency 144MHz	1.08	1.14	1.20	V
		VOS bit in PWR_CR register= 1Max frequency 168MHz	1.20	1.26	1.32	V
	Regulator OFF:1.2 V external voltage must be supplied from external regulator on $V_{CAP\_1}/V_{CAP\_2}$ pins	Max frequency 144MHz	1.10	1.14	1.20	V
		Max frequency 168MHz	1.20	1.26	1.30	V
$V_{IN}$	Input voltage on RST and FT pins(6)	2 V ≤ $V_{DD}$ ≤ 3.6 V	-0.3	-	5.5	V
		$V_{DD}$ ≤ 2 V	-0.3	-	5.2
	Input voltage on TTa pins	-	-0.3	-	$V_{DDA}^{+}$ 0.3
	Input voltage on B pin	-	-	-	5.5
$P_{D}$	Power dissipation at $T_{A}$ = 85 °C for suffix 6 or $T_{A}$ = 105 °C for suffix 7(7)	LQFP64	-	-	435	mW
		LQFP100	-	-	465
		LQFP144	-	-	500
		LQFP176	-	-	526
		UFBGA176	-	-	513
		WLCSP90	-	-	543
$T_{A}$	Ambient temperature for 6 suffix version	Maximum power dissipation	-40	-	85	°C
		Low-power dissipation(8)	-40	-	105
	Ambient temperature for 7 suffix version	Maximum power dissipation	-40	-	105	°C
		Low-power dissipation(8)	-40	-	125
$T_{J}$	Junction temperature range	6 suffix version	-40	-	105	°C
		7 suffix version	-40	-	125

1. The average expected gain in power consumption when VOS = 0 compared to VOS = 1 is around 10% for the whole temperature range, when the system clock frequency is between 30 and 144 MHz.
2. V_{DD}/V_{DDA} minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF).
3. When the ADC is used, refer to Table 67: ADC characteristics.
4. If V_{REF+} pin is present, it must respect the following condition: V_{DDA}-V_{REF+} < 1.2 V .
5. It is recommended to power V_{DD} and V_{DDA} from the same source. A maximum difference of 300 mV between V_{DD} and V_{DDA} can be tolerated during power-up and power-down operation.
6. To sustain a voltage higher than V_{DD}+0.3 , the internal pull-up and pull-down resistors must be disabled.
7. If T_{A} is lower, higher P_{D} values are allowed as long as T_{J} does not exceed T_{Jmax} .
8. In low-power dissipation state, T_{A} can be extended to this range as long as T_{J} does not exceed T_{Jmax} .

Table 15. Limitations depending on the operating power supply range

Operating power supply range	ADC operation	Maximum flash memory access frequency with no wait state (fFlashmax)	Maximum flash memory access frequency with wait states(1) (2)	I/O operation	Clock output Frequency on I/O pins	Possible flash memory operations
VDD=1.8 to 2.1 V(3)	Conversion time up to 1.2 Msps	20 MHz(4)	160 MHz with 7 wait states	- Degraded speed performance- No I/O compensation	up to 30 MHz	8-bit erase and program operations only
VDD=2.1 to 2.4 V	Conversion time up to 1.2 Msps	22 MHz	168 MHz with 7 wait states	- Degraded speed performance- No I/O compensation	up to 30 MHz	16-bit erase and program operations
VDD=2.4 to 2.7 V	Conversion time up to 2.4 Msps	24 MHz	168 MHz with 6 wait states	- Degraded speed performance- I/O compensation works	up to 48 MHz	16-bit erase and program operations
VDD=2.7 to 3.6 V(5)	Conversion time up to 2.4 Msps	30 MHz	168 MHz with 5 wait states	- Full-speed operation- I/O compensation works	- up to 60 MHz when VDD=3.0 to 3.6 V- up to 48 MHz when VDD=2.7 to 3.0 V	32-bit erase and program operations

1. It applies only when code executed from flash memory access, when code executed from RAM, no wait state is required.
2. Thanks to the ART accelerator and the 128-bit flash memory, the number of wait states given here does not impact the execution speed from flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state program execution.
3. V_{DD}/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF).
4. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and power.
5. The voltage range for OTG USB FS can drop down to 2.7 V. However it is degraded between 2.7 and 3 V.

6.3.2 V_{CAP\_1}/V_{CAP\_2} external capacitor

Stabilization for the main regulator is achieved by connecting an external capacitor C_{EXT} to the V_{CAP\_1}/V_{CAP\_2} pins. C_{EXT} is specified in Table 16.

Figure 23. External capacitor C_{EXT}

1. Legend: ESR is the equivalent series resistance.

Table 16. V_{CAP\_1}/V_{CAP\_2} operating conditions ^{(1)}

Symbol	Parameter	Conditions
CEXT	Capacitance of external capacitor	2.2 μF
ESR	ESR of external capacitor	< 2 Ω

1. When bypassing the voltage regulator, the two 2.2 \mu F V_{CAP} capacitors are not required and should be replaced by two 100 nF decoupling capacitors.

6.3.3 Operating conditions at power-up / power-down (regulator ON)

Subject to general operating conditions for T_{A} .

Table 17. Operating conditions at power-up / power-down (regulator ON)

Symbol	Parameter	Min	Max	Unit
$t_{VDD}$	$V_{DD}$ rise time rate	20	$\infty$	$\mu s/V$
	$V_{DD}$ fall time rate	20	$\infty$

6.3.4 Operating conditions at power-up / power-down (regulator OFF)

Subject to general operating conditions for T_{A} .

Table 18. Operating conditions at power-up / power-down (regulator OFF) ^{(1)}

Symbol	Parameter	Conditions	Min	Max	Unit
$t_{VDD}$	$V_{DD}$ rise time rate	Power-up	20	∞	μs/V
	$V_{DD}$ fall time rate	Power-down	20	∞
$t_{VCAP}$	$V_{CAP\_1}$ and $V_{CAP\_2}$ rise time rate	Power-up	20	∞
	$V_{CAP\_1}$ and $V_{CAP\_2}$ fall time rate	Power-down	20	∞

1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when V_{DD} reach below minimum value of V_{12} .

6.3.5 Embedded reset and power control block characteristics

The parameters given in Table 19 are derived from tests performed under ambient temperature and V_{DD} supply voltage conditions summarized in Table 14.

Table 19. Embedded reset and power control block characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
$V_{PVD}$	Programmable voltage detector level selection	PLS[2:0]=000 (rising edge)	2.09	2.14	2.19	V
		PLS[2:0]=000 (falling edge)	1.98	2.04	2.08	V
		PLS[2:0]=001 (rising edge)	2.23	2.30	2.37	V
		PLS[2:0]=001 (falling edge)	2.13	2.19	2.25	V
		PLS[2:0]=010 (rising edge)	2.39	2.45	2.51	V
		PLS[2:0]=010 (falling edge)	2.29	2.35	2.39	V
		PLS[2:0]=011 (rising edge)	2.54	2.60	2.65	V
		PLS[2:0]=011 (falling edge)	2.44	2.51	2.56	V
		PLS[2:0]=100 (rising edge)	2.70	2.76	2.82	V
		PLS[2:0]=100 (falling edge)	2.59	2.66	2.71	V
		PLS[2:0]=101 (rising edge)	2.86	2.93	2.99	V
		PLS[2:0]=101 (falling edge)	2.75	2.84	2.92	V
		PLS[2:0]=110 (rising edge)	2.96	3.03	3.10	V
		PLS[2:0]=110 (falling edge)	2.85	2.93	2.99	V
		PLS[2:0]=111 (rising edge)	3.07	3.14	3.21	V
		PLS[2:0]=111 (falling edge)	2.95	3.03	3.09	V
$V_{PVDhyst}^{(1)}$	PVD hysteresis	-	-	100	-	mV
$V_{POR/PDR}$	Power-on/power-down reset threshold	Falling edge	1.60	1.68	1.76	V
		Rising edge	1.64	1.72	1.80	V
$V_{PDRhyst}^{(1)}$	PDR hysteresis	-	-	40	-	mV
$V_{BOR1}$	Brownout level 1 threshold	Falling edge	2.13	2.19	2.24	V
		Rising edge	2.23	2.29	2.33	V
$V_{BOR2}$	Brownout level 2 threshold	Falling edge	2.44	2.50	2.56	V
		Rising edge	2.53	2.59	2.63	V
$V_{BOR3}$	Brownout level 3 threshold	Falling edge	2.75	2.83	2.88	V
		Rising edge	2.85	2.92	2.97	V
$V_{BORhyst}^{(1)}$	BOR hysteresis	-	-	100	-	mV
$T_{RSTTEMPO}^{(1)(2)}$	Reset temporization	-	0.5	1.5	3.0	ms
$I_{RUSH}^{(1)}$	InRush current on voltage regulator power-on (POR or wakeup from Standby)	-	-	160	200	mA
$E_{RUSH}^{(1)}$	InRush energy on voltage regulator power-on (POR or wakeup from Standby)	$V_{DD} = 1.8 \text{ V}, T_{A} = 105 \text{ }^{\circ}\text{C}, I_{RUSH} = 171 \text{ mA for } 31 \mu\text{s}$	-	-	5.4	$\mu\text{C}$

1. Specified by design.
2. The reset temporization is measured from the power-on (POR reset or wakeup from V_{BAT} ) to the instant when first instruction is read by the user application code.

6.3.6 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in Figure 22: Current consumption measurement scheme.

All Run mode current consumption measurements given in this section are performed using a CoreMark-compliant code.

Typical and maximum current consumption

The MCU is placed under the following conditions:

• At startup, all I/O pins are configured as analog inputs by firmware.
• All peripherals are disabled except if it is explicitly mentioned.
• The flash memory access time is adjusted to f_{HCLK} frequency (0 wait state from 0 to 30 MHz, 1 wait state from 30 to 60 MHz, 2 wait states from 60 to 90 MHz, 3 wait states from 90 to 120 MHz, 4 wait states from 120 to 150 MHz, and 5 wait states from 150 to 168 MHz).
• When the peripherals are enabled HCLK is the system clock, f_{PCLK1} = f_{HCLK}/4 , and f_{PCLK2} = f_{HCLK}/2 , except is explicitly mentioned.
• The maximum values are obtained for V_{DD} = 3.6 \, \text{V} and maximum ambient temperature ( T_A ), and the typical values for T_A = 25 \, ^\circ\text{C} and V_{DD} = 3.3 \, \text{V} unless otherwise specified.

Table 20. Typical and maximum current consumption in Run mode, code with data processing running from flash memory (ART accelerator enabled) or RAM (1)

Symbol	Parameter	Conditions	fHCLK	Typ	Max(2)		Unit
				TA=25°C	TA=85°C	TA=105°C
IDD	Supply current in Run mode	External clock(3), all peripherals enabled(4)(5)	168 MHz	87	102	109	mA
			144 MHz	67	80	86
			120 MHz	56	69	75
			90 MHz	44	56	62
			60 MHz	30	42	49
			30 MHz	16	28	35
			25 MHz	12	24	31
			16 MHz(6)	9	20	28
			8 MHz	5	17	24
			4 MHz	3	15	22
			2 MHz	2	14	21
		External clock(3), all peripherals disabled(4)(5)	168 MHz	40	54	61
			144 MHz	31	43	50
			120 MHz	26	38	45
			90 MHz	20	32	39
			60 MHz	14	26	33
			30 MHz	8	20	27
			25 MHz	6	18	25
			16 MHz(6)	5	16	24
			8 MHz	3	15	22
			4 MHz	2	14	21
			2 MHz	2	14	21

1. Code and data processing running from SRAM1 using boot pins.
2. Evaluated by characterization, tested in production at V_{DD} max and f_{HCLK} max with peripherals enabled.
3. External clock is 4 MHz and PLL is on when f_{HCLK} > 25 MHz.
4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part.
5. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered.
6. In this case HCLK = system clock/2.

Table 21. Typical and maximum current consumption in Run mode, code with data processing running from flash memory (ART accelerator disabled)

Symbol	Parameter	Conditions	$f_{HCLK}$	Typ	$Max^{(1)}$		Unit
				$T_A = 25 °C$	$T_A = 85 °C$	$T_A = 105 °C$
$I_{DD}$	Supply current in Run mode	External $clock^{(2)}$ , all peripherals $enabled^{(3)(4)}$	168 MHz	93	109	117	mA
			144 MHz	76	89	96
			120 MHz	67	79	86
			90 MHz	53	65	73
			60 MHz	37	49	56
			30 MHz	20	32	39
			25 MHz	16	27	35
			16 MHz	11	23	30
			8 MHz	6	18	25
			4 MHz	4	16	23
			2 MHz	3	15	22
		External $clock^{(2)}$ , all peripherals $disabled^{(3)(4)}$	168 MHz	46	61	69
			144 MHz	40	52	60
			120 MHz	37	48	56
			90 MHz	30	42	50
			60 MHz	22	33	41
			30 MHz	12	24	31
			25 MHz	10	21	29
			16 MHz	7	19	26
			8 MHz	4	16	23
			4 MHz	3	15	22
			2 MHz	2	14	21

1. Evaluated by characterization, tested in production at V_{DD} max and f_{HCLK} max with peripherals enabled.
2. External clock is 4 MHz and PLL is on when f_{HCLK} > 25 MHz.
3. When analog peripheral blocks such as (ADCs, DACs, HSE, LSE, HSI,LSI) are on, an additional power consumption should be considered.
4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part.

Figure 24. Typical current consumption versus temperature, Run mode, code with data processing running from flash (ART accelerator ON) or RAM, and peripherals OFF

line

CPU Frequency (MHz)	(-45{}^{\circ}C ()mA)	(0{}^{\circ}C ()mA)	(25{}^{\circ}C ()mA)	(55{}^{\circ}C ()mA)	(85{}^{\circ}C ()mA)	(105{}^{\circ}C ()mA)
0	~1.5	~1.5	~1.5	~2.0	~5.0	~8.0
25	~5.5	~5.5	~5.5	~6.0	~9.5	~12.0
168	~37.5	~37.5	~37.5	~39.0	~42.5	~45.0

MS19974V1

Figure 25. Typical current consumption versus temperature, Run mode, code with data processing running from flash (ART accelerator ON) or RAM, and peripherals ON

line

CPU Frequency (MHz)	(-45{}^{\circ}C (mA))	(0{}^{\circ}C (mA))	(25{}^{\circ}C (mA))	(55{}^{\circ}C (mA))	(85{}^{\circ}C (mA))	(105{}^{\circ}C (mA))
0	~2	~2	~2	~5	~6	~8
25	~11	~11	~11	~14	~16	~18
168	~82	~83	~83	~87	~88	~90

MS19975V1

Figure 26. Typical current consumption versus temperature, Run mode, code with data processing running from flash (ART accelerator OFF) or RAM, and peripherals OFF

line

CPU Frequency (MHz)	(-45{}^{\circ}C ()mA)	(0{}^{\circ}C ()mA)	(25{}^{\circ}C ()mA)	(55{}^{\circ}C ()mA)	(85{}^{\circ}C ()mA)	(105{}^{\circ}C ()mA)
0	~1.5	~1.5	~1.5	~2.0	~5.5	~8.0
25	~8.5	~8.5	~9.0	~10.0	~13.0	~15.5
50	~18.0	~18.0	~19.0	~20.0	~23.0	~26.0
75	~27.0	~27.0	~28.0	~29.0	~32.0	~35.0
100	~35.0	~35.0	~36.0	~37.0	~40.0	~43.0
125	~42.0	~42.0	~43.0	~44.0	~47.0	~50.0
150	~48.0	~48.0	~49.0	~50.0	~53.0	~56.0
170	~53.0	~53.0	~54.0	~55.0	~59.0	~62.0

MS19976V1

Figure 27. Typical current consumption versus temperature, Run mode, code with data processing running from flash (ART accelerator OFF) or RAM, and peripherals ON

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CPU Frequency (MHz)	(-45{}^{\circ}C ()mA)	(0{}^{\circ}C ()mA)	(25{}^{\circ}C ()mA)	(55{}^{\circ}C ()mA)	(85{}^{\circ}C ()mA)	(105{}^{\circ}C ()mA)
0	~2	~3	~4	~5	~6	~8
25	~14	~15	~16	~17	~18	~20
168	~88	~89	~90	~91	~95	~98

MS19977V1

Table 22. Typical and maximum current consumption in Sleep mode

Symbol	Parameter	Conditions	$f_{HCLK}$	Typ	$Max^{(1)}$		Unit
				$T_A = 25 °C$	$T_A = 85 °C$	$T_A = 105 °C$
$I_{DD}$	Supply current in Sleep mode	External $clock^{(2)}$ , all peripherals $enabled^{(3)}$	168 MHz	59	77	84	mA
			144 MHz	46	61	67
			120 MHz	38	53	60
			90 MHz	30	44	51
			60 MHz	20	34	41
			30 MHz	11	24	31
			25 MHz	8	21	28
			16 MHz	6	18	25
			8 MHz	3	16	23
			4 MHz	2	15	22
			2 MHz	2	14	21
		External $clock^{(2)}$ , all peripherals disabled	168 MHz	12	27	35
			144 MHz	9	22	29
			120 MHz	8	20	28
			90 MHz	7	19	26
			60 MHz	5	17	24
			30 MHz	3	16	23
			25 MHz	2	15	22
			16 MHz	2	14	21
			8 MHz	1	14	21
			4 MHz	1	13	21
			2 MHz	1	13	21

1. Evaluated by characterization, tested in production at V_{DD} max and f_{HCLK} max with peripherals enabled.
2. External clock is 4 MHz and PLL is on when f_{HCLK} > 25 MHz.
3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register).

Table 23. Typical and maximum current consumptions in Stop mode

Symbol	Parameter	Conditions	Typ	Max			Unit
			$T_A$ =25°C	$T_A$ =25°C	$T_A$ =85°C	$T_A$ =105°C
$I_{DD\_STOP}$	Supply current in Stop mode with main regulator in Run mode	Flash in Stop mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog)	0.45	1.5	11.00	20.00	mA
		Flash in Deep power-down mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog)	0.40	1.5	11.00	20.00
	Supply current in Stop mode with main regulator in Low-power mode	Flash in Stop mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog)	0.31	1.1	8.00	15.00
		Flash in Deep power-down mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog)	0.28	1.1	8.00	15.00

Table 24. Typical and maximum current consumptions in Standby mode

Symbol	Parameter	Conditions	Typ			Max(1)		Unit
			TA=25°C			TA=85°C	TA=105°C
			VDD=1.8 V	VDD=2.4 V	VDD=3.3 V	VDD=3.6 V
IDD_STBY	Supply current in Standby mode	Backup SRAM ON, low-speed oscillator and RTC ON	3.0	3.4	4.0	20	36	μA
		Backup SRAM OFF, low-speed oscillator and RTC ON	2.4	2.7	3.3	16	32
		Backup SRAM ON, RTC OFF	2.4	2.6	3.0	12.5	24.8
		Backup SRAM OFF, RTC OFF	1.7	1.9	2.2	9.8	19.2

1. Evaluated by characterization - not tested in production.

Table 25. Typical and maximum current consumptions in V_{BAT} mode

Symbol	Parameter	Conditions	Typ			Max(1)		Unit
			TA=25°C			TA=85°C	TA=105°C
			VBAT=1.8 V	VBAT=2.4 V	VBAT=3.3 V	VBAT=3.6 V
IDD_VBAT	Backup domain supply current	Backup SRAM ON, low-speed oscillator and RTC ON	1.29	1.42	1.68	6	11	μA
		Backup SRAM OFF, low-speed oscillator and RTC ON	0.62	0.73	0.96	3	5
		Backup SRAM ON, RTC OFF	0.79	0.81	0.86	5	10
		Backup SRAM OFF, RTC OFF	0.10	0.10	0.10	2	4

1. Evaluated by characterization - not tested in production.

Figure 28. Typical V_{BAT} current consumption (LSE and RTC ON/backup RAM OFF)

line

Temperature (({}^{\circ}C))	1.65V	1.8V	2V	2.4V	2.7V	3V	3.3V	3.6V
0	~0.55	~0.62	~0.65	~0.72	~0.85	~0.88	~0.92	~1.05
25	~0.58	~0.65	~0.68	~0.75	~0.88	~0.92	~0.95	~1.08
60	~0.75	~0.82	~0.85	~0.92	~1.05	~1.10	~1.18	~1.30
85	~1.20	~1.28	~1.32	~1.42	~1.55	~1.60	~1.72	~1.88
105	~2.20	~2.30	~2.35	~2.48	~2.60	~2.70	~2.85	~3.02

MS19990V1

Figure 29. Typical V_{BAT} current consumption (LSE and RTC ON/backup RAM ON)

line

Temperature (({}^{\circ}C))	1.65V (µA)	1.8V (µA)	2V (µA)	2.4V (µA)	2.7V (µA)	3V (µA)	3.3V (µA)	3.6V (µA)
0	~1.2	~1.3	~1.3	~1.4	~1.4	~1.5	~1.6	~1.7
25	~1.25	~1.3	~1.3	~1.4	~1.5	~1.6	~1.7	~1.8
60	~1.7	~1.75	~1.8	~1.85	~1.9	~2.0	~2.1	~2.2
85	~2.25	~2.7	~2.8	~2.9	~3.0	~3.1	~3.2	~3.3
105	~4.7	~4.7	~4.7	~4.8	~4.9	~5.1	~5.4	~5.6

MS19991V1

Additional current consumption

The MCU is placed under the following conditions:

• All I/O pins are configured in analog mode.

• The flash memory access time is adjusted to f_{HCLK} frequency.
• The voltage scaling is adjusted to f_{HCLK} frequency as follows:
• Scale 2 for f_{HCLK} \leq 144 MHz
• Scale 1 for 144 MHz < f _{HCLK} ≤ 168 MHz. • The system clock is HCLK, f_{PCLK1} = f_{HCLK}/4 , and f_{PCLK2} = f_{HCLK}/2 . • The HSE crystal clock frequency is 25 MHz.
• T_{A}=25^{\circ}C.

Table 26. Typical current consumption in Run mode, code with data processing running from flash memory, regulator ON (ART accelerator enabled except prefetch), V_{DD} = 1.8 V^{(1)}

Symbol	Parameter	Conditions	$f_{HCLK}$ (MHz)	Typ. at $T_A$ =25 °C	Unit
IDD	Supply current in Run mode	All peripheral disabled	160	36.2	mA
			144	29.3
			120	24.7
			90	19.3
			60	13.4
			30	7.7
			25	6.0

1. When peripherals are enabled, the power consumption corresponding to the analog part of the peripherals (such as ADC or DAC) is not included.

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as input with pull-up or pull-down generate current consumption when the pin is externally held to the opposite level. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 48: I/O static characteristics.

For the output pins, any internal or external pull-up or pull-down and external load must also be considered to estimate the current consumption.

Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption measured previously (see Table 28: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load internal and external connected to the pin:

\mathrm{I} _ {\mathrm{SW}} = \mathrm{V} _ {\mathrm{DD}} \times \mathrm{f} _ {\mathrm{SW}} \times \mathrm{C}

where

I_{SW} is the current sunk by a switching I/O to charge/discharge the capacitive load

V_{DD} is the MCU supply voltage

f_{SW} is the I/O switching frequency

C is the total capacitance seen by the I/O pin: C = C_{INT} + C_{EXT}

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

Table 27. Switching output I/O current consumption

Symbol	Parameter	Conditions(1)	I/O toggling frequency (fSW)	Typ	Unit
IDDIO	I/O switching current	VDD=3.3 V(2)C=CINT	2 MHz	0.02	mA
			8 MHz	0.14
			25 MHz	0.51
			50 MHz	0.86
			60 MHz	1.30
		VDD=3.3 VCEXT=0 pFC=CINT+CEXT+CS	2 MHz	0.10
			8 MHz	0.38
			25 MHz	1.18
			50 MHz	2.47
			60 MHz	2.86
		VDD=3.3 VCEXT=10 pFC=CINT+CEXT+CS	2 MHz	0.17
			8 MHz	0.66
			25 MHz	1.70
			50 MHz	2.65
			60 MHz	3.48
		VDD=3.3 VCEXT=22 pFC=CINT+CEXT+CS	2 MHz	0.23
			8 MHz	0.95
			25 MHz	3.20
			50 MHz	4.69
			60 MHz	8.06
		VDD=3.3 VCEXT=33 pFC=CINT+CEXT+CS	2 MHz	0.30
			8 MHz	1.22
			25 MHz	3.90
			50 MHz	8.82
			60 MHz	_(3)

1. C_{S} is the PCB board capacitance including the pad pin. C_{S} = 7 pF (estimated value).
2. This test is performed by cutting the LQFP package pin (pad removal).
3. At 60 MHz, C maximum load is specified 30 pF.

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 28. The MCU is placed under the following conditions:

• At startup, all I/O pins are configured as analog pins by firmware. • All peripherals are disabled unless otherwise mentioned
• The code is running from flash memory and the flash memory access time is equal to 5 wait states at 168 MHz.
• The code is running from flash memory and the flash memory access time is equal to 4 wait states at 144 MHz, and the power scale mode is set to 2. • The ART accelerator is ON.
• The given value is calculated by measuring the difference of current consumption – with all peripherals clocked off – with one peripheral clocked on (with only the clock applied)
• When the peripherals are enabled: HCLK is the system clock, f_{PCLK1} = f_{HCLK}/4 , and f_{PCLK2} = f_{HCLK}/2 .
• The typical values are obtained for V_{DD} = 3.3 \, \text{V} and T_A = 25 \, ^\circ\text{C} , unless otherwise specified.

Table 28. Peripheral current consumption

Peripheral		$I_{DD}(Typ)^{(1)}$		Unit
		Scale1(up t 168 MHz)	Scale2(up to 144 MHz)
AHB1(up to 168 MHz)	GPIOA	2.70	2.40	μA/MHz
	GPIOB	2.50	2.22
	GPIOC	2.54	2.28
	GPIOD	2.55	2.28
	GPIOE	2.68	2.40
	GPIOF	2.53	2.28
	GPIOG	2.51	2.22
	GPIOH	2.51	2.22
	GPIOI	2.50	2.22
	OTG_HS+ULPI	28.33	25.38
	CRC	0.41	0.40
	BKPSRAM	0.63	0.58
	DMA1	37.44	33.58
	DMA2	37.69	33.93
	ETH_MACETH_MAC_TXETH_MAC_RXETH_MAC_PTP	20.43	18.39
AHB2(up to 168 MHz)	OTG_FS	26.45	26.67	μA/MHz
	DCMI	5.87	5.35
	RNG	1.50	1.67
AHB3(up to 168 MHz)	FSMC	12.46	11.31	μA/MHz
Bus matrix(2)		13.10	11.81	μA/MHz
APB1(up to 42 MHz)	TIM2	16.71	16.50	μA/MHz
	TIM3	12.33	11.94
	TIM4	13.45	12.92
	TIM5	17.14	16.58
	TIM6	2.43	3.06
	TIM7	2.43	2.22
	TIM12	6.62	6.83
	TIM13	5.05	5.47
	TIM14	5.26	5.61
	PWR	1.00	0.56
	USART2	2.69	2.78
	USART3	2.74	2.78
	UART4	3.24	3.33
	UART5	2.69	2.78
	I2C1	2.67	2.50
	I2C2	2.83	2.78
	I2C3	2.81	2.78
	SPI2	2.43	2.22
	SPI3	2.43	2.22
	$I2S2^{(3)}$	2.43	2.22
	$I2S3^{(3)}$	2.26	2.22
	CAN1	5.12	5.56
	CAN2	4.81	5.28
	$DAC^{(4)}$	1.67	1.67
	WWDG	1.00	0.83
APB2(up to 84 MHz)	SDIO	7.08	7.92	μA/MHz
	TIM1	16.79	15.51
	TIM8	17.88	16.53
	TIM9	7.64	7.28
	TIM10	4.89	4.82
	TIM11	5.19	4.82
	$ADC1^{(5)}$	4.67	4.58
	$ADC2^{(5)}$	4.67	4.58
	$ADC3^{(5)}$	4.43	4.44
	SPI1	1.32	1.39
	USART1	3.51	3.72
	USART6	3.55	3.75
	SYSCFG	0.74	0.56

1. When the I/O compensation cell is ON, I_{DD} typical value increases by 0.22 mA.
2. The BusMatrix is automatically active when at least one master is ON.
3. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI_I2SCFGR register.
4. When the DAC is ON and EN1/2 bits are set in DAC_CR register, add an additional power consumption of 0.8 mA per DAC channel for the analog part.
5. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part.

6.3.7 Wakeup time from low-power mode

The wakeup times given in Table 29 is measured on a wakeup phase with a 16 MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode:

• Stop or Standby mode: the clock source is the RC oscillator
• Sleep mode: the clock source is the clock that was set before entering Sleep mode.

All timings are derived from tests performed under ambient temperature and V_{DD} supply voltage conditions summarized in Table 14.

Table 29. Low-power mode wakeup timings

Symbol	Parameter	Min(1)	Typ(1)	Max(1)	Unit
$t_{WUSLEEP}^{(2)}$	Wakeup from Sleep mode	-	5	-	CPU clock cycle
$t_{WUSTOP}^{(2)}$	Wakeup from Stop mode (regulator in Run mode and flash memory in Stop mode)	-	13	-	μs
	Wakeup from Stop mode (regulator in low-power mode and flash memory in Stop mode)	-	17	40
	Wakeup from Stop mode (regulator in Run mode and flash memory in Deep power-down mode)	-	105	-
	Wakeup from Stop mode (regulator in low-power mode and flash memory in Deep power-down mode)	-	110	-
$t_{WUSTDBY}^{(2)(3)}$	Wakeup from Standby mode	260	375	480	μs

1. Evaluated by characterization - not tested in production.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.
3. t_{WUSTDBY} minimum and maximum values are given at 105\ °C and -45\ °C , respectively.

6.3.8 External clock source characteristics

High-speed external user clock generated from an external source

The characteristics given in Table 30 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 14.

Table 30. High-speed external user clock characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
$f_{HSE\_ext}$	External user clock source frequency(1)	-	1	-	50	MHz
$V_{HSEH}$	OSC_IN input pin high level voltage		$0.7V_{DD}$	-	$V_{DD}$	V
$V_{HSEL}$	OSC_IN input pin low level voltage		$V_{SS}$	-	$0.3V_{DD}$
$t_{w(HSE)}$ $t_{w(HSE)}$	OSC_IN high or low time(1)		5	-	-	ns
$t_{r(HSE)}$ $t_{f(HSE)}$	OSC_IN rise or fall time(1)		-	-	10
$C_{in(HSE)}$	OSC_IN input capacitance(1)	-	-	5	-	pF
$DuCy_{(HSE)}$	Duty cycle	-	45	-	55	%
$I_L$	OSC_IN Input leakage current	$V_{SS} \leq V_{IN} \leq V_{DD}$	-	-	±1	μA

1. Specified by design.

Low-speed external user clock generated from an external source

The characteristics given in Table 31 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 14.

Table 31. Low-speed external user clock characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
$f_{LSE\_ext}$	User External clock source frequency(1)	-	-	32.768	1000	kHz
$V_{LSEH}$	OSC32_IN input pin high level voltage		$0.7V_{DD}$	-	$V_{DD}$	V
$V_{LSEL}$	OSC32_IN input pin low level voltage		$V_{SS}$	-	$0.3V_{DD}$
$t_{w(LSE)}$ $t_{f(LSE)}$	OSC32_IN high or low time(1)		450	-	-	ns
$t_{r(LSE)}$ $t_{f(LSE)}$	OSC32_IN rise or fall time(1)		-	-	50
$C_{in(LSE)}$	OSC32_IN input capacitance(1)	-	-	5	-	pF
$DuCy_{(LSE)}$	Duty cycle	-	30	-	70	%
$I_{L}$	OSC32_IN Input leakage current	$V_{SS} \leq V_{IN} \leq V_{DD}$	-	-	±1	μA

1. Specified by design.

Figure 30. High-speed external clock source AC timing diagram

flowchart

graph LR
  A["External clock source"] --> B["fHSE_ext"]
  B --> C["OSC_IN"]
  C --> D["STM32F"]
  D --> E["t_HSE"]
  E --> F["t_HSE_HSE"]
  F --> G["t_W(HSE)"]
  G --> H["t_W(HSE)"]
  H --> I["t_W(HSE)"]
  I --> J["t_HSE"]
  J --> K["t_HSE_HSE"]
  K --> L["t_HSE_HSE_HSE"]
  L --> M["t_HSE_HSE_HSE_HSE"]
  M --> N["t_HSE_HSE_HSE_HSE_HSE"]
  N --> O["t_HSE_HSE_HSE_HSE_HSE_HSE"]
  O --> P["t_HSE_HSE_HSE_HSE_HSE_HSE_HSE"]
  P --> Q["t_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE"]
  Q --> R["t_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE"]
  R --> S["t_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE"]
  S --> T["t_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE"]
  T --> U["t_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE"]
  U --> V["t_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE"]
  V --> W["t_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE_HSE

Figure 31. Low-speed external clock source AC timing diagram

flowchart

This diagram illustrates the timing and signal flow of an external clock source (STM32F) in an oscilloscope system, showing the relationship between the clock signal, switching logic, and external clock output.

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 32. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Table 32. HSE 4-26 MHz oscillator characteristics (1)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
$f_{OSC\_IN}$	Oscillator frequency	-	4	-	26	MHz
$R_F$	Feedback resistor	-	-	200	-	kΩ
$G_m$	Oscillator transconductance	Startup	5	-	-	mA/V
$G_{mcritmax}$	Maximum critical crystal $G_m$		-	-	1
$t_{SU(HSE)}^{(2)}$	Startup time	$V_{DD}$ is stabilized	-	2	-	ms

1. Specified by design.
2. Evaluated by characterization - not tested in production. t_{\mathrm{SU(HSE)}} is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and can vary significantly with the crystal manufacturer

For C_{L1} and C_{L2} , it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 32). C_{L1} and C_{L2} are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C_{L1} and C_{L2} . PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing C_{L1} and C_{L2} .

Note: For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 32. Typical application with an 8 MHz crystal

text_image

Resonator with integrated capacitors CL1 8 MHz resonator CL2 REXT(1) OSC_IN RF OSC_OUT Bias controlled gain STM32F fHSE ai17530

1. R_{EXT} value depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 33. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Table 33. LSE oscillator characteristics ( f_{LSE} = 32.768 kHz) (1)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fOSC_IN	Oscillator frequency	-	-	32.768	-	kHz
RF	Feedback resistor	-	-	18.4	-	MΩ
IDD	LSE current consumption	-	-	-	1	μA
Gm	Oscillator transconductance	Startup	2.8	-	-	μA/V
Gmcritmax	Maximum critical crystal Gm		-	-	0.56
tSU(LSE)(2)	Startup time	VDD is stabilized	-	2	-	s

1. Specified by design.
2. Evaluated by characterization - not tested in production. t_{SU(LSE)} is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer

Note: For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com.

Figure 33. Typical application with a 32.768 kHz crystal

text_image

Resonator with integrated capacitors C_L1 32.768 kHz resonator C_L2 OSC32_IN RF Bias controlled gain OSC32_OUT f_LSE STM32F

ai17531

6.3.9 Internal clock source characteristics

The parameters given in Table 34 and Table 35 are derived from tests performed under ambient temperature and V_{DD} supply voltage conditions summarized in Table 14.

High-speed internal (HSI) RC oscillator

Table 34. HSI oscillator characteristics (1)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
$f_{HSI}$	Frequency	-	-	16	-	MHz
$ACC_{HSI}$	HSI user trimming $step^{(2)}$	-	-	-	1	%
	Accuracy of the HSI oscillator	$T_A = -40 to 105 °C^{(3)}$	-8	-	4.5	%
		$T_A = -10 to 85 °C^{(3)}$	-4	-	4	%
		$T_A = 25 °C^{(4)}$	-1	-	1	%
$t_{su(HSI)}^{(2)}$	HSI oscillator startup time	-	-	2.2	4	μs
$I_{DD(HSI)}^{(2)}$	HSI oscillator power consumption	-	-	60	80	μA

1. V_{DD} = 3.3 V, PLL OFF, T_{A} = -40 to 125 \, ^{\circ}C unless otherwise specified.
2. Specified by design.
3. Evaluated by characterization - not tested in production.
4. Factory calibrated, parts not soldered.

Low-speed internal (LSI) RC oscillator

Table 35. LSI oscillator characteristics (1)

Symbol	Parameter	Min	Typ	Max	Unit
$f_{LSI}^{(2)}$	Frequency	17	32	47	kHz
$t_{su(LSI)}^{(3)}$	LSI oscillator startup time	-	15	40	μs
$I_{DD(LSI)}^{(3)}$	LSI oscillator power consumption	-	0.4	0.6	μA

1. V_{DD} = 3 V, T_{A} = -40 to 105^{\circ}C unless otherwise specified.
2. Evaluated by characterization - not tested in production.
3. Specified by design.

Figure 34. ACC _{LSI} versus temperature

line

Temperature (({}^{\circ}C))	max (%)	avg (%)	min (%)
-45	~39	~3	~-33
-35	~38	~3	~-32
-25	~37	~3	~-31
-15	~36	~3	~-30
-5	~35	~3	~-29
5	~34	~3	~-28
15	~33	~3	~-27
25	~32	~3	~-26
35	~31	~2	~-26
45	~30	~2	~-26
55	~29	~1	~-26
65	~28	~1	~-26
75	~27	~0	~-26
85	~26	~0	~-26
95	~25	~-1	~-26
105	~23	~-2	~-27

MS19013V1

6.3.10 PLL characteristics

The parameters given in Table 36 and Table 37 are derived from tests performed under temperature and V_{DD} supply voltage conditions summarized in Table 14.

Table 36. Main PLL characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
$f_{PLL\_IN}$	PLL input clock(1)	-	0.95(2)	1	2.10	MHz
$f_{PLL\_OUT}$	PLL multiplier output clock	-	24	-	168	MHz
$f_{PLL48\_OUT}$	48 MHz PLL multiplier output clock	-	-	48	75	MHz
$f_{VCO\_OUT}$	PLL VCO output	-	100	-	432	MHz
$t_{LOCK}$	PLL lock time	VCO freq = 100 MHz	75	-	200	μs
		VCO freq = 432 MHz	100	-	300

Table 36. Main PLL characteristics (continued)

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
Jitter(3)	Cycle-to-cycle jitter	System clock 120 MHz	RMS	-	25	-	ps
			peak to peak	-	±150	-
	Period Jitter		RMS	-	15	-
			peak to peak	-	±200	-
	Main clock output (MCO) for RMII Ethernet	Cycle to cycle at 50 MHz on 1000 samples		-	32	-
	Main clock output (MCO) for MII Ethernet	Cycle to cycle at 25 MHz on 1000 samples		-	40	-
	Bit Time CAN jitter	Cycle to cycle at 1 MHz on 1000 samples		-	330	-
$I_{DD(PLL)}^{(4)}$	PLL power consumption on VDD	VCO freq = 100 MHzVCO freq = 432 MHz		0.150.45	-	0.400.75	mA
$I_{DDA(PLL)}^{(4)}$	PLL power consumption on VDDA	VCO freq = 100 MHzVCO freq = 432 MHz		0.300.55	-	0.400.85	mA

1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S.
2. Specified by design.
3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
4. Evaluated by characterization - not tested in production.

Table 37. PLLI2S (audio PLL) characteristics

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
$f_{\text{PLLI2S\_IN}}$	PLLI2S input clock(1)	-		$0.95^{(2)}$	1	2.10	MHz
$f_{\text{PLLI2S\_OUT}}$	PLLI2S multiplier output clock	-		-	-	216	MHz
$f_{\text{VCO\_OUT}}$	PLLI2S VCO output	-		100	-	432	MHz
$t_{\text{LOCK}}$	PLLI2S lock time	VCO freq = 100 MHz		75	-	200	μs
		VCO freq = 432 MHz		100	-	300
$Jitter^{(3)}$	Master $I^2S$ clock jitter	Cycle to cycle at 12.288 MHz on 48KHz period, N=432, R=5	RMS	-	90	-
			peak to peak	-	±280	-	ps
		Average frequency of 12.288 MHz N = 432, R = 5 on 1000 samples		-	90	-	ps
	WS $I^2S$ clock jitter	Cycle to cycle at 48 KHz on 1000 samples		-	400	-	ps
$I_{DD(PLL12S)}^{(4)}$	PLLI2S power consumption on $V_{DD}$	VCO freq = 100 MHz	0.15	-	0.40	mA
		VCO freq = 432 MHz	0.45		0.75
$I_{DDA(PLL12S)}^{(4)}$	PLLI2S power consumption on $V_{DDA}$	VCO freq = 100 MHz	0.30	-	0.40	mA
		VCO freq = 432 MHz	0.55		0.85

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Specified by design.
3. Value given with main PLL running.
4. Evaluated by characterization - not tested in production.

6.3.11 PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 44: EMI characteristics for fHSE = 25 MH and fCPU = 168 MHz). It is available only on the main PLL.

Table 38. SSCG parameters constraint

Symbol	Parameter	Min	Typ	Max(1)	Unit
$f_{Mod}$	Modulation frequency	-	-	10	KHz
md	Peak modulation depth	0.25	-	2	%
MODEPER * INCSTEP	-	-	-	$2^{15}-1$	-

1. Specified by design.

Equation 1

The frequency modulation period (MODEPER) is given by the equation below:

\text {MODEPER} = \text {round} \left[ f _ {\text {PLL\_IN}} / \left(4 \times f _ {\text {Mod}}\right) \right]

f_{PLL\_IN} and f_{Mod} must be expressed in Hz.

As an example:

If f_{PLL\_IN} = 1 MHz, and f_{MOD} = 1 kHz, the modulation depth (MODEPER) is given by equation 1:

\text {MODEPER} = \text {round} \left[ 1 0 ^ {6} / \left(4 \times 1 0 ^ {3}\right) \right] = 2 5 0

Equation 2

Equation 2 allows to calculate the increment step (INCSTEP):

\text {INCSTEP} = \text {round} \left[ \left(\left(2 ^ {1 5} - 1\right) \times \mathrm{md} \times \text {PLLN}\right) / (1 0 0 \times 5 \times \text {MODEPER}) \right]

f_{VCO\_OUT} must be expressed in MHz.

With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz):

\text {INCSTEP} = \text {round} \left[ \left(\left(2 ^ {1 5} - 1\right) \times 2 \times 2 4 0\right) / (1 0 0 \times 5 \times 2 5 0) \right] = 1 2 6 \mathrm{md} (\text {quantitized})\%

An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula:

\mathrm{md} _ {\text {quantized}} \% = (\text {MODEPER} \times \text {INCSTEP} \times 100 \times 5) / ((2 ^ {15} - 1) \times \text {PLLN})

As a result:

\mathrm{md} _ {\text {quantized}} \% = (250 \times 126 \times 100 \times 5) / ((2 ^ {15} - 1) \times 240) = 2.002 \% (\text {peak})

Figure 35 and Figure 36 show the main PLL output clock waveforms in center spread and down spread modes, where:

F0 is fPLL_OUT nominal.

T_{mode} is the modulation period.

md is the modulation depth.

Figure 35. PLL output clock waveforms in center spread mode

line

Time	Frequency (PLL_OUT)
0	F0
tmode	F0
2xtmode	F0

ai17291

Figure 36. PLL output clock waveforms in down spread mode

line

Time	Frequency (PLL_OUT)
0	F0
tmode	F0
2xmode	F0

6.3.12 Memory characteristics

Flash memory

The characteristics are given at T_{A} = -40 to 105\;^{\circ}C unless otherwise specified.

The devices are shipped to customers with the flash memory erased.

Table 39. Flash memory characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
$I_{DD}$	Supply current	Write / Erase 8-bit mode, $V_{DD} = 1.8$ V	-	5	-	mA
		Write / Erase 16-bit mode, $V_{DD} = 2.1$ V	-	8	-
		Write / Erase 32-bit mode, $V_{DD} = 3.3$ V	-	12	-

Table 40. Flash memory programming

Symbol	Parameter	Conditions	$Min^{(1)}$	Typ	$Max^{(1)}$	Unit
$t_{prog}$	Word programming time	Program/erase parallelism (PSIZE) = x 8/16/32	-	16	$100^{(2)}$	μs
$t_{ERASE16KB}$	Sector (16 KB) erase time	Program/erase parallelism (PSIZE) = x 8	-	400	800	ms
		Program/erase parallelism (PSIZE) = x 16	-	300	600
		Program/erase parallelism (PSIZE) = x 32	-	250	500
$t_{ERASE64KB}$	Sector (64 KB) erase time	Program/erase parallelism (PSIZE) = x 8	-	1200	2400	ms
		Program/erase parallelism (PSIZE) = x 16	-	700	1400
		Program/erase parallelism (PSIZE) = x 32	-	550	1100
$t_{ERASE128KB}$	Sector (128 KB) erase time	Program/erase parallelism (PSIZE) = x 8	-	2	4	s
		Program/erase parallelism (PSIZE) = x 16	-	1.3	2.6
		Program/erase parallelism (PSIZE) = x 32	-	1	2
$t_{ME}$	Mass erase time	Program/erase parallelism (PSIZE) = x 8	-	16	32	s
		Program/erase parallelism (PSIZE) = x 16	-	11	22
		Program/erase parallelism (PSIZE) = x 32	-	8	16
$V_{prog}$	Programming voltage	32-bit program operation	2.7	-	3.6	V
		16-bit program operation	2.1	-	3.6	V
		8-bit program operation	1.8	-	3.6	V

1. Evaluated by characterization - not tested in production.
2. The maximum programming time is measured after 100K erase operations.

Table 41. Flash memory programming with V_{PP}

Symbol	Parameter	Conditions	$Min^{(1)}$	Typ	$Max^{(1)}$	Unit
$t_{prog}$	Double word programming	$T_A=0 to +40 °C$ $V_{DD}=3.3 V$ $V_{PP}=8.5 V$	-	16	$100^{(2)}$	μs
$t_{ERASE16KB}$	Sector (16 KB) erase time		-	230	-	ms
$t_{ERASE64KB}$	Sector (64 KB) erase time		-	490	-
$t_{ERASE128KB}$	Sector (128 KB) erase time		-	875	-
$t_{ME}$	Mass erase time		-	6.9	-	s
$V_{prog}$	Programming voltage	-	2.7	-	3.6	V
$V_{PP}$	$V_{PP}$ voltage range	-	7	-	9	V
$I_{PP}$	Minimum current sunk on the $V_{PP}$ pin	-	10	-	-	mA
$t_{VPP}^{(3)}$	Cumulative time during which $V_{PP}$ is applied	-	-	-	1	hour

1. Specified by design.
2. The maximum programming time is measured after 100K erase operations.
3. V_{PP} should only be connected during programming/erasing.

Table 42. Flash memory endurance and data retention

Symbol	Parameter	Conditions	Value	Unit
			Min(1)
NEND	Endurance	TA=-40 to +85 °C (6 suffix versions)	10	kcycles
		TA=-40 to +105 °C (7 suffix versions)
tRET	Data retention	1 kcycle(2) at TA=85 °C	30	Years
		1 kcycle(2) at TA=105 °C	10
		10 kcycles(2) at TA=55 °C	20

1. Evaluated by characterization - not tested in production.
2. Cycling performed over the whole temperature range.

6.3.13 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports), the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A burst of fast transient voltage (positive and negative) is applied to V_{DD} and V_{SS} through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 43. They are based on the EMS levels and classes defined in application note AN1709.

Table 43. EMS characteristics

Symbol	Parameter	Conditions	Level/Class
$V_{FESD}$	Voltage limits to be applied on any I/O pin to induce a functional disturbance	$V_{DD} = 3.3 \text{ V, LQFP176, } T_{A} = +25 \, ^{\circ}\text{C}, f_{HCLK} = 168 \text{ MHz, conforms to IEC 61000-4-2}$	2B
$V_{EFTB}$	Fast transient voltage burst limits to be applied through 100 pF on $V_{DD}$ and $V_{SS}$ pins to induce a functional disturbance	$V_{DD} = 3.3 \text{ V, LQFP176, } T_{A} = +25 \, ^{\circ}\text{C}, f_{HCLK} = 168 \text{ MHz, conforms to IEC 61000-4-2}$	4A

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter

• Unexpected reset • Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading.

Table 44. EMI characteristics for f_{HSE} = 25 MH and f_{CPU} = 168 MHz

Symbol	Parameter	Conditions	Monitored frequency band	Value	Unit
SEMI	Peak(1)	VDD=3.3 V, TA=25 °C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running from flash memory with ART accelerator enabled	0.1 to 30 MHz	32	dBμV
			30 to 130 MHz	25
			130 MHz to 1GHz	29
	Level(2)		0.1 MHz to 2 GHz	4	-
	Peak(1)	VDD=3.3 V, TA=25 °C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running from flash memory with ART accelerator and PLL spread spectrum enabled	0.1 to 30 MHz	19	dBμV
			30 to 130 MHz	16
			130 MHz to 1GHz	18
	Level(2)		0.1 MHz to 2 GHz	3.5	-

1. Refer to AN1709 "EMI radiated test" chapter.
2. Refer to AN1709 "EMI level classification" chapter.

6.3.14 Absolute maximum ratings (electrical sensitivity)

Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard.

Table 45. ESD absolute maximum ratings

Symbol	Ratings	Conditions	Class	Maximum value(1)	Unit
$V_{ESD(HBM)}$	Electrostatic discharge voltage (human body model)	$T_A = +25 °C$ conforming to JESD22-A114	2	2000(2)	V
$V_{ESD(CDM)}$	Electrostatic discharge voltage (charge device model)	$T_A = +25 °C$ conforming to ANSI/ESDA/JEDEC JS-002	II	250

1. Evaluated by characterization - not tested in production.

2. On V_{BAT} pin, V_{ESD(HBM)} is limited to 1000 V.

Static latchup

Two complementary static tests are required on six parts to assess the latchup performance:

• A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latchup standard.

Table 46. Electrical sensitivities

Symbol	Parameter	Conditions	Class
LU	Static latch-up class	$ T_{A}=+105\ ^{\circ}C $ conforming to JESD78A	II level A

6.3.15 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below V_{SS} or above V_{DD} (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of 5 \mu A/+0 \mu A range), or other functional failure (for example reset, oscillator frequency deviation).

Negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection.

The test results are given in Table 47.

Table 47. I/O current injection susceptibility

Symbol	Description	Functional susceptibility		Unit
		Negative injection	Positive injection
$I_{INJ}^{(1)}$	Injected current on BOOT0 pin	-0	NA	mA
	Injected current on NRST pin	-0	NA
	Injected current on PE2, PE3, PE4, PE5, PE6, PI8, PC13, PC14, PC15, PI9, PI10, PI11, PF0, PF1, PF2, PF3, PF4, PF5, PF10, PH0/OSC_IN, PH1/OSC_OUT, PC0, PC1, PC2, PC3, PB6, PB7, PB8, PB9, PE0, PE1, PI4, PI5, PI6, PI7, PDR_ON, BYPASS_REG	-0	NA
	Injected current on all FT pins	-5	NA
	Injected current on any other pin	-5	+5

1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

6.3.16 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under the conditions summarized in Table 14. All I/Os are CMOS and TTL compliant.

Note: For information on GPIO configuration, refer to application note AN4899 "STM32 GPIO configuration for hardware settings and low-power consumption" available from the ST website www.st.com.

Table 48. I/O static characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
$V_{IL}$	FT, TTa and NRST I/O input low level voltage	1.7 V ≤ $V_{DD}$ ≤3.6 V	-	-	$0.3V_{DD}-0.04^{(1)}$	V
			-	-	$0.3V_{DD}^{(2)}$
	BOOT0 I/O input low level voltage	1.75 V ≤ $V_{DD}$ ≤3.6 V-40 °C≤ $T_A$ ≤105 °C	-	-	$0.1V_{DD}-+0.1^{(1)}$
		1.7 V ≤ $V_{DD}$ ≤3.6 V0 °C≤ $T_A$ ≤105 °C	-	-
$V_{IH}$	FT, TTa and NRST I/O input low level voltage	1.7 V ≤ $V_{DD}$ ≤3.6 V	$0.45V_{DD}+0.3^{(1)}$	-	-
			$0.7V_{DD}^{(2)}$	-	-
	BOOT0 I/O input low level voltage	1.75 V ≤ $V_{DD}$ ≤3.6 V-40 °C≤ $T_A$ ≤105 °C	$0.17V_{DD}+0.7^{(1)}$	-	-
		1.7 V ≤ $V_{DD}$ ≤3.6 V0 °C≤ $T_A$ ≤105 °C		-	-
$V_{HYS}$	FT, TTa and NRST I/O input hysteresis		1.7 V ≤ $V_{DD}$ ≤3.6 V	$10\%V_{DD}^{(3)}$	-	-	V
	BOOT0 I/O input hysteresis		1.75 V ≤ $V_{DD}$ ≤3.6 V-40 °C≤ $T_A$ ≤105 °C	0.1	-	-
			1.7 V ≤ $V_{DD}$ ≤3.6 V0 °C≤ $T_A$ ≤105 °C
$I_{Ikg}$	I/O input leakage current (4)		$V_{SS}$ ≤ $V_{IN}$ ≤ $V_{DD}$	-	-	±1	μA
	I/O FT input leakage current (5)		$V_{IN}$ = 5 V	-	-	3
$R_{PU}$	Weak pull-up equivalent resistor(6)	All pins except for PA10 and PB12 (OTG_FS_ID, OTG_HS_ID)	$V_{IN}$ = $V_{SS}$	30	40	50	kΩ
		PA10 and PB12 (OTG_FS_ID, OTG_HS_ID)	-	7	10	14
$R_{PD}$	Weak pull-down equivalent resistor(7)	All pins except for PA10 and PB12	$V_{IN}$ = $V_{DD}$	30	40	50
		PA10 and PB12	-	7	10	14
$C_{IO}^{(8)}$	I/O pin capacitance	-	-	-	5	-	pF

1. Specified by design.
2. Tested in production.
3. With a minimum of 200 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 47: I/O current injection susceptibility
5. To sustain a voltage higher than V_{DD} + 0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 47: I/O current injection susceptibility.
6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimum ( \sim 10% order).
7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the series resistance is minimum (~10% order).
8. Hysteresis voltage between Schmitt trigger switching levels. Evaluated by characterization - not tested in production.

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters.

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed V_{OL}/V_{OH} ) except PC13, PC14 and PC15 which can sink or source up to ±3mA. When using the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF.

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2. In particular:

• The sum of the currents sourced by all the I/Os on V_{DD} , plus the maximum Run consumption of the MCU sourced on V_{DD} , cannot exceed the absolute maximum rating I_{VDD} (see Table 12).
• The sum of the currents sunk by all the I/Os on V_{SS} plus the maximum Run consumption of the MCU sunk on V_{SS} cannot exceed the absolute maximum rating I_{VSS} (see Table 12).

Output voltage levels

Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under ambient temperature and V_{DD} supply voltage conditions summarized in Table 14. All I/Os are CMOS and TTL compliant.

Table 49. Output voltage characteristics ^{(1)}

Symbol	Parameter	Conditions	Min	Max	Unit
$V_{OL}^{(2)}$	Output low level voltage	CMOS port $I_{IO} = +8 mA$ $2.7 V < V_{DD} < 3.6 V$	-	0.4	V
$V_{OH}^{(3)}$	Output high level voltage		$V_{DD}-0.4$	-
$V_{OL}^{(2)}$	Output low level voltage	TTL port $I_{IO} = +8 mA$ $2.7 V < V_{DD} < 3.6 V$	-	0.4	V
$V_{OH}^{(3)}$	Output high level voltage		2.4	-
$V_{OL}^{(2)(4)}$	Output low level voltage	$I_{IO} = +20 mA$ $2.7 V < V_{DD} < 3.6 V$	-	1.3	V
$V_{OH}^{(3)(4)}$	Output high level voltage		$V_{DD}-1.3$	-
$V_{OL}^{(2)(4)}$	Output low level voltage	$I_{IO} = +6 mA$ $2 V < V_{DD} < 2.7 V$	-	0.4	V
$V_{OH}^{(3)(4)}$	Output high level voltage		$V_{DD}-0.4$	-

1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED).
2. The I_{IO} current sunk by the device must always respect the absolute maximum rating specified in Table 12 and the sum of I_{IO} (I/O ports and control pins) must not exceed I_{VSS} .
3. The I_{IO} current sourced by the device must always respect the absolute maximum rating specified in Table 12 and the sum of I_{IO} (I/O ports and control pins) must not exceed I_{VDD} .
4. Evaluated by characterization - not tested in production.

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in Figure 37 and Table 50, respectively.

Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under the ambient temperature and V_{DD} supply voltage conditions summarized in Table 14.

Table 50. I/O AC characteristics ^{(1)(2)}

OSPEEDRy [1:0] bit value(1)	Symbol	Parameter	Conditions	Min	Typ	Max	Unit
00	$f_{max(IO)out}$	Maximum frequency(3)	$C_L=50 pF, V_{DD}>2.70 V$	-	-	4	MHz
			$C_L=50 pF, V_{DD}>1.8 V$	-	-	2
			$C_L=10 pF, V_{DD}>2.70 V$	-	-	8
			$C_L=10 pF, V_{DD}>1.8 V$	-	-	4
	$t_{f(IO)out}/ t_{r(IO)out}$	Output high to low level fall time and output low to high level rise time	$C_L=50 pF, V_{DD}=1.8 V to 3.6 V$	-	-	100	ns
01	$f_{max(IO)out}$	Maximum frequency(3)	$C_L=50 pF, V_{DD}>2.70 V$	-	-	25	MHz
			$C_L=50 pF, V_{DD}>1.8 V$	-	-	12.5
			$C_L=10 pF, V_{DD}>2.70 V$	-	-	$50^{(4)}$
			$C_L=10 pF, V_{DD}>1.8 V$	-	-	20
	$t_{f(IO)out}/ t_{r(IO)out}$	Output high to low level fall time and output low to high level rise time	$C_L=50 pF, V_{DD}>2.7 V$	-	-	10	ns
			$C_L=50 pF, V_{DD}>1.8 V$	-	-	20
			$C_L=10 pF, V_{DD}>2.70 V$	-	-	6
			$C_L=10 pF, V_{DD}>1.8 V$	-	-	10
10	$f_{max(IO)out}$	Maximum frequency(3)	$C_L=40 pF, V_{DD}>2.70 V$	-	-	$50^{(4)}$	MHz
			$C_L=40 pF, V_{DD}>1.8 V$	-	-	25
			$C_L=10 pF, V_{DD}>2.70 V$	-	-	$100^{(4)}$
			$C_L=10 pF, V_{DD}>1.8 V$	-	-	$50^{(4)}$
	$t_{f(IO)out}/ t_{r(IO)out}$	Output high to low level fall time and output low to high level rise time	$C_L=40 pF, V_{DD}>2.70 V$	-	-	6	ns
			$C_L=40 pF, V_{DD}>1.8 V$	-	-	10
			$C_L=10 pF, V_{DD}>2.70 V$	-	-	4
			$C_L=10 pF, V_{DD}>1.8 V$	-	-	6
11	$F_{max(IO)out}$	Maximum frequency(3)	$C_L = 30 \text{ pF}, V_{DD} > 2.70 \text{ V}$	-	-	100(4)	MHz
			$C_L = 30 \text{ pF}, V_{DD} > 1.8 \text{ V}$	-	-	50(4)
			$C_L = 10 \text{ pF}, V_{DD} > 2.70 \text{ V}$	-	-	180(4)
			$C_L = 10 \text{ pF}, V_{DD} > 1.8 \text{ V}$	-	-	100(4)
	$t_{f(IO)out}/t_{r(IO)out}$	Output high to low level fall time and output low to high level rise time	$C_L = 30 \text{ pF}, V_{DD} > 2.70 \text{ V}$	-	-	4	ns
			$C_L = 30 \text{ pF}, V_{DD} > 1.8 \text{ V}$	-	-	6
			$C_L = 10 \text{ pF}, V_{DD} > 2.70 \text{ V}$	-	-	2.5
			$C_L = 10 \text{ pF}, V_{DD} > 1.8 \text{ V}$	-	-	4
-	$t_{EXTIpw}$	Pulse width of external signals detected by the EXTI controller	-	10	-	-	ns

1. Evaluated by characterization - not tested in production.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 37.
4. For maximum frequencies above 50 MHz, the compensation cell should be used.

Figure 37. I/O AC characteristics definition

line

Parameter	Value
Peak-to-Peak (10%)	10%
Peak-to-Peak (50%)	50%
Peak-to-Peak (90%)	90%
Peak-to-Peak (10%)	10%
Peak-to-Peak (50%)	50%
Peak-to-Peak (90%)	90%
T (Time Interval)	tr(IO)out
T (Time Interval)	tf(IO)out

Maximum frequency is achieved with a duty cycle at 45-55% when loaded by the specified capacitance

MSv75936V1

6.3.17 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R_{PU} (see Table 48).

Unless otherwise specified, the parameters given in Table 51 are derived from tests performed under the ambient temperature and V_{DD} supply voltage conditions summarized in Table 14.

Table 51. NRST pin characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
$V_{IL(NRST)}^{(1)}$	NRST Input low level voltage	TTL ports $2.7\ V \leq V_{DD} \leq 3.6\ V$	-	-	0.8	V
$V_{IH(NRST)}^{(1)}$	NRST Input high level voltage		2	-	-
$V_{IL(NRST)}^{(1)}$	NRST Input low level voltage	CMOS ports $1.8\ V \leq V_{DD} \leq 3.6\ V$	-	-	$0.3V_{DD}$
$V_{IH(NRST)}^{(1)}$	NRST Input high level voltage		$0.7V_{DD}$	-	-
$V_{hys(NRST)}$	NRST Schmitt trigger voltage hysteresis	-	-	200	-	mV
$R_{PU}$	Weak pull-up equivalent resistor $^{(2)}$	$V_{IN} = V_{SS}$	30	40	50	kΩ
$V_{F(NRST)}^{(1)}$	NRST Input filtered pulse	-	-	-	100	ns
$V_{NF(NRST)}^{(1)}$	NRST Input not filtered pulse	$V_{DD} > 2.7\ V$	300	-	-	ns
$T_{NRST\_OUT}$	Generated reset pulse duration	Internal reset source	20	-	-	μs

1. Specified by design.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order).

Figure 38. Recommended NRST pin protection

text_image

External reset circuit(1) 0.1 µF NRST(2) VDD RPU Filter Internal Reset STM32F ai14132c

1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V_{\mathrm{IL(NRST)}} max level specified in Table 51. Otherwise the reset is not taken into account by the device.

6.3.18 TIM timer characteristics

The parameters given in Table 52 and Table 53 are specified by design.

Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output).

Table 52. Characteristics of TIMx connected to the APB1 domain ^{(1)}

Symbol	Parameter	Conditions	Min	Max	Unit
$t_{res(TIM)}$	Timer resolution time	AHB/APB1 prescaler distinct from 1, $f_{TIMxCLK}=84 MHz$	1	-	$t_{TIMxCLK}$
			11.9	-	ns
		AHB/APB1 prescaler = 1, $f_{TIMxCLK}=42 MHz$	1	-	$t_{TIMxCLK}$
			23.8	-	ns
$f_{EXT}$	Timer external clock frequency on CH1 to CH4	$f_{TIMxCLK}=84 MHz$ APB1= 42 MHz	0	$f_{TIMxCLK}/2$	MHz
			0	42	MHz
$Res_{TIM}$	Timer resolution		-	16/32	bit
$t_{COUNTER}$	16-bit counter clock period when internal clock is selected		1	65536	$t_{TIMxCLK}$
			0.0119	780	μs
	32-bit counter clock period when internal clock is selected		1	-	$t_{TIMxCLK}$
			0.0119	51130563	μs
$t_{MAX\_COUNT}$	Maximum possible count		-	65536 × 65536	$t_{TIMxCLK}$
			-	51.1	s

1. TIMx is used as a general term to refer to the TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, and TIM12 timers.

Table 53. Characteristics of TIMx connected to the APB2 domain ^{(1)}

Symbol	Parameter	Conditions	Min	Max	Unit
$t_{res(TIM)}$	Timer resolution time	AHB/APB2 prescaler distinct from 1, $f_{TIMxCLK}$ = 168 MHz	1	-	$t_{TIMxCLK}$
			5.95	-	ns
		AHB/APB2 prescaler = 1, $f_{TIMxCLK}$ = 84 MHz	1	-	$t_{TIMxCLK}$
			11.9	-	ns
$f_{EXT}$	Timer external clock frequency on CH1 to CH4	$f_{TIMxCLK}$ = 168 MHz APB2 = 84 MHz	0	$f_{TIMxCLK}/2$	MHz
			0	84	MHz
$Res_{TIM}$	Timer resolution		-	16	bit
$t_{COUNTER}$	16-bit counter clock period when internal clock is selected		1	65536	$t_{TIMxCLK}$
$t_{MAX\_COUNT}$	Maximum possible count		-	32768	$t_{TIMxCLK}$

1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers.

6.3.19 Communications interfaces

I^{2}C interface characteristics

The I ^{2} C interface meets the timings requirements of the I ^{2} C-bus specification and user manual rev. 03 for:

• Standard-mode (Sm): with a bit rate up to 100 kbit/s • Fast-mode (Fm): with a bit rate up to 400 kbit/s.

The I ^{2} C timings requirements are specified by design when the I2C peripheral is properly configured (refer to RM0090 reference manual).

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V_{DD} is disabled, but is still present. Refer to Section 6.3.16: I/O port characteristics for more details on the I^{2}C I/O characteristics.

All I ^{2} C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics:

Table 54. I2C analog filter characteristics ^{(1)}

Symbol	Parameter	Min	Max	Unit
$t_{AF}$	Maximum pulse width of spikes that are suppressed by the analog filter	$50^{(2)}$	$260^{(3)}$	ns

1. Specified by design.
2. Spikes with widths below t_{AF(min)} are filtered.
3. Spikes with widths above t_{AF(max)} are not filtered

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 55 for SPI are derived from tests performed under the ambient temperature, f_{PCLKx} frequency and V_{DD} supply voltage conditions summarized in Table 14 with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 V _{DD}

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 55. SPI dynamic characteristics ^{(1)}

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
$f_{SCK}$	SPI clock frequency	Master mode, SPI1, 2.7V < $V_{DD}$ < 3.6V	-	-	42	MHz
		Slave mode, SPI1, 2.7V < $V_{DD}$ < 3.6V			42
$1/t_{c(SCK)}$		Master mode, SPI1/2/3, 1.7V < $V_{DD}$ < 3.6V	-	-	21
		Slave mode, SPI1/2/3, 1.7V < $V_{DD}$ < 3.6V			21
Duty(SCK)	Duty cycle of SPI clock frequency	Slave mode	30	50	70	%
$t_{w(SCKH)}$	SCK high and low time	Master mode, SPI presc = 2, 2.7V < $V_{DD}$ < 3.6V	$T_{PCLK}-0.5$	$T_{PCLK}$	$T_{PCLK}+0.5$	ns
$t_{w(SCKL)}$		Master mode, SPI presc = 2, 1.7V < $V_{DD}$ < 3.6V	$T_{PCLK}-2$	$T_{PCLK}$	$T_{PCLK}+2$
$t_{su(NSS)}$	NSS setup time	Slave mode, SPI presc = 2	4 x $T_{PCLK}$	-	-
$t_{h(NSS)}$	NSS hold time	Slave mode, SPI presc = 2	2 x $T_{PCLK}$
$t_{su(MI)}$	Data input setup time	Master mode	6.5	-	-
$t_{su(SI)}$		Slave mode	2.5	-	-
$t_{h(MI)}$	Data input hold time	Master mode	2.5	-	-
$t_{h(SI)}$		Slave mode	4	-	-
$t_{a(SO)}^{(2)}$	Data output access time	Slave mode, SPI presc = 2	0	-	4 x $T_{PCLK}$
$t_{dis(SO)}^{(3)}$	Data output disable time	Slave mode, SPI1, 2.7V < $V_{DD}$ < 3.6V	0	-	7.5
		Slave mode, SPI1/2/3 1.7V < $V_{DD}$ < 3.6V	0	-	16.5
$t_{v(SO)}$	Data output valid/hold time	Slave mode (after enable edge), SPI1, 2.7V < $V_{DD}$ < 3.6V	-	11	13
		Slave mode (after enable edge), SPI2/3, 2.7V < $V_{DD}$ < 3.6V	-	12	16.5
$t_{h(SO)}$		Slave mode (after enable edge), SPI1, 1.7V < $V_{DD}$ < 3.6V	-	15.5	19
		Slave mode (after enable edge), SPI2/3, 1.7V < $V_{DD}$ < 3.6V	-	18	20.5
$t_{v(MO)}$	Data output valid time	Master mode (after enable edge), SPI1, 2.7V < $V_{DD}$ < 3.6V	-	-	2.5
		Master mode (after enable edge), SPI1/2/3, 1.7V < $V_{DD}$ < 3.6V	-	-	4.5
$t_{h(MO)}$	Data output hold time	Master mode (after enable edge)	0	-	-

1. Evaluated by characterization - not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.

Figure 39. SPI timing diagram - slave mode and CPHA = 0

flowchart

graph LR
  NSS_input["NSS input"] -->|t_cSCK| SCK_input
  SCK_input -->|t_hNSS| NSS_input
  SCK_input -->|t_wSCKH| SCK_input
  SCK_input -->|t_suNSS| SCK_input
  SCK_input -->|t_aSO| MISO_output
  SCK_input -->|t_wSCKL| MISO_output
  SCK_input -->|t_vSO| MISO_output
  SCK_input -->|t_hSO| MISO_output
  SCK_input -->|t_disSO| MISO_output
  MISO_output -->|First bit OUT| MISO_output
  MISO_output -->|Next bits OUT| MISO_output
  MISO_output -->|Last bit OUT| MISO_output
  MOSI_input -->|First bit IN| MOSI_input
  MOSI_input -->|Next bits IN| MOSI_input
  MOSI_input -->|Last bit IN| MOSI_input

Figure 40. SPI timing diagram - slave mode and CPHA = 1

flowchart

graph LR
  NSS_input["NSS input"] -->|t_cSCK| SCK_input
  SCK_input -->|t_aSO| MISO_output
  SCK_input -->|t_hSCKH| SCK_input
  SCK_input -->|t_hNSS| SCK_input
  SCK_input -->|t_hSO| MISO_output
  SCK_input -->|t_disSO| MISO_output
  MISO_output -->|First bit OUT| SCK_input
  MISO_output -->|First bit IN| MOSI_input
  MISO_output -->|Next bits IN| MOSI_input
  MISO_output -->|Last bit IN| MOSI_input

Figure 41. SPI timing diagram - master mode

flowchart

graph LR
  subgraph High
    NSS_input["NSS input"]
    SCK_output1["SCK output\nCPHA=0, CPOL=0\nCPHA=0, CPOL=1"]
    SCK_output2["SCK output\nCPHA=1, CPOL=0\nCPHA=1, CPOL=1"]
    MISO_input["MISO input"]
    MOSI_output["MOSI output"]
  end

  subgraph Timing Signals
  NSS_input -->|t_cSCK| SCK_output1
  SCK_output1 -->|t_wSCKH| SCK_output2
  SCK_output2 -->|t_wSCKL| SCK_output1
  MISO_input -->|t_suMI| MOSI_output
  MOSI_output -->|t_hMI| MISO_input

    subgraph Timing Signals
  MISO_input -->|First bit IN| NextBitsIn["Next bits_IN"]
  NextBitsIn -->|Next bits IN| LastBitIn["Last bit_IN"]
  NextBitsIn -->|Next bits OUT| MOSI_output
  MOSI_output -->|First bit OUT| NextBitsOut["Next bits_OUT"]
  NextBitsOut -->|Next bits OUT| MOSI_output
  MOSI_output -->|t_vMO| NextBitsOut
  NextBitsOut -->|t_hMO| MOSI_output
  end

I²S interface characteristics

Unless otherwise specified, the parameters given in Table 56 for the i^{2}S interface are derived from tests performed under the ambient temperature, f_{PCLKx} frequency and V_{DD} supply voltage conditions summarized in Table 14, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 V _{DD}

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS).

Table 56. I²S dynamic characteristics(1)

Symbol	Parameter	Conditions	Min	Max	Unit
$f_{MCK}$	$I^2S$ main clock output	-	256 x 8K	$256 \times F_{S}^{(2)}$	MHz
$f_{CK}$	$I^2S$ clock frequency	Master data: 32 bits	-	$64 \times F_{S}$	MHz
		Slave data: 32 bits	-	$64 \times F_{S}$
$D_{CK}$	$I^2S$ clock frequency duty cycle	Slave receiver	30	70	%
$t_{v(WS)}$	WS valid time	Master mode	0	6	ns
$t_{h(WS)}$	WS hold time	Master mode	0	-
$t_{su(WS)}$	WS setup time	Slave mode	1	-
$t_{h(WS)}$	WS hold time	Slave mode	0	-
$t_{su(SD_MR)}$	Data input setup time	Master receiver	7.5	-
$t_{su(SD_SR)}$		Slave receiver	2	-
$t_{h(SD_MR)}$	Data input hold time	Master receiver	0	-
$t_{h(SD_SR)}$		Slave receiver	0	-
$t_{v(SD_ST)}$	Data output valid time	Slave transmitter (after enable edge)	-	27
$t_{h(SD_ST)}$		Master transmitter (after enable edge)	-	20
$t_{v(SD_MT)}$	Data output hold time	Master transmitter (after enable edge)	2.5	-

1. Evaluated by characterization - not tested in production.
2. The maximum value of 256 \times F_{S} is 42 MHz (APB1 maximum frequency).

Note: Refer to the I²S section of RM0090 reference manual for more details on the sampling frequency ( F_{S} ). f_{MCK} , f_{CK} , and D_{CK} values reflect only the digital peripheral behavior. The value of these parameters might be slightly impacted by the source clock accuracy. D_{CK} depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of I2SDIV / (2 x I2SDIV + ODD) and a maximum value of (I2SDIV + ODD) / (2 x I2SDIV + ODD). F_{S} maximum value is supported for each mode/condition.

Figure 42. I²S slave timing diagram (Philips protocol)

flowchart

graph LR
  subgraph CK_Input
    CPOL["CPOL = 0"]
    CPOL2["CPOL = 1"]
  end

  WS_input["WS input"]
  SD_transmit["SD_transmit"]
  SD_receive["SD_receive"]

  CPOL -->|t_cCK| CPOL2
  CPOL2 -->|t_wCKH| CPOL
  CPOL -->|t_wCKL| CPOL2
  CPOL2 -->|t_hWS| WS_input

  WS_input -->|tsuWS| SD_transmit
  SD_transmit -->|tsuSD_SR| SD_receive

  SD_transmit -->|tsuSD_ST| SD_receive
  SD_receive -->|tsuSD_SR| SD_transmit
  SD_receive -->|tsuSD_SR| SD_receive

  SD_transmit -->|MSB_transmit| Bitn_transmit
  SD_transmit -->|MSB receive| Bitn_receive
  SDReceive["SD receive"] -->|MSB receive| BitnReceive["Bitn receive"]
  SDReceive -->|Bitn receive| BSB_receive

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 43. I²S master timing diagram (Philips protocol)(1)

flowchart

graph LR
  subgraph CK_output
    CPOL["CPOL = 0"]
    CPOL2["CPOL = 1"]
    WS_output["WS output"]
    SD_transmit["SD_transmit"]
    SD_receive["SD_receive"]
  end

  subgraph Signal Stream
  CPOL -->|tfCK| CPOL2
  CPOL -->|trCK| CPOL2
  CPOL -->|twCKH| CPOL2
  CPOL -->|tvWS| WS_output
  CPOL -->|twCKL| WS_output
  CPOL -->|thWS| WS_output
  WS_output -->|tvSD_MT| SD_transmit
  WS_output -->|thSD_MT| SD_transmit
  WS_output -->|tvWS| SD_receive
  WS_output -->|thWS| SD_receive
  end

  subgraph Signal Stream
  SD_transmit -->|LSB_transmit2| MSB_transmit
  SD_transmit -->|Bitn_transmit| MSB_transmit
  SD_transmit -->|LSB_transmit| SD_receive
  SD_receive -->|tsuSD_MR| MSB_receive
  SD_receive -->|thSD_MR| MSB_receive
  end

  CPOL -->|tfCK| CPOL2
  CPOL -->|trCK| CPOL2
  CPOL -->|twCKH| CPOL2
  CPOL -->|tvWS| WS_output
  CPOL -->|thWS| WS_output
  MSB_transmit -->|tvSD_MT| SD_transmit
  MSB_transmit -->|Bitn_transmit| SD_transmit
  MSB_transmit -->|LSB_transmit| SD_receive
  MSB_receive -->|tsuSD_MR| SD_receive
  MSB_receive -->|thSD_MR| SD_receive
  SD_receive -->|LSB receive| SD_receive

1. Evaluated by characterization - not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

USB OTG FS characteristics

This interface is present in both the USB OTG HS and USB OTG FS controllers.

Table 57. USB OTG FS startup time

Symbol	Parameter	Max	Unit
$t_{STARTUP}^{(1)}$	USB OTG FS transceiver startup time	1	μs

1. Specified by design.

Table 58. USB OTG FS DC electrical characteristics

Symbol		Parameter	Conditions	Min.(1)	Typ.	Max.(1)	Unit
Input levels	$V_{DD}$	USB OTG FS operating voltage	-	$3.0^{(2)}$	-	3.6	V
	$V_{DI}^{(3)}$	Differential input sensitivity	I(USB_FS_DP/DM,USB_HS_DP/DM)	0.2	-	-	V
	$V_{CM}^{(3)}$	Differential common mode range	Includes $V_{DI}$ range	0.8	-	2.5
	$V_{SE}^{(3)}$	Single ended receiver threshold	-	1.3	-	2.0
Output levels	$V_{OL}$	Static output level low	$R_L$ of 1.5 kΩ to 3.6 $V^{(4)}$	-	-	0.3	V
	$V_{OH}$	Static output level high	$R_L$ of 15 kΩ to $V_{SS}^{(4)}$	2.8	-	3.6
$R_{PD}$		PA11, PA12, PB14, PB15(USB_FS_DP/DM,USB_HS_DP/DM)	$V_{IN}=V_{DD}$	17	21	24	kΩ
		PA9, PB13(OTG_FS_VBUS,OTG_HS_VBUS)		0.65	1.1	2.0
$R_{PU}$		PA12, PB15 (USB_FS_DP,USB_HS_DP)	$V_{IN}=V_{SS}$	1.5	1.8	2.1
		PA9, PB13(OTG_FS_VBUS,OTG_HS_VBUS)	$V_{IN}=V_{SS}$	0.25	0.37	0.55

1. All the voltages are measured from the local ground potential.
2. The STM32F405xx and STM32F407xx USB OTG FS functionality is ensured down to 2.7 V but not the full USB OTG FS electrical characteristics which are degraded in the 2.7-to-3.0 V V_{DD} voltage range.
3. Specified by design.
4. R_{L} is the load connected on the USB OTG FS drivers

Figure 44. USB OTG FS timings: definition of data signal rise and fall time

text_image

Cross over points Differential data lines VCRS Vss tr tr ai14137b

Table 59. USB OTG FS electrical characteristics ^{(1)}

Driver characteristics
Symbol	Parameter	Conditions	Min	Max	Unit
$t_r$	Rise time $^{(2)}$	$C_L$ =50 pF	4	20	ns
$t_f$	Fall time $^{(2)}$	$C_L$ =50 pF	4	20	ns
$t_{rfm}$	Rise/ fall time matching	$t_f/t_f$	90	110	%
$V_{CRS}$	Output signal crossover voltage	-	1.3	2.0	V

1. Specified by design.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0).

USB HS characteristics

Unless otherwise specified, the parameters given in Table 62 for ULPI are derived from tests performed under the ambient temperature, f_{HCLK} frequency summarized in Table 61 and V_{DD} supply voltage conditions summarized in Table 60, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5V_{DD} .

Refer to Section Section 6.3.16: I/O port characteristics for more details on the input/output characteristics.

Table 60. USB HS DC electrical characteristics

Symbol		Parameter	Min.(1)	Max.(1)	Unit
Input level	$V_{DD}$	USB OTG HS operating voltage	2.7	3.6	V

1. All the voltages are measured from the local ground potential.

Table 61. USB HS clock timing parameters ^{(1)}

Parameter		Symbol	Min	Nominal	Max	Unit
$f_{HCLK}$ value to guarantee proper operation of USB HS interface		-	30	-	-	MHz
Frequency (first transition)	8-bit ±10%	$F_{START\_8BIT}$	54	60	66	MHz

Table 61. USB HS clock timing parameters ^{(1)}

Parameter		Symbol	Min	Nominal	Max	Unit
Frequency (steady state) ±500 ppm		$F_{STEADY}$	59.97	60	60.03	MHz
Duty cycle (first transition)	8-bit ±10%	$D_{START\_8BIT}$	40	50	60	%
Duty cycle (steady state) ±500 ppm		$D_{STEADY}$	49.975	50	50.025	%
Time to reach the steady state frequency and duty cycle after the first transition		$T_{STEADY}$	-	-	1.4	ms
Clock startup time after the de-assertion of SuspendM	Peripheral	$T_{START\_DEV}$	-	-	5.6	ms
	Host	$T_{START\_HOST}$	-	-	-
PHY preparation time after the first transition of the input clock		$T_{PREP}$	-	-	-	μs

1. Specified by design.

Table 62. ULPI timing

Parameter	Symbol	Value(1)		Unit
		Min.	Max.
Control in (ULPI_DIR) setup time	$t_{SC}$	-	2.0	ns
Control in (ULPI_NXT) setup time		-	1.5
Control in (ULPI_DIR, ULPI_NXT) hold time	$t_{HC}$	0	-
Data in setup time	$t_{SD}$	-	2.0
Data in hold time	$t_{HD}$	0	-
Control out (ULPI_STP) setup time and hold time	$t_{DC}$	-	9.2
Data out available from clock rising edge	$t_{DD}$	-	10.7

1. V_{DD} = 2.7 V to 3.6 V and T_{A} = -40 to 85 °C.

Figure 45. ULPI timing diagram

text_image

Clock Control In (ULPI_DIR, ULPI_NXT) data In (8-bit) Control out (ULPI_STP) data out (8-bit) ai17361c tSC tHC tSD tHD tDC tDC tDD

Ethernet characteristics

Unless otherwise specified, the parameters given in Table 64, Table 65 and Table 66 for SMI, RMII and MII are derived from tests performed under the ambient temperature, f_{HCLK} frequency summarized in Table 14 and VDD supply voltage conditions summarized in Table 63, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5V_{DD} .

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output characteristics.

Table 63. Ethernet DC electrical characteristics

Symbol		Parameter	Min.(1)	Max.(1)	Unit
Input level	$V_{DD}$	Ethernet operating voltage	2.7	3.6	V

1. All the voltages are measured from the local ground potential.

Table 64 gives the list of Ethernet MAC signals for the SMI (station management interface) and Figure 46 shows the corresponding timing diagram.

Figure 46. Ethernet SMI timing diagram

text_image

ETH_MDC tMDC td(MDIO) ETH_MDIO(O) tsu(MDIO) th(MDIO) ETH_MDIO(I) MS31384V1

Table 64. Dynamic characteristics: Ethernet MAC signals for SMI ^{(1)}

Symbol	Parameter	Min	Typ	Max	Unit
$t_{\text{MDC}}$	MDC cycle time(2.38 MHz)	411	420	425	ns
$T_{\text{d(MDIO)}}$	Write data valid time	6	10	13
$t_{\text{su(MDIO)}}$	Read data setup time	12	-	-
$t_{\text{h(MDIO)}}$	Read data hold time	0	-	-

1. Evaluated by characterization - not tested in production.

Table 65 gives the list of Ethernet MAC signals for the RMII and Figure 47 shows the corresponding timing diagram.

Figure 47. Ethernet RMII timing diagram

text_image

RMII_REF_CLK RMII_TX_EN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRS_DV td(TXEN) td(TXD) tsu(RXD) tsu(CRS) tih(RXD) tih(CRS) ai15667

Table 65. Dynamic characteristics: Ethernet MAC signals for RMII

Symbol	Rating	Min	Typ	Max	Unit
$t_{su(RXD)}$	Receive data setup time	2	-	-	ns
$t_{ih(RXD)}$	Receive data hold time	1	-	-	ns
$t_{su(CRS)}$	Carrier sense set-up time	0.5	-	-	ns
$t_{ih(CRS)}$	Carrier sense hold time	2	-	-	ns
$t_{d(TXEN)}$	Transmit enable valid delay time	8	9.5	11	ns
$t_{d(TXD)}$	Transmit data valid delay time	8.5	10	11.5	ns

Table 66 gives the list of Ethernet MAC signals for MII and Figure 47 shows the corresponding timing diagram.

Figure 48. Ethernet MII timing diagram

flowchart

graph LR
  subgraph MII_RX_CLK
  A["tsu(RXD)"] --> B["tsu(ER)"]
  B --> C["tsu(DV)"]
  C --> D["tih(RXD)"]
  D --> E["tih(ER)"]
  E --> F["tih(DV)"]
  end

  subgraph MII_RXD[3:0]
  G[""MII_RXD[3:0"]"] --> H["MII_RX_DV"]
  H --> I["MII_RX_ER"]
  end

  subgraph MII_TX_CLK
  J["MII_TX_CLK"] --> K["MII_TX_EN"]
  K --> L[""MII_TXD[3:0"]"]
  L --> M["t_d(TXEN)"]
  M --> N["t_d(TXD)"]
  end

  A -.->|t_d(TXEN)| K
  B -.->|t_d(TXD)| N
  C -.->|t_d(TXEN)| K
  D -.->|t_d(TXD)| N
  E -.->|t_d(TXEN)| K
  F -.->|t_d(TXD)| N
  G -.->|t_d(TXEN)| K
  H -.->|t_d(TXD)| N
  I -.->|t_d(TXD)| K
  J -.->|t_d(TXD)| N
  K -.->|t_d(TXD)| N
  L -.->|t_d(TXD)| N
  M -.->|t_d(TXD)| N
  N -.->|t_d(TXD)| K

Table 66. Dynamic characteristics: Ethernet MAC signals for MII ^{(1)}

Symbol	Parameter	Min	Typ	Max	Unit
$t_{su(RXD)}$	Receive data setup time	9	-	-	ns
$t_{ih(RXD)}$	Receive data hold time	10	-	-
$t_{su(DV)}$	Data valid setup time	9	-	-
$t_{ih(DV)}$	Data valid hold time	8	-	-
$t_{su(ER)}$	Error setup time	6	-	-
$t_{ih(ER)}$	Error hold time	8	-	-
$t_{d(TXEN)}$	Transmit enable valid delay time	0	10	14
$t_{d(TXD)}$	Transmit data valid delay time	0	10	15

1. Evaluated by characterization - not tested in production.

6.3.20 CAN (controller area network) interface

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX).

6.3.21 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 67 are derived from tests performed under the ambient temperature, f_{PCLK2} frequency and V_{DDA} supply voltage conditions summarized in Table 14.

Table 67. ADC characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
$V_{DDA}$	Power supply	-	$1.8^{(1)}$	-	3.6	V
$V_{REF+}$	Positive reference voltage	-	$1.8^{(1)(2)(3)}$	-	$V_{DDA}$
$V_{REF-}$	Negative reference voltage	-	-	0	-
$f_{ADC}$	ADC clock frequency	$V_{DDA} = 1.8^{(1)(3)}$ to 2.4 V	0.6	15	18	MHz
		$V_{DDA} = 2.4$ to $3.6$ V $^{(3)}$	0.6	30	36	MHz
$f_{TRIG}^{(4)}$	External trigger frequency	$f_{ADC} = 30$ MHz, 12-bit resolution	-	-	1764	kHz
		-	-	-	17	$1/f_{ADC}$
$V_{AIN}$	Conversion voltage range $^{(5)}$	-	$0$ ( $V_{SSA}$ or $V_{REF-}$ tied to ground)	-	$V_{REF+}$	V
$R_{AIN}^{(4)}$	External input impedance	See Equation 1 for details	-	-	50	$\kappa\Omega$
$R_{ADC}^{(4)(6)}$	Sampling switch resistance	-	-	-	6	$\kappa\Omega$
$C_{ADC}^{(4)}$	Internal sample and hold capacitor	-	-	4	-	pF
$t_{lat}^{(4)}$	Injection trigger conversion latency	$f_{ADC}$ =30 MHz	-	-	0.100	μs
			-	-	$3^{(7)}$	$1/f_{ADC}$
$t_{latr}^{(4)}$	Regular trigger conversion latency	$f_{ADC}$ =30 MHz	-	-	0.067	μs
			-	-	$2^{(7)}$	$1/f_{ADC}$
$t_{S}^{(4)}$	Sampling time	$f_{ADC}$ =30 MHz	0.100	-	16	μs
		-	3	-	480	$1/f_{ADC}$
$t_{STAB}^{(4)}$	Power-up time	-	-	2	3	μs
$t_{CONV}^{(4)}$	Total conversion time (including sampling time)	$f_{ADC}$ =30 MHz12-bit resolution	0.50	-	16.40	μs
		$f_{ADC}$ =30 MHz10-bit resolution	0.43	-	16.34	μs
		$f_{ADC}$ =30 MHz8-bit resolution	0.37	-	16.27	μs
		$f_{ADC}$ =30 MHz6-bit resolution	0.30	-	16.20	μs
		9 to 492 ( $t_{S}$ for sampling +n-bit resolution for successive approximation)				$1/f_{ADC}$
$f_{S}^{(4)}$	Sampling rate( $f_{ADC}$ =30 MHz, and $t_{S}$ =3 ADC cycles)	12-bit resolutionSingle ADC	-	-	2	Msps
		12-bit resolutionInterleave Dual ADC mode	-	-	3.75	Msps
		12-bit resolutionInterleave Triple ADC mode	-	-	6	Msps
$I_{VREF+}^{(4)}$	ADC $V_{REF}$ DC current consumption in conversion mode	-	-	300	500	μA
$I_{VDDA}^{(4)}$	ADC $V_{DDA}$ DC current consumption in conversion mode	-	-	1.6	1.8	mA

1. V_{DD}/V_{DDA} minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF).
2. It is recommended to maintain the voltage difference between V_{REF+} and V_{DDA} below 1.8 V.
3. V_{DDA} - V_{REF+} < 1.2 V.
4. Evaluated by characterization - not tested in production.
5. V_{REF+} is internally connected to V_{DDA} and V_{REF-} is internally connected to V_{SSA} .
6. R_{ADC} maximum value is given for V_{DD}=1.8 V, and minimum value for V_{DD}=3.3 V.
7. For external triggers, a delay of 1/f_{PCLK2} must be added to the latency specified in Table 67.

Equation 1: R_{AIN} max formula

R _ {\mathrm{AIN}} = \frac {(k - 0 . 5)}{f _ {\mathrm{ADC}} \times C _ {\mathrm{ADC}} \times \ln \left(2 ^ {N + 2}\right)} - R _ {\mathrm{ADC}}

The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register.

Table 68. ADC accuracy at f_{ADC} = 30 MHz

Symbol	Parameter	Test conditions	Typ	Max(1)	Unit
ET	Total unadjusted error	$f_{PCLK2} = 60 MHz,$ $f_{ADC} = 30 MHz, R_{AIN} < 10 k\Omega,$ $V_{DDA} = 1.8^{(2)}$ to 3.6 V	±2	±5	LSB
EO	Offset error		±1.5	±2.5
EG	Gain error		±1.5	±3
ED	Differential linearity error		±1	±2
EL	Integral linearity error		±1.5	±3

1. Evaluated by characterization - not tested in production.
2. V_{DD}/V_{DDA} minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF).

Note:

ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for I_{INJ(PIN)} and SI_{INJ(PIN)} in Section 6.3.16 does not affect the ADC accuracy.

Figure 49. ADC accuracy characteristics

line

VREF+ (VDDA)	Output code
(1/2n)*VREF+	1
(2/2n)*VREF+	2
(3/2n)*VREF+	3
(4/2n)*VREF+	4
(5/2n)*VREF+	5
(6/2n)*VREF+	6
(7/2n)*VREF+	7
(2n-3/2n)*VREF+	8
(2n-2/2n)*VREF+	9
(2n-1/2n)*VREF+	10

Figure 50. Typical connection diagram when using the ADC with FT/TT pins featuring analog switch function

text_image

R_{AIN}^{(1)} V_{AIN} C_{parasitic}^{(2)} I_{Ikg}^{(3)} V_{SS} V_{SS} I/O analog switch V_{DDA}^{(4)} V_{REF+}^{(4)} Sampling switch with multiplexing Sample-and-hold ADC converter R_{ADC} Converter C_{ADC} V_{SSA} MSv67871V3

1. Refer to Table 67: ADC characteristics for the values of R_{AIN} , R_{ADC} and C_{ADC} .
2. C_{parasitic} represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (refer to Table 48: I/O static characteristics) A high C_{parasitic} value downgrades conversion accuracy. To remedy this, f_{ADC} should be reduced.
3. Refer to Table 48: I/O static characteristics.
4. Refer to Figure 21: Power supply scheme.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 51 or Figure 52, depending on whether V_{REF+} is connected to V_{DDA} or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 51. Power supply and reference decoupling ( V_{REF+} not connected to V_{DDA} )

text_image

STM32F VREF+ (1) 1 µF // 10 nF VDDA 1 µF // 10 nF VSSA/VREF- (1) ai17535b

1. V_{REF+} and V_{REF-} inputs are both available on UFBGA176. V_{REF+} is also available on LQFP100, LQFP144, and LQFP176. When V_{REF+} and V_{REF-} are not available, they are internally connected to V_{DDA} and V_{SSA} .

Figure 52. Power supply and reference decoupling ( V_{REF+} connected to V_{DDA} )

text_image

STM32F VREF+/VDDA(1) 1 μF // 10 nF VREF-/VSSA (1) ai17536c

1. V_{REF+} and V_{REF-} inputs are both available on UFBGA176. V_{REF+} is also available on LQFP100, LQFP144, and LQFP176. When V_{REF+} and V_{REF-} are not available, they are internally connected to V_{DDA} and V_{SSA} .

6.3.22 Temperature sensor characteristics

Table 69. Temperature sensor characteristics

Symbol	Parameter	Min	Typ	Max	Unit
$T_{L}^{(1)}$	$V_{SENSE}$ linearity with temperature	-	±1	±2	°C
$Avg\_Slope^{(1)}$	Average slope	-	2.5	-	mV/°C
$V_{25}^{(1)}$	Voltage at 25 °C	-	0.76	-	V
$t_{START}^{(2)}$	Startup time	-	6	10	μs
$T_{S\_temp}^{(2)}$	ADC sampling time when reading the temperature (1 °C accuracy)	10	-	-	μs

1. Evaluated by characterization - not tested in production.
2. Specified by design.

Table 70. Temperature sensor calibration values

Symbol	Parameter	Memory address
TS_CAL1	TS ADC raw data acquired at temperature of 30 °C, VDDA=3.3 V	0x1FFF 7A2C - 0x1FFF 7A2D
TS_CAL2	TS ADC raw data acquired at temperature of 110 °C, VDDA=3.3 V	0x1FFF 7A2E - 0x1FFF 7A2F

6.3.23 V_{BAT} monitoring characteristics

Table 71. V_{BAT} monitoring characteristics

Symbol	Parameter	Min	Typ	Max	Unit
R	Resistor bridge for VBAT	-	50	-	KΩ
Q	Ratio on VBAT measurement	-	2	-	-
Er(1)	Error on Q	-1	-	+1	%
TS_vbat(2)(2)	ADC sampling time when reading the VBAT1 mV accuracy	5	-	-	μs

1. Specified by design.
2. Shortest sampling time can be determined in the application by multiple iterations.

6.3.24 Embedded reference voltage

The parameters given in Table 72 are derived from tests performed under ambient temperature and V_{DD} supply voltage conditions summarized in Table 14.

Table 72. Embedded internal reference voltage

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
$V_{REFINT}$	Internal reference voltage	$-40^{\circ}C < T_A < +105^{\circ}C$	1.18	1.21	1.24	V
$T_{S\_vrefint}^{(1)}$	ADC sampling time when reading the internal reference voltage	-	10	-	-	μs
$V_{RERINT\_s}^{(2)}$	Internal reference voltage spread over the temperature range	$V_{DD} = 3 V$	-	3	5	mV
$T_{Coeff}^{(2)}$	Temperature coefficient	-	-	30	50	ppm/°C
$t_{START}^{(2)}$	Startup time	-	-	6	10	μs

1. Shortest sampling time can be determined in the application by multiple iterations.
2. Specified by design.

Table 73. Internal reference voltage calibration values

Symbol	Parameter	Memory address
$V_{REFIN\_CAL}$	Raw data acquired at temperature of 30 °C, $V_{DDA}$ =3.3 V	0x1FFF 7A2A - 0x1FFF 7A2B

6.3.25 DAC electrical characteristics

Table 74. DAC characteristics

Symbol	Parameter	Min	Typ	Max	Unit	Comments
$V_{DDA}$	Analog supply voltage	$1.8^{(1)}$	-	3.6	V	-
$V_{REF+}$	Reference supply voltage	$1.8^{(1)}$	-	3.6	V	$V_{REF+} \leq V_{DDA}$
$V_{SSA}$	Ground	0	-	0	V	-
$R_{LOAD}^{(2)}$	Resistive load with buffer ON	5	-	-	kΩ	-
$R_{O}^{(2)}$	Impedance output with buffer OFF	-	-	15	kΩ	When the buffer is OFF, the Minimum resistive load between DAC_OUT and $V_{SS}$ to have a 1% accuracy is 1.5 MΩ
$C_{LOAD}^{(2)}$	Capacitive load	-	-	50	pF	Maximum capacitive load at DAC_OUT pin (when the buffer is ON).
$DAC\_OUT\ min^{(2)}$	Lower DAC_OUT voltage with buffer ON	0.2	-	-	V	It gives the maximum output excursion of the DAC.It corresponds to 12-bit input code (0x0E0) to (0xF1C) at $V_{REF+} = 3.6$ V and (0x1C7) to (0xE38) at $V_{REF+} = 1.8$ V
$DAC\_OUT\ max^{(2)}$	Higher DAC_OUT voltage with buffer ON	-	-	$V_{DDA} - 0.2$	V
$DAC\_OUT\ min^{(2)}$	Lower DAC_OUT voltage with buffer OFF	-	0.5	-	mV	It gives the maximum output excursion of the DAC.
$DAC\_OUT\ max^{(2)}$	Higher DAC_OUT voltage with buffer OFF	-	-	$V_{REF+} - 1LSB$	V
$I_{VREF+}^{(4)}$	DAC DC $V_{REF}$ current consumption in quiescent mode (Standby mode)	-	170	240	μA	With no load, worst code (0x800) at $V_{REF+} = 3.6$ V in terms of DC consumption on the inputs
		-	50	75		With no load, worst code (0xF1C) at $V_{REF+} = 3.6$ V in terms of DC consumption on the inputs
$I_{DDA}^{(4)}$	DAC DC VDDA current consumption in quiescent mode(3)	-	280	380	μA	With no load, middle code (0x800) on the inputs
		-	475	625	μA	With no load, worst code (0xF1C) at $V_{REF+} = 3.6$ V in terms of DC consumption on the inputs
$DNL^{(4)}$	Differential non linearity Difference between two consecutive code-1LSB)	-	-	±0.5	LSB	Given for the DAC in 10-bit configuration.
		-	-	±2	LSB	Given for the DAC in 12-bit configuration.
$INL^{(4)}$	Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023)	-	-	±1	LSB	Given for the DAC in 10-bit configuration.
		-	-	±4	LSB	Given for the DAC in 12-bit configuration.
Offset(4)	Offset error(difference between measured value at Code (0x800) and the ideal value = VREF+/2)	-	-	±10	mV	Given for the DAC in 12-bit configuration
		-	-	±3	LSB	Given for the DAC in 10-bit at VREF+ = 3.6 V
		-	-	±12	LSB	Given for the DAC in 12-bit at VREF+ = 3.6 V
Gain error(4)	Gain error	-	-	±0.5	%	Given for the DAC in 12-bit configuration
tSETTLING(4)	Settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when DAC_OUT reaches final value ±4LSB	-	3	6	μs	CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
THD(4)	Total Harmonic Distortion Buffer ON	-	-	-	dB	CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
Update rate(2)	Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB)	-	-	1	MS/s	CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
tWAKEUP(4)	Wakeup time from off state (Setting the ENx bit in the DAC Control register)	-	6.5	10	μs	CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones.
PSRR+ (2)	Power supply rejection ratio (to VDDA) (static DC measurement)	-	-67	-40	dB	No RLOAD, CLOAD = 50 pF

1. V_{DD}/V_{DDA} minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF).
2. Specified by design.
3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs.
4. Evaluated by characterization - not tested in production.

Figure 53. 12-bit buffered /non-buffered DAC

flowchart

graph LR
  A["12-bit digital to analog converter"] --> B["Buffer(1)"]
  B --> C["DAC_OUTx"]
  C --> D["RL"]
  D --> E["C_L"]
  E --> F["Ground"]
  F --> G["Output"]
  G --> B

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

6.3.26 FSMC characteristics

Unless otherwise specified, the parameters given in Table 75 to Table 86 for the FSMC interface are derived from tests performed under the ambient temperature, f_{HCLK} frequency and V_{DD} supply voltage conditions summarized in Table 14, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5V_{DD}

Refer to Section Section 6.3.16: I/O port characteristics for more details on the input/output characteristics.

Asynchronous waveforms and timings

Figure 54 through Figure 57 represent asynchronous waveforms and Table 75 through Table 78 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration:

• AddressSetupTime = 1
• AddressHoldTime = 0x1
• DataSetupTime = 0x1 • BusTurnAroundDuration = 0x0

In all timing tables, the T_{HCLK} is the HCLK clock period.

Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

flowchart

graph LR
  FSMC_NE["FSMC_NE"] -->|twNE| t_w(NE)
  FSMC_NOE["FSMC_NOE"] -->|twNOE| t_w(NOE)
  FSMC_NWE["FSMC_NWE"] -->|tvA_NE| t_v(A_NE)
  FSMC_A["25:0"] -->|Address| t_h(A_NOE)
  FSMC_NBL["1:0"] -->|tvBL_NE| t_h(BL_NOE)
  FSMC_D["15:0"] -->|tsuData_NOE| t_h(Data_NOE)
  FSMC_NADV["1"] -->|tvNADV_NE| t_w(NADV)
  FSMC_NADV -->|twNADV| t_w(NADV)
  t_w(NE)_1["t_w(NE)"] --> t_w(NE)
  t_w(NE)_2["t_w(NOE)"] --> t_h(NE_NOE)
  t_h(NE_NOE)_1["t_h(NE_NOE)"] --> t_h(NE)
  t_h(BL_NE)_1["t_v(BL_NE)"] --> t_h(BL_NOE)_1
  t_h(BL_NOE)_1["t_h(BL_NOE)"] --> t_h(Data_NE)
  t_h(Data_NE)_1["t_h(Data_NOE)"] --> t_h(Data_NOE)
  t_h(Data_NE)_2["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data_NE)_3["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data_NE)_4["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data_NE)_5["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data_NE)_6["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data_NE)_7["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data_NE)_8["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data_NE)_9["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data_NE)_10["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data_NE)_11["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data_NE)_12["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_13["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_14["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_15["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_16["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_17["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_18["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_19["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_20["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_21["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_22["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_23["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_24["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_25["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_26["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_27["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_28["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_29["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_30["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_31["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_32["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_33["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_34["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_35["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_36["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_37["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_38["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_39["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_40["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_41["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_42["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_43["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_44["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_45["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_46["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_47["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_48["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_49["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_50["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_51["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_52["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_53["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_54["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_55["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_56["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_57["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_58["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_59["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_60["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_61["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_62["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_63["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_64["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_65["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_66["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_67["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_68["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_69["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_70["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_71["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_72["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_73["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_74["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_75["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_76["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_77["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_78["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_79["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_80["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_81["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_82["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_83["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_84["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_85["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_86["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_87["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_88["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_89["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_90["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_91["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_92["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_93["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_94["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_95["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_96["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_97["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_98["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_99["t_h(Data_NOE)"] --> t_h(Data)
  t_h(Data)_100["t_h(Data_NOE)"] --> t_h(Data)
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:0] --> t_h(D)[15:0]
  t_h(D)[15:

1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings ^{(1)(2)}

Symbol	Parameter	Min	Max	Unit
$t_{w(NE)}$	FSMC_NE low time	$2T_{HCLK}-0.5$	$2T_{HCLK}+1$	ns
$t_{v(NOE_NE)}$	FSMC_NEx low to FSMC_NOE low	0.5	3	ns
$t_{w(NOE)}$	FSMC_NOE low time	$2T_{HCLK}-2$	$2T_{HCLK}+2$	ns
$t_{h(NE_NOE)}$	FSMC_NOE high to FSMC_NE high hold time	0	-	ns
$t_{v(A_NE)}$	FSMC_NEx low to FSMC_A valid	-	4.5	ns
$t_{h(A_NOE)}$	Address hold time after FSMC_NOE high	4	-	ns
$t_{v(BL_NE)}$	FSMC_NEx low to FSMC_BL valid	-	1.5	ns
$t_{h(BL_NOE)}$	FSMC_BL hold time after FSMC_NOE high	0	-	ns
$t_{su(Data_NE)}$	Data to FSMC_NEx high setup time	$T_{HCLK}+4$	-	ns
$t_{su(Data_NOE)}$	Data to FSMC_NOEx high setup time	$T_{HCLK}+4$	-	ns
$t_{h(Data_NOE)}$	Data hold time after FSMC_NOE high	0	-	ns
$t_{h(Data_NE)}$	Data hold time after FSMC_NEx high	0	-	ns
$t_{v(NADV_NE)}$	FSMC_NEx low to FSMC_NADV low	-	2	ns
$t_{w(NADV)}$	FSMC_NADV low time	-	$T_{HCLK}$	ns

1. C_{L} = 30 pF.
2. Evaluated by characterization - not tested in production.

Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

flowchart

graph LR
  FSMC_NEX["FSMC_NEX"] -->|twNE| FSMC_NEX
  FSMC_NOE["FSMC_NOE"] -->|tvNWE_NE| FSMC_NWE
  FSMC_NWE -->|tvA_NE| FSMC_A["25:0"] |
  FSMC_A["25:0"] -->|Address| FSMC_A
  FSMC_A["25:0"] -->|tvBL_NE| FSMC_NBL["1:0"] |
  FSMC_NBL["1:0"] -->|NBL| FSMC_NBL
  FSMC_D["15:0"] -->|tvData_NE| FSMC_D
  FSMC_D["15:0"] -->|tvNADV_NE| FSMC_NADV(1)
  FSMC_NADV(1) -->|twNADV| FSMC_NADV
  FSMC_NWE -->|thNE_NWE| FSMC_NWE
  FSMC_NWE -->|thA_NWE| FSMC_A
  FSMC_NWE -->|thBL_NWE| FSMC_NBL
  FSMC_NWE -->|thData_NWE| FSMC_D
  FSMC_NWE -->|thNE_NWE| FSMC_NWE

ai14990

1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings ^{(1)(2)}

Symbol	Parameter	Min	Max	Unit
$t_{w(NE)}$	FSMC_NE low time	$3T_{HCLK}$	$3T_{HCLK}+4$	ns
$t_{v(NWE\_NE)}$	FSMC_NEx low to FSMC_NWE low	$T_{HCLK}-0.5$	$T_{HCLK}+0.5$	ns
$t_{w(NWE)}$	FSMC_NWE low time	$T_{HCLK}-1$	$T_{HCLK}+2$	ns
$t_{h(NE\_NWE)}$	FSMC_NWE high to FSMC_NE high hold time	$T_{HCLK}-1$	-	ns
$t_{v(A\_NE)}$	FSMC_NEx low to FSMC_A valid	-	0	ns
$t_{h(A\_NWE)}$	Address hold time after FSMC_NWE high	$T_{HCLK}-2$	-	ns
$t_{v(BL\_NE)}$	FSMC_NEx low to FSMC_BL valid	-	1.5	ns
$t_{h(BL\_NWE)}$	FSMC_BL hold time after FSMC_NWE high	$T_{HCLK}-1$	-	ns
$t_{v(Data\_NE)}$	Data to FSMC_NEx low to Data valid	-	$T_{HCLK}+3$	ns
$t_{h(Data\_NWE)}$	Data hold time after FSMC_NWE high	$T_{HCLK}-1$	-	ns
$t_{v(NADV\_NE)}$	FSMC_NEx low to FSMC_NADV low	-	2	ns
$t_{w(NADV)}$	FSMC_NADV low time	-	$T_{HCLK}+0.5$	ns

1. C_{L} = 30 \, pF.
2. Evaluated by characterization - not tested in production.

Figure 56. Asynchronous multiplexed PSRAM/NOR read waveforms

flowchart

graph LR
  FSMC_NE["FSMC_NE"] -->|twNE| FSMC_NE
  FSMC_NE -->|tvNOE_NE| FSMC_NOE
  FSMC_NOE -->|thNE_NOE| FSMC_NOE
  FSMC_NWE -->|tvA_NE| FSMC_A["25:16"]
  FSMC_A["25:16"] -->|Address| FSMC_A["25:16"]
  FSMC_A["25:16"] -->|tvBL_NE| FSMC_NBL["1:0"]
  FSMC_NBL["1:0"] -->|NBL| FSMC_NBL["1:0"]
  FSMC_NBL["1:0"] -->|tvA_NE| FSMC_AD["15:0"]
  FSMC_AD -->|Address| FSMC_AD["15:0"]
  FSMC_AD -->|tvNADV_NE| FSMC_NADV
  FSMC_NADV -->|thAD_NADV| FSMC_NADV
  FSMC_NADV -->|tvNADV| FSMC_NADV
  FSMC_NNE -->|thA_NOE| FSMC_A["25:16"]
  FSMC_A["25:16"] -->|thBL_NOE| FSMC_NBL["1:0"]
  FSMC_NBL["1:0"] -->|thData_NE| FSMC_NBL["1:0"]
  FSMC_NBL["1:0"] -->|tsuData_NE| FSMC_AD["15:0"]
  FSMC_AD -->|tsuData_NOE| FSMC_AD["15:0"]
  FSMC_AD -->|thData_NOE| FSMC_AD["15:0"]
  FSMC_AD -->|thAD_NADV| FSMC_NADV

Table 77. Asynchronous multiplexed PSRAM/NOR read timings ^{(1)(2)}

Symbol	Parameter	Min	Max	Unit
$t_{w(NE)}$	FSMC_NE low time	$3T_{HCLK}-1$	$3T_{HCLK}+1$	ns
$t_{v(NOE\_NE)}$	FSMC_NEx low to FSMC_NOE low	$2T_{HCLK}-0.5$	$2T_{HCLK}+0.5$	ns
$t_{w(NOE)}$	FSMC_NOE low time	$T_{HCLK}-1$	$T_{HCLK}+1$	ns
$t_{h(NE\_NOE)}$	FSMC_NOE high to FSMC_NE high hold time	0	-	ns
$t_{v(A\_NE)}$	FSMC_NEx low to FSMC_A valid	-	3	ns
$t_{v(NADV\_NE)}$	FSMC_NEx low to FSMC_NADV low	1	2	ns
$t_{w(NADV)}$	FSMC_NADV low time	$T_{HCLK}-2$	$T_{HCLK}+1$	ns
$t_{h(AD\_NADV)}$	FSMC_AD(adress) valid hold time after FSMC_NADV high)	$T_{HCLK}$	-	ns
$t_{h(A\_NOE)}$	Address hold time after FSMC_NOE high	$T_{HCLK}-1$	-	ns
$t_{h(BL\_NOE)}$	FSMC_BL time after FSMC_NOE high	0	-	ns
$t_{v(BL\_NE)}$	FSMC_NEx low to FSMC_BL valid	-	2	ns
$t_{su(Data\_NE)}$	Data to FSMC_NEx high setup time	$T_{HCLK}+4$	-	ns
$t_{su(Data\_NOE)}$	Data to FSMC_NOE high setup time	$T_{HCLK}+4$	-	ns
$t_{h(Data\_NE)}$	Data hold time after FSMC_NEx high	0	-	ns
$t_{h(Data\_NOE)}$	Data hold time after FSMC_NOE high	0	-	ns

1. C_{L}=30\ pF.
2. Evaluated by characterization - not tested in production.

Figure 57. Asynchronous multiplexed PSRAM/NOR write waveforms

flowchart

graph LR
  FSMC_NEX["FSMC_NEx"] -->|twNE| NWE["NWE"]
  FSMC_NOE["FSMC_NOE"] -->|tvNWE_NE| NWE
  FSMC_NWE["FSMC_NWE"] -->|tvA_NE| A[""A[25:16"]"]
  FSMC_A[""FSMC_A[25:16"]"] -->|Address| NBL["NBL"]
  FSMC_NBL[""FSMC_NBL[1:0"]"] -->|tvBL_NE| NBL
  FSMC_AD[""FSMC_AD[15:0"]"] -->|tvA_NE| AD["Address"]
  FSMC_NADV["FSMC_NADV"] -->|tvNADV_NE| AD
  FSMC_NWE -->|thNE_NWE| NWE
  FSMC_A[""FSMC_A[25:16"]"] -->|thA_NWE| NWE
  FSMC_A[""FSMC_A[25:16"]"] -->|thBL_NWE| NBL
  FSMC_NBL[""FSMC_NBL[1:0"]"] -->|NBL| NBL
  FSMC_AD[""FSMC_AD[15:0"]"] -->|tvData_NADV| Data["Data"]
  FSMC_NADV["FSMC_NADV"] -->|thAD_NADV| Data
  FSMC_AD[""FSMC_AD[15:0"]"] -->|tvNADV_NE| AD
  FSMC_NADV["FSMC_NADV"] -->|twNADV| AD

Table 78. Asynchronous multiplexed PSRAM/NOR write timings ^{(1)(2)}

Symbol	Parameter	Min	Max	Unit
$t_{w(NE)}$	FSMC_NE low time	$4T_{HCLK}-0.5$	$4T_{HCLK}+3$	ns
$t_{v(NWE\_NE)}$	FSMC_NEx low to FSMC_NWE low	$T_{HCLK}-0.5$	$T_{HCLK}-0.5$	ns
$t_{w(NWE)}$	FSMC_NWE low tim e	$2T_{HCLK}-0.5$	$2T_{HCLK}+3$	ns
$t_{h(NE\_NWE)}$	FSMC_NWE high to FSMC_NE high hold time	$T_{HCLK}$	-	ns
$t_{v(A\_NE)}$	FSMC_NEx low to FSMC_A valid	-	0	ns
$t_{v(NADV\_NE)}$	FSMC_NEx low to FSMC_NADV low	1	2	ns
$t_{w(NADV)}$	FSMC_NADV low time	$T_{HCLK}-2$	$T_{HCLK}+1$	ns
$t_{h(AD\_NADV)}$	FSMC_AD(address) valid hold time after FSMC_NADV high)	$T_{HCLK}-2$	-	ns
$t_{h(A\_NWE)}$	Address hold time after FSMC_NWE high	$T_{HCLK}$	-	ns
$t_{h(BL\_NWE)}$	FSMC_BL hold time after FSMC_NWE high	$T_{HCLK}-2$	-	ns
$t_{v(BL\_NE)}$	FSMC_NEx low to FSMC_BL valid	-	1.5	ns
$t_{v(Data\_NADV)}$	FSMC_NADV high to Data valid	-	$T_{HCLK}-0.5$	ns
$t_{h(Data\_NWE)}$	Data hold time after FSMC_NWE high	$T_{HCLK}$	-	ns

1. C_{L} = 30 pF.

2. Evaluated by characterization - not tested in production.

Synchronous waveforms and timings

Figure 58 through Figure 61 represent synchronous waveforms and Table 80 through Table 82 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration:

• BurstAccessMode = FSMC_BurstAccessMode_Enable; • MemoryType = FSMC_MemoryType_CRAM; • WriteBurst = FSMC_WriteBurst_Enable;
• CLKDivision = 1; (0 is not supported, see the STM32F40xxx/41xxx reference manual)
• DataLatency = 1 for NOR flash; DataLatency = 0 for PSRAM

In all timing tables, the T_{HCLK} is the HCLK clock period (with maximum FSMC_CLK = 60 MHz).

Figure 58. Synchronous multiplexed NOR/PSRAM read timings

flowchart

This diagram illustrates the timing and signal flow of various FSMC communication signals (CLK, NEX, NADV, A, NOE, AD, NWAIT) during a burst operation, including delay and activation states.

Table 79. Synchronous multiplexed NOR/PSRAM read timings ^{(1)(2)}

Symbol	Parameter	Min	Max	Unit
$t_{w(CLK)}$	FSMC_CLK period	$2T_{HCLK}$	-	ns
$t_{d(CLKL-NExL)}$	FSMC_CLK low to FSMC_NEx low (x=0..2)	-	0	ns
$t_{d(CLKL-NExH)}$	FSMC_CLK low to FSMC_NEx high (x= 0...2)	2	-	ns
$t_{d(CLKL-NADVL)}$	FSMC_CLK low to FSMC_NADV low	-	2	ns
$t_{d(CLKL-NADVH)}$	FSMC_CLK low to FSMC_NADV high	2	-	ns
$t_{d(CLKL-AV)}$	FSMC_CLK low to FSMC_Ax valid (x=16...25)	-	0	ns
$t_{d(CLKL-AIV)}$	FSMC_CLK low to FSMC_Ax invalid (x=16...25)	0	-	ns
$t_{d(CLKL-NOEL)}$	FSMC_CLK low to FSMC_NOE low	-	0	ns
$t_{d(CLKL-NOEH)}$	FSMC_CLK low to FSMC_NOE high	2	-	ns
$t_{d(CLKL-ADV)}$	FSMC_CLK low to FSMC_AD[15:0] valid	-	4.5	ns
$t_{d(CLKL-ADIV)}$	FSMC_CLK low to FSMC_AD[15:0] invalid	0	-	ns
$t_{su(ADV-CLKH)}$	FSMC_A/D[15:0] valid data before FSMC_CLK high	6	-	ns
$t_{h(CLKH-ADV)}$	FSMC_A/D[15:0] valid data after FSMC_CLK high	0	-	ns
$t_{su(NWAIT-CLKH)}$	FSMC_NWAIT valid before FSMC_CLK high	4	-	ns
$t_{h(CLKH-NWAIT)}$	FSMC_NWAIT valid after FSMC_CLK high	0	-	ns

1. C_{L} = 30 pF.
2. Evaluated by characterization - not tested in production.

Figure 59. Synchronous multiplexed PSRAM write timings

flowchart

This diagram illustrates the timing and signal flow of various FSMC communication signals (CLK, NEx, NADV, A, NWE, AD, NWAIT, NBL) during a data delay event.

Table 80. Synchronous multiplexed PSRAM write timings ^{(1)(2)}

Symbol	Parameter	Min	Max	Unit
$t_{w(CLK)}$	FSMC_CLK period	$2T_{HCLK}$	-	ns
$t_{d(CLKL-NExL)}$	FSMC_CLK low to FSMC_NEx low (x=0..2)	-	1	ns
$t_{d(CLKL-NExH)}$	FSMC_CLK low to FSMC_NEx high (x= 0...2)	1	-	ns
$t_{d(CLKL-NADVL)}$	FSMC_CLK low to FSMC_NADV low	-	0	ns
$t_{d(CLKL-NADVH)}$	FSMC_CLK low to FSMC_NADV high	0	-	ns
$t_{d(CLKL-AV)}$	FSMC_CLK low to FSMC_Ax valid (x=16...25)	-	0	ns
$t_{d(CLKL-AIV)}$	FSMC_CLK low to FSMC_Ax invalid (x=16...25)	8	-	ns
$t_{d(CLKL-NWEL)}$	FSMC_CLK low to FSMC_NWE low	-	0.5	ns
$t_{d(CLKL-NWEH)}$	FSMC_CLK low to FSMC_NWE high	0	-	ns
$t_{d(CLKL-ADIV)}$	FSMC_CLK low to FSMC_AD[15:0] invalid	0	-	ns
$t_{d(CLKL-DATA)}$	FSMC_A/D[15:0] valid data after FSMC_CLK low	-	3	ns
$t_{d(CLKL-NBLH)}$	FSMC_CLK low to FSMC_NBL high	0	-	ns
$t_{su(NWAIT-CLKH)}$	FSMC_NWAIT valid before FSMC_CLK high	4	-	ns
$t_{h(CLKH-NWAIT)}$	FSMC_NWAIT valid after FSMC_CLK high	0	-	ns

1. C_{L}=30\ pF.
2. Evaluated by characterization - not tested in production.

Figure 60. Synchronous non-multiplexed NOR/PSRAM read timings

flowchart

This diagram illustrates the timing and signal flow of various FSMC communication signals (CLK, NEX, NADV, A, NOE, D, NWAIT) during a burst operation, including delay and timing relationships.

Table 81. Synchronous non-multiplexed NOR/PSRAM read timings ^{(1)(2)}

Symbol	Parameter	Min	Max	Unit
$t_{w(CLK)}$	FSMC_CLK period	$2T_{HCLK}-0.5$	-	ns
$t_{d(CLKL-NExL)}$	FSMC_CLK low to FSMC_NEx low (x=0..2)	-	0.5	ns
$t_{d(CLKL-NExH)}$	FSMC_CLK low to FSMC_NEx high (x=0..2)	0	-	ns
$t_{d(CLKL-NADVL)}$	FSMC_CLK low to FSMC_NADV low	-	2	ns
$t_{d(CLKL-NADVH)}$	FSMC_CLK low to FSMC_NADV high	3	-	ns
$t_{d(CLKL-AV)}$	FSMC_CLK low to FSMC_Ax valid (x=16..25)	-	0	ns
$t_{d(CLKL-AIV)}$	FSMC_CLK low to FSMC_Ax invalid (x=16..25)	2	-	ns
$t_{d(CLKL-NOEL)}$	FSMC_CLK low to FSMC_NOE low	-	0.5	ns
$t_{d(CLKL-NOEH)}$	FSMC_CLK low to FSMC_NOE high	1.5	-	ns
$t_{su(DV-CLKH)}$	FSMC_D[15:0] valid data before FSMC_CLK high	6	-	ns
$t_{h(CLKH-DV)}$	FSMC_D[15:0] valid data after FSMC_CLK high	3	-	ns
$t_{su(NWAIT-CLKH)}$	FSMC_NWAIT valid before FSMC_CLK high	4	-	ns
$t_{h(CLKH-NWAIT)}$	FSMC_NWAIT valid after FSMC_CLK high	0	-	ns

1. C_{L} = 30 pF.
2. Evaluated by characterization - not tested in production.

Figure 61. Synchronous non-multiplexed PSRAM write timings

flowchart

graph LR
  subgraph TimeTiming
  t_w(CLK) --> t_d(CLKL-NExL)
  t_d(CLKL-NExL) --> t_d(CLKL-NADVL)
  t_d(CLKL-NADVL) --> t_d(CLKL-NADVH)
  t_d(CLKL-NADVH) --> t_d(CLKL-AIV)
  t_d(CLKL-AIV) --> t_d(CLKL-NWEH)
  t_d(CLKL-AIV) --> t_d(CLKL-AV)
  t_d(CLKL-AV) --> t_d(CLKL-NWEL)
  t_d(CLKL-NWEL) --> t_d(CLKL-Data)
  t_d(CLKL-Data) --> t_d(CLKL-Data)
  t_d(CLKL-Data) --> D1
  D1 --> D2
  D2 --> D2
  D2 --> D1
  D1 --> t_h(CLKH-NWAITV)
  D2 --> t_h(CLKH-NWAITV)
  D1 --> t_su(NWA)TV-CLKH)
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su(NWA)TV-CLKH
  t_su(NWA)TV-CLKH --> t_su

Table 82. Synchronous non-multiplexed PSRAM write timings ^{(1)(2)}

Symbol	Parameter	Min	Max	Unit
$t_{w(CLK)}$	FSMC_CLK period	$2T_{HCLK}$	-	ns
$t^{d(CLKL-NExL)}$	FSMC_CLK low to FSMC_NEx low (x=0..2)	-	1	ns
$t_{d(CLKL-NExH)}$	FSMC_CLK low to FSMC_NEx high (x= 0...2)	1	-	ns
$t_{d(CLKL-NADVL)}$	FSMC_CLK low to FSMC_NADV low	-	7	ns
$t_{d(CLKL-NADVH)}$	FSMC_CLK low to FSMC_NADV high	6	-	ns
$t_{d(CLKL-AV)}$	FSMC_CLK low to FSMC_Ax valid (x=16...25)	-	0	ns
$t_{d(CLKL-AIV)}$	FSMC_CLK low to FSMC_Ax invalid (x=16...25)	6	-	ns
$t_{d(CLKL-NWEL)}$	FSMC_CLK low to FSMC_NWE low	-	1	ns
$t_{d(CLKL-NWEH)}$	FSMC_CLK low to FSMC_NWE high	2	-	ns
$t_{d(CLKL-Data)}$	FSMC_D[15:0] valid data after FSMC_CLK low	-	3	ns
$t_{d(CLKL-NBLH)}$	FSMC_CLK low to FSMC_NBL high	3	-	ns
$t_{su(NWAIT-CLKH)}$	FSMC_NWAIT valid before FSMC_CLK high	4	-	ns
$t_{h(CLKH-NWAIT)}$	FSMC_NWAIT valid after FSMC_CLK high	0	-	ns

1. C_{L} = 30 pF.
2. Evaluated by characterization - not tested in production.

PC Card/CompactFlash controller waveforms and timings

Figure 62 through Figure 67 represent synchronous waveforms, and Table 83 and Table 84 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration:

• COM.FSMC_SetupTime = 0x04; • COM.FSMC_WaitSetupTime = 0x07; • COM.FSMC_HoldSetupTime = 0x04; • COM.FSMC_HiZSetupTime = 0x00;

• ATT.FSMC_SetupTime = 0x04;
• ATT.FSMC_WaitSetupTime = 0x07; • ATT.FSMC_HoldSetupTime = 0x04; • ATT.FSMC_HiZSetupTime = 0x00; • IO.FSMC_SetupTime = 0x04; • IO.FSMC_WaitSetupTime = 0x07; • IO.FSMC_HoldSetupTime = 0x04; • IO.FSMC_HiZSetupTime = 0x00;
• TCLRSetupTime = 0;
• TARSetupTime = 0.

In all timing tables, the T_{HCLK} is the HCLK clock period.

Figure 62. PC Card/CompactFlash controller waveforms for common memory read access

text_image

FSMC_NCE4_2(1) FSMC_NCE4_1 t_v(NCEx-A) t_h(NCEx-AI) FSMC_A[10:0] t_d(NREG-NCEx) t_d(NIORD-NCEx) t_h(NCEx-NREG) t_h(NCEx-NIORD) t_h(NCEx-NIOWR) FSMC_NREG FSMC_NIOWR FSMC_NIORD FSMC_NWE t_d(NCE4_1-NOE) t_w(NOE) FSMC_NOE t_su(D-NOE) t_h(NOE-D) FSMC_D[15:0] ai14895b

1. FSMC_NCE4_2 remains high (inactive during 8-bit access.

Figure 63. PC Card/CompactFlash controller waveforms for common memory write access

flowchart

This diagram illustrates the timing relationships and signal transitions between various FSMC and SMC control signals, including High, NREG, NIORD, NWE, and D signals.

Figure 64. PC Card/CompactFlash controller waveforms for attribute memory read access

flowchart

This diagram illustrates the timing relationships and signal transitions between various FSMC communication signals (NCE4, NIOWR, NREG, NWE, NOE, D) over time.

1. Only data bits 0...7 are read (bits 8...15 are disregarded).

Figure 65. PC Card/CompactFlash controller waveforms for attribute memory write access

flowchart

graph LR
  FSMC_NCE4_1["FSMC_NCE4_1"] -->|High| FSMC_NCE4_2["FSMC_NCE4_2"]
  FSMC_NCE4_2 -->|High| FSMC_A["10:0"]["FSMC_A["10:0"]"]
  FSMC_NCE4_2 -->|High| FSMC_NIOWR["FSMC_NIOWR\nFSMC_NIORD"]
  FSMC_NCE4_2 -->|High| FSMC_NREG["FSMC_NREG"]
  FSMC_NCE4_2 -->|High| FSMC_NWE["FSMC_NWE"]
  FSMC_NCE4_2 -->|High| FSMC_NOE["FSMC_NOE"]
  FSMC_NCE4_2 -->|High| FSMC_D["7:0"](1)["FSMC_D["7:0"](1)"]
  FSMC_A["10:0"] -->|High| FSMC_A["10:0"] -->|tvNCE4_1-A| FSMC_A["10:0"] -->|thNCE4_1-AI| FSMC_A["10:0"] -->|thNCE4_1-AI| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A["10:0"] -->|thNCE4_1-NREG| FSMC_A[

1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z).

Figure 66. PC Card/CompactFlash controller waveforms for I/O space read access

text_image

FSMC_NCE4_1 FSMC_NCE4_2 t_v(NCEx-A) t_h(NCE4_1-AI) FSMC_A[10:0] FSMC_NREG FSMC_NWE FSMC_NOE FSMC_NIOWR t_d(NIORD-NCE4_1) t_w(NIORD) FSMC_NIORD t_su(D-NIORD) t_d(NIORD-D) FSMC_D[15:0] ai14899B

Figure 67. PC Card/CompactFlash controller waveforms for I/O space write access

text_image

FSMC_NCE4_1 FSMC_NCE4_2 t_v(NCEx-A) t_h(NCE4_1-AI) FSMC_A[10:0] FSMC_NREG FSMC_NWE FSMC_NOE FSMC_NIORD t_d(NCE4_1-NIOWR) t_w(NIOWR) FSMC_NIOWR ATTxHIZ =1 t_v(NIOWR-D) t_h(NIOWR-D) FSMC_D[15:0] ai14900c

Table 83. Switching characteristics for PC Card/CF read and write cycles in attribute/common space ^{(1)(2)}

Symbol	Parameter	Min	Max	Unit
$t_{v(NCEx-A)}$	FSMC_Ncex low to FSMC_Ay valid	-	0	ns
$t_{h(NCEx_AI)}$	FSMC_NCEx high to FSMC_Ax invalid	4	-	ns
$t_{d(NREG-NCEx)}$	FSMC_NCEx low to FSMC_NREG valid	-	3.5	ns
$t_{h(NCEx-NREG)}$	FSMC_NCEx high to FSMC_NREG invalid	$T_{HCLK}+4$	-	ns
$t_{d(NCEx-NWE)}$	FSMC_NCEx low to FSMC_NWE low	-	$5T_{HCLK}+0.5$	ns
$t_{d(NCEx-NOE)}$	FSMC_NCEx low to FSMC_NOE low	-	$5T_{HCLK}+0.5$	ns
$t_{w(NOE)}$	FSMC_NOE low width	$8T_{HCLK}-1$	$8T_{HCLK}+1$	ns
$t_{d(NOE_NCEx)}$	FSMC_NOE high to FSMC_NCEx high	$5T_{HCLK}+2.5$	-	ns
$t_{su(D-NOE)}$	FSMC_D[15:0] valid data before FSMC_NOE high	4.5	-	ns
$t_{h(NOE-D)}$	FSMC_NOE high to FSMC_D[15:0] invalid	3	-	ns
$t_{w(NWE)}$	FSMC_NWE low width	$8T_{HCLK}-0.5$	$8T_{HCLK}+3$	ns
$t_{d(NWE_NCEx)}$	FSMC_NWE high to FSMC_NCEx high	$5T_{HCLK}-1$	-	ns
$t_{d(NCEx-NWE)}$	FSMC_NCEx low to FSMC_NWE low	-	$5T_{HCLK}+1$	ns
$t_{v(NWE-D)}$	FSMC_NWE low to FSMC_D[15:0] valid	-	0	ns
$t_{h(NWE-D)}$	FSMC_NWE high to FSMC_D[15:0] invalid	$8T_{HCLK}-1$	-	ns
$t_{d(D-NWE)}$	FSMC_D[15:0] valid before FSMC_NWE high	$13T_{HCLK}-1$	-	ns

1. C_{L}=30\ pF.
2. Evaluated by characterization - not tested in production.

Table 84. Switching characteristics for PC Card/CF read and write cycles in I/O space ^{(1)(2)}

Symbol	Parameter	Min	Max	Unit
$t_{w(NIOWR)}$	FSMC_NIOWR low width	$8T_{HCLK}-1$	-	ns
$t_{v(NIOWR-D)}$	FSMC_NIOWR low to FSMC_D[15:0] valid	-	$5T_{HCLK}-1$	ns
$t_{h(NIOWR-D)}$	FSMC_NIOWR high to FSMC_D[15:0] invalid	$8T_{HCLK}-2$	-	ns
$t_{d(NCE4_1-NIOWR)}$	FSMC_NCE4_1 low to FSMC_NIOWR valid	-	$5T_{HCLK}+2.5$	ns
$t_{h(NCEx-NIOWR)}$	FSMC_NCEx high to FSMC_NIOWR invalid	$5T_{HCLK}-1.5$	-	ns
$t_{d(NIORD-NCEx)}$	FSMC_NCEx low to FSMC_NIORD valid	-	$5T_{HCLK}+2$	ns
$t_{h(NCEx-NIORD)}$	FSMC_NCEx high to FSMC_NIORD) valid	$5T_{HCLK}-1.5$	-	ns
$t_{w(NIORD)}$	FSMC_NIORD low width	$8T_{HCLK}-0.5$	-	ns
$t_{su(D-NIORD)}$	FSMC_D[15:0] valid before FSMC_NIORD high	9	-	ns
$t_{d(NIORD-D)}$	FSMC_D[15:0] valid after FSMC_NIORD high	0	-	ns

1. C_{L}=30\ pF.
2. Evaluated by characterization - not tested in production.

NAND controller waveforms and timings

Figure 68 and Figure 69 represent synchronous waveforms, and Table 85 and Table 86 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration:

• COM.FSMC_SetupTime = 0x01; • COM.FSMC_WaitSetupTime = 0x03; • COM.FSMC_HoldSetupTime = 0x02; • COM.FSMC_HiZSetupTime = 0x01;

• ATT.FSMC_SetupTime = 0x01; • ATT.FSMC_WaitSetupTime = 0x03; • ATT.FSMC_HoldSetupTime = 0x02; • ATT.FSMC_HiZSetupTime = 0x01; • Bank = FSMC_Bank_NAND; • MemoryDataWidth = FSMC_MemoryDataWidth_16b;
• ECC = FSMC_ECC_Enable;
• ECCPageSize = FSMC_ECCPageSize_512Bytes;
• TCLRSetupTime = 0;
• TARSetupTime = 0.

In all timing tables, the T_{HCLK} is the HCLK clock period.

Figure 68. NAND controller waveforms for read access

text_image

FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) FMC_NWE FMC_NOE (NRE) FMC_D[y:0] MSv73150V1 td(ALE-NOE) tw(NOE) tsu(D-NOE) th(NOE-ALE) th(D-NOE-D)

1. y = 7 or 15 depending on the NAND flash memory interface.

Figure 69. NAND controller waveforms for write access

text_image

FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) FMC_NWE FMC_NOE (NRE) FMC_D[y:0] MSv73151V1 td(ALE-NWE) tw(NWE) th(NWE-ALE) td(D-NWE) tv(NWE-D) th(NWE-D)

1. y = 7 or 15 depending on the NAND flash memory interface.

Table 85. Switching characteristics for NAND flash read cycles ^{(1)}

Symbol	Parameter	Min	Max	Unit
$t_{w(NOE)}$	FSMC_NOE low width	$4T_{HCLK-0.5}$	$4T_{HCLK+3}$	ns
$t_{su(D-NOE)}$	FSMC_D[15-0] valid data before FSMC_NOE high	10	-	ns
$t_{h(NOE-D)}$	FSMC_D[15-0] valid data after FSMC_NOE high	0	-	ns
$t_{d(ALE-NOE)}$	FSMC_ALE valid before FSMC_NOE low	-	$3T_{HCLK}$	ns
$t_{h(NOE-ALE)}$	FSMC_NWE high to FSMC_ALE invalid	$3T_{HCLK-2}$	-	ns

1. C_{L}=30\ pF.

Table 86. Switching characteristics for NAND flash write cycles ^{(1)}

Symbol	Parameter	Min	Max	Unit
$t_{w(NWE)}$	FSMC_NWE low width	$4T_{HCLK}-1$	$4T_{HCLK}+3$	ns
$t_{v(NWE-D)}$	FSMC_NWE low to FSMC_D[15-0] valid	-	0	ns
$t_{h(NWE-D)}$	FSMC_NWE high to FSMC_D[15-0] invalid	$3T_{HCLK}-2$	-	ns
$t_{d(D-NWE)}$	FSMC_D[15-0] valid before FSMC_NWE high	$5T_{HCLK}-3$	-	ns
$t_{d(ALE-NWE)}$	FSMC_ALE valid before FSMC_NWE low	-	$3T_{HCLK}$	ns
$t_{h(NWE-ALE)}$	FSMC_NWE high to FSMC_ALE invalid	$3T_{HCLK}-2$	-	ns

1. C_{L} = 30 pF.

6.3.27 Camera interface (DCMI) timing specifications

Unless otherwise specified, the parameters given in Table 87 for DCMI are derived from tests performed under the ambient temperature, f_{HCLK} frequency and V_{DD} supply voltage summarized in Table 13, with the following configuration:

• PCK polarity: falling • VSYNC and HSYNC polarity: high • Data format: 14 bits

Figure 70. DCMI timing diagram

text_image

1/DCMI_PIXCLK DCMI_PIXCLK DCMI_HSYNC DCMI_VSYNC DATA[0:13] tsu(HSYNC) th(HSYNC) tsu(VSYNC) th(HSYNC) tsu(DATA) th(DATA) MS32414V2

Table 87. DCMI characteristics ^{(1)}

Symbol	Parameter	Min	Max	Unit
-	Frequency ratio DCMI_PIXCLK/ $f_{HCLK}$	-	0.4	-
DCMI_PIXCLK	Pixel clock input	-	54	MHz
$D_{pixel}$	Pixel clock input duty cycle	30	70	%
$t_{su(DATA)}$	Data input setup time	2.5	-	ns
$t_{h(DATA)}$	Data hold time	1	-
$t_{su(HSYNC)}, t_{su(VSYNC)}$	HSYNC/VSYNC input setup time	2	-
$t_{h(HSYNC)}, t_{h(VSYNC)}$	HSYNC/VSYNC input hold time	0.5	-

1. Evaluated by characterization - not tested in production.

6.3.28 SD/SDIO MMC card host interface (SDIO) characteristics

Unless otherwise specified, the parameters given in Table 88 are derived from tests performed under ambient temperature, f_{PCLKx} frequency and V_{DD} supply voltage conditions summarized in Table 14 with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5V_{DD}

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output characteristics.

Figure 71. SDIO high-speed mode

text_image

tf tr tC tW(CKH) tW(CKL) CK tOV tOH D, CMD (output) tISU tIH D, CMD (input)

ai14887

Figure 72. SD default mode

text_image

CK D, CMD (output) tOVD tOHD

ai14888

Table 88. Dynamic characteristics: SD/MMC characteristics ^{(1)}

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
$f_{PP}$	Clock frequency in data transfer mode	-	0	-	48	MHz
	SDIO_CK/ $f_{PCLK2}$ frequency ratio	-	-	-	8/3	-
$t_{W(CKL)}$	Clock low time	$f_{PP}=48 MHz$	8.5	9	-	ns
$t_{W(CKH)}$	Clock high time	$f_{PP}=48 MHz$	8.3	10	-
CMD, D inputs (referenced to CK) in MMC and SD HS mode
$t_{ISU}$	Input setup time HS	$f_{PP}=48 MHz$	3	-	-	ns
$t_{IH}$	Input hold time HS	$f_{PP}=48 MHz$	0	-	-
CMD, D outputs (referenced to CK) in MMC and SD HS mode
$t_{OV}$	Output valid time HS	$f_{PP}=48 MHz$	-	4.5	6	ns
$t_{OH}$	Output hold time HS	$f_{PP}=48 MHz$	1	-	-
CMD, D inputs (referenced to CK) in SD default mode
$t_{ISUD}$	Input setup time SD	$f_{PP}=24 MHz$	1.5	-	-	ns
$t_{IHD}$	Input hold time SD	$f_{PP}=24 MHz$	0.5	-	-
CMD, D outputs (referenced to CK) in SD default mode
$t_{OVD}$	Output valid default time SD	$f_{PP}=24 MHz$	-	4.5	7	ns
$t_{OHD}$	Output hold default time SD	$f_{PP}=24 MHz$	0.5	-	-

1. Evaluated by characterization - not tested in production.

6.3.29 RTC characteristics

Table 89. RTC characteristics

Symbol	Parameter	Conditions	Min	Max
-	$f_{PCLK1}$ /RTCCLK frequency ratio	Any read/write operation from/to an RTC register	4	-

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

7.1 Device marking

Refer to technical note “Reference device marking schematics for STM32 microcontrollers and microprocessors” (TN1433), available on www.st.com, for the location of pin 1 / ball A1 as well as the location and orientation of the marking areas versus pin 1 / ball A1.

Parts marked as “ES”, “E”, or accompanied by an engineering sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity.

A WLCSP simplified marking example (if any) is provided in the corresponding package information subsection.

7.2 WLCSP90 package information

Figure 73. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package outline

text_image

e1 A1 ball location 10 e 1 A e e2 J G F

BOTTOM VIEW BUMP SIDE

text_image

//bbb Z Detail A A3 A2 A

SIDE VIEW

text_image

A A2 A3

FRONT VIEW

text_image

D A1 orientation reference E aaa (4X)

TOP VIEW WAFER BACK SIDE

text_image

Bump eee A1 b Seating plane Z a X φ φccc φddd Detail A (Rotated 90°)

A0JW_ME_V4

1. Drawing is not to scale.

Table 90. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package mechanical data

Symbol	millimeters			inches(1)
	Min	Typ	Max	Min	Typ	Max
A	0.540	0.570	0.600	0.0213	0.0224	0.0236
A1	-	0.190	-	-	0.0075	-
A2	-	0.380	-	-	0.0150	-
A3(2)	-	0.025	-	-	0.0010	-
b(3)	0.240	0.270	0.300	0.0094	0.0106	0.0118
D	4.188	4.223	4.258	0.1649	0.1663	0.1676
E	3.934	3.969	4.004	0.1549	0.1563	0.1576
e	-	0.400	-	-	0.0157	-
e1	-	3.600	-	-	0.1417	-
e2	-	3.200	-	-	0.1260	-
F	-	0.3115	-	-	0.0123	-
G	-	0.3845	-	-	0.0151	-
aaa	-	0.100	-	-	0.0039	-
bbb	-	0.100	-	-	0.0039	-
ccc	-	0.100	-	-	0.0039	-
ddd	-	0.050	-	-	0.0020	-
eee	-	0.050	-	-	0.0020	-

1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Back side coating.
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

Figure 74. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package recommended footprint

text_image

Dpad Dsm

MS18965V2

Table 91. WLCSP90 recommended PCB design rules

Dimension	Recommended values
Pitch	0.4 mm
Dpad	260 μm max. (circular)220 μm recommended
Dsm	300 μm min. (for 260 μm diameter pad)
PCB pad design	Non-solder mask defined via underbump allowed

Device marking for WLCSP90

The following figure gives an example of topside marking and ball A1 position identifier location.

The printed markings may differ depending on the supply chain.

Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below.

Figure 75. WLCSP90 marking example (package top view)

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity.

7.3 LQFP64 package information (5W)

This LQFP is 64-pin, 10 x 10 mm low-profile quad flat package.

Figure 76. LQFP64 - Outline ^{(15)}

text_image

BOTTOM VIEW 4x N/4 TIPS aaa C A-B D 1/4 (6) E 1/4 bbb H A-B D 4x SECTION A-A θ2 (2) θ1 R1 R2 SECTION B-B B 0.25 θ S L L1 (1) (11) θ3 (13) (N - 4)x A A2 A1 (12) b ddd C A-B D ccc C (0.05) C D (4) (5) (2) D1 (10) N E 1/4 D 1/4 (6) (3) A A (Section A-A) B (3) (5) (2) E1 E (9) (11) WITH PLATING (11) c c1 b1 (11) BASE METAL SECTION B-B TOP VIEW 5W_LQFP64_ME_V1

Table 92. LQFP64 - Mechanical data

Symbol	millimeters			inches(14)
	Min	Typ	Max	Min	Typ	Max
A	-	-	1.60	-	-	0.0630
A1(12)	0.05	-	0.15	0.0020	-	0.0059
A2	1.35	1.40	1.45	0.0531	0.0551	0.0570
b(9)(11)	0.17	0.22	0.27	0.0067	0.0087	0.0106
b1(11)	0.17	0.20	0.23	0.0067	0.0079	0.0091
c(11)	0.09	-	0.20	0.0035	-	0.0079
c1(11)	0.09	-	0.16	0.0035	-	0.0063
D(4)	12.00 BSC			0.4724 BSC
D1(2)(5)	10.00 BSC			0.3937 BSC
E(4)	12.00 BSC			0.4724 BSC
E1(2)(5)	10.00 BSC			0.3937 BSC
e	0.50 BSC			0.1970 BSC
L	0.45	0.60	0.75	0.0177	0.0236	0.0295
L1	1.00 REF			0.0394 REF
N(13)	64
θ	0°	3.5°	7°	0°	3.5°	7°
θ1	0°	-	-	0°	-	-
θ2	10°	12°	14°	10°	12°	14°
θ3	10°	12°	14°	10°	12°	14°
R1	0.08	-	-	0.0031	-	-
R2	0.08	-	0.20	0.0031	-	0.0079
S	0.20	-	-	0.0079	-	-
aaa(1)	0.20			0.0079
bbb(1)	0.20			0.0079
ccc(1)	0.08			0.0031
ddd(1)	0.08			0.0031

Notes:

1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum "b" dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.

7.4 LQFP100 package information (1L)

This LQFP is a 100-pin, 14 x 14 mm low-profile quad flat package.

Note: See list of notes in the notes section.

Figure 77. LQFP100 - Outline ^{(15)}

text_image

4x N/4 TIPS aaa C A-B D D1/4 (6) E1/4 4x bbb H A-B D

BOTTOM VIEW

text_image

H θ2 (2) θ1 R1 R2 SECTION B-B B Gauge PLANE θ S L θ3 L1

(1) (11) SECTION A-A

text_image

(N-4) x e (13) A 0.05 A2 A1 (12) b φ aaa③C A-BD C ccc|C

SIDE VIEW

text_image

(9) (11) b WITH PLATING (11) c c1 (11) b1 (11) BASE METAL

SECTION B-B

text_image

(2) (5) (10) N D D1 D (3) E1/4 E1 E (6) A SECTION A-A A B (4) (2) (5) E

TOP VIEW 1L_LQFP100_ME_V3

Table 93. LQFP100 - Mechanical data

Symbol	millimeters			inches(14)
	Min	Typ	Max	Min	Typ	Max
A	-	1.50	1.60	-	0.0590	0.0630
A1(12)	0.05	-	0.15	0.0019	-	0.0059
A2	1.35	1.40	1.45	0.0531	0.0551	0.0570
b(9)(11)	0.17	0.22	0.27	0.0067	0.0087	0.0106
b1(11)	0.17	0.20	0.23	0.0067	0.0079	0.0090
c(11)	0.09	-	0.20	0.0035	-	0.0079
c1(11)	0.09	-	0.16	0.0035	-	0.0063
D(4)	16.00 BSC			0.6299 BSC
D1(2)(5)	14.00 BSC			0.5512 BSC
E(4)	16.00 BSC			0.6299 BSC
E1(2)(5)	14.00 BSC			0.5512 BSC
e	0.50 BSC			0.0197 BSC
L	0.45	0.60	0.75	0.177	0.0236	0.0295
L1(1)(11)	1.00			-	0.0394	-
N(13)	100
θ	0°	3.5°	7°	0°	3.5°	7°
θ1	0°	-	-	0°	-	-
θ2	10°	12°	14°	10°	12°	14°
θ3	10°	12°	14°	10°	12°	14°
R1	0.08	-	-	0.0031	-	-
R2	0.08	-	0.20	0.0031	-	0.0079
S	0.20	-	-	0.0079	-	-
aaa(1)	0.20			0.0079
bbb(1)	0.20			0.0079
ccc(1)	0.08			0.0031
ddd(1)	0.08			0.0031

Notes:

1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at the seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All dimensions are in millimeters.
8. No intrusion is allowed inwards the leads.
9. Dimension b does not include a dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. The dambar cannot be located on the lower radius or the foot. The minimum space between the protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. The exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead that is between 0.10 mm and 0.25 mm from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package body.
13. N is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to four decimal digits.
15. Drawing is not to scale.

Figure 78. LQFP100 - Footprint example

text_image

75 51 76 0.5 0.3 16.7 14.3 100 26 1 25 1.2 12.3 16.7

1L_LQFP100_FP_V1

1. Dimensions are expressed in millimeters.

7.5 LQFP144 package information (1A)

This LQFP is a 144-pin, 20 x 20 mm low-profile quad flat package.

Note: See list of notes in the notes section.

Figure 79. LQFP144 - Outline ^{(15)}

text_image

BOTTOM VIEW 4x N/4 TIPS aaa C A-B D D 1/4 (6) E 1/4 bbb H A-B D 4x SECTION A-A θ2 (2) θ1 R1 R2 SECTION B-B B 0.25 θ S L θ3 (L1) (1) (11) N-4)x e A 0.05 A2 A1 (12) b ddd C A-B D ccc C D D1 (4) (2)(5) (10) N (3) D E 1/4 (6) (3) A D 1/4 B (3) (2) (5) E1 E (Section A-A) A A (Section A-A) B WITH PLATING WITH PLATING (11) c c1 (11) BASE METAL SECTION B-B TOP VIEW 1A_LQFP144_ME_V2

Table 94. LQFP144 - Mechanical data

Symbol	millimeters			inches(14)
	Min	Typ	Max	Min	Typ	Max
A	-	-	1.60	-	-	0.0630
A1(12)	0.05	-	0.15	0.0020	-	0.0059
A2	1.35	1.40	1.45	0.0531	0.0551	0.0571
b(9)(11)	0.17	0.22	0.27	0.0067	0.0087	0.0106
b1(11)	0.17	0.20	0.23	0.0067	0.0079	0.0090
c(11)	0.09	-	0.20	0.0035	-	0.0079
c1(11)	0.09	-	0.16	0.0035	-	0.0063
D(4)	22.00 BSC			0.8661 BSC
D1(2)(5)	20.00 BSC			0.7874 BSC
E(4)	22.00 BSC			0.8661 BSC
E1(2)(5)	20.00 BSC			0.7874 BSC
e	0.50 BSC			0.0197 BSC
L	0.45	0.60	0.75	0.0177	0.0236	0.0295
L1	1.00 REF			0.0394 REF
N(13)	144
θ	0°	3.5°	7°	0°	3.5°	7°
θ1	0°	-	-	0°	-	-
θ2	10°	12°	14°	10°	12°	14°
θ3	10°	12°	14°	10°	12°	14°
R1	0.08	-	-	0.0031	-	-
R2	0.08	-	0.20	0.0031	-	0.0079
S	0.20	-	-	0.0079	-	-
aaa	0.20			0.0079
bbb	0.20			0.0079
ccc	0.08			0.0031
ddd	0.08			0.0031

Notes:

1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at the seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All dimensions are in millimeters.
8. No intrusion is allowed inwards the leads.
9. Dimension b does not include a dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. The dambar cannot be located on the lower radius or the foot. The minimum space between the protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. The exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead that is between 0.10 mm and 0.25 mm from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package body.
13. N is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to four decimal digits.
15. Drawing is not to scale.

Figure 80. LQFP144 - Footprint example

text_image

108 109 0.35 0.50 144 1 19.90 36 22.60 73 1.35 72 17.85 37 22.60

1A_LQFP144_FP

1. Dimensions are expressed in millimeters.

7.6 UFBGA(176+25) package information (A0E7)

This UFBGA is a 176+25-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package.

Figure 81. UFBGA(176+25) - Outline

text_image

Seating plane C A4 A2 A3 b A1 A ddd C A1 ball identifier E1 F A D1 e e R 15 1 BOTTOM VIEW Øb (176 + 25 balls) Ø eee M C A B Ø fff M C A1 ball index area E D B TOP VIEW A0E7_ME_V10

1. Drawing is not to scale.

Table 95. UFBGA(176+25) - Mechanical data

Symbol	millimeters			inches(1)
	Min.	Typ.	Max.	Min.	Typ.	Max.
A	-	-	0.600	-	-	0.0236
A1	0.050	0.080	0.110	0.0020	0.0031	0.0043
A2	-	0.450	-	-	0.0177	-
A3	-	0.130	-	-	0.0051	-
A4	-	0.320	-	-	0.0126	-
b	0.240	0.290	0.340	0.0094	0.0114	0.0134
D	9.850	10.000	10.150	0.3878	0.3937	0.3996
D1	-	9.100	-	-	0.3583	-
E	9.850	10.000	10.150	0.3878	0.3937	0.3996
E1	-	9.100	-	-	0.3583	-
e	-	0.650	-	-	0.0256	-
F	-	0.450	-	-	0.0177	-
ddd	-	-	0.080	-	-	0.0031
eee	-	-	0.150	-	-	0.0059
fff	-	-	0.050	-	-	0.0020

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 82. UFBGA(176+25) - Footprint example

text_image

Dpad Dsm

BGA_WLCSP_FT_V1

Table 96. UFBGA(176+25) - Example of PCB design rules (0.65 mm pitch BGA)

Dimension	Values
Pitch	0.65 mm
Dpad	0.300 mm
Dsm	0.400 mm typ. (depends on the soldermask registration tolerance)
Stencil opening	0.300 mm
Stencil thickness	Between 0.100 mm and 0.125 mm
Pad trace width	0.100 mm

7.7 LQFP176 package information (1T)

This LQFP is a 176-pin, 24 x 24 mm, 0.5 mm pitch, low profile quad flat package.

Note: See list of notes in the notes section.

Figure 83. LQFP176 - Outline ^{(15)}

text_image

4x N/4 TIPS aaa C A-B D D1/4 (6) E1/4 4x bbb H A-B D

BOTTOM VIEW

text_image

θ2 (2) R1 R2 B(See SECTION B-B) GAUGE PLANE 0.25 θ S L θ3 (L1) (1) (11)

SECTION A-A

text_image

A2 0.05 (N-4) x e (13) A A1 (12) b φ dddM C A-BD C ccc C

SIDE VIEW

text_image

(2) (5) (10) N E1/4 D1 D (3) D1/4 (6) A B (3) (5) (2) E1 E SECTION A-A A A

TOP VIEW

text_image

(9) (11) WITH PLATING (11) c c1 (11) b1 (11) BASE METAL

SECTION B-B

1T_LQFP176_ME_V2

Table 97. LQFP176 - Mechanical data

Symbol	millimeters			inches(14)
	Min	Typ	Max	Min	Typ	Max
A	-	-	1.600	-	-	0.0630
A1(12)	0.050	-	0.150	0.0020	-	0.0059
A2	1.350	1.400	1.450	0.0531	0.0551	0.0571
b(9)(11)	0.170	0.220	0.270	0.0067	0.0087	0.0106
b1(11)	0.170	0.200	0.230	0.0067	0.0079	0.0091
c(11)	0.090	-	0.200	0.0035	-	0.0079
c1(11)	0.090	-	0.160	0.0035	-	0.063
D(4)	26.000			1.0236
D1(2)(5)	24.000			0.9449
E(4)	26.000			0.0197
E1(2)(5)	24.000			0.9449
e	0.500			0.1970
L	0.450	0.600	0.750	0.0177	0.0236	0.0295
L1(1)(11)	1			0.0394 REF
N(13)	176
θ	0°	3.5°	7°	0°	3.5°	7°
θ1	0°	-	-	0°	-	-
θ2	10°	12°	14°	10°	12°	14°
θ3	10°	12°	14°	10°	12°	14°
R1	0.080	-	-	0.0031	-	-
R2	0.080	-	0.200	0.0031	-	0.0079
S	0.200	-	-	0.0079	-	-
aaa(1)	0.200			0.0079
bbb(1)	0.200			0.0079
ccc(1)	0.080			0.0031
ddd(1)	0.080			0.0031

Notes:

1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at the seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All dimensions are in millimeters.
8. No intrusion is allowed inwards the leads.
9. Dimension b does not include a dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. The dambar cannot be located on the lower radius or the foot. The minimum space between the protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. The exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead that is between 0.10 mm and 0.25 mm from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package body.
13. N is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to four decimal digits.
15. Drawing is not to scale.

Figure 84. LQFP176 - Footprint example

text_image

176 1 0.5 133 132 0.3 26.7 21.8 44 45 89 88 1.2 21.8 26.7 1T_FP_V1

1. Dimensions are expressed in millimeters.

7.8 Thermal characteristics

The maximum chip-junction temperature, T_{J} max, in degrees Celsius, may be calculated using the following equation:

T _ {J} \max = T _ {A} \max + (P _ {D} \max \times \Theta_ {J A})

Where:

• T_{A} max is the maximum ambient temperature in ^{\circ}C ,
• \Theta_{JA} is the package junction-to-ambient thermal resistance, in ^\circ C/W ,
• P_{D} max is the sum of P_{INT} max and P_{I/O} max ( P_{D} max = P_{INT} max + P_{I/O} max),
• P_{INT} max is the product of I_{DD} and V_{DD} , expressed in Watts. This is the maximum chip internal power.

P_{I/O} max represents the maximum power dissipation on output pins where:

P _ {I / O} \max = \Sigma (V _ {O L} \times I _ {O L}) + \Sigma ((V _ {D D} - V _ {O H}) \times I _ {O H}),

taking into account the actual V_{OL} / I_{OL} and V_{OH} / I_{OH} of the I/Os at low and high level in the application.

Table 98. Package thermal characteristics

Symbol	Parameter	Value	Unit
$\Theta_{JA}$	Thermal resistance junction-ambientLQFP64 - 10 × 10 mm / 0.5 mm pitch	46	°C/W
	Thermal resistance junction-ambientLQFP100 - 14 × 14 mm / 0.5 mm pitch	43
	Thermal resistance junction-ambientLQFP144 - 20 × 20 mm / 0.5 mm pitch	40
	Thermal resistance junction-ambientLQFP176 - 24 × 24 mm / 0.5 mm pitch	38
	Thermal resistance junction-ambientUFBGA176 - 10× 10 mm / 0.65 mm pitch	39
	Thermal resistance junction-ambientWLCSP90 - 0.400 mm pitch	38.1

Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org.

8 Ordering information

For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.

Appendix A Application block diagrams

A.1 USB OTG full speed (FS) interface solutions

Figure 85. USB controller configured as peripheral-only and used in Full speed mode

flowchart

graph LR
  VDD["VDD"] -->|Input| STM32F4xx
  STM32F4xx -->|OSC_IN| OSC_IN
  STM32F4xx -->|OSC_OUT| OSC_OUT
  OSC_IN -->|PA11//PB14| USBStdBConnector
  OSC_OUT -->|PA12/PB15| USBStdBConnector
  USBStdBconnector["USB Std-B connector"] -->|VBUS| n5VToVdd["5V to VDD"]
  USBStdBconnector -->|DM| n5VToVdd
  USBStdBconnector -->|DP| n5VToVdd
  USBStdBconnector -->|Vss| VSS["VSS"]

1. External voltage regulator only needed when building a V_{BUS} powered device.
2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.

Figure 86. USB controller configured as host-only and used in full speed mode

flowchart

graph LR
  Input["Input"] -->|OSC_IN| STM32F4xx
  Input -->|OSC_OUT| STM32F4xx
  STM32F4xx -->|GPIO| CurrentLimiter["Current limiter power switch(1)"]
  STM32F4xx -->|GPIO+IRQ| CurrentLimiter
  CurrentLimiter -->|EN| CurrentLimiter
  CurrentLimiter -->|Overcurrent| CurrentLimiter
  CurrentLimiter -->|5 V Pwr| USBStdA["USB Std-A connector"]
  CurrentLimiter -->|VBUS| USBStdA
  CurrentLimiter -->|DM| USBStdA
  CurrentLimiter -->|DP| USBStdA
  CurrentLimiter -->|VSS| USBStdA
  USBStdA -->|VSS| Output["Output"]

1. The current limiter is required only if the application has to support a V_{BUS} powered device. A basic power switch can be used if 5 V are available on the application board.
2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.

Figure 87. USB controller configured in dual mode and used in full speed mode

flowchart

graph LR
  VDD["VDD"] --> GPIO["GPIO"]
  GPIO -->|EN| CurrentLimiter["Current limiter power switch(2)"]
  CurrentLimiter -->|5 V Pwr| VDD
  CurrentLimiter -->|Overcurrent| GPIO
  VDD --> VDDRegulator["5 V to VDD voltage regulator(1)"]
  VDDRegulator --> VDDRegulator
  VDDRegulator --> USBMicro["USBmicro-AB connector"]
  USBMicro -->|VBUS| PA9/PB13["PA9/PB13"]
  USBMicro -->|DM| PA11/PB14["PA11/PB14"]
  USBMicro -->|DP| PA12/PB15["PA12/PB15"]
  USBMicro -->|ID3| PA10/PB12["PA10/PB12"]
  PA9Pb13["PA9/PB13"] --> USBMicro
  PA11Pb14["PA11/PB14"] --> USBMicro
  PA12Pb15["PA12/PB15"] --> USBMicro
  PA10Pb12["PA10/PB12"] --> USBMicro
  VSS["Vss"] --> USBMicro

1. External voltage regulator only needed when building a V_{BUS} powered device.
2. The current limiter is required only if the application has to support a V_{BUS} powered device. A basic power switch can be used if 5 V are available on the application board.
3. The ID pin is required in dual role only.
4. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.

A.2 USB OTG high speed (HS) interface solutions

Figure 88. USB controller configured as peripheral, host, or dual-mode and used in high speed mode

flowchart

graph LR
  subgraph STM32F4xx
  A["USB HS\nOTG Ctrl"] -->|DP not connected| B["FS PHY"]
  B -->|DM not connected| A
  B -->|DP not connected| C["High speed\nOTG PHY"]
  D["ULPI_CLK"] --> C
  E[""ULPI_D[7:0"]"] --> C
  F["ULPI_DIR"] --> C
  G["ULPI_STP"] --> C
  H["ULPI_NXT"] --> C
  I["PLL"] --> J["PLL"]
  J --> K["24 or 26 MHz XT(1)"]
  K --> L["XT1"]
  L --> M["MCO1 or MCO2"]
  M --> N["XI"]
  end
  subgraph USBconnector
    O["USB connector"]
  end
  C --> O
  C --> O
  C --> P["DP"]
  C --> Q["DM"]
  C --> R["ID(2)"]
  C --> S["VBUS"]
  C --> T["VSS"]

1. It is possible to use MCO1 or MCO2 to save a crystal. It is however not mandatory to clock the STM32F40xxx with a 24 or 26 MHz crystal when using USB HS. The above figure only shows an example of a possible connection.
2. The ID pin is required in dual role only.

A.3 Ethernet interface solutions

Figure 89. MII mode using a 25 MHz crystal

flowchart

This diagram illustrates the architecture and signal flow of an STM32 microcontroller, showing the interaction between the MCU, Ethernet, PTP, and MT2 components with associated data streams and control signals.

1. f_{HCLK} must be greater than 25 MHz.
2. Pulse per second when using IEEE1588 PTP optional signal.

Figure 90. RMII with a 50 MHz oscillator

flowchart

This diagram illustrates the architecture and signal flow of an STM32 microcontroller, showing the interaction between the MCU, Ethernet MAC, and LTE (XT1) via clock and timer input, and the corresponding data flow between the two.

1. f_{HCLK} must be greater than 25 MHz.

Figure 91. RMII with a 25 MHz crystal and PHY with PLL

flowchart

This diagram illustrates the architecture and signal flow of an STM32F microcontroller, showing the interaction between the MCU, Ethernet, and PHY components with associated data streams and timing parameters.

1. f_{HCLK} must be greater than 25 MHz.
2. The 25 MHz (PHY_CLK) must be derived directly from the HSE oscillator, before the PLL block.

9 Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST product(s) identified in this documentation may be certified by various security certification bodies and/or may implement our own security measures as set forth herein. However, no level of security certification and/or built-in security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the customer needs both in relation to the ST product alone, as well as when combined with other components and/or software for the customer end product or application. In particular, take note that:

• ST products may have been certified by one or more security certification bodies, such as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received security certification along with the level and current status of such certification, either visit the relevant certification standards website or go to the relevant product page on www.st.com for the most up to date information. As the status and/or level of security certification for an ST product can change from time to time, customers should re-check security certification status/level as needed. If an ST product is not shown to be certified under a particular security standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST products. These certification bodies are therefore independently responsible for granting or revoking security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations, assessments, testing, or other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard technologies which may be used in conjunction with an ST product are based on standards which were not developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open technologies or for any methods which have been or may be developed to bypass, decrypt or crack such algorithms or technologies.
• While robust security testing may be done, no level of certification can absolutely guarantee protections against all attacks, including, for example, against advanced attacks which have not been tested for, against new or unidentified forms of attack, or against any form of attack when using an ST product outside of its specification or intended use, or in conjunction with other components or software which are used by customer to create their end product or application. ST is not responsible for resistance against such attacks. As such, regardless of the incorporated security features and/or any information or support that may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for meets their needs, both in relation to the ST product alone and when incorporated into a customer end product or application.
• All security features of ST products (inclusive of any hardware, software, documentation, and the like), including but not limited to any enhanced security features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the applicable written and signed contract terms specifically provide otherwise.

10 Revision history

Table 99. Document revision history

Date	Revision	Changes
15-Sep-2011	1	Initial release.
24-Jan-2012	2	Added WLCSP90 package on cover page.Renamed USART4 and USART5 into UART4 and UART5, respectively.Updated number of USB OTG HS and FS in Table 3: STM32F405xx and STM32F407xx: features and peripheral counts.Updated Figure 3: Compatible board design between STM32F10xx/STM32F2/STM32F40xxx for LQFP144 package and Figure 4: Compatible board design between STM32F2 and STM32F40xxx for LQFP176 and BGA176 packages, and removed note 1 and 2.Updated Section 3.0.9: Flexible static memory controller (FSMC).Modified I/Os used to reprogram the flash memory for CAN2 and USB OTG FS in Section 3.0.13: Boot modes.Updated note in Section 3.0.14: Power supply schemes.PDR_ON no more available on LQFP100 package. Updated Section 3.0.16: Voltage regulator. Updated condition to obtain a minimum supply voltage of 1.7 V in the whole document.Renamed USART4/5 to UART4/5 and added LIN and IrDA feature for UART4 and UART5 in Table 6: USART feature comparison.Removed support of I2C for OTG PHY in Section 3.0.30: Universal serial bus on-the-go full-speed (OTG_FS).Added Table 7: Legend/abbreviations used in the pinout table.Table 8: STM32F40xxx pin and ball definitions: replaced VSS_3, VSS_4, and VSS_8 by VSS; reformatted Table 8: STM32F40xxx pin and ball definitions to better highlight I/O structure, and alternate functions versus additional functions; signal corresponding to LQFP100 pin 99 changed from PDR_ON to VSS; EVENTOUT added in the list of alternate functions for all I/Os; ADC3_IN8 added as alternate function for PF10; FSMC_CLE and FSMC_ALE added as alternate functions for PD11 and PD12, respectively; PH10 alternate function TIM15_CH1_ETR renamed TIM5_CH1; updated PA4 and PA5 I/O structure to TTa.Removed OTG_HS_SCL, OTG_HS_SDA, OTG_FS_INTN in Table 8: STM32F40xxx pin and ball definitions and Table 10: Alternate function mapping.Changed TCM data RAM to CCM data RAM in Figure 18: STM32F40xxx memory map.Added IVDD and IVSS maximum values in Table 14: Current characteristics.Added Note 1 related to fHCLK, updated Note 2 in Table 16: General operating conditions, and added maximum power dissipation values.Updated Table 17: Limitations depending on the operating power supply range.
24-Jan-2012	2(continued)	Added V12 in Table 21: Embedded reset and power control block characteristics.Updated Table 23: Typical and maximum current consumption in Run mode, code with data processing running from flash memory (ART accelerator disabled) and Table 22: Typical and maximum current consumption in Run mode, code with data processing running from flash memory (ART accelerator enabled) or RAM. Added Figure , Figure 25, Figure 26, and Figure 27.Updated Table 24: Typical and maximum current consumption in Sleep mode and removed Note 1.Updated Table 25: Typical and maximum current consumptions in Stop mode and Table 26: Typical and maximum current consumptions in Standby mode, Table 27: Typical and maximum current consumptions in VBAT mode, and Table 29: Switching output I/O current consumption.Section : On-chip peripheral current consumption: modified conditions, and updated Table 30: Peripheral current consumption and Note 2.Changed fHSE_ext to 50 MHz and tr(HSE)/tf(HSE) maximum value in Table 32: High-speed external user clock characteristics.Added Cin(LSE) in Table 33: Low-speed external user clock characteristics.Updated maximum PLL input clock frequency, removed related note, and deleted jitter for MCO for RMII Ethernet typical value in Table 38: Main PLL characteristics. Updated maximum PLLI2S input clock frequency and removed related note in Table 39: PLLI2S (audio PLL) characteristics.Updated Section : Flash memory to specify that the devices are shipped to customers with the flash memory erased. Updated Table 41: Flash memory characteristics, and added tME in Table 42: Flash memory programming.Updated Table 45: EMS characteristics, and Table 46: EMI characteristics.Updated Table 58: I2S dynamic characteristicsUpdated Figure 45: ULPI timing diagram and Table 64: ULPI timing.Added tCOUNTER and tMAX_COUNT in Table 54: Characteristics of TIMx connected to the APB1 domain and Table 55: Characteristics of TIMx connected to the APB2 domain. Updated Table 67: Dynamic characteristics: Ethernet MAC signals for RMII.Removed USB-IF certification in Section : USB OTG FS characteristics.
24-Jan-2012	2(continued)	Updated Table 63: USB HS clock timing parametersUpdated Table 69: ADC characteristics.Updated Table 70: ADC accuracy at fADC = 30 MHz.Updated Note 1 in Table 76: DAC characteristics.Section 6.3.26: FSMC characteristics: updated Table 77 toTable 88, changed CL value to 30 pF, and modified FSMC configuration for asynchronous timings and waveforms. Updated Figure 59: Synchronous multiplexed PSRAM write timings.Updated Table 100: Package thermal characteristics.Appendix A.1: USB OTG full speed (FS) interface solutions: modified Figure 93: USB controller configured as peripheral-only and used in Full speed mode added Note 2, updated Figure 94: USB controller configured as host-only and used in full speed mode and added Note 2, changed Figure 95: USB controller configured in dual mode and used in full speed mode and added Note 3.Appendix A.2: USB OTG high speed (HS) interface solutions: removed figures USB OTG HS device-only connection in FS mode and USB OTG HS host-only connection in FS mode, and updated Figure 96: USB controller configured as peripheral, host, or dual-mode and used in high speed mode and added Note 2.Added Appendix A.3: Ethernet interface solutions.
31-May-2012	3	Updated Figure 5: STM32F40xxx block diagram and Figure 7: Power supply supervisor interconnection with internal reset OFFAdded SDIO, added notes related to FSMC and SPI/I2S in Table 3: STM32F405xx and STM32F407xx: features and peripheral counts.Starting from Silicon revision Z, USB OTG full-speed interface is now available for all STM32F405xx devices.Added full information on WLCSP90 package together with corresponding part numbers.Changed number of AHB buses to 3.Modified available flash memory sizes in Section 3.0.4: Embedded flash memory.Modified number of maskable interrupt channels in Section 3.0.10: Nested vectored interrupt controller (NVIC).Updated case of Regulator ON/internal reset ON, Regulator ON/internal reset OFF, and Regulator OFF/internal reset ON in Section 3.0.16: Voltage regulator.Updated standby mode description in Section 3.0.19: Low-power modes.Added Note 1 below Figure 16: STM32F40xxx UFBGA176 bailout.Added Note 1 below Figure 17: STM32F40xxx WLCSP90 bailout.Updated Table 8: STM32F40xxx pin and ball definitions.Added Table 9: FSMC pin definition.Removed OTG_HS_INTN alternate function in Table 8: STM32F40xxx pin and ball definitions and Table 10: Alternate function mapping.Removed I2S2_WS on PB6/AF5 in Table 10: Alternate function mapping.Replaced JTRST by NJTRST, removed ETH_RMII _TX_CLK, and modified I2S3ext_SD on PC11 in Table 10: Alternate function mapping.Added Table 12: register boundary addresses.Updated Figure 18: STM32F40xxx memory map.Updated VDDA and VREF+ decoupling capacitor in Figure 21: Power supply scheme.Added power dissipation maximum value for WLCSP90 in Table 16: General operating conditions.Updated VPOR/PDR in Table 21: Embedded reset and power control block characteristics.Updated notes in Table 23: Typical and maximum current consumption in Run mode, code with data processing running from flash memory (ART accelerator disabled), Table 22: Typical and maximum current consumption in Run mode, code with data processing running from flash memory (ART accelerator enabled) or RAM, and Table 24: Typical and maximum current consumption in Sleep mode.Updated maximum current consumption at TA = 25 °n Table 25: Typical and maximum current consumptions in Stop mode.
31-May-2012	3(continued)	Removed fHSE_ext typical value in Table 32: High-speed external user clock characteristics. Updated Table 34: HSE 4-26 MHz oscillator characteristics and Table 35: LSE oscillator characteristics (fLSE = 32.768 kHz).Added fPLL48_OUT maximum value in Table 38: Main PLL characteristics.Modified equation 1 and 2 in Section 6.3.11: PLL spread spectrum clock generation (SSCG) characteristics.Updated Table 41: Flash memory characteristics, Table 42: Flash memory programming, and Table 43: Flash memory programming with VPP.Updated Section : Output driving current.Table 56: I2C characteristics: Note 4 updated and applied to th(SDA) in Fast mode, and removed note 4 related to th(SDA) minimum value.Updated Table 69: ADC characteristics. Updated note concerning ADC accuracy vs. negative injection current below Table 70: ADC accuracy at fADC = 30 MHz.Added WLCSP90 thermal resistance in Table 100: Package thermal characteristics.Updated Table 92: WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package mechanical data.Updated Figure 87: UFBGA176+25 ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outline and Table 97: UFBGA176+25 ball, 10 x 10 x 0.65 mm pitch, ultra thin fine pitch ball grid array mechanical data.Added Figure 91: LQFP176 - 176-pin, 24 x 24 mm low profile quad flat recommended footprint.Removed 256 and 768 Kbyte flash memory density from Table : .
04-Jun-2013	4	Modified Note 1 below Table 3: STM32F405xx and STM32F407xx: features and peripheral counts.Updated Figure 4 title.Updated Note 3 below Figure 21: Power supply scheme.Changed simplex mode into half-duplex mode in Section 3.0.25: Inter-integrated sound (I2S).Replaced DAC1_OUT and DAC2_OUT by DAC_OUT1 and DAC_OUT2, respectively.Updated pin 36 signal in Figure 15: STM32F40xxx LQFP176 pinout.Changed pin number from F8 to D4 for PA13 pin in Table 8: STM32F40xxx pin and ball definitions.Replaced TIM2_CH1/TIM2_ETR by TIM2_CH1_ETR for PA0 and PA5 pins in Table 10: Alternate function mapping.Changed system memory into System memory + OTP in Figure 18: STM32F40xxx memory map.Added Note 1 below Table 18: VCAP_1/VCAP_2 operating conditions.Updated IDDA description in Table 76: DAC characteristics.Removed PA9/PB13 connection to VBUS in Figure 93: USB controller configured as peripheral-only and used in Full speed mode and Figure 94: USB controller configured as host-only and used in full speed mode.Updated SPI throughput on front page and Section 3.0.24: Serial peripheral interface (SPI)Updated operating voltages in Table 3: STM32F405xx and STM32F407xx: features and peripheral counts.Updated note in Section 3.0.14: Power supply schemesUpdated Section 3.0.15: Power supply supervisorUpdated “Regulator ON” paragraph in Section 3.0.16: Voltage regulatorRemoved note in Section 3.0.19: Low-power modesCorrected wrong reference manual in Section 3.0.28: Ethernet MAC interface with dedicated DMA and IEEE 1588 supportUpdated Table 17: Limitations depending on the operating power supply rangeUpdated Table 26: Typical and maximum current consumptions in Standby modeUpdated Table 27: Typical and maximum current consumptions in VBAT modeUpdated Table 39: PLLI2S (audio PLL) characteristicsUpdated Table 46: EMI characteristicsUpdated Table 51: Output voltage characteristicsUpdated Table 53: NRST pin characteristicsUpdated Table 57: SPI dynamic characteristicsUpdated Table 58: I2S dynamic characteristicsDeleted Table 59Updated Table 64: ULPI timingUpdated Figure 46: Ethernet SMI timing diagram
04-Jun-2013	4(continued)	Updated Figure 87: UFBGA176+25 ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outlineUpdated Table 97: UFBGA176+25 ball, 10 x 10 x 0.65 mm pitch, ultra thin fine pitch ball grid array mechanical dataUpdated Figure 5: STM32F40xxx block diagramUpdated Section 2: DescriptionUpdated footnote (3) in Table 3: STM32F405xx and STM32F407xx: features and peripheral counts.Updated Figure 3: Compatible board design between STM32F10xx/STM32F2/STM32F40xxx for LQFP144 packageUpdated Figure 4: Compatible board design between STM32F2 and STM32F40xxx for LQFP176 and BGA176 packagesUpdated Section 3.0.14: Power supply schemesUpdated Section 3.0.15: Power supply supervisorUpdated Section 3.0.16: Voltage regulator, including figures.Updated Table 16: General operating conditions, including footnote (2).Updated Table 17: Limitations depending on the operating power supply range, including footnote (3).Updated footnote (1) in Table 69: ADC characteristics.Updated footnote (2) in Table 70: ADC accuracy at fADC = 30 MHz.Updated footnote (1) in Table 76: DAC characteristics.Updated Figure 9: Regulator OFF.Updated Figure 7: Power supply supervisor interconnection with internal reset OFF.Added Section 3.0.17: Regulator ON/OFF and internal reset ON/OFF availability.Updated footnote (2) of Figure 21: Power supply scheme.Replaced respectively “I2S3S_WS” by “I2S3_WS”, “I2S3S_CK” by “I2S3_CK” and “FSMC_BLN1” by “FSMC_NBL1” in Table 10: Alternate function mapping.Added “EVENTOUT” as alternate function “AF15” for pin PC13, PC14, PC15, PH0, PH1, PI8 in Table 10: Alternate function mappingReplaced “DCMI_12” by “DCMI_D12” in Table 8: STM32F40xxx pin and ball definitions.Removed the following sentence from Section : I2C interface characteristics: ”Unless otherwise specified, the parameters given in Table 56 are derived from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 16.”.In Table 8: STM32F40xxx pin and ball definitions on page 53:- For pin PC13, replaced “RTC_AF1” by “RTC_OUT, RTC_TAMP1, RTC_TS”- for pin PI8, replaced “RTC_AF2” by “RTC_TAMP1, RTC_TAMP2, RTC_TS”.- for pin PB15, added RTC_REFIN in Alternate functions column.In Table 10: Alternate function mapping on page 70, for port PB15, replaced “RTC_50Hz” by “RTC_REFIN”.
04-Jun-2013	4(continued)	Updated Figure 6: Multi-AHB matrix.Updated Figure 7: Power supply supervisor interconnection with internal reset OFFChanged 1.2 V to V12 in Section : Regulator OFFUpdated LQFP176 pin 48.Updated Section 1: Introduction.Updated Section 2: Description.Updated operating voltage in Table 3: STM32F405xx and STM32F407xx: features and peripheral counts.Updated Note 1.Updated Section 3.0.15: Power supply supervisor.Updated Section 3.0.16: Voltage regulator.Updated Figure 9: Regulator OFF.Updated Table 4: Regulator ON/OFF and internal reset ON/OFF availability.Updated Section 3.0.19: Low-power modes.Updated Section 3.0.20: VBAT operation.Updated Section 3.0.22: Inter-integrated circuit interface (I2C).Updated pin 48 in Figure 15: STM32F40xxx LQFP176 pinout.Updated Table 7: Legend/abbreviations used in the pinout table.Updated Table 8: STM32F40xxx pin and ball definitions.Updated Table 16: General operating conditions.Updated Table 17: Limitations depending on the operating power supply range.Updated Section 6.3.7: Wakeup time from low-power mode.Updated Table 36: HSI oscillator characteristics.Updated Section 6.3.15: I/O current injection characteristics.Updated Table 50: I/O static characteristics.Updated Table 53: NRST pin characteristics.Updated Table 56: I2C characteristics.Updated Figure 39: I2C bus AC waveforms and measurement circuit.Updated Section 6.3.19: Communications interfaces.Updated Table 69: ADC characteristics.Added Table 72: Temperature sensor calibration values.Added Table 75: Internal reference voltage calibration values.Updated Section 6.3.26: FSMC characteristics.Updated Section 6.3.28: SD/SDIO MMC card host interface (SDIO) characteristics.Updated Table 25: Typical and maximum current consumptions in Stop mode.Updated Section : SPI interface characteristics included Table 57.Updated Section : I2S interface characteristics included Table 58.Updated Table 66: Dynamic characteristics: Ethernet MAC signals for SMI.Updated Table 68: Dynamic characteristics: Ethernet MAC signals for MII.
04-Jun-2013	4(continued)	Updated Table 66: Dynamic characteristics: Ethernet MAC signals for SMI.Updated Table 68: Dynamic characteristics: Ethernet MAC signals for MII.Updated Table 81: Synchronous multiplexed NOR/PSRAM read timings.Updated Table 82: Synchronous multiplexed PSRAM write timings.Updated Table 83: Synchronous non-multiplexed NOR/PSRAM read timings.Updated Table 84: Synchronous non-multiplexed PSRAM write timings.Updated Section 6.3.27: Camera interface (DCMI) timing specifications including Table 89: DCMI characteristics and addition of Figure 72: DCMI timing diagram.Updated Section 6.3.28: SD/SDIO MMC card host interface (SDIO) characteristics including Table 90.Updated Chapter Figure 9.
06-Mar-2015	5	Replace Cortex-M4F by Cortex-M4 with FPU throughout the document.Updated Section : Regulator OFF and Table 4: Regulator ON/OFF and internal reset ON/OFF availability for LQFP176.Updated Figure 15: STM32F40xxx LQFP176 pinout and Table 8: STM32F40xxx pin and ball definitions.Updated Figure 6: Multi-AHB matrix.Added note 1 below Figure 12: STM32F40xxx LQFP64 pinout, Figure 13: STM32F40xxx LQFP100 pinout, Figure 14: STM32F40xxx LQFP144 pinout and Figure 15: STM32F40xxx LQFP176 pinout.Updated IVDD and IVSS in Table 14: Current characteristics.Updated PLS[2:0]=101 (falling edge) configuration in Table 21: Embedded reset and power control block characteristics.Added Section : Additional current consumption. Updated Section : On-chip peripheral current consumption.Updated Table 31: Low-power mode wakeup timings.Updated Table 34: HSE 4-26 MHz oscillator characteristics and Table 35: LSE oscillator characteristics (fLSE = 32.768 kHz).Changed condition related to VESD(CDM) in Table 47: ESD absolute maximum ratings.Updated Table 49: I/O current injection susceptibility, Table 50: I/O static characteristics, Table 51: Output voltage characteristics conditions, Table 52: I/O AC characteristics and Figure 37: I/O AC characteristics definition.Updated Section : I2C interface characteristics.Remove note 3 in Table 71: Temperature sensor characteristics.Updated Figure 72: DCMI timing diagram.Modified Figure 75: WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package outline and Table 92: WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package mechanical data. Added Figure 76: WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale recommended footprint and Table 93: WLCSP90 recommended PCB design rules. /Modified Figure 78: LQFP64 – 64-pin, 10 x 10 mm low-profile quad flat package outline and Table 94: LQFP64 – 64-pin 10 x 10 mm low-profile quad flat package mechanical data.Updated Figure 87: UFBGA176+25 ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outline and Table 97: UFBGA176+25 ball, 10 x 10 x 0.65 mm pitch, ultra thin fine pitch ball grid array mechanical data. Added Figure 88: UFBGA176+25 - 201- ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array recommended footprint and Table 98: UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA).Updated Figure 90: LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package outline.Added Section : Device marking for WLCSP90, Section : Device marking for LQFP64, Section : Device marking for LFP100, Section : Device marking for LQFP144, Section : Device marking for UFBGA176+25 and Section : Device marking for LQFP176.
22-Oct-2015	6	In the whole document, updated notes related to values specified by design or by characterization.Updated Table 36: HSI oscillator characteristics.Changed fVCO_OUT minimum value and VCO freq to 100 MHz in Table 38: Main PLL characteristics and Table 39: PLLI2S (audio PLL) characteristics.Updated Figure 39: SPI timing diagram - slave mode and CPHA = 0.Updated Figure 53: 12-bit buffered /non-buffered DAC.Removed note 1 related to better performance using a restricted VDD range in Table 70: ADC accuracy at fADC = 30 MHz.Upated Figure 84: LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline.Updated Figure 87: UFBGA176+25 ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outline and Table 97: UFBGA176+25 ball, 10 x 10 x 0.65 mm pitch, ultra thin fine pitch ball grid array mechanical data.
16-Mar-2016	7	Updated Figure 2: Compatible board designSTM32F10xx/STM32F2/STM32F40xxx for LQFP100 package.Updated |VSSX- VSS| in Table 13: Voltage characteristics to add VREF-.Added VREF- in Table 69: ADC characteristics.Updated Table 92: WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package mechanical data.
09-Sep-2016	8	Removed note 1 below Figure 5: STM32F40xxx block diagram.Updated definition of stresses above maximum ratings in Section 6.2: Absolute maximum ratings.Updated th(NSS) in Figure 39: SPI timing diagram - slave mode and CPHA = 0 and Figure 40: SPI timing diagram - slave mode and CPHA = 1.Added note related to optional marking and inset/upset marks in all package marking sections.Updated Figure 87: UFBGA176+25 ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outline and Table 97: UFBGA176+25 ball, 10 x 10 x 0.65 mm pitch, ultra thin fine pitch ball grid array mechanical data.
14-Aug-2020	9	Renamed Section 3 and Section 8 into Functional overview and Ordering information, respectively.Added Arm logo and legal notice in Section 1: Introduction and updated Arm wordmark in the whole document. Removed USB certified logos.Updated camera interfaces for STM32F405OE in Table 3: STM32F405xx and STM32F407xx: features and peripheral counts.Added OTP memory in Features and Section 3.0.4: Embedded flash memory.Changed random number generator to true random number generator in the whole document and updated Section 3.0.34: True random number generator (RNG).Added Note 1 related to UFBGA176 in Table 8: STM32F40xxx pin and ball definitions.Updated Section 6.2: Absolute maximum ratings introduction.Updated VPVD minimum value for PLS[2:0]=101 (falling edge) in Table 21: Embedded reset and power control block characteristics.Updated Note 1 in Table 36: HSI oscillator characteristics.Added reference to application note AN4899 in Section 6.3.16: I/O port characteristics.Replaced DCMI_PIXCK by DCMI_PIXCLK in Table 10: Alternate function mapping.Renamed Section 8 into Ordering information.Updated D1 in Figure 87: UFBGA176+25 ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outline.
08-Nov-2024	10	Updated:– Cover page– Section 1: Introduction– Figure 5: STM32F40xxx block diagram– Section 3.18: Real-time clock (RTC), backup SRAM and backup registers– Table 7: STM32F40xxx pin and ball definitions– Table 9: Alternate function mapping– I/O system current consumption– Note 1 in Table 34: HSI oscillator characteristics.– Table 33: LSE oscillator characteristics ( $f_{LSE} = 32.768$ kHz)– Figure 37: I/O AC characteristics definition– Figure 39: SPI timing diagram - slave mode and CPHA = 0, Figure 40: SPI timing diagram - slave mode and CPHA = 1, and Figure 41: SPI timing diagram - master mode– Table 44: EMI characteristics for fHSE = 25 MH and fCPU = 168 MHz– Figure 49: ADC accuracy characteristics and Figure 50: Typical connection diagram when using the ADC with FT/TT pins featuring analog switch function– Figure 68: NAND controller waveforms for read access and Figure 69: NAND controller waveforms for write access– Table 96: UFBGA(176+25) - Example of PCB design rules (0.65 mm pitch BGA) title– Section 7: Package informationAdded Section 9: Important security notice
04-Feb-2026	11	Updated Figure 7: Power supply supervisor interconnection with internal reset OFF.Updated Figure 8: PDR_ON and NRST control with internal reset OFF.Updated Figure 9: Regulator OFF.Updated Figure 18: STM32F40xxx memory map.Updated Figure 20: Pin input voltage.Updated Table 45: ESD absolute maximum ratings.Updated Section 7.3: LQFP64 package information (5W).
18-Mar-2026	12	Re-numbering of Section 3: Functional overview sub-sections.

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