9bbe117f97
用户选定最彻底方案(B2):DMA + 定时器 TRGO 硬件触发 + 消费上一拍 已完成的半区。对应 P1-5 拆出的"单拍硬上界",现已办结。 硬件事实更正(查 CubeMX 器件库 + 本仓 HAL 头证实):F4 上 ADC1 的 外部触发清单里没有 TIM6/TIM7 TRGO(只接 DAC)。故 1 kHz 节拍源由 TIM6 改为 TIM3(PSC 83 / ARR 999,TRGO=UPDATE),同一个更新事件 同时 ① ISR 脉冲 TPAFE CONVST ② 经 TRGO 触发 ADC1 一轮 9 通道 ③ 置位 ADC_WAKE_FLAG 唤醒 adcTask。TIM6 从 .ioc 整体移除。 代码: - Src/tim.c/h:新增 MX_TIM3_Init(含 MasterSlaveMode),删 htim6 - Src/adc.c:ExternalTrigConv=T3_TRGO + EDGE_RISING + DMAContinuousRequests=ENABLE;MspInit 挂 hdma_adc1(DMA2_Stream4 循环模式)。DDS 位关掉 = 一轮只发一次请求,静默丢 8 路 - Src/dma.c:DMA2_Stream4 NVIC 优先级 6(CubeMX 换流会把它重置为 0, 优先级 0 会抢占 FreeRTOS 临界区,违反"外设中断 ≥5") - Src/main.c:周期回调加 TIM3 分支;stm32f4xx_it.c 向量同步 - App/algo/adc_input.c:stm32_scan() → stm32_take(),逐通道 PollForConversion 全删;乒乓半区由完成计数奇偶推出(只读一个 32 位量 → 与 ISR 无竞态);STM32 侧数据固定滞后 1 拍 - App/task/adc_task.c:心跳日志拆出四类计数 观测性:adc1_seq(完成计数)/ adc1_gap(seq 前进 >1 = 丢帧)/ adc1_err(连续 ≥2 拍无新帧 = 停摆)/ adc1_hw(HAL 错误回调)。 单拍无新帧是消费者相位伪影(DMA 完成落在唤醒后 ≈67 µs),不计故障。 验证: - 主机单测 79 → 101 全绿;反向验证四连均咬(半区奇偶取反 11 条、 停摆拍置 valid 4 条、STALL_RUN_MAX 改 1 为 6 条、gap 阈值 1 条) - @build 0 错 0 警,Code 256872 → 257660 - @test PASS:adcp 122 µs → 8 µs、adc1_err=0、adc1_hw=0、 adc1_gap=27/20002 拍、adc1_seq 与 seq 恒定偏移 2 - stack_report 7/7 PASS,adcTask 832 B / 余 59%(不变) - cubemx-survival 新增 5 项审计(TIM3 分支 / T3_TRGO / DDS / DMA 挂载 / 流优先级),28 通过 0 失败 文档:ADC 采样节拍设计说明新增 §11;看门狗停摆分析 §4.4 与 §8 收口; 算法规划 L1-1/L1-3、通道映射、测试说明、各 README 同步。
113 lines
2.8 KiB
C
113 lines
2.8 KiB
C
/* USER CODE BEGIN Header */
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/**
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******************************************************************************
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* @file tim.c
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* @brief This file provides code for the configuration
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* of the TIM instances.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2026 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* USER CODE END Header */
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/* Includes ------------------------------------------------------------------*/
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#include "tim.h"
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/* USER CODE BEGIN 0 */
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/* USER CODE END 0 */
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TIM_HandleTypeDef htim3;
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/* TIM3 init function */
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void MX_TIM3_Init(void)
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{
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/* USER CODE BEGIN TIM3_Init 0 */
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/* USER CODE END TIM3_Init 0 */
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TIM_ClockConfigTypeDef sClockSourceConfig = {0};
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TIM_MasterConfigTypeDef sMasterConfig = {0};
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/* USER CODE BEGIN TIM3_Init 1 */
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/* USER CODE END TIM3_Init 1 */
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htim3.Instance = TIM3;
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htim3.Init.Prescaler = 83;
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htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
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htim3.Init.Period = 999;
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htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
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htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
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if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
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{
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Error_Handler();
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}
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sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
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if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
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{
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Error_Handler();
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}
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sMasterConfig.MasterOutputTrigger = TIM_TRGO_UPDATE;
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sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_ENABLE;
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if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
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{
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Error_Handler();
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}
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/* USER CODE BEGIN TIM3_Init 2 */
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/* USER CODE END TIM3_Init 2 */
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}
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void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
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{
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if(tim_baseHandle->Instance==TIM3)
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{
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/* USER CODE BEGIN TIM3_MspInit 0 */
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/* USER CODE END TIM3_MspInit 0 */
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/* TIM3 clock enable */
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__HAL_RCC_TIM3_CLK_ENABLE();
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/* TIM3 interrupt Init */
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HAL_NVIC_SetPriority(TIM3_IRQn, 6, 0);
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HAL_NVIC_EnableIRQ(TIM3_IRQn);
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/* USER CODE BEGIN TIM3_MspInit 1 */
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/* USER CODE END TIM3_MspInit 1 */
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}
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}
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void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle)
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{
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if(tim_baseHandle->Instance==TIM3)
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{
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/* USER CODE BEGIN TIM3_MspDeInit 0 */
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/* USER CODE END TIM3_MspDeInit 0 */
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/* Peripheral clock disable */
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__HAL_RCC_TIM3_CLK_DISABLE();
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/* TIM3 interrupt Deinit */
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HAL_NVIC_DisableIRQ(TIM3_IRQn);
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/* USER CODE BEGIN TIM3_MspDeInit 1 */
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/* USER CODE END TIM3_MspDeInit 1 */
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}
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}
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/* USER CODE BEGIN 1 */
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/* USER CODE END 1 */
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