清理全库行尾空格与文件尾换行（pre-commit 自动修复基线）
This commit is contained in:
+17
-17
@@ -204,11 +204,11 @@ for(i=0;i<10;i++){
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```c
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int calculate_sum(int a, int b, int c, int d) {
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int sum;
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sum = a + b
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+ c
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sum = a + b
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+ c
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+ d;
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return sum;
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}
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```
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@@ -272,7 +272,7 @@ while (1) ;
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void delay_ms(unsigned int ms) {
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unsigned int i;
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unsigned int j;
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for (i = 0; i < ms; i++) {
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for (j = 0; j < 123; j++) {
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}
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@@ -302,12 +302,12 @@ uint16_t crc_calculate(uint8_t *data, uint16_t length)
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uint16_t crc = 0xFFFF;
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uint16_t i;
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uint16_t j;
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/* 遍历所有数据字节 */
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for (i = 0; i < length; i++) {
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/* 将当前字节与CRC寄存器低8位异或 */
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crc ^= data[i];
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/* 对每个位进行处理 */
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for (j = 0; j < 8; j++) {
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/* 检查最低位是否为1 */
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@@ -320,7 +320,7 @@ uint16_t crc_calculate(uint8_t *data, uint16_t length)
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}
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}
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}
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/* 返回计算得到的CRC值 */
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return crc;
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}
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@@ -338,14 +338,14 @@ void function(void) {
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uint8_t status = 0;
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uint16_t count = 0;
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uint8_t *p_data = NULL;
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p_data = (uint8_t *)malloc(100);
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if (p_data == NULL) {
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return;
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}
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/* 使用p_data */
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free(p_data);
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p_data = NULL;
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}
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@@ -372,11 +372,11 @@ switch (command) {
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case COMMAND_START:
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start_process();
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break;
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case COMMAND_STOP:
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stop_process();
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break;
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default:
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handle_unknown_command();
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break;
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@@ -395,13 +395,13 @@ uint8_t uart_send_data(uint8_t *data, uint16_t length) {
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if (data == NULL) {
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return UART_STATUS_ERROR;
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}
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if (length == 0 || length > UART_BUFFER_SIZE) {
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return UART_STATUS_ERROR;
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}
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/* 发送数据 */
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return UART_STATUS_OK;
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}
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```
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@@ -492,4 +492,4 @@ uint8_t led_toggle(uint8_t led_num);
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#endif
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#endif /* __LED_H */
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```
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```
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+1
-1
@@ -218,4 +218,4 @@ DP-{NN}
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| 原则 | 覆盖用例 |
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|------|----------|
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```
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```
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@@ -738,4 +738,3 @@ ECC 状态（`ECCS1:ECCS0`）：`00`=无错；`01/10/11`=纠正 1/2/3 bit；`10`
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| Feature 寄存器 | 0xB0；ECC_EN=4, QE=0 |
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| Protect 寄存器 | 0xA0；init 后写 0x00 解除保护 |
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| SPI 引脚 | CS=PE0, SCK=PB3, MISO=PB4, MOSI=PB5, WP=PB8, HOLD=PE1 |
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+1
-1
@@ -1363,4 +1363,4 @@ T1 是 ethernet 网络变压器，其中心抽头分别通过电容 C8 和 C9
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CH395P 可通过 J2、J3 跳线帽选择所需通信接口。关于接口配置详参 6.1 章节。
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从 CH395L 升级到 CH395P，虽然两者引脚基本兼容，但网络变压器等外围电路连接可能需要调整，具体改动请参考 WCH 官方论坛相关文章或联系技术支持。
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从 CH395L 升级到 CH395P，虽然两者引脚基本兼容，但网络变压器等外围电路连接可能需要调整，具体改动请参考 WCH 官方论坛相关文章或联系技术支持。
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+139
-139
File diff suppressed because one or more lines are too long
+166
-166
@@ -40,24 +40,24 @@ REVISION HISTORY
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## Table of Contents
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1. GENERAL DESCRIPTION....1
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2. FEATURES....2
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3. SYSTEM APPLICATIONS....3
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4. BLOCK DIAGRAM....4
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1. GENERAL DESCRIPTION....1
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2. FEATURES....2
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3. SYSTEM APPLICATIONS....3
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4. BLOCK DIAGRAM....4
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5. PIN ASSIGNMENTS ....5
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5.1. PIN ASSIGNMENTS DIAGRAM....5
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5.2. PACKAGE IDENTIFICATION....5
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5.1. PIN ASSIGNMENTS DIAGRAM....5
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5.2. PACKAGE IDENTIFICATION....5
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5.3. PIN ASSIGNMENTS TABLE....6
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6. PIN DESCRIPTIONS....7
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6.1. PIN ASSIGNMENT CODES 7
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6.2. MEDIA CONNECTION PINS 7
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6.3. MISCELLANEOUS PINS 8
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6.4. PORT LED PINS 8
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6.5. STRAPPING PINS....9
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6.6. REGULATOR PINS....9
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6.1. PIN ASSIGNMENT CODES 7
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6.2. MEDIA CONNECTION PINS 7
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6.3. MISCELLANEOUS PINS 8
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6.4. PORT LED PINS 8
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6.5. STRAPPING PINS....9
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6.6. REGULATOR PINS....9
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6.7. POWER AND GND PINS....9
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7. BASIC FUNCTION DESCRIPTIONS....10
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@@ -66,51 +66,51 @@ REVISION HISTORY
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7.1.1. Flow Control....10
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7.1.1.1 IEEE 802.3x Full Duplex Flow Control....10
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7.1.1.1 IEEE 802.3x Full Duplex Flow Control....10
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7.1.1.2 Half Duplex Back Pressure....10
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7.1.2. Address Search, Learning, and Aging....11
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7.1.3. Half Duplex Operation....11
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7.1.4. InterFrame Gap....11
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7.1.2. Address Search, Learning, and Aging....11
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7.1.3. Half Duplex Operation....11
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7.1.4. InterFrame Gap....11
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7.1.5. Illegal Frame....11
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7.2. PHYSICAL LAYER FUNCTIONAL OVERVIEW 12
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7.2.1. Auto-Negotiation....12
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7.2.2. 10Base-T Transmit Function....12
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7.2.3. 10Base-T Receive Function....12
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7.2.4. Link Monitor....12
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7.2.5. 100Base-TX Transmit Function....12
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7.2.6. 100Base-TX Receive Function....12
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7.2.7. Power-Down Mode....13
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7.2.8. Crossover Detection and Auto Correction....13
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7.2.1. Auto-Negotiation....12
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7.2.2. 10Base-T Transmit Function....12
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7.2.3. 10Base-T Receive Function....12
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7.2.4. Link Monitor....12
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7.2.5. 100Base-TX Transmit Function....12
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7.2.6. 100Base-TX Receive Function....12
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7.2.7. Power-Down Mode....13
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7.2.8. Crossover Detection and Auto Correction....13
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7.2.9. Polarity Detection and Correction....13
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7.3. GENERAL FUNCTION OVERVIEW....14
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7.3.1. Power-On Sequence 14
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7.3.2. Setup and Configuration....15
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7.3.1. Power-On Sequence 14
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7.3.2. Setup and Configuration....15
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7.3.3. Serial EEPROM Example....16
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7.3.3.1 EEPROM Device Operation....16
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7.3.3.1 EEPROM Device Operation....16
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7.3.3.2 EEPROM Size Selection....18
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7.3.4. SMI....18
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7.3.5. Head-Of-Line Blocking 18
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7.3.6. Filtering/Forwarding Reserved Control Frame....19
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7.3.7. Loop Detection....19
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7.3.8. Reg.0.14 PHY Digital Loopback Return to Internal....21
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7.3.9. LDO for 1.0V Power Generation 22
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7.3.4. SMI....18
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7.3.5. Head-Of-Line Blocking 18
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7.3.6. Filtering/Forwarding Reserved Control Frame....19
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7.3.7. Loop Detection....19
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7.3.8. Reg.0.14 PHY Digital Loopback Return to Internal....21
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7.3.9. LDO for 1.0V Power Generation 22
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7.3.10. Crystal/Oscillator 22
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## 8. ADVANCED FUNCTION DESCRIPTIONS ....23
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8.1. VLAN FUNCTION ....23
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8.1.1. VLAN Description ....23
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8.1.2. Port-Based VLAN....24
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8.1.3. IEEE 802.1Q Tagged-VID Based VLAN 24
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8.1.4. Insert/Remove/Replace Tag....24
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8.1.1. VLAN Description ....23
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8.1.2. Port-Based VLAN....24
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8.1.3. IEEE 802.1Q Tagged-VID Based VLAN 24
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8.1.4. Insert/Remove/Replace Tag....24
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8.1.5. Ingress and Egress Rules....25
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8.2. IEEE 802.1P REMARKING FUNCTION....25
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@@ -119,46 +119,46 @@ REVISION HISTORY
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8.3.1. Bandwidth Control 26
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8.3.1.1 Output (TX) Bandwidth Control....26
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8.3.1.1 Output (TX) Bandwidth Control....26
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8.3.1.2 Input (RX) Bandwidth Control 27
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8.3.2. Priority Assignment....27
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8.3.2.1 Queue Number Selection....27
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8.3.2.2 Port-Based Priority Assignment....27
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||||
8.3.2.3 IEEE 802.1p/Q-Based Priority Assignment....28
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8.3.2.4 DSCP-Based Priority Assignment 28
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8.3.2.5 IP Address-Based Priority....28
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||||
8.3.2.6 Reassigned Priority....28
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||||
8.3.2.7 RLDP-Based Priority....28
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8.3.2.1 Queue Number Selection....27
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8.3.2.2 Port-Based Priority Assignment....27
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||||
8.3.2.3 IEEE 802.1p/Q-Based Priority Assignment....28
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8.3.2.4 DSCP-Based Priority Assignment 28
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||||
8.3.2.5 IP Address-Based Priority....28
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||||
8.3.2.6 Reassigned Priority....28
|
||||
8.3.2.7 RLDP-Based Priority....28
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||||
8.3.2.8 Packet Priority Selection....29
|
||||
|
||||
8.4. LOOKUP TABLE FUNCTION ....30
|
||||
|
||||
8.4.1. Function Description....30
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||||
8.4.2. Address Search, Learning, and Aging....30
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||||
8.4.1. Function Description....30
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||||
8.4.2. Address Search, Learning, and Aging....30
|
||||
8.4.3. Lookup Table Definition....31
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||||
|
||||
8.5. STORM FILTER FUNCTION....32
|
||||
8.6. INPUT AND OUTPUT DROP FUNCTION 32
|
||||
8.7. LED FUNCTION....33
|
||||
8.8. ENERGY-EFFICIENT ETHERNET (EEE)....34
|
||||
8.5. STORM FILTER FUNCTION....32
|
||||
8.6. INPUT AND OUTPUT DROP FUNCTION 32
|
||||
8.7. LED FUNCTION....33
|
||||
8.8. ENERGY-EFFICIENT ETHERNET (EEE)....34
|
||||
8.9. CABLE DIAGNOSIS 34
|
||||
|
||||
## 9. CHARACTERISTICS....35
|
||||
|
||||
9.1. ELECTRICAL CHARACTERISTICS/MAXIMUM RATINGS ....35
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||||
9.2. OPERATING RANGE....35
|
||||
9.3. DC CHARACTERISTICS....35
|
||||
9.1. ELECTRICAL CHARACTERISTICS/MAXIMUM RATINGS ....35
|
||||
9.2. OPERATING RANGE....35
|
||||
9.3. DC CHARACTERISTICS....35
|
||||
9.4. THERMAL CHARACTERISTICS....36
|
||||
|
||||
9.4.1. Simulation Conditions 36
|
||||
9.4.1. Simulation Conditions 36
|
||||
9.4.2. Thermal Characteristics Results ....36
|
||||
|
||||
9.5. DIGITAL TIMING CHARACTERISTICS ....37
|
||||
|
||||
9.5.1. LED Timing....37
|
||||
9.5.2. Reception/Transmission Data Timing of SMI Interface 37
|
||||
9.5.1. LED Timing....37
|
||||
9.5.2. Reception/Transmission Data Timing of SMI Interface 37
|
||||
9.5.3. EEPROM Auto-Load Timing....38
|
||||
|
||||
## 10. MECHANICAL DIMENSIONS....39
|
||||
@@ -221,26 +221,26 @@ TABLE 25. ORDERING INFORMATION ....41
|
||||
|
||||
## List of Figures
|
||||
|
||||
FIGURE 1. BLOCK DIAGRAM....4
|
||||
FIGURE 2. PIN ASSIGNMENTS ....5
|
||||
FIGURE 3. COLLISION-BASED BACKPRESSURE SIGNAL TIMING....10
|
||||
FIGURE 4. POWER-ON SEQUENCE....14
|
||||
FIGURE 5. RESET 15
|
||||
FIGURE 6. START AND STOP DEFINITION....17
|
||||
FIGURE 7. OUTPUT ACKNOWLEDGE ....17
|
||||
FIGURE 8. RANDOM READ....17
|
||||
FIGURE 9. SEQUENTIAL READ ....17
|
||||
FIGURE 10. LOOP EXAMPLE ....19
|
||||
FIGURE 11. LED AND BUZZER CONTROL SIGNAL FOR LOOP DETECTION ....20
|
||||
FIGURE 12. LOOP EXAMPLE 2 ....21
|
||||
FIGURE 13. REG. 0.14 LOOPBACK ....21
|
||||
FIGURE 14. PACKET-SCHEDULING DIAGRAM....26
|
||||
FIGURE 15. RTL8305NBI PRIORITY ASSIGNMENT DIAGRAM....27
|
||||
FIGURE 16. BROADCAST INPUT DROP VS. OUTPUT DROP....32
|
||||
FIGURE 17. MULTICAST INPUT DROP VS. OUTPUT DROP....32
|
||||
FIGURE 18. FLOATING AND PULL-HIGH OF LED PINS FOR LED ....33
|
||||
FIGURE 19. RECEPTION DATA TIMING OF SMI INTERFACE....37
|
||||
FIGURE 20. TRANSMISSION DATA TIMING OF SMI INTERFACE....37
|
||||
FIGURE 1. BLOCK DIAGRAM....4
|
||||
FIGURE 2. PIN ASSIGNMENTS ....5
|
||||
FIGURE 3. COLLISION-BASED BACKPRESSURE SIGNAL TIMING....10
|
||||
FIGURE 4. POWER-ON SEQUENCE....14
|
||||
FIGURE 5. RESET 15
|
||||
FIGURE 6. START AND STOP DEFINITION....17
|
||||
FIGURE 7. OUTPUT ACKNOWLEDGE ....17
|
||||
FIGURE 8. RANDOM READ....17
|
||||
FIGURE 9. SEQUENTIAL READ ....17
|
||||
FIGURE 10. LOOP EXAMPLE ....19
|
||||
FIGURE 11. LED AND BUZZER CONTROL SIGNAL FOR LOOP DETECTION ....20
|
||||
FIGURE 12. LOOP EXAMPLE 2 ....21
|
||||
FIGURE 13. REG. 0.14 LOOPBACK ....21
|
||||
FIGURE 14. PACKET-SCHEDULING DIAGRAM....26
|
||||
FIGURE 15. RTL8305NBI PRIORITY ASSIGNMENT DIAGRAM....27
|
||||
FIGURE 16. BROADCAST INPUT DROP VS. OUTPUT DROP....32
|
||||
FIGURE 17. MULTICAST INPUT DROP VS. OUTPUT DROP....32
|
||||
FIGURE 18. FLOATING AND PULL-HIGH OF LED PINS FOR LED ....33
|
||||
FIGURE 19. RECEPTION DATA TIMING OF SMI INTERFACE....37
|
||||
FIGURE 20. TRANSMISSION DATA TIMING OF SMI INTERFACE....37
|
||||
FIGURE 21. EEPROM AUTO-LOAD TIMING....38
|
||||
|
||||
## 1. General Description
|
||||
@@ -251,9 +251,9 @@ In order to accomplish diagnostics in complex network systems, the RTL8305NBI pr
|
||||
|
||||
The RTL8305NBI supports several advanced QoS functions with four-level priority queues to improve multimedia or real-time networking applications, including:
|
||||
|
||||
• Multi-priority assignment
|
||||
- Differential queue weight
|
||||
• Port-based rate limitation
|
||||
• Multi-priority assignment
|
||||
- Differential queue weight
|
||||
• Port-based rate limitation
|
||||
- Queue-based rate limitation
|
||||
|
||||
## DRAFT
|
||||
@@ -274,67 +274,67 @@ To simplify the peripheral power circuit, the RTL8305NBI integrates one LDO regu
|
||||
|
||||
## DRAFT
|
||||
|
||||
■ 5-port switch controller with memory and transceiver for 10Base-T and 100Base-TX
|
||||
■ Non-blocking wire-speed reception and transmission and non-head-of-line-blocking forwarding
|
||||
■ Complies with IEEE 802.3/802.3u auto-negotiation
|
||||
■ Built-in high efficiency SRAM for packet buffer, with 2K-entry lookup table and two 4-way associative hash algorithms
|
||||
■ 2048 byte maximum packet length
|
||||
■ Flow control fully supported
|
||||
◆ Half duplex: Back pressure flow control
|
||||
■ 5-port switch controller with memory and transceiver for 10Base-T and 100Base-TX
|
||||
■ Non-blocking wire-speed reception and transmission and non-head-of-line-blocking forwarding
|
||||
■ Complies with IEEE 802.3/802.3u auto-negotiation
|
||||
■ Built-in high efficiency SRAM for packet buffer, with 2K-entry lookup table and two 4-way associative hash algorithms
|
||||
■ 2048 byte maximum packet length
|
||||
■ Flow control fully supported
|
||||
◆ Half duplex: Back pressure flow control
|
||||
◆ Full duplex: IEEE 802.3x flow control
|
||||
|
||||
## Service Quality
|
||||
|
||||
■ Supports high performance QoS function on each port
|
||||
◆ Supports 4-level priority queues
|
||||
◆ Weighted round robin service
|
||||
◆ Supports strict priority
|
||||
◆ Input/Output port bandwidth control
|
||||
◆ Queue-based bandwidth control
|
||||
◆ 1Q-based, Port-based, DSCP-based, IP address-based, and other types of priority assignments
|
||||
■ Supports high performance QoS function on each port
|
||||
◆ Supports 4-level priority queues
|
||||
◆ Weighted round robin service
|
||||
◆ Supports strict priority
|
||||
◆ Input/Output port bandwidth control
|
||||
◆ Queue-based bandwidth control
|
||||
◆ 1Q-based, Port-based, DSCP-based, IP address-based, and other types of priority assignments
|
||||
■ Supports IEEE 802.1p Traffic Remarking
|
||||
|
||||
## DRAFT
|
||||
|
||||
## Security and Management
|
||||
|
||||
■ Supports reserved control frame filtering
|
||||
■ Supports advanced storm filtering
|
||||
■ Supports reserved control frame filtering
|
||||
■ Supports advanced storm filtering
|
||||
■ Optional EEPROM interface for configuration
|
||||
|
||||
## VLAN Functions
|
||||
|
||||
■ Supports up to 16 VLAN groups
|
||||
■ Flexible 802.1Q port/tag-based VLAN
|
||||
■ Supports four IVLs
|
||||
■ Supports up to 16 VLAN groups
|
||||
■ Flexible 802.1Q port/tag-based VLAN
|
||||
■ Supports four IVLs
|
||||
■ Leaky VLAN for unicast/multicast/broadcast/ARP packets
|
||||
|
||||
## Power Saving Functions
|
||||
|
||||
■ Supports Energy-Efficient Ethernet (EEE) function (IEEE 802.3az)
|
||||
■ Supports Energy-Efficient Ethernet (EEE) function (IEEE 802.3az)
|
||||
■ Link Down Power Saving Mode
|
||||
|
||||
## Diagnostic Functions
|
||||
|
||||
■ Supports hardware loop detection function with LEDs and buzzer to indicate the existence of a loop
|
||||
■ Supports cable diagnosis (RTCT function)
|
||||
■ Flexible LED indicators
|
||||
◆ RTCT status indication
|
||||
◆ Loop status indication
|
||||
■ Supports hardware loop detection function with LEDs and buzzer to indicate the existence of a loop
|
||||
■ Supports cable diagnosis (RTCT function)
|
||||
■ Flexible LED indicators
|
||||
◆ RTCT status indication
|
||||
◆ Loop status indication
|
||||
◆ LEDs blink upon reset for LED diagnostics
|
||||
|
||||
## Other Features
|
||||
|
||||
■ Optional MDI/MDIX auto crossover for plug-and-play
|
||||
|
||||
■ Physical layer port Polarity Detection and Correction function
|
||||
■ Robust baseline wander correction for improved 100Base-TX performance
|
||||
■ Physical layer port Polarity Detection and Correction function
|
||||
■ Robust baseline wander correction for improved 100Base-TX performance
|
||||
■ 25MHz crystal or 3.3V OSC input
|
||||
|
||||
## DRAFT
|
||||
|
||||
■ Single 3.3V power input can be transformed by integrating an LDO regulator to generate 1.0V from 3.3V via a low-cost external diode
|
||||
■ Low power, 1.0/3.3V, 55nm CMOS technology
|
||||
■ Single 3.3V power input can be transformed by integrating an LDO regulator to generate 1.0V from 3.3V via a low-cost external diode
|
||||
■ Low power, 1.0/3.3V, 55nm CMOS technology
|
||||
■ 48-pin QFN ‘Green’ package
|
||||
|
||||
## 3. System Applications
|
||||
@@ -560,8 +560,8 @@ If the buffer is ready to overflow, this mechanism will force a collision. When
|
||||
|
||||
The Reschedule procedure is:
|
||||
|
||||
- The RTL8305NBI will drive TXEN to high and send the preamble; SFD and a 4-byte Jam signal (pattern is 0xAA). The RTL8305NBI will then drive TXEN to low
|
||||
- When the link partner receives the Jam signal, it will feedback a 4-byte signal (pattern is CRC^0x01), it will then drive RXDV to low
|
||||
- The RTL8305NBI will drive TXEN to high and send the preamble; SFD and a 4-byte Jam signal (pattern is 0xAA). The RTL8305NBI will then drive TXEN to low
|
||||
- When the link partner receives the Jam signal, it will feedback a 4-byte signal (pattern is CRC^0x01), it will then drive RXDV to low
|
||||
- The link partner waits for a random back-off time then re-sends the packet. The timing is shown in Figure 3
|
||||
|
||||
|
||||
@@ -687,10 +687,10 @@ When the RTL8305NBI operates in 10Base-T mode, it automatically reverses the pol
|
||||
|
||||
Two power voltage types are required for RTL8305NBI normal operation; 3.3V and 1.0V. The 1.0V is converted from 3.3V via the LDO of the RTL8305NBI.
|
||||
|
||||
- Ta is the moment when 3.3V power is higher than 2.6V (±5%). 3.3V power never falls lower than 2.6V (±5%) after Ta
|
||||
- Tb is the moment when 1.0V power is higher than 0.71V (±10%). 1.0V power never falls lower than 0.71V (±10%) after Tb
|
||||
- Tc is the moment when both 3.3V and 1.0V power are stable (the voltage is always in the legal operating range)
|
||||
- Td is the moment that the pin reset signal is de-asserted
|
||||
- Ta is the moment when 3.3V power is higher than 2.6V (±5%). 3.3V power never falls lower than 2.6V (±5%) after Ta
|
||||
- Tb is the moment when 1.0V power is higher than 0.71V (±10%). 1.0V power never falls lower than 0.71V (±10%) after Tb
|
||||
- Tc is the moment when both 3.3V and 1.0V power are stable (the voltage is always in the legal operating range)
|
||||
- Td is the moment that the pin reset signal is de-asserted
|
||||
- Te is the moment that the RTL8305NBI device is ready to be accessed by an external CPU
|
||||
|
||||
|
||||
@@ -712,15 +712,15 @@ Figure 4. Power-On Sequence
|
||||
|
||||
## The requirements are:
|
||||
|
||||
- The time of Ta should be between $500\mu \mathrm{s}$ and $20\mathrm{ms}$
|
||||
- The sequence of Ta is always less than Tb for the LDO of the RTL8305NBI. In principle, the sequence of Td and Ta/Tb/Tc is also not required. The sequence of Td > 5ms is recommended
|
||||
- The time from Te to the later of Ta/Tb/Td is the sum of the time of the EEPROM loading + 30ms. The EEPROM loading time varies according to the autoloaded data bytes in the serial EEPROM
|
||||
- The time of Ta should be between $500\mu \mathrm{s}$ and $20\mathrm{ms}$
|
||||
- The sequence of Ta is always less than Tb for the LDO of the RTL8305NBI. In principle, the sequence of Td and Ta/Tb/Tc is also not required. The sequence of Td > 5ms is recommended
|
||||
- The time from Te to the later of Ta/Tb/Td is the sum of the time of the EEPROM loading + 30ms. The EEPROM loading time varies according to the autoloaded data bytes in the serial EEPROM
|
||||
- Reset
|
||||
|
||||
Depending on the type of reset, the whole or just part of the RTL8305NBI is initialized. There are several ways to reset the RTL8305NBI.
|
||||
|
||||
- Hardware reset for the whole chip via pin RESET# or power-on
|
||||
- Soft reset for packet buffer, queue, and MIB counter via register SoftReset
|
||||
- Hardware reset for the whole chip via pin RESET# or power-on
|
||||
- Soft reset for packet buffer, queue, and MIB counter via register SoftReset
|
||||
• PHY software reset for each PHY by register reset
|
||||
|
||||
Hardware Reset: Power-on, or pull the RESET# pin low for at least 1μs. The RTL8305NBI resets the whole chip and after all power is ready and the RESET# pin is de-asserted, it gets initial values from pins and serial EEPROM.
|
||||
@@ -729,7 +729,7 @@ Soft Reset: The RTL8305NBI does not reset the LUT, LED circuit, and all register
|
||||
|
||||
PHY Software Reset: Write bit15 of Reg0 of a PHY as 1. The RTL8305NBI will then reset this PHY.
|
||||
|
||||
|
||||
|
||||
Figure 5. Reset
|
||||
|
||||
Some setting values for operation modes are latched from those corresponding mode pins upon hardware reset. ‘Upon reset’ is defined as a short time after the end of a hardware reset. Other advanced configuration parameters may be latched from serial EEPROM.
|
||||
@@ -738,19 +738,19 @@ Some setting values for operation modes are latched from those corresponding mod
|
||||
|
||||
The RTL8305NBI can be configured easily and flexibly by:
|
||||
|
||||
• Hardware pins upon reset
|
||||
- Optional serial EEPROM upon reset (contact Realtek for detailed EEPROM configuration settings)
|
||||
• Hardware pins upon reset
|
||||
- Optional serial EEPROM upon reset (contact Realtek for detailed EEPROM configuration settings)
|
||||
- Internal registers (including PHY registers for each port and global MAC registers) accessed via SMI (Serial Management Interface: MDC/MDIO, also known as MII Management Interface)
|
||||
|
||||
There are three methods of configuration:
|
||||
|
||||
- Only hardware pins for normal switch applications
|
||||
• Hardware pins and serial EEPROM for advanced switch applications
|
||||
- Only hardware pins for normal switch applications
|
||||
• Hardware pins and serial EEPROM for advanced switch applications
|
||||
- Hardware pins and internal registers via SMI for applications with processor
|
||||
|
||||
Two types of pins, each with internal pull-high or pull-low resistors, are used for configuration:
|
||||
|
||||
- Input/Output pins used for strapping upon reset and used as output pins after reset
|
||||
- Input/Output pins used for strapping upon reset and used as output pins after reset
|
||||
- Input/Output pins used for strapping upon reset and used as LED indicator pins after reset. The LED statuses are represented as active-low or high depending on input strapping
|
||||
|
||||
Pins with default value=0 are internal pull-low and use I/O pads. They can be left floating to set the input value as low, but should not be connected to VDD without a pull-high resistor.
|
||||
@@ -889,7 +889,7 @@ The RTL8305NBI incorporates a mechanism to prevent Head-Of-Line blocking problem
|
||||
|
||||
The RTL8305NBI supports the ability to forward or drop the frames of the IEEE 802.1 specified reserved Ethernet multicast addresses.
|
||||
|
||||
Table 10. Reserved Ethernet Multicast Addresses
|
||||
Table 10. Reserved Ethernet Multicast Addresses
|
||||
B: Broadcast (Search the Look-Up Table) D: Drop
|
||||
|
||||
<table><tr><td>Assignment</td><td>Value</td><td>Available Action</td></tr><tr><td>Bridge Group Address</td><td>01-80-C2-00-00-00</td><td>D, B (Default)</td></tr><tr><td>IEEE Std 802.3, 1988 Edition, Full Duplex PAUSE Operation</td><td>01-80-C2-00-00-01</td><td>D (Default), B</td></tr><tr><td>IEEE 802.3ad Slow_Protocols-Multicast Address</td><td>01-80-C2-00-00-02</td><td>D (Default), B</td></tr><tr><td>IEEE 802.1X PAE Address</td><td>01-80-C2-00-00-03</td><td>D, B (Default)</td></tr><tr><td>Reserved for Future Standards</td><td>01-80-C2-00-00-04~01-80-C2-00-00-0D, 01-80-C2-00-00-0F</td><td>D (Default), B</td></tr><tr><td>LLDP IEEE Std 802.1AB Link Layer Discovery Protocol Multicast Address</td><td>01-80-C2-00-00-0E</td><td>D, B (Default)</td></tr><tr><td>All LANs Bridge Management Group Address</td><td>01-80-C2-00-00-10</td><td>D (Default), B</td></tr><tr><td>Reserved for 01-80-C2-00-00-1x</td><td>01-80-C2-00-00-11~01-80-C2-00-00-1F</td><td>D, B (Default)</td></tr><tr><td>GMRP Address</td><td>01-80-C2-00-00-20</td><td>D (Default), B</td></tr><tr><td>GVRP Address</td><td>01-80-C2-00-00-21</td><td>D, B (Default)</td></tr><tr><td>Reserved for use by Multiple Registration Protocol (MRP) Applications</td><td>01-80-C2-00-00-22~01-80-C2-00-00-2F</td><td>D (Default), B</td></tr><tr><td>802.1ag PDU CCM/LTM</td><td>01-80-C2-00-00-31~01-80-C2-00-00-3F</td><td>D, B (Default)</td></tr></table>
|
||||
@@ -915,18 +915,18 @@ Figure 10. Loop Example
|
||||
|
||||
The loop detect function can be enabled/disabled via strapping pin or registers. When the loop detection function is enabled, the RTL8305NBI sends out a broadcast 64-byte loop frame (the frequency is configured by register) and sniffs for the sent loop frame on each port to detect whether there is a network loop (or bridge loop). If a loop is detected, the RTL8305NBI will drive the external LEDs and buzzer alarm.
|
||||
|
||||
• The LED driven by the LDIND pin will blink
|
||||
- The LEDs driven by port LED pins (see Table 4, page 8) of the ports on which the network loop is detected will all blink simultaneously
|
||||
• The LED driven by the LDIND pin will blink
|
||||
- The LEDs driven by port LED pins (see Table 4, page 8) of the ports on which the network loop is detected will all blink simultaneously
|
||||
- The buzzer driven by the LDIND pin will buzz at the same frequency as the LED blinking
|
||||
|
||||
Both passive and active buzzers can be supported. The resonant frequency for the passive buzzer is approximately 2kHz. The buzzer and all LEDs will turn on/off simultaneously. In Figure 11, T1 is the turned-off period and T2 is the turned-on period. T1 and T2 are equal and can be configured to 400ms or 800ms.
|
||||
|
||||
|
||||
|
||||
Figure 11. LED and Buzzer Control Signal for Loop Detection
|
||||
|
||||
Loop status, LED, and buzzer indications can be cleared when one of the following conditions occurs.
|
||||
|
||||
- Loop frame is not detected in the next loop detection period
|
||||
- Loop frame is not detected in the next loop detection period
|
||||
• The loop port links down
|
||||
|
||||
The Loop frame length is 64 bytes. Its format is shown below.
|
||||
@@ -1014,11 +1014,11 @@ The priority assigned to all ingress packets of the VLAN specified by the VID fi
|
||||
|
||||
The main VLAN features of the RTL8305NBI are as follows:
|
||||
|
||||
• Supports up to 16 VLAN groups
|
||||
• Flexible IEEE 802.1Q port/tag-based VLAN
|
||||
- Four IVLs
|
||||
- Leaky VLAN for ARP broadcast/unicast/multicast packets
|
||||
- Leaky inter-VLAN mirror function
|
||||
• Supports up to 16 VLAN groups
|
||||
• Flexible IEEE 802.1Q port/tag-based VLAN
|
||||
- Four IVLs
|
||||
- Leaky VLAN for ARP broadcast/unicast/multicast packets
|
||||
- Leaky inter-VLAN mirror function
|
||||
- VLAN tag Insert/Remove function
|
||||
|
||||
## 8.1.2. Port-Based VLAN
|
||||
@@ -1047,8 +1047,8 @@ The RTL8305NBI supports the VLAN Insertion/Removal/replacing action for each por
|
||||
|
||||
The RTL8305NBI provides flexible VLAN ingress and egress rules to permit comprehensive traffic control. The RTL8305NBI can filter packets on ingress according to the tag condition of the packet. For a normalized VLAN application and VLAN translation application, each of the RTL8305NBI ports can be independently configured to:
|
||||
|
||||
- ‘admit all frames’
|
||||
- ‘admit only tagged frames’
|
||||
- ‘admit all frames’
|
||||
- ‘admit only tagged frames’
|
||||
- ‘admit only untagged frames’
|
||||
|
||||
Note: The priority tagged frame (VID=0) will be treated as an untagged frame.
|
||||
@@ -1057,10 +1057,10 @@ The RTL8305NBI can optionally discard a frame associated with a VLAN of which th
|
||||
|
||||
For the egress filter, the RTL8305NBI drops the frame if this frame belongs to a VLAN but its egress port is not one of the VLAN's member ports. However, there are 5 leaky options to provide exceptions for special applications.
|
||||
|
||||
- ‘Unicast leaky VLAN’ enables inter-VLAN unicast packet forwarding. That is, if the layer 2 lookup table search has a hit, then the unicast packet will be forwarded to the egress port, ignoring the egress rule
|
||||
- ‘Multicast leaky VLAN’ enables inter-VLAN multicast packet forwarding. Packets may be flooded to all the multicast address group member sets, ignoring the VLAN member set domain limitation
|
||||
- ‘Broadcast leaky VLAN’ enables inter-VLAN broadcast packet forwarding. Packets may be flooded to all the other ports, ignoring the VLAN member set domain limitation
|
||||
- ‘ARP leaky VLAN’ enables broadcasting of ARP packets to all other ports, ignoring the egress rule
|
||||
- ‘Unicast leaky VLAN’ enables inter-VLAN unicast packet forwarding. That is, if the layer 2 lookup table search has a hit, then the unicast packet will be forwarded to the egress port, ignoring the egress rule
|
||||
- ‘Multicast leaky VLAN’ enables inter-VLAN multicast packet forwarding. Packets may be flooded to all the multicast address group member sets, ignoring the VLAN member set domain limitation
|
||||
- ‘Broadcast leaky VLAN’ enables inter-VLAN broadcast packet forwarding. Packets may be flooded to all the other ports, ignoring the VLAN member set domain limitation
|
||||
- ‘ARP leaky VLAN’ enables broadcasting of ARP packets to all other ports, ignoring the egress rule
|
||||
- ‘Inter-VLAN mirror function’ enables the inter-VLAN mirror function, ignoring the VLAN member set domain limitation. The default value is ‘Enable the inter-VLAN mirror’
|
||||
|
||||
## 8.2. IEEE 802.1p Remarking Function
|
||||
@@ -1083,8 +1083,8 @@ The RTL8305NBI supports MIN-MAX packet scheduling.
|
||||
|
||||
Packet scheduling offers three modes:
|
||||
|
||||
- Type I leaky bucket, which specifies the average rate of one queue (see Figure 14; only Q2 and Q3 have leaky bucket, Q0 and Q1 do not). The queue rate can be configured from 0kbps to the line rate in steps of 64kbps
|
||||
- Weighted Round Robin (WRR), which decides which queue is selected in one slot time to guarantee the minimal packet rate of one queue
|
||||
- Type I leaky bucket, which specifies the average rate of one queue (see Figure 14; only Q2 and Q3 have leaky bucket, Q0 and Q1 do not). The queue rate can be configured from 0kbps to the line rate in steps of 64kbps
|
||||
- Weighted Round Robin (WRR), which decides which queue is selected in one slot time to guarantee the minimal packet rate of one queue
|
||||
- Port bandwidth control (type II leaky bucket) to control the bandwidth of the whole port. The port rate can be configured from 0kbps to the line rate in steps of 64kbps
|
||||
|
||||
In addition, the RTL8305NBI can select one of the two sets of packet-scheduling configurations according to the packet-scheduling mode. Figure 14 shows the RTL8305NBI packet-scheduling diagram.
|
||||
@@ -1131,11 +1131,11 @@ Priority assignment specifies the priority of a received packet according to var
|
||||
|
||||
The RTL8305NBI identifies the priority of packets based on several types of QoS priority information:
|
||||
|
||||
• Port-based priority
|
||||
• IEEE 802.1p/Q VLAN Priority Tag
|
||||
- DSCP Priority field
|
||||
- IP Address
|
||||
• Reassigned priority
|
||||
• Port-based priority
|
||||
• IEEE 802.1p/Q VLAN Priority Tag
|
||||
- DSCP Priority field
|
||||
- IP Address
|
||||
• Reassigned priority
|
||||
- RLDP priority
|
||||
|
||||
Below is a block diagram of the priority assignment.
|
||||
@@ -1204,9 +1204,9 @@ To support the loop detection effectively, the RTL8305NBI provides the RLDP-base
|
||||
|
||||
As one received packet may simultaneously support several priority assignment mechanisms, e.g., Port-Based Priority, 1Q-Based Priority, DSCP-Based Priority, it may get several different priority values.
|
||||
|
||||
- RLDP-based priority has the highest priority
|
||||
- If RLDP-based priority is disabled, the final priority is equal to the reassigned priority
|
||||
- If RLDP-based priority and reassigned priority is disabled, the final priority is equal to the IP address priority
|
||||
- RLDP-based priority has the highest priority
|
||||
- If RLDP-based priority is disabled, the final priority is equal to the reassigned priority
|
||||
- If RLDP-based priority and reassigned priority is disabled, the final priority is equal to the IP address priority
|
||||
- If RLDP-based priority, reassigned priority and IP address priority are disabled, the following rules are used to decide a final priority for the other five types of priority
|
||||
|
||||
There is a 2-bit register for each of the three types of priority that represent the weight of the priority. The higher value in the register indicates a higher weight for the priority. If more than one of the three types of priority is the same, the final priority will be the one of the three types, whose priority value is greatest.
|
||||
@@ -1219,8 +1219,8 @@ The 2-bit priority has four numbers; however, every port has at most four output
|
||||
|
||||
## 8.4.1. Function Description
|
||||
|
||||
• 2048-entry Lookup Table (LUT)
|
||||
• 4-way entry for each entry index
|
||||
• 2048-entry Lookup Table (LUT)
|
||||
• 4-way entry for each entry index
|
||||
- Supports LRU (Least Recently Used) function for lookup table learning
|
||||
|
||||
## 8.4.2. Address Search, Learning, and Aging
|
||||
@@ -1291,12 +1291,12 @@ If some destination ports are blocking, or the buffer is full, the frames to the
|
||||
|
||||
There are two types of drop:
|
||||
|
||||
- Input Drop: Drop the frame directly. Do not forward to any port
|
||||
- Input Drop: Drop the frame directly. Do not forward to any port
|
||||
- Output Drop: Forward only to non-blocking ports
|
||||
|
||||
For the RTL8305NBI, the dropping of broadcast, multicast, and unknown DA frames can be controlled independently.
|
||||
|
||||
1. Broadcast packet from Port 0.
|
||||
1. Broadcast packet from Port 0.
|
||||
2. Buffer of Port 4 is full, others are not full.
|
||||
|
||||
|
||||
@@ -1332,7 +1332,7 @@ graph LR
|
||||
|
||||
Figure 16. Broadcast Input Drop vs. Output Drop
|
||||
|
||||
1. Multicast packet from Port 0.
|
||||
1. Multicast packet from Port 0.
|
||||
2. Buffer of Port 4 is full, Port 1 is not full.
|
||||
|
||||
|
||||
@@ -1381,7 +1381,7 @@ Some LED pins are dual function pins: input operation for configuration upon res
|
||||
|
||||
Figure 18 shows example circuits for LEDs. Typical values for pull-down resistors are 10KΩ.
|
||||
|
||||
|
||||
|
||||
Figure 18. Floating and Pull-High of LED Pins for LED
|
||||
|
||||
## 8.8. Energy-Efficient Ethernet (EEE)
|
||||
@@ -1392,7 +1392,7 @@ At the transmitter side, the RTL8305NBI port 0\~4 can automatically enter or qui
|
||||
|
||||
There are two types of wake-up:
|
||||
|
||||
- Packets in a high priority queue or a control packet (e.g., a PAUSE frame). These can wake up the port immediately
|
||||
- Packets in a high priority queue or a control packet (e.g., a PAUSE frame). These can wake up the port immediately
|
||||
- Packet in a low priority queue that reach a preset number. A port in LPI mode can be woken up by low priority packets when the number of the cumulated low priority packets exceeds the preset threshold or a delay timer expires
|
||||
|
||||
At the receiver side, each embedded PHY of the RTL8305NBI will automatically respond to the request from the link partner to enter or quit the LPI mode.
|
||||
@@ -1429,11 +1429,11 @@ Table 18. DC Characteristics
|
||||
|
||||
<table><tr><td>Parameter</td><td>SYM</td><td>Condition</td><td>Min</td><td>Typical</td><td>Max</td><td>Units</td></tr><tr><td>TTL Input High Voltage</td><td> $V_{ih}$ </td><td>-</td><td>2.0</td><td>-</td><td>-</td><td>V</td></tr><tr><td>TTL Input Low Voltage</td><td> $V_{il}$ </td><td>-</td><td>-</td><td>-</td><td>0.8</td><td>V</td></tr><tr><td>TTL Input Current</td><td> $I_{in}$ </td><td>-</td><td>-10</td><td>-</td><td>10</td><td>μA</td></tr><tr><td>TTL Input Capacitance</td><td> $C_{in}$ </td><td>-</td><td>-</td><td>3</td><td>-</td><td>pF</td></tr><tr><td>Output High Voltage</td><td> $V_{oh}$ </td><td>-</td><td>2.25</td><td>-</td><td>-</td><td>V</td></tr><tr><td>Output Low Voltage</td><td> $V_{ol}$ </td><td>-</td><td>-</td><td>-</td><td>0.4</td><td>V</td></tr><tr><td>Output Three State Leakage Current</td><td> $|I_{OZ}|$ </td><td>-</td><td>-</td><td>-</td><td>10</td><td>μA</td></tr><tr><td rowspan="5">Power Supply Current for 1.0V</td><td rowspan="5">Icc</td><td>10Base-T, idle</td><td>-</td><td>31</td><td>-</td><td rowspan="5">mA</td></tr><tr><td>10Base-T, Peak continuous 100% utilization</td><td>-</td><td>32</td><td>-</td></tr><tr><td>100Base-TX, idle</td><td>-</td><td>81</td><td>-</td></tr><tr><td>100Base-TX, Peak continuous 100% utilization</td><td>-</td><td>81</td><td>-</td></tr><tr><td>Link down</td><td>-</td><td>30</td><td>-</td></tr><tr><td rowspan="5">Power Supply Current for 3.3V</td><td rowspan="5">Icc</td><td>10Base-T, idle</td><td>-</td><td>18</td><td>-</td><td rowspan="5">mA</td></tr><tr><td>10Base-T, Peak continuous 100% utilization</td><td>-</td><td>81</td><td>-</td></tr><tr><td>100Base-TX, idle</td><td>-</td><td>95</td><td>-</td></tr><tr><td>100Base-TX, Peak continuous 100% utilization</td><td>-</td><td>95</td><td>-</td></tr><tr><td>Link down</td><td>-</td><td>18</td><td>-</td></tr><tr><td rowspan="5">Total Power Consumption for All Ports</td><td rowspan="5">PS</td><td>10Base-T, idle</td><td>-</td><td>89.4</td><td>-</td><td>mW</td></tr><tr><td>10Base-T, Peak continuous 100% utilization</td><td>-</td><td>301.6</td><td>-</td><td></td></tr><tr><td>100Base-TX, idle</td><td>-</td><td>391.5</td><td>-</td><td></td></tr><tr><td>100Base-TX, Peak continuous 100% utilization</td><td>-</td><td>393.5</td><td>-</td><td></td></tr><tr><td>Link down</td><td>-</td><td>89.4</td><td>-</td><td></td></tr></table>
|
||||
|
||||
Note: All power supply currents are measured under the following conditions:
|
||||
1. DVDDL=AVDDL=AVDDHPLL=1.0V; DVDDH=AVDDH=AVDDHPLL=3.3V.
|
||||
2. Room temperature.
|
||||
3. The EEE and Green features are disabled.
|
||||
4. All LEDs are in low-active mode.
|
||||
Note: All power supply currents are measured under the following conditions:
|
||||
1. DVDDL=AVDDL=AVDDHPLL=1.0V; DVDDH=AVDDH=AVDDHPLL=3.3V.
|
||||
2. Room temperature.
|
||||
3. The EEE and Green features are disabled.
|
||||
4. All LEDs are in low-active mode.
|
||||
5. LDO power is not included.
|
||||
|
||||
## 9.4. Thermal Characteristics
|
||||
@@ -1525,7 +1525,7 @@ Table 24. EEPROM Auto-Load Timing Characteristics
|
||||
|
||||
<table><tr><td rowspan="2">Symbol</td><td colspan="3">Dimension in mm</td><td colspan="3">Dimension in inch</td></tr><tr><td>Min</td><td>Nom</td><td>Max</td><td>Min</td><td>Nom</td><td>Max</td></tr><tr><td>A</td><td>0.75</td><td>0.85</td><td>1.00</td><td>0.030</td><td>0.034</td><td>0.039</td></tr><tr><td>A1</td><td>0.00</td><td>0.02</td><td>0.05</td><td>0.000</td><td>0.001</td><td>0.002</td></tr><tr><td>A3</td><td colspan="3">0.20 REF</td><td colspan="3">0.008 REF</td></tr><tr><td>b</td><td>0.15</td><td>0.20</td><td>0.25</td><td>0.006</td><td>0.008</td><td>0.010</td></tr><tr><td>D/E</td><td colspan="3">6.00BSC</td><td colspan="3">0.236BSC</td></tr><tr><td>D2/E2</td><td>4.15</td><td>4.4</td><td>4.65</td><td>0.163</td><td>0.173</td><td>0.183</td></tr><tr><td>e</td><td colspan="3">0.40BSC</td><td colspan="3">0.016BSC</td></tr><tr><td>L</td><td>0.30</td><td>0.40</td><td>0.50</td><td>0.012</td><td>0.016</td><td>0.020</td></tr></table>
|
||||
|
||||
Note 1: CONTROLLING DIMENSION: MILLIMETER (mm).
|
||||
Note 1: CONTROLLING DIMENSION: MILLIMETER (mm).
|
||||
Note 2: REFERENCE DOCUMENT: JEDEC MO-220.
|
||||
|
||||
## 11. Ordering Information
|
||||
@@ -1546,4 +1546,4 @@ Hsinchu Science Park, Hsinchu 300, Taiwan
|
||||
|
||||
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
|
||||
|
||||
www.realtek.com
|
||||
www.realtek.com
|
||||
|
||||
+45
-45
@@ -16,34 +16,34 @@ SD2506API内置单路定时/报警中断输出,报警中断时间可最长设至
|
||||
|
||||
## 2.特性
|
||||
|
||||
低功耗： 0.8μA 典型值(内部电池供电，Ta=25℃)。
|
||||
工作电压：2.7V～5.5V，工作温度：-30℃～+80℃。
|
||||
标准IIC总线接口方式,最高速度400KHZ(4.5V～5.5V)。
|
||||
年、月、日、星期、时、分、秒的BCD码输入/输出,并可通过独立的地址访问各时间寄存器。
|
||||
闰年自动调整功能(从2000年～2099年)。
|
||||
可选择12/24小时制式.
|
||||
. 内置年、月、日、星期、时、分、秒共7字节的报警数据寄存器及1字节的报警允许寄存器。
|
||||
内置70字节通用SRAM寄存器可用于存储用户的一般数据。
|
||||
三种中断均可选择从INT脚输出,并具有两个中断标志位。
|
||||
内置年、月、日、星期、时、分、秒共7字节的报警数据寄存器及1字节的报警允许寄存器，共有96种组合报警方式，并有单事件报警和周期性报警两种中断输出模式，报警时间最长可设至100年。
|
||||
低功耗： 0.8μA 典型值(内部电池供电，Ta=25℃)。
|
||||
工作电压：2.7V～5.5V，工作温度：-30℃～+80℃。
|
||||
标准IIC总线接口方式,最高速度400KHZ(4.5V～5.5V)。
|
||||
年、月、日、星期、时、分、秒的BCD码输入/输出,并可通过独立的地址访问各时间寄存器。
|
||||
闰年自动调整功能(从2000年～2099年)。
|
||||
可选择12/24小时制式.
|
||||
. 内置年、月、日、星期、时、分、秒共7字节的报警数据寄存器及1字节的报警允许寄存器。
|
||||
内置70字节通用SRAM寄存器可用于存储用户的一般数据。
|
||||
三种中断均可选择从INT脚输出,并具有两个中断标志位。
|
||||
内置年、月、日、星期、时、分、秒共7字节的报警数据寄存器及1字节的报警允许寄存器，共有96种组合报警方式，并有单事件报警和周期性报警两种中断输出模式，报警时间最长可设至100年。
|
||||
周期性频率中断输出:从4096Hz～1/16Hz……1秒共十四种方波脉冲.
|
||||
|
||||
自动重置的三字节共24位的倒计时定时器,可选的2种时钟源（4096Hz、1024Hz）。
|
||||
内置8bit转换结果的数字温度传感器，为了节省电池电量消耗，设为VDD模式下60S间隔测温一次，电池模式600S间隔测温一次。
|
||||
内置记录历史高、低温发生时刻及相关温度值的功能；可设置高、低温报警值并从INT脚输出中断。
|
||||
内置晶振和谐振电容，模块内部通过高精度补偿方法，实现在宽温范围内高精度的计时功能，其中25℃精度<±3.8ppm，即时钟年误差小于2分钟(在25±1℃下)。
|
||||
内置充电电池及充电电路，累计电池电量超过550mAH,在电池满充的常温情况下内部时钟走时时间在8个月左右，电池使用寿命为5～8年时间。
|
||||
内置电池电压检测功能，可读取当前电池电压值(三位有效数)，设置高低电池报警电压值并从INT脚输出中断。
|
||||
模块依据不同的电压自动从VDD切换到VBAT或从VBAT切换到VDD。当模块检测到主电源VDD掉到2.4V电压以下且VDD小于VBAT,模块会转为由接在VBAT的后备电池供电；当VDD大于VBAT或VDD大于2.4V,则模块会转为由VDD供电。（内置电源模式指示位PMF,VDD模式时PMF=0，VBAT模式时PMF=1）。
|
||||
内置总线0.5秒自动复位功能(从Start命令开始计时)，保证时钟数据的有效性及可靠性,避免IIC总线挂死问题。
|
||||
内置三个时钟数据写保护位, 避免对数据的误写操作，可更好地保护数据。
|
||||
内置软件可控VBAT模式IIC总线通信禁止功能（BATIIC=0，VBAT模式下禁止IIC通信；BATIIC=1，VBAT模式下允许IIC通信.上电默认值BATIIC=0)，从而避免在电池供电时CPU对时钟操作所消耗的电池电量，也可避免在VDD上、下电的过程中因CPU的I/O端口所输出的不受控的杂波信号对时钟模块的误写操作，进一步提高时钟模块的可靠性。
|
||||
在VBAT模式下，模块具有中断输出允许或禁止的功能,可满足在备用电池供电时输出中断的需要。
|
||||
内置上电复位电路及指示位RTCF，当包括电池在内的所有电源第一次上电时该位置1。
|
||||
内置电源稳压,内部计时电压可低至2.0V。
|
||||
内置8字节的ID码，模块出厂之前设定的、全球唯一的身份识别码。
|
||||
模块在兴威帆的评估板上可通过4KV的群脉冲(EFT)干扰
|
||||
CMOS工艺。
|
||||
自动重置的三字节共24位的倒计时定时器,可选的2种时钟源（4096Hz、1024Hz）。
|
||||
内置8bit转换结果的数字温度传感器，为了节省电池电量消耗，设为VDD模式下60S间隔测温一次，电池模式600S间隔测温一次。
|
||||
内置记录历史高、低温发生时刻及相关温度值的功能；可设置高、低温报警值并从INT脚输出中断。
|
||||
内置晶振和谐振电容，模块内部通过高精度补偿方法，实现在宽温范围内高精度的计时功能，其中25℃精度<±3.8ppm，即时钟年误差小于2分钟(在25±1℃下)。
|
||||
内置充电电池及充电电路，累计电池电量超过550mAH,在电池满充的常温情况下内部时钟走时时间在8个月左右，电池使用寿命为5～8年时间。
|
||||
内置电池电压检测功能，可读取当前电池电压值(三位有效数)，设置高低电池报警电压值并从INT脚输出中断。
|
||||
模块依据不同的电压自动从VDD切换到VBAT或从VBAT切换到VDD。当模块检测到主电源VDD掉到2.4V电压以下且VDD小于VBAT,模块会转为由接在VBAT的后备电池供电；当VDD大于VBAT或VDD大于2.4V,则模块会转为由VDD供电。（内置电源模式指示位PMF,VDD模式时PMF=0，VBAT模式时PMF=1）。
|
||||
内置总线0.5秒自动复位功能(从Start命令开始计时)，保证时钟数据的有效性及可靠性,避免IIC总线挂死问题。
|
||||
内置三个时钟数据写保护位, 避免对数据的误写操作，可更好地保护数据。
|
||||
内置软件可控VBAT模式IIC总线通信禁止功能（BATIIC=0，VBAT模式下禁止IIC通信；BATIIC=1，VBAT模式下允许IIC通信.上电默认值BATIIC=0)，从而避免在电池供电时CPU对时钟操作所消耗的电池电量，也可避免在VDD上、下电的过程中因CPU的I/O端口所输出的不受控的杂波信号对时钟模块的误写操作，进一步提高时钟模块的可靠性。
|
||||
在VBAT模式下，模块具有中断输出允许或禁止的功能,可满足在备用电池供电时输出中断的需要。
|
||||
内置上电复位电路及指示位RTCF，当包括电池在内的所有电源第一次上电时该位置1。
|
||||
内置电源稳压,内部计时电压可低至2.0V。
|
||||
内置8字节的ID码，模块出厂之前设定的、全球唯一的身份识别码。
|
||||
模块在兴威帆的评估板上可通过4KV的群脉冲(EFT)干扰
|
||||
CMOS工艺。
|
||||
封装形式:8脚的DIP封装。
|
||||
|
||||
## 3.原理框图和管脚定义
|
||||
@@ -162,8 +162,8 @@ GND
|
||||
|
||||
注:
|
||||
|
||||
1.在上电复位时，芯片内部不对实时时钟数据寄存器作清零或置位处理。
|
||||
2.当写实时时间数据时 $\mathrm { ( 0 0 H \widetilde { \Omega } 0 6 H ) }$ ,不可以单独对 7 个时间数据中的某一位进行写操作,否则可能会引起时间数据的错误进位,所以要修改其中某一个数据, 应一次性写入全部 7 个实时时钟数据。
|
||||
1.在上电复位时，芯片内部不对实时时钟数据寄存器作清零或置位处理。
|
||||
2.当写实时时间数据时 $\mathrm { ( 0 0 H \widetilde { \Omega } 0 6 H ) }$ ,不可以单独对 7 个时间数据中的某一位进行写操作,否则可能会引起时间数据的错误进位,所以要修改其中某一个数据, 应一次性写入全部 7 个实时时钟数据。
|
||||
3. 当芯片收到读实时时钟数据命令,则所有实时时钟数据被锁存（时钟走时并不受影
|
||||
|
||||
响）,此功能可以避免时间数据的错读现象。
|
||||
@@ -198,7 +198,7 @@ INT脚中断输出选通表
|
||||
|
||||
特别：
|
||||
|
||||
1.当日报警与星期报警均被允许即 EAD=EAW=1时，只有日报警有效,而星期报警无效，所以时间报警中断共有 96种组合方式。
|
||||
1.当日报警与星期报警均被允许即 EAD=EAW=1时，只有日报警有效,而星期报警无效，所以时间报警中断共有 96种组合方式。
|
||||
2.星期报警寄存器的数据格式与实时时钟数据星期的格式不同,星期报警寄存器的位AW6、AW5、AW4、AW3、AW2、AW1、AW0分别对应星期六、星期五、星期四、星期三、星期二、
|
||||
|
||||
星期一、星期日,并可多位置 1,例如 AW6,AW1=1,其它位为 0,则对应在星期六，星期一会有报警。
|
||||
@@ -534,10 +534,10 @@ SD2506API 写数据示例(向 14H,15H 地址写数据):
|
||||
|
||||
特别注意:
|
||||
|
||||
1．除了 WRTC1、WRTC2、WRTC3 三个写允许位，对寄存器(00H\~71H)的写操作必须确认模块处于写允状态,否则写无效。
|
||||
2．写时间同步：每次对实时时间秒寄存器的写操作时，当秒数据的 8个 bit完全写入并收到 ACK信号后，就会对秒以下的内部计数器清零，使时间同步。
|
||||
3. 从当前地址开始,每次读写完一个字节地址自动加 1。
|
||||
4．如果写入的时间数据不存在,则不改写相对应的时间寄存器的值。
|
||||
1．除了 WRTC1、WRTC2、WRTC3 三个写允许位，对寄存器(00H\~71H)的写操作必须确认模块处于写允状态,否则写无效。
|
||||
2．写时间同步：每次对实时时间秒寄存器的写操作时，当秒数据的 8个 bit完全写入并收到 ACK信号后，就会对秒以下的内部计数器清零，使时间同步。
|
||||
3. 从当前地址开始,每次读写完一个字节地址自动加 1。
|
||||
4．如果写入的时间数据不存在,则不改写相对应的时间寄存器的值。
|
||||
5．为了提高数据的可靠性，当写完成后，应将模块置于写禁止状态。（参见 5.7）
|
||||
|
||||
（4）SD2506API 数据传输的读模式
|
||||
@@ -606,7 +606,7 @@ SD2506API 内置电池充电电路,当 VDD 电压正常时,内部充电自动进
|
||||
|
||||
## 特别提示：
|
||||
|
||||
1.为了保证充电功能的正常运行，用户的程序须在每一次上电时重置 18H 寄存器的值为 82H。
|
||||
1.为了保证充电功能的正常运行，用户的程序须在每一次上电时重置 18H 寄存器的值为 82H。
|
||||
2.对内置充电电池的时钟模块不上电充电时间不能超过 8 个月，不要等电池的电耗光后再去充电，否则会减少电池的使用寿命。
|
||||
|
||||
## 8.上电复位
|
||||
@@ -615,7 +615,7 @@ SD2506API 内置电池充电电路,当 VDD 电压正常时,内部充电自动进
|
||||
|
||||
## 9.使用说明
|
||||
|
||||
1.为了防止电路噪声问题,请在此模块的旁边放置两个旁路电容,分别是 0.1uF 电容和10uF 电容。
|
||||
1.为了防止电路噪声问题,请在此模块的旁边放置两个旁路电容,分别是 0.1uF 电容和10uF 电容。
|
||||
2.为了防止干扰,在 PCB 制作时请保证模块底部无大电流信号通过,最好能铺地。
|
||||
|
||||
## 10. 应用参考电路
|
||||
@@ -645,7 +645,7 @@ VDD 、VBAT 、SCL、SDA 和 INT 引脚上的电压（相对于地）………
|
||||
|
||||
注：
|
||||
|
||||
1.因模块内置电池本体的表面温度不能超过 85℃，本产品不可以采用回流焊或波峰焊方式，最好采用烙铁焊接方式。
|
||||
1.因模块内置电池本体的表面温度不能超过 85℃，本产品不可以采用回流焊或波峰焊方式，最好采用烙铁焊接方式。
|
||||
2.强度超出所列的极限参数可能导致器件的永久性损坏。这些仅仅是极限参数，并不意味着在极限条件下或在任何其它超出推荐工作条件所示参数的情况下器件能有效地工作。延长在极限参数条件上的工作时间会影响器件的可靠性。
|
||||
|
||||
## 12.直流特性
|
||||
@@ -662,7 +662,7 @@ Note1:此时最大电流 2mA主要是充电电流.当内部电池电压为 0V时
|
||||
|
||||
<table><tr><td rowspan="2">符号</td><td rowspan="2">参数</td><td rowspan="2">条件</td><td colspan="3">标准模式(fSCL=100kHz)</td><td colspan="3">快速模式(fSCL I=400kHz)</td><td rowspan="2">单位</td></tr><tr><td>最小值</td><td>典型值</td><td>最大值</td><td>最小值</td><td>典型值</td><td>最大值</td></tr><tr><td>fSCL</td><td>SCL 频率</td><td></td><td></td><td></td><td>100</td><td></td><td></td><td>400</td><td>kHz</td></tr><tr><td>VIL</td><td>SDA 和 SCL 低电平输入电压</td><td></td><td>-0.3</td><td></td><td>0.3×VDD</td><td>-0.3</td><td></td><td>0.3×VDD</td><td>V</td></tr><tr><td>VIH</td><td>SDA 和 SCL 高电平输入电压</td><td></td><td>0.7×VDD</td><td></td><td>VDD+0.3</td><td>0.7×VDD</td><td></td><td>VDD+0.3</td><td>V</td></tr><tr><td>Vhys</td><td>SDA 和 SCL 施密特触发输入滞后</td><td></td><td>0.05×VDD</td><td></td><td></td><td>0.05×VDD</td><td></td><td></td><td>V</td></tr><tr><td>VOL</td><td>低电平输出电压</td><td>SDA 输出低电平状态下,吸收 2mA 电流时的电压</td><td></td><td>0.4</td><td></td><td></td><td>0.4</td><td></td><td>V</td></tr><tr><td>Cpin</td><td>SDA 和 SCL引脚电容</td><td>TA=25°C f=1MHzVDD=5V VIN=0V VOUT=0V</td><td></td><td></td><td>10</td><td></td><td></td><td>10</td><td>pF</td></tr><tr><td>tIN</td><td>SDA 和 SCL 输入端的脉冲宽度抑制时间</td><td></td><td></td><td></td><td>100</td><td></td><td></td><td>50</td><td>ns</td></tr><tr><td>tAA</td><td>SCL 下降沿到 SDA 输出数据有效</td><td>SCL 下降到 0.3×VDD,直到 SDA 不在 0.3×VDD至 0.7×VDD区间。</td><td></td><td></td><td>900</td><td></td><td></td><td>900</td><td>ns</td></tr><tr><td>tBUF</td><td>总线在 STOP 和 START之间的空闲时间</td><td>SDA 在 STOP 条件下上升到 0.7×VDD,在开始条件下下降到 0.7×VDD。</td><td>4700</td><td></td><td></td><td>1300</td><td></td><td></td><td>ns</td></tr><tr><td>tLOW</td><td>时钟低电平时间</td><td>在 0.3×VDD处测量</td><td>4700</td><td></td><td></td><td>1300</td><td></td><td></td><td>ns</td></tr><tr><td>tHIGH</td><td>时钟高电平时间</td><td>在 0.7×VDD处测量</td><td>4000</td><td></td><td></td><td>600</td><td></td><td></td><td>ns</td></tr><tr><td>tSU:STA</td><td>IIC 启动信号的建立时间</td><td>SCL 上升到 0.7×VDD至 SDA 下降沿到 0.7×VDD</td><td>4700</td><td></td><td></td><td>600</td><td></td><td></td><td>ns</td></tr><tr><td>tHD:STA</td><td>IIC 停止信号的保持时间</td><td>在 SDA 下降沿到 0.3×VDD, SCL 下降沿到 0.7×VDD</td><td>4000</td><td></td><td></td><td>600</td><td></td><td></td><td>ns</td></tr><tr><td>tSU:DAT</td><td>输入数据的建立时间</td><td>从 SDA 不在 0.3×VDD至 0.7×VDD范围,到 SCL 上升沿的 0.3×VDD</td><td>250</td><td></td><td></td><td>100</td><td></td><td></td><td>ns</td></tr><tr><td>tHD:DAT</td><td>输入数据保持时间</td><td>SCL 下降沿的 0.3×VDD,到 SDA 在 0.3×VDD至 0.7×VDD区间</td><td>0</td><td></td><td></td><td>0</td><td></td><td></td><td>ns</td></tr><tr><td>tSU:STO</td><td>停止条件的建立时间</td><td>从 SCL 上升沿经过 0.7×VDD,到 SDA上升沿 0.3×VDD</td><td>4000</td><td></td><td></td><td>600</td><td></td><td></td><td>ns</td></tr><tr><td>tDH</td><td>数据输出的保持时间</td><td>从 SCL 下降沿 0.7×VDD,到 SDA 0.3×VDD至 0.7×VDD区间</td><td>0</td><td></td><td></td><td>0</td><td></td><td></td><td>ns</td></tr><tr><td> $t_{R}$ </td><td>SDA 和 SCL 的上升时间</td><td> $0.3 \times V_{DD}$ 至 $0.7 \times V_{DD}$ 区间</td><td></td><td></td><td>1000</td><td></td><td></td><td>300</td><td>ns</td></tr><tr><td> $t_{F}$ </td><td>SDA 和 SCL 的下降时间</td><td> $0.3 \times V_{DD}$ 至 $0.7 \times V_{DD}$ 区间</td><td></td><td></td><td>300</td><td></td><td></td><td>300</td><td>ns</td></tr></table>
|
||||
|
||||
IIC Timing Chart
|
||||
IIC Timing Chart
|
||||
|
||||
|
||||
<details>
|
||||
@@ -802,12 +802,12 @@ SD2506 封装尺寸（管脚尺寸：0.5\*0.3mm，管脚公差±0.05mm）
|
||||
|
||||
## 一. SD2506系列应用中硬件注意事项:
|
||||
|
||||
(1) 对 SD2506 及 MCU 的电源\~地之间加 104 电容去高频。
|
||||
(2) 对SD2506及MCU所在的板数字电源\~地的输入端加220uF以上的电解及104电容去除电源扰动.
|
||||
(3) 为了防止干扰,在 PCB 制作时请保证模块底部无大电流信号通过,最好能铺地.
|
||||
(1) 对 SD2506 及 MCU 的电源\~地之间加 104 电容去高频。
|
||||
(2) 对SD2506及MCU所在的板数字电源\~地的输入端加220uF以上的电解及104电容去除电源扰动.
|
||||
(3) 为了防止干扰,在 PCB 制作时请保证模块底部无大电流信号通过,最好能铺地.
|
||||
(4) 对MCU的复位端尽量采用可靠的复位方式,而摒弃阻容复位或直接连到VDD的方式.以下推荐廉价的三极管复位方式,当然用电压检测器或专用复位电路就更好啦.
|
||||
|
||||
|
||||
|
||||
图中 R2,R3 为分压电阻,其选值可用以下公式:
|
||||
|
||||
Vbe/Vrst=R2/(R2+R3)
|
||||
@@ -822,9 +822,9 @@ D1为延时电容的放电二极管,可选用.
|
||||
|
||||
## 二. SD2506系列应用中软件注意事项
|
||||
|
||||
1) 软件上电开始做一个几百毫秒的延时，等 MCU端口稳定后再去进行读写操作。
|
||||
2) 时钟最多半秒才读一次：这样做主要目的是考虑到时间数据的改变需要 1S，频繁去读的话是在做无用功，不但会加大电源功耗，而且会引入干扰。
|
||||
3） IIC 总线”START”里:在置 SDA 为高后要再判断 SDA 是否为高,即 SDA 是否被箝位为低,否则等 SDA 线
|
||||
1) 软件上电开始做一个几百毫秒的延时，等 MCU端口稳定后再去进行读写操作。
|
||||
2) 时钟最多半秒才读一次：这样做主要目的是考虑到时间数据的改变需要 1S，频繁去读的话是在做无用功，不但会加大电源功耗，而且会引入干扰。
|
||||
3） IIC 总线”START”里:在置 SDA 为高后要再判断 SDA 是否为高,即 SDA 是否被箝位为低,否则等 SDA 线
|
||||
置高。在写命令字时:要判断ACK 是否正常,否则退出
|
||||
|
||||
4）IIC 总线”STOP”里:在置 SDA 为高后要再判断 SDA 是否为高,即 SDA 是否被箝位为低,否则多置 SCL 脉
|
||||
@@ -847,4 +847,4 @@ https://www.whwave.com.cn/filedownload/420894
|
||||
|
||||
## (2) 温度对精度的影响:
|
||||
|
||||
SD2506时钟具有温度补偿功能。
|
||||
SD2506时钟具有温度补偿功能。
|
||||
|
||||
+25
-25
@@ -2,24 +2,24 @@
|
||||
|
||||
## Features
|
||||
|
||||
• 8 Simultaneously Sampled Inputs
|
||||
- Single 5-V Analog Supply and 1.71-V to 5-V $V_{DRIVE}$
|
||||
• 16-Bit ADC with 350 kSPS on All Channels
|
||||
• Bipolar Inputs Ranges: ±10 V, ±5 V
|
||||
- Analog Input Clamp Protection
|
||||
• 1-MΩ Analog Input Impedance
|
||||
- On-Chip Reference and Buffer
|
||||
• On-Chip Oversampling Digital Filter
|
||||
- SPI Compatible Interface
|
||||
• Temperature Range: -40°C to 125°C
|
||||
• 8 Simultaneously Sampled Inputs
|
||||
- Single 5-V Analog Supply and 1.71-V to 5-V $V_{DRIVE}$
|
||||
• 16-Bit ADC with 350 kSPS on All Channels
|
||||
• Bipolar Inputs Ranges: ±10 V, ±5 V
|
||||
- Analog Input Clamp Protection
|
||||
• 1-MΩ Analog Input Impedance
|
||||
- On-Chip Reference and Buffer
|
||||
• On-Chip Oversampling Digital Filter
|
||||
- SPI Compatible Interface
|
||||
• Temperature Range: -40°C to 125°C
|
||||
• Package: LQFP10×10-64
|
||||
|
||||
## Applications
|
||||
|
||||
- Power Line Monitor
|
||||
• Power Line Protection Relays
|
||||
- Motor Control
|
||||
• Data Acquisition System (DAS)
|
||||
- Power Line Monitor
|
||||
• Power Line Protection Relays
|
||||
- Motor Control
|
||||
• Data Acquisition System (DAS)
|
||||
• Industrial Automation and Controls
|
||||
|
||||
## Description
|
||||
@@ -32,7 +32,7 @@ The TPAFE5160 can accept ±10-V or ± 5-V true bipolar inputs with a single 5-V
|
||||
|
||||
The zero-latency conversion with high performance also makes the device suitable for industrial automation and control applications.
|
||||
|
||||
Typical Application Circuit
|
||||
Typical Application Circuit
|
||||
|
||||
|
||||
<details>
|
||||
@@ -193,15 +193,15 @@ All test conditions: $T_{A} = 25^{\circ}C$ , unless otherwise noted.
|
||||
|
||||
<table><tr><td colspan="2">Parameter</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td></td><td>AVDD to AGND</td><td>-0.3</td><td>7</td><td>V</td></tr><tr><td></td><td>DVDD to DGND</td><td>-0.3</td><td>7</td><td>V</td></tr><tr><td></td><td>AGND to DGND</td><td>-0.3</td><td>0.3</td><td>V</td></tr><tr><td></td><td>Analog Input Voltage to AGND</td><td>-15</td><td>15</td><td>V</td></tr><tr><td></td><td>Digital Input to DGND</td><td>-0.3</td><td>DVDD + 0.3</td><td>V</td></tr><tr><td></td><td>REFIN to AGND</td><td>-0.3</td><td>AVDD + 0.3</td><td>V</td></tr><tr><td></td><td>Input Current to Any Pin Except Supplies</td><td>-10</td><td>10</td><td>mA</td></tr><tr><td> $T_J$ </td><td>Maximum Junction Temperature</td><td>-40</td><td>150</td><td>°C</td></tr><tr><td> $T_A$ </td><td>Operating Temperature Range</td><td>-40</td><td>125</td><td>°C</td></tr><tr><td> $T_{STG}$ </td><td>Storage Temperature Range</td><td>-65</td><td>150</td><td>°C</td></tr><tr><td> $T_L$ </td><td>Lead Temperature (Soldering, 10 sec)</td><td></td><td>260</td><td>°C</td></tr></table>
|
||||
|
||||
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.
|
||||
(2) This data was taken with the JEDEC low effective thermal conductivity test board.
|
||||
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.
|
||||
(2) This data was taken with the JEDEC low effective thermal conductivity test board.
|
||||
(3) This data was taken with the JEDEC standard multilayer test boards.
|
||||
|
||||
ESD, Electrostatic Discharge Protection
|
||||
|
||||
<table><tr><td>Symbol</td><td>Parameter</td><td>Condition</td><td>Minimum Level</td><td>Unit</td></tr><tr><td>HBM</td><td>Human Body Model ESD for all pins except analog input pins</td><td>ANSI/ESDA/JEDEC JS-001 (1)</td><td>±5000</td><td>V</td></tr><tr><td>HBM</td><td>Human Body Model ESD for analog input pins only</td><td>ANSI/ESDA/JEDEC JS-001 (1)</td><td>±7000</td><td>V</td></tr><tr><td>CDM</td><td>Charged Device Model ESD</td><td>ANSI/ESDA/JEDEC JS-002 (2)</td><td>±1500</td><td>V</td></tr></table>
|
||||
|
||||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
|
||||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
|
||||
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
|
||||
|
||||
Recommended Operating Conditions
|
||||
@@ -250,7 +250,7 @@ All test conditions: $AV_{CC} = 5 V$ , $V_{DRIVE} = 1.7 V$ to 5.5 V, $V_{REF} =
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
Timing Diagrams
|
||||
Timing Diagrams
|
||||
|
||||
|
||||
<details>
|
||||
@@ -318,7 +318,7 @@ V7
|
||||
V8
|
||||
</details>
|
||||
|
||||
Figure 3. Parallel Mode, Separate CS and RD Pulses
|
||||
Figure 3. Parallel Mode, Separate CS and RD Pulses
|
||||
|
||||
|
||||
<details>
|
||||
@@ -649,7 +649,7 @@ Information in the following application sections is not part of the 3PEAK's com
|
||||
|
||||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||||
|
||||
Tape and Reel Information
|
||||
Tape and Reel Information
|
||||
|
||||
|
||||
<details>
|
||||
@@ -689,8 +689,8 @@ K0
|
||||
|
||||
LQFP10x10-64
|
||||
|
||||
Package Outline Dimensions
|
||||
QP5(LQFP10X10-64-A)
|
||||
Package Outline Dimensions
|
||||
QP5(LQFP10X10-64-A)
|
||||
|
||||
|
||||
<details>
|
||||
@@ -751,7 +751,7 @@ DETAIL Y
|
||||
|
||||
## NOTES
|
||||
|
||||
1. Do not include mold flash or protrusion.
|
||||
1. Do not include mold flash or protrusion.
|
||||
2. This drawing is subject to change without notice.
|
||||
|
||||
<table><tr><td rowspan="2">Symbol</td><td colspan="2">Dimensions In Millimeters</td><td colspan="2">Dimensions In Inches</td></tr><tr><td>MIN</td><td>MAX</td><td>MIN</td><td>MAX</td></tr><tr><td>A</td><td>1.400</td><td>1.600</td><td>0.055</td><td>0.063</td></tr><tr><td>A1</td><td>0.050</td><td>0.150</td><td>0.002</td><td>0.006</td></tr><tr><td>A2</td><td>1.350</td><td>1.450</td><td>0.053</td><td>0.057</td></tr><tr><td>b</td><td>0.170</td><td>0.270</td><td>0.007</td><td>0.011</td></tr><tr><td>c</td><td>0.090</td><td>0.200</td><td>0.004</td><td>0.008</td></tr><tr><td>D</td><td>11.800</td><td>12.200</td><td>0.465</td><td>0.480</td></tr><tr><td>D1</td><td>9.900</td><td>10.100</td><td>0.390</td><td>0.398</td></tr><tr><td>E</td><td>11.800</td><td>12.200</td><td>0.465</td><td>0.480</td></tr><tr><td>E1</td><td>9.900</td><td>10.100</td><td>0.390</td><td>0.398</td></tr><tr><td>e</td><td colspan="2">0.500 BSC</td><td colspan="2">0.020 BSC</td></tr><tr><td>L</td><td>0.450</td><td>0.750</td><td>0.018</td><td>0.030</td></tr><tr><td>θ</td><td>0</td><td>7°</td><td>0</td><td>7°</td></tr></table>
|
||||
@@ -774,4 +774,4 @@ Trademarks. Any of the 思瑞浦 or 3PEAK trade names, trademarks, graphic marks
|
||||
|
||||
Performance Information. Performance tests or performance range contained in this document/material are either results of design simulation or actual tests conducted under designated testing environment. Any variation in testing environment or simulation environment, including but not limited to testing method, testing process or testing temperature, may affect actual performance of the product.
|
||||
|
||||
Disclaimer. 3PEAK provides technical and reliability data (including data sheets), design resources (including reference designs), application or other design recommendations, networking tools, security information and other resources "As Is". 3PEAK makes no warranty as to the absence of defects, and makes no warranties of any kind, express or implied, including without limitation, implied warranties as to merchantability, fitness for a particular purpose or non-infringement of any third-party's intellectual property rights. Unless otherwise specified in writing, products supplied by 3PEAK are not designed to be used in any life-threatening scenarios, including critical medical applications, automotive safety-critical systems, aviation, aerospace, or any situations where failure could result in bodily harm, loss of life, or significant property damage. 3PEAK disclaims all liability for any such unauthorized use.
|
||||
Disclaimer. 3PEAK provides technical and reliability data (including data sheets), design resources (including reference designs), application or other design recommendations, networking tools, security information and other resources "As Is". 3PEAK makes no warranty as to the absence of defects, and makes no warranties of any kind, express or implied, including without limitation, implied warranties as to merchantability, fitness for a particular purpose or non-infringement of any third-party's intellectual property rights. Unless otherwise specified in writing, products supplied by 3PEAK are not designed to be used in any life-threatening scenarios, including critical medical applications, automotive safety-critical systems, aviation, aerospace, or any situations where failure could result in bodily harm, loss of life, or significant property damage. 3PEAK disclaims all liability for any such unauthorized use.
|
||||
|
||||
@@ -132,4 +132,3 @@ if (ok) {
|
||||
- 返回“连续区间”的辅助函数，其返回值是起点还是终点必须在注释/命名中明确，
|
||||
调用方与实现必须一致
|
||||
- 这类错位 bug 往往只在“区间贴到设备边界”时才触发，正常情况能过，建议测试覆盖边界块
|
||||
|
||||
|
||||
Reference in New Issue
Block a user