777 lines
56 KiB
Markdown
777 lines
56 KiB
Markdown
# 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
## Features
|
||
|
||
• 8 Simultaneously Sampled Inputs
|
||
- Single 5-V Analog Supply and 1.71-V to 5-V $V_{DRIVE}$
|
||
• 16-Bit ADC with 350 kSPS on All Channels
|
||
• Bipolar Inputs Ranges: ±10 V, ±5 V
|
||
- Analog Input Clamp Protection
|
||
• 1-MΩ Analog Input Impedance
|
||
- On-Chip Reference and Buffer
|
||
• On-Chip Oversampling Digital Filter
|
||
- SPI Compatible Interface
|
||
• Temperature Range: -40°C to 125°C
|
||
• Package: LQFP10×10-64
|
||
|
||
## Applications
|
||
|
||
- Power Line Monitor
|
||
• Power Line Protection Relays
|
||
- Motor Control
|
||
• Data Acquisition System (DAS)
|
||
• Industrial Automation and Controls
|
||
|
||
## Description
|
||
|
||
The TPAFE5160 is a 16-bit, 8-channel simultaneous sampling, successive approximation (SAR) ADC. Each channel has a complete analog front end, as well as an ADC operating at 350 kSPS per channel. The analog front end features the input clamp, a programmable gain amplifier (PGA) with a high input impedance of 1 MΩ, a low pass filter, and an ADC input driver.
|
||
|
||
The device features an internal precision reference with buffer to drive the ADC. A digital interface supports serial, parallel and parallel byte communication, which can be used with various host controllers.
|
||
|
||
The TPAFE5160 can accept ±10-V or ± 5-V true bipolar inputs with a single 5-V supply. Also, the high input impedance allows direct connection to transformers or other sensors without external driver circuits.
|
||
|
||
The zero-latency conversion with high performance also makes the device suitable for industrial automation and control applications.
|
||
|
||
Typical Application Circuit
|
||
|
||
|
||
<details>
|
||
<summary>flowchart</summary>
|
||
|
||
This diagram illustrates the architecture and signal flow of an electronic circuit, specifically detailing the signal processing flow from input AIN to digital interface, including amplification, ADC driver, and feedback loops.
|
||
</details>
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
## Table of Contents
|
||
|
||
Features....1
|
||
|
||
Applications....1
|
||
|
||
Description....1
|
||
|
||
Typical Application Circuit....1
|
||
|
||
Product Family Table....3
|
||
|
||
Revision History....4
|
||
|
||
Pin Configuration and Functions....5
|
||
|
||
Specifications....8
|
||
|
||
Absolute Maximum Ratings (1)....8
|
||
|
||
ESD, Electrostatic Discharge Protection....8
|
||
|
||
Recommended Operating Conditions....8
|
||
|
||
Thermal Information....9
|
||
|
||
Electrical Characteristics....10
|
||
|
||
Timing Specifications....13
|
||
|
||
Timing Diagrams....16
|
||
|
||
Detailed Description....18
|
||
|
||
Overview....18
|
||
|
||
Feature Description....18
|
||
|
||
Device Functional Modes....19
|
||
|
||
Device Modes of Operation....21
|
||
|
||
Application and Implementation....24
|
||
|
||
Tape and Reel Information....25
|
||
|
||
Package Outline Dimensions....26
|
||
|
||
LQFP10x10-64....26
|
||
|
||
Order Information....27
|
||
|
||
IMPORTANT NOTICE AND DISCLAIMER....28
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
Product Family Table
|
||
|
||
<table><tr><td>Order Number</td><td>Input Range (V)</td><td>Package</td></tr><tr><td>TPAFE5160SI08-QP7R</td><td>±10, ±5</td><td>LQFP10×10-64</td></tr></table>
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
Revision History
|
||
|
||
<table><tr><td>Date</td><td>Revision</td><td>Notes</td></tr><tr><td>2021-11-15</td><td>Rev.Pre.0</td><td>Pre-release version.</td></tr><tr><td>2022-03-01</td><td>Rev.Pre.1</td><td>Updated the diagram and the EC table.</td></tr><tr><td>2022-05-10</td><td>Rev.Pre.2</td><td>Updated the EC table.</td></tr><tr><td>2022-05-22</td><td>Rev.Pre.3</td><td>Updated the tape and reel parameters.</td></tr><tr><td>2022-06-20</td><td>Rev.Pre.4</td><td>Updated the EC table.</td></tr><tr><td>2022-11-21</td><td>Rev.Pre.5</td><td>Updated Timing Specifications and Timing Diagrams.</td></tr><tr><td>2023-07-10</td><td>Rev.A.0</td><td>Initial released version.</td></tr><tr><td>2024-11-26</td><td>Rev.A.1</td><td>Updated to a new datasheet format.Updated Timing Specifications.</td></tr></table>
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
## Pin Configuration and Functions
|
||
|
||
|
||
|
||
<details>
|
||
<summary>text_image</summary>
|
||
|
||
AIN_8GND
|
||
AIN_8P
|
||
AIN_7GND
|
||
AIN_7P
|
||
AIN_6GND
|
||
AIN_6P
|
||
AIN_5GND
|
||
AIN_5P
|
||
AIN_4GND
|
||
AIN_4P
|
||
AIN_3GND
|
||
AIN_3P
|
||
AIN_2GND
|
||
AIN_2P
|
||
AIN_1GND
|
||
AIN_1P
|
||
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
|
||
AVDD 1
|
||
AGND 2
|
||
OS0 3
|
||
OS1 4
|
||
OS2 5
|
||
PAR/SER/BYTE SEL 6
|
||
STBY 7
|
||
RANGE 8
|
||
CONVSTA 9
|
||
CONVSTB 10
|
||
RESET 11
|
||
RD/SCLK 12
|
||
OS 13
|
||
BUSY 14
|
||
FRSTDATA 15
|
||
DB0 16
|
||
48 AVDD
|
||
47 AGND
|
||
46 REF/GND
|
||
45 REF/CAPB
|
||
44 REF/CAPA
|
||
43 REF/GND
|
||
42 REF/IN/REFOUT
|
||
41 AGND
|
||
40 AGND
|
||
39 REGCAP2
|
||
38 AVDD
|
||
37 AVDD
|
||
36 REGCAP1
|
||
35 AGND
|
||
34 REF/SEL
|
||
33 DB15/BYTE SEL
|
||
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
|
||
DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14/HBEN
|
||
</details>
|
||
|
||
Table 1. Pin Functions
|
||
|
||
<table><tr><td colspan="2">Pin</td><td rowspan="2">I/O</td><td rowspan="2">Description</td></tr><tr><td>No.</td><td>Name</td></tr><tr><td>1</td><td>AVDD</td><td>P</td><td>Analog supply pin.</td></tr><tr><td>2</td><td>AGND</td><td>P</td><td>Analog ground pin.</td></tr><tr><td>3</td><td>OS0</td><td>DI</td><td>Oversampling control pin.</td></tr><tr><td>4</td><td>OS1</td><td>DI</td><td>Oversampling control pin.</td></tr><tr><td>5</td><td>OS2</td><td>DI</td><td>Oversampling control pin.</td></tr><tr><td>6</td><td> $\overline{PAR/SER/BYTE SEL}$ </td><td>DI</td><td>Control pin to select the serial, parallel, or parallel byte interface mode.</td></tr><tr><td>7</td><td> $\overline{STBY}$ </td><td>DI</td><td>Control pin to select the standby or shutdown mode, active low.</td></tr><tr><td>8</td><td>RANGE</td><td>DI</td><td>Multi-function logic input pin:When STBY is low, this pin selects between the standby and shutdown modes.When STBY is high, this pin selects an input range of ±10 V or ±5 V.</td></tr><tr><td>9</td><td>CONVSTA</td><td>DI</td><td>Active high logic input to control the start of the conversion for the first half count of the input channels of the device.</td></tr><tr><td>10</td><td>CONVSTB</td><td>DI</td><td>Active high logic input to control the start of the conversion for the second half count of the input channels of the device.</td></tr><tr><td>11</td><td>RESET</td><td>DI</td><td>Active high logic input to reset the digital logic of the device.</td></tr><tr><td>12</td><td> $\overline{RD/SCLK}$ </td><td>DI</td><td>Multi-function logic input pin:This pin is active-low ready input pin in the parallel and parallel byte interface.This pin is the clock input pin in the serial interface mode.</td></tr><tr><td>13</td><td> $\overline{CS}$ </td><td>DI</td><td>Active low logic input chip-select signal.</td></tr><tr><td>14</td><td>BUSY</td><td>DO</td><td>Active high digital output indicating ongoing conversion.</td></tr><tr><td>15</td><td>FRSTDATA</td><td>DO</td><td>Active high digital output indicating data read back from channel 1 of the device.</td></tr><tr><td>16</td><td>DB0</td><td>DO</td><td>Data output DB0 (LSB) in the parallel interface mode.</td></tr></table>
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
<table><tr><td colspan="2">Pin</td><td rowspan="2">I/O</td><td rowspan="2">Description</td></tr><tr><td>No.</td><td>Name</td></tr><tr><td>17</td><td>DB1</td><td>DO</td><td>Data output DB1 in the parallel interface mode.</td></tr><tr><td>18</td><td>DB2</td><td>DO</td><td>Data output DB2 in the parallel interface mode.</td></tr><tr><td>19</td><td>DB3</td><td>DO</td><td>Data output DB3 in the parallel interface mode.</td></tr><tr><td>20</td><td>DB4</td><td>DO</td><td>Data output DB4 in the parallel interface mode.</td></tr><tr><td>21</td><td>DB5</td><td>DO</td><td>Data output DB5 in the parallel interface mode.</td></tr><tr><td>22</td><td>DB6</td><td>DO</td><td>Data output DB6 in the parallel interface mode.</td></tr><tr><td>23</td><td>DVDD</td><td>P</td><td>Digital supply pin; decouple with AGND on pin 26.</td></tr><tr><td>24</td><td>DB7/ DOUTA</td><td>DO</td><td>Multi-function logic output pin:This pin is data output DB7 in the parallel and parallel byte interface mode.This pin is a data output pin in serial interface mode.</td></tr><tr><td>25</td><td>DB8/ DOUTB</td><td>DO</td><td>Multi-function logic output pin:This pin is data output DB8 in the parallel and parallel byte interface mode.This pin is a data output pin in the serial interface mode.</td></tr><tr><td>26</td><td>AGND</td><td>P</td><td>Analog ground pin.</td></tr><tr><td>27</td><td>DB9</td><td>DO</td><td>Data output DB9 in the parallel interface mode.</td></tr><tr><td>28</td><td>DB10</td><td>DO</td><td>Data output DB10 in the parallel interface mode.</td></tr><tr><td>29</td><td>DB11</td><td>DO</td><td>Data output DB11 in the parallel interface mode.</td></tr><tr><td>30</td><td>DB12</td><td>DO</td><td>Data output DB12 in the parallel interface mode.</td></tr><tr><td>31</td><td>DB13</td><td>DO</td><td>Data output DB13 in the parallel interface mode.</td></tr><tr><td>32</td><td>DB14/ HBEN</td><td>DO</td><td>Multi-function logic input or output pin:This pin is data output DB14 in the parallel interface mode.This pin is a control input pin for byte selection (high or low) in the parallel byte interface mode.</td></tr><tr><td>33</td><td>DB15/ BYTE SEL</td><td>DO</td><td>Multi-function logic input or output pin:This pin is data output DB15 (MSB) in parallel interface mode.This pin is an active high-control input pin to enable the parallel byte interface mode.</td></tr><tr><td>34</td><td>REFSEL</td><td>DI</td><td>Active high logic input to enable the internal reference.</td></tr><tr><td>35</td><td>AGND</td><td>P</td><td>Analog ground pin.</td></tr><tr><td>36</td><td>REGCAP1</td><td>AO</td><td>Output pin 1 for the internal voltage regulator; decouple separately to AGND using a 1-μF capacitor. Typical 4 V.</td></tr><tr><td>37</td><td>AVDD</td><td>P</td><td>Analog supply pin.</td></tr><tr><td>38</td><td>AVDD</td><td>P</td><td>Analog supply pin.</td></tr><tr><td>39</td><td>REGCAP2</td><td>AO</td><td>Output pin 2 for the internal voltage regulator; decouple separately to AGND using a 1-μF capacitor. Typical 4 V.</td></tr><tr><td>40</td><td>AGND</td><td>P</td><td>Analog ground pin.</td></tr><tr><td>41</td><td>AGND</td><td>P</td><td>Analog ground pin.</td></tr><tr><td>42</td><td>REFIN/ REFOUT</td><td>AIO</td><td>This pin acts as an internal 2.5 V reference output when REFSEL is high.This pin functions as an input pin for the external reference when REFSEL is low; decouple with REFGND on pin 43 using a 10-μF capacitor.</td></tr></table>
|
||
|
||
16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
<table><tr><td colspan="2">Pin</td><td rowspan="2">I/O</td><td rowspan="2">Description</td></tr><tr><td>No.</td><td>Name</td></tr><tr><td>43</td><td>REFGND</td><td>P</td><td>Reference GND pin. This pin must be shorted to the analog GND plane and decoupled with REFIN/REFOUT on pin 42 using a 10-μF capacitor.</td></tr><tr><td>44</td><td>REFCAPA</td><td>AO</td><td>Reference amplifier output pins. This pin must be shorted to REFCAPB and decoupled to AGND using a low ESR, 10-μF ceramic capacitor. Typical 4 V.</td></tr><tr><td>45</td><td>REFCAPB</td><td>AO</td><td>Reference amplifier output pins. This pin must be shorted to REFCAPA and decoupled to AGND using a low ESR, 10-μF ceramic capacitor. Typical 4 V.</td></tr><tr><td>46</td><td>REFGND</td><td>P</td><td>Reference GND pin. This pin must be shorted to the analog GND plane and decoupled with REFIN/REFOUT on pin 42 using a 10-μF capacitor.</td></tr><tr><td>47</td><td>AGND</td><td>P</td><td>Analog ground pin.</td></tr><tr><td>48</td><td>AVDD</td><td>P</td><td>Analog supply pin.</td></tr><tr><td>49</td><td>AIN_1P</td><td>AIO</td><td>Analog input channel 1: positive input.</td></tr><tr><td>50</td><td>AIN_1GND</td><td>AIO</td><td>Analog input channel 1: negative input.</td></tr><tr><td>51</td><td>AIN_2P</td><td>AIO</td><td>Analog input channel 2: positive input.</td></tr><tr><td>52</td><td>AIN_2GND</td><td>AIO</td><td>Analog input channel 2: negative input.</td></tr><tr><td>53</td><td>AIN_3P</td><td>AIO</td><td>Analog input channel 3: positive input.</td></tr><tr><td>54</td><td>AIN_3GND</td><td>AIO</td><td>Analog input channel 3: negative input.</td></tr><tr><td>55</td><td>AIN_4P</td><td>AIO</td><td>Analog input channel 4: positive input.</td></tr><tr><td>56</td><td>AIN_4GND</td><td>AIO</td><td>Analog input channel 4: negative input.</td></tr><tr><td>57</td><td>AIN_5P</td><td>AIO</td><td>Analog input channel 5: positive input.</td></tr><tr><td>58</td><td>AIN_5GND</td><td>AIO</td><td>Analog input channel 5: negative input.</td></tr><tr><td>59</td><td>AIN_6P</td><td>AIO</td><td>Analog input channel 6: positive input.</td></tr><tr><td>60</td><td>AIN_6GND</td><td>AIO</td><td>Analog input channel 6: negative input.</td></tr><tr><td>61</td><td>AIN_7P</td><td>AIO</td><td>Analog input channel 7: positive input.</td></tr><tr><td>62</td><td>AIN_7GND</td><td>AIO</td><td>Analog input channel 7: negative input.</td></tr><tr><td>63</td><td>AIN_8P</td><td>AIO</td><td>Analog input channel 8: positive input.</td></tr><tr><td>64</td><td>AIN_8GND</td><td>AIO</td><td>Analog input channel 8: negative input.</td></tr></table>
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
## Specifications
|
||
|
||
## Absolute Maximum Ratings (1)
|
||
|
||
All test conditions: $T_{A} = 25^{\circ}C$ , unless otherwise noted.
|
||
|
||
<table><tr><td colspan="2">Parameter</td><td>Min</td><td>Max</td><td>Unit</td></tr><tr><td></td><td>AVDD to AGND</td><td>-0.3</td><td>7</td><td>V</td></tr><tr><td></td><td>DVDD to DGND</td><td>-0.3</td><td>7</td><td>V</td></tr><tr><td></td><td>AGND to DGND</td><td>-0.3</td><td>0.3</td><td>V</td></tr><tr><td></td><td>Analog Input Voltage to AGND</td><td>-15</td><td>15</td><td>V</td></tr><tr><td></td><td>Digital Input to DGND</td><td>-0.3</td><td>DVDD + 0.3</td><td>V</td></tr><tr><td></td><td>REFIN to AGND</td><td>-0.3</td><td>AVDD + 0.3</td><td>V</td></tr><tr><td></td><td>Input Current to Any Pin Except Supplies</td><td>-10</td><td>10</td><td>mA</td></tr><tr><td> $T_J$ </td><td>Maximum Junction Temperature</td><td>-40</td><td>150</td><td>°C</td></tr><tr><td> $T_A$ </td><td>Operating Temperature Range</td><td>-40</td><td>125</td><td>°C</td></tr><tr><td> $T_{STG}$ </td><td>Storage Temperature Range</td><td>-65</td><td>150</td><td>°C</td></tr><tr><td> $T_L$ </td><td>Lead Temperature (Soldering, 10 sec)</td><td></td><td>260</td><td>°C</td></tr></table>
|
||
|
||
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.
|
||
(2) This data was taken with the JEDEC low effective thermal conductivity test board.
|
||
(3) This data was taken with the JEDEC standard multilayer test boards.
|
||
|
||
ESD, Electrostatic Discharge Protection
|
||
|
||
<table><tr><td>Symbol</td><td>Parameter</td><td>Condition</td><td>Minimum Level</td><td>Unit</td></tr><tr><td>HBM</td><td>Human Body Model ESD for all pins except analog input pins</td><td>ANSI/ESDA/JEDEC JS-001 (1)</td><td>±5000</td><td>V</td></tr><tr><td>HBM</td><td>Human Body Model ESD for analog input pins only</td><td>ANSI/ESDA/JEDEC JS-001 (1)</td><td>±7000</td><td>V</td></tr><tr><td>CDM</td><td>Charged Device Model ESD</td><td>ANSI/ESDA/JEDEC JS-002 (2)</td><td>±1500</td><td>V</td></tr></table>
|
||
|
||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
|
||
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
|
||
|
||
Recommended Operating Conditions
|
||
|
||
<table><tr><td colspan="2">Parameter</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td>AVDD</td><td>Analog Supply Voltage</td><td>4.75</td><td>5</td><td>5.25</td><td>V</td></tr><tr><td>DVDD</td><td>Digital Supply Voltage</td><td>1.71</td><td>3.3</td><td>AVDD</td><td>V</td></tr></table>
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
Thermal Information
|
||
|
||
<table><tr><td>Package Type</td><td> $\theta_{JA}$ </td><td> $\theta_{JC}$ </td><td>Unit</td></tr><tr><td>LQFP10×10-64</td><td>46</td><td>7.8</td><td>°C/W</td></tr></table>
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
## Electrical Characteristics
|
||
|
||
All test conditions: $V_{REF} = 2.5$ V external/internal, AVDD = 4.75 V to 5.25 V, $V_{DRIVE} = 1.71$ V to AVDD, $f_{SAMPLE} = 350$ kSPS, $T_{A} = -40^{\circ}C$ to $125^{\circ}C$ , Low Bandwidth Mode, unless otherwise noted.
|
||
|
||
<table><tr><td>Symbol</td><td>Parameter</td><td colspan="2">Test condition</td><td>Min</td><td>Typ</td><td>Max</td><td>Unit</td></tr><tr><td colspan="8">Dynamic Performance</td></tr><tr><td rowspan="4">SNR</td><td rowspan="4">Signal-to-Noise Ratio</td><td rowspan="2">fin = 1 kHz sine wave, unless otherwise noted</td><td>±10 V No oversampling</td><td>86</td><td>89.7</td><td></td><td>dB</td></tr><tr><td>±5 V No oversampling</td><td>85.5</td><td>89.5</td><td></td><td>dB</td></tr><tr><td>fin = 130 Hz</td><td>Oversampling by 16, ±10-V Range</td><td>91</td><td>95.2</td><td></td><td>dB</td></tr><tr><td>fin = 130 Hz</td><td>Oversampling by 16, ±5-V Range</td><td>91</td><td>94.7</td><td></td><td>dB</td></tr><tr><td rowspan="2">SINAD</td><td rowspan="2">Signal to Noise + Distortion Ratio</td><td rowspan="2">fin = 1 kHz sine wave, unless otherwise noted</td><td>±10 V No oversampling</td><td></td><td>89.5</td><td></td><td>dB</td></tr><tr><td>±5 V No oversampling</td><td></td><td>89.4</td><td></td><td>dB</td></tr><tr><td>THD</td><td>Total Harmonic Distortion</td><td>All input range, fin =1 kHz</td><td></td><td></td><td>-106</td><td></td><td>dB</td></tr><tr><td>SFDR</td><td>Spurious Free Dynamic Range</td><td>fin = 1 kHz</td><td></td><td></td><td>-106</td><td></td><td>dB</td></tr><tr><td colspan="8">Analog Input Filter</td></tr><tr><td rowspan="4">BW (-3 dB)</td><td rowspan="4">Small Signal Bandwidth</td><td>Low Bandwidth Mode</td><td>-3 dB, ±10 V</td><td></td><td>20.0</td><td></td><td>kHz</td></tr><tr><td>Low Bandwidth Mode</td><td>-3 dB, ±5 V</td><td></td><td>12.7</td><td></td><td>kHz</td></tr><tr><td>High Bandwidth Mode</td><td>-3 dB, ±10 V</td><td></td><td>26.5</td><td></td><td>kHz</td></tr><tr><td>High Bandwidth Mode</td><td>-3 dB, ±5 V</td><td></td><td>16.4</td><td></td><td>kHz</td></tr><tr><td rowspan="4">BW (-0.1 dB)</td><td rowspan="4">Small Signal Bandwidth</td><td>Low Bandwidth Mode</td><td>-0.1 dB, ±10 V</td><td></td><td>3.3</td><td></td><td>kHz</td></tr><tr><td>Low Bandwidth Mode</td><td>-0.1 dB, ±5 V</td><td></td><td>2.2</td><td></td><td>kHz</td></tr><tr><td>High Bandwidth Mode</td><td>-0.1 dB, ±10 V</td><td></td><td>4.3</td><td></td><td>kHz</td></tr><tr><td>High Bandwidth Mode</td><td>-0.1 dB, ±5 V</td><td></td><td>2.6</td><td></td><td>kHz</td></tr><tr><td rowspan="4">Tgroup_delay</td><td rowspan="4">Group Delay</td><td>Low Bandwidth Mode</td><td>±10 V</td><td></td><td>10</td><td></td><td>μs</td></tr><tr><td>Low Bandwidth Mode</td><td>±5 V</td><td></td><td>16</td><td></td><td>μs</td></tr><tr><td>High Bandwidth Mode</td><td>±10 V</td><td></td><td>8</td><td></td><td>μs</td></tr><tr><td>High Bandwidth Mode</td><td>±5 V</td><td></td><td>12</td><td></td><td>μs</td></tr><tr><td colspan="8">DC Accuracy</td></tr><tr><td></td><td>Resolution</td><td></td><td>NO missing code</td><td></td><td>16</td><td></td><td>bit</td></tr><tr><td>DNL</td><td>Differential Nonlinearity</td><td colspan="2"> $f_{SAMPLE}$ = 200 kSPS, -40~85°C</td><td>-0.99</td><td>±0.5</td><td>1.5</td><td>LSB</td></tr><tr><td rowspan="2">INL</td><td rowspan="2">Integral Nonlinearity</td><td colspan="2"> $f_{SAMPLE}$ = 200 kSPS, -40~85°C</td><td></td><td>±0.7</td><td>±2</td><td>LSB</td></tr><tr><td colspan="2"> $f_{SAMPLE}$ = 350 kSPS, -40~85°C</td><td></td><td>±1</td><td>±2.5</td><td>LSB</td></tr></table>
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
<table><tr><td rowspan="2"></td><td rowspan="2">Positive and Negative Full-Scale Error</td><td>Ext reference</td><td></td><td></td><td>±4</td><td>±50</td><td>LSB</td></tr><tr><td>Int reference</td><td></td><td></td><td>±15</td><td></td><td>LSB</td></tr><tr><td rowspan="2"></td><td rowspan="2">Positive Full-Scale Error Drift</td><td>Ext reference</td><td></td><td></td><td>±2</td><td></td><td>ppm/C</td></tr><tr><td>Int reference</td><td></td><td></td><td>±10</td><td></td><td>ppm/C</td></tr><tr><td rowspan="2"></td><td rowspan="2">Negative Full-Scale Error Drift</td><td>Ext reference</td><td></td><td></td><td>±2</td><td></td><td>ppm/C</td></tr><tr><td>Int reference</td><td></td><td></td><td>±10</td><td></td><td>ppm/C</td></tr><tr><td rowspan="2"></td><td rowspan="2">Bipolar Zero Code Error</td><td></td><td>±10 V</td><td></td><td rowspan="2">±1</td><td rowspan="2">±15</td><td rowspan="2">LSB</td></tr><tr><td></td><td>±5 V</td><td></td></tr><tr><td rowspan="2"></td><td rowspan="2">Bipolar Zero Code Error Drift</td><td></td><td>±10 V</td><td></td><td>±10</td><td></td><td>μV/C</td></tr><tr><td></td><td>±5 V</td><td></td><td>±5</td><td></td><td>μV/C</td></tr><tr><td></td><td>Bipolar Full-Scale Error Matching</td><td></td><td></td><td></td><td>±6</td><td>±22</td><td>LSB</td></tr><tr><td></td><td>Bipolar Zero Code Error matching</td><td></td><td>±5 V±10 V</td><td></td><td>±3</td><td>±20</td><td>LSB</td></tr><tr><td colspan="8">Analog Input</td></tr><tr><td rowspan="2"></td><td rowspan="2">Input Range</td><td rowspan="2">Vx - VxGND</td><td>RANGE = 1, ±10-V range</td><td>-10</td><td></td><td>10</td><td rowspan="2">V</td></tr><tr><td>RANGE = 0, ±5-V range</td><td>-5</td><td></td><td>5</td></tr><tr><td rowspan="2"></td><td rowspan="2">Analog Input Current</td><td></td><td>10-V range</td><td></td><td rowspan="2">(VIN - 2) / RIN</td><td></td><td>μA</td></tr><tr><td></td><td>5-V range</td><td></td><td></td><td>μA</td></tr><tr><td>CIN</td><td>Input Capacitance</td><td></td><td></td><td></td><td>5</td><td></td><td>pF</td></tr><tr><td>RIN</td><td>Input Resistance</td><td></td><td></td><td></td><td>1</td><td></td><td>Mohm</td></tr><tr><td></td><td>Input Impedance Drift</td><td></td><td></td><td></td><td>±20</td><td></td><td>ppm/C</td></tr><tr><td colspan="8">Reference Input/Output</td></tr><tr><td></td><td>Reference Input Voltage</td><td colspan="2">REF SELECT = 0, select Ext Ref, force voltage on REFIN/REFOUT</td><td>2.475</td><td>2.5</td><td>2.525</td><td>V</td></tr><tr><td></td><td>Reference Output Voltage</td><td colspan="2">REF_SELECT = 1, REFIN/REFOUT output voltage TA = 25°C</td><td>2.495</td><td>2.5</td><td>2.505</td><td>V</td></tr><tr><td></td><td>Reference Voltage TC</td><td colspan="2"></td><td></td><td>±10</td><td></td><td>ppm/C</td></tr><tr><td></td><td>V (REFCAPA/B)</td><td colspan="2">Voltage on REFCAPA and REFCAPB, also used for ADC</td><td></td><td>4</td><td></td><td>V</td></tr><tr><td colspan="8">Logic Input</td></tr><tr><td>VIH</td><td>Input High Voltage</td><td>Input logic high voltage</td><td></td><td>0.7 × VDRIVE</td><td></td><td></td><td>V</td></tr><tr><td>VIL</td><td>Input Low Voltage</td><td>Input logic low voltage</td><td></td><td></td><td></td><td>0.3 × VDRIVE</td><td>V</td></tr><tr><td>CI</td><td>Input Capacitance</td><td>Input capacitance</td><td></td><td></td><td>5</td><td></td><td>pF</td></tr><tr><td>I1</td><td>Input Current</td><td>Input current</td><td></td><td></td><td></td><td>±2</td><td>μA</td></tr></table>
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
<table><tr><td colspan="8">Logic Output</td></tr><tr><td> $V_{OH}$ </td><td>Output High Voltage</td><td></td><td>Current source = 100 μA</td><td> $V_{DRIVE}$ - 0.2</td><td></td><td></td><td>V</td></tr><tr><td> $V_{OL}$ </td><td>Output Low Voltage</td><td></td><td>Current sink = 100 μA</td><td></td><td></td><td>0.2</td><td>V</td></tr><tr><td></td><td>Float State Leakage Current</td><td></td><td></td><td></td><td>±1</td><td>±20</td><td>μA</td></tr><tr><td> $C_O$ </td><td>Output Capacitance</td><td></td><td></td><td></td><td>5</td><td></td><td>pF</td></tr><tr><td colspan="8">Conversion Rate</td></tr><tr><td></td><td>Conversion Time</td><td></td><td></td><td></td><td>1.65</td><td></td><td>μs</td></tr><tr><td></td><td>Acquisition Time</td><td></td><td></td><td></td><td>1.2</td><td></td><td>μs</td></tr><tr><td></td><td>Throughput Rate</td><td>Per channel</td><td></td><td></td><td></td><td>350</td><td>kSPS</td></tr><tr><td colspan="8">Timing specifications</td></tr><tr><td rowspan="2">SCLK</td><td rowspan="2">Frequency of Serial Interface</td><td></td><td> $V_{DRIVE}$ > 2.7 V</td><td></td><td></td><td>23.5</td><td>MHz</td></tr><tr><td></td><td> $V_{DRIVE}$ > 1.7 V</td><td></td><td></td><td>15</td><td>MHz</td></tr><tr><td></td><td>AVCC Normal</td><td></td><td></td><td></td><td>41</td><td>51</td><td>mA</td></tr><tr><td></td><td>AVCC Standby</td><td></td><td></td><td></td><td>5</td><td>9</td><td>mA</td></tr><tr><td></td><td>AVCC Shutdown</td><td></td><td></td><td></td><td>11</td><td>25</td><td>μA</td></tr></table>
|
||
|
||
(1) 100% tested at $T_{A} = 25^{\circ}C$ .
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
## Timing Specifications
|
||
|
||
All test conditions: $AV_{CC} = 5 V$ , $V_{DRIVE} = 1.7 V$ to 5.5 V, $V_{REF} = 2.5 V$ , $T_{A} = T_{MIN}$ to $T_{MAX}$ , unless otherwise noted.
|
||
|
||
<table><tr><td rowspan="2">Parameter</td><td colspan="3">Limit at TMIN, TMAX (0.1 × VDRIVE and 0.9 × VDRIVE Logic Input Levels)</td><td rowspan="2">Unit</td><td rowspan="2">Description</td></tr><tr><td>Min</td><td>Typ</td><td>Max</td></tr><tr><td colspan="6">Parallel/Serial/Byte Mode</td></tr><tr><td rowspan="4">tCYCLE</td><td></td><td></td><td></td><td></td><td>1/throughput rate</td></tr><tr><td></td><td>2.85</td><td></td><td>μs</td><td>Parallel mode, reading during or after conversion; or serial mode: VDRIVE = 2.7 V to 5.5 V, reading during conversion using DOUTA and DOUTB lines</td></tr><tr><td></td><td>4.5</td><td></td><td>μs</td><td>Serial mode: VDRIVE = 2.7 V, reading after a conversion using DOUTA and DOUTB lines</td></tr><tr><td></td><td>6</td><td></td><td>μs</td><td>Serial mode: VDRIVE = 1.7 V, reading after a conversion using DOUTA and DOUTB lines</td></tr><tr><td rowspan="8">tCONV</td><td></td><td></td><td></td><td></td><td>Conversion time</td></tr><tr><td></td><td>1.74</td><td></td><td>μs</td><td>Oversampling off</td></tr><tr><td></td><td>4.4</td><td></td><td>μs</td><td>Oversampling by 2</td></tr><tr><td></td><td>9.6</td><td></td><td>μs</td><td>Oversampling by 4</td></tr><tr><td></td><td>20</td><td></td><td>μs</td><td>Oversampling by 8</td></tr><tr><td></td><td>41</td><td></td><td>μs</td><td>Oversampling by 16</td></tr><tr><td></td><td>83</td><td></td><td>μs</td><td>Oversampling by 32</td></tr><tr><td></td><td>167</td><td></td><td>μs</td><td>Oversampling by 64</td></tr><tr><td>tWAKE-UP STANDBY</td><td></td><td>100</td><td></td><td>μs</td><td>STBY rising edge to CONVST × rising edge; power-up time from standby mode</td></tr><tr><td>tWAKE-UP SHUTDOWN Internal Reference</td><td></td><td>180</td><td></td><td>ms</td><td>STBY rising edge to CONVST × rising edge; power-up time from shutdown mode</td></tr><tr><td>tWAKE-UP SHUTDOWN External Reference</td><td></td><td>13</td><td></td><td>ms</td><td>STBY rising edge to CONVST × rising edge; power-up time from shutdown mode</td></tr><tr><td>tRESET</td><td></td><td>100</td><td></td><td>ns</td><td>RESET high pulse width</td></tr><tr><td>t1</td><td></td><td>40</td><td></td><td>ns</td><td>CONVST × high to BUSY high</td></tr><tr><td>t2</td><td>25</td><td></td><td></td><td>ns</td><td>Minimum CONVST × low pulse</td></tr><tr><td>t3</td><td>25</td><td></td><td></td><td>ns</td><td>Minimum CONVST × high pulse</td></tr><tr><td>t4</td><td>45</td><td></td><td></td><td>ns</td><td>BUSY falling edge to CS falling edge setup time</td></tr><tr><td>t5</td><td></td><td>0.5</td><td></td><td>ms</td><td>Maximum delay allowed between CONVST A, CONVST B rising edges</td></tr></table>
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
<table><tr><td>t6</td><td>110</td><td></td><td></td><td>ns</td><td>Minimum time between last $\overline{CS}$ rising edge and BUSY falling edge</td></tr><tr><td>t7</td><td>200</td><td></td><td></td><td>ns</td><td>Minimum delay between RESET low to CONVST × high</td></tr><tr><td colspan="6">Parallel/Byte Read Operation</td></tr><tr><td>t8</td><td>0</td><td></td><td></td><td>ns</td><td> $\overline{CS}$ to $\overline{RD}$ setup time</td></tr><tr><td>t9</td><td>0</td><td></td><td></td><td>ns</td><td> $\overline{CS}$ to $\overline{RD}$ hold time</td></tr><tr><td rowspan="3">t10</td><td></td><td></td><td></td><td></td><td> $\overline{RD}$ low pulse width</td></tr><tr><td>22</td><td></td><td></td><td>ns</td><td> $V_{DRIVE}$ above 2.7 V</td></tr><tr><td>32</td><td></td><td></td><td>ns</td><td> $V_{DRIVE}$ above 1.7 V</td></tr><tr><td>t11</td><td>10</td><td></td><td></td><td>ns</td><td> $\overline{RD}$ high pulse width</td></tr><tr><td>t12</td><td>10</td><td></td><td></td><td>ns</td><td> $\overline{CS}$ high pulse width; $\overline{CS}$ and $\overline{RD}$ linked</td></tr><tr><td rowspan="3">t13</td><td></td><td></td><td></td><td></td><td>Delay from $\overline{CS}$ until DB [15:0] three-state disabled</td></tr><tr><td></td><td></td><td>21</td><td>ns</td><td> $V_{DRIVE}$ above 2.7 V</td></tr><tr><td></td><td></td><td>30</td><td>ns</td><td> $V_{DRIVE}$ above 1.7 V</td></tr><tr><td rowspan="3">t14</td><td></td><td></td><td></td><td></td><td>Data access time after $\overline{RD}$ falling edge</td></tr><tr><td></td><td></td><td>21</td><td>ns</td><td> $V_{DRIVE}$ above 2.7 V</td></tr><tr><td></td><td></td><td>30</td><td>ns</td><td> $V_{DRIVE}$ above 1.7 V</td></tr><tr><td>t15</td><td>6</td><td></td><td></td><td>ns</td><td>Data hold time after $\overline{RD}$ falling edge</td></tr><tr><td>t16</td><td>6</td><td></td><td></td><td>ns</td><td> $\overline{CS}$ to DB [15:0] hold time</td></tr><tr><td>t17</td><td></td><td></td><td>20</td><td>ns</td><td>Delay from $\overline{CS}$ rising edge to DB [15:0] three-state enabled</td></tr><tr><td colspan="6">Serial Read Operation</td></tr><tr><td rowspan="3">fSCLK</td><td></td><td></td><td></td><td></td><td>Frequency of serial read clock</td></tr><tr><td></td><td></td><td>23.5</td><td>MHz</td><td> $V_{DRIVE}$ above 2.7 V</td></tr><tr><td></td><td></td><td>15</td><td>MHz</td><td> $V_{DRIVE}$ above 1.7 V</td></tr><tr><td rowspan="3">t18</td><td></td><td></td><td></td><td></td><td>Delay from CS until $D_{OUTA}/D_{OUTB}$ three-state disabled/delay from $\overline{CS}$ until MSB valid</td></tr><tr><td></td><td></td><td>10</td><td>ns</td><td> $V_{DRIVE}$ above 2.7 V</td></tr><tr><td></td><td></td><td>15</td><td>ns</td><td> $V_{DRIVE}$ above 1.7 V</td></tr><tr><td rowspan="3">t19</td><td></td><td></td><td></td><td></td><td>Data access time after SCLK rising edge</td></tr><tr><td></td><td></td><td>21</td><td>ns</td><td> $V_{DRIVE}$ above 2.7 V</td></tr><tr><td></td><td></td><td>30</td><td>ns</td><td> $V_{DRIVE}$ above 1.7 V</td></tr><tr><td>t20</td><td>0.4tSCLK</td><td></td><td></td><td>ns</td><td>SCLK low pulse width</td></tr><tr><td>t21</td><td>0.4tSCLK</td><td></td><td></td><td>ns</td><td>SCLK high pulse width</td></tr><tr><td>t22</td><td>6</td><td></td><td></td><td>ns</td><td>SCLK rising edge to $D_{OUTA}/D_{OUTB}$ valid hold time</td></tr><tr><td>t23</td><td></td><td></td><td>15</td><td>ns</td><td> $\overline{CS}$ rising edge to $D_{OUTA}/D_{OUTB}$ three-state enabled</td></tr><tr><td colspan="6">FRATDATA Operation</td></tr><tr><td>t24</td><td></td><td></td><td></td><td></td><td>Delay from $\overline{CS}$ falling edge until FRSTDATA three-state disabled</td></tr></table>
|
||
|
||
16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
<table><tr><td rowspan="2">t24</td><td></td><td></td><td>11</td><td>ns</td><td>VDRIVE above 2.7 V</td></tr><tr><td></td><td></td><td>20</td><td>ns</td><td>VDRIVE above 1.7 V</td></tr><tr><td rowspan="3">t25</td><td></td><td></td><td></td><td></td><td>Delay from CS falling edge until FRSTDATA high, serial mode</td></tr><tr><td></td><td></td><td>11</td><td>ns</td><td>VDRIVE above 2.7 V</td></tr><tr><td></td><td></td><td>20</td><td>ns</td><td>VDRIVE above 1.7 V</td></tr><tr><td rowspan="3">t26</td><td></td><td></td><td></td><td></td><td>Delay from RD falling edge to FRSTDATA high</td></tr><tr><td></td><td></td><td>22</td><td>ns</td><td>VDRIVE above 2.7 V</td></tr><tr><td></td><td></td><td>32</td><td>ns</td><td>VDRIVE above 1.7 V</td></tr><tr><td rowspan="3">t27</td><td></td><td></td><td></td><td></td><td>Delay from RD falling edge to FRSTDATA low</td></tr><tr><td></td><td></td><td>22</td><td>ns</td><td>VDRIVE above 2.7 V</td></tr><tr><td></td><td></td><td>32</td><td>ns</td><td>VDRIVE above 1.7 V</td></tr><tr><td rowspan="3">t28</td><td></td><td></td><td></td><td></td><td>Delay from the 16th SCLK falling edge to FRSTDATA low</td></tr><tr><td></td><td></td><td>22</td><td>ns</td><td>VDRIVE above 2.7 V</td></tr><tr><td></td><td></td><td>32</td><td>ns</td><td>VDRIVE above 1.7 V</td></tr><tr><td>t29</td><td></td><td></td><td>20</td><td>ns</td><td>Delay from CS rising edge until FRSTDATA three-state enabled</td></tr></table>
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
Timing Diagrams
|
||
|
||
|
||
<details>
|
||
<summary>flowchart</summary>
|
||
|
||
```mermaid
|
||
graph LR
|
||
CONVST_A["CONVST A, CONVST B"] -->|t5| CONVST_B["CONVST A, CONVST B"]
|
||
CONVST_B -->|tCYCLE| CONVST_B
|
||
CONVST_B -->|t2| CONVST_B
|
||
CONVST_B -->|t3| BUSY["BUSY"]
|
||
BUSY -->|t1| CS["CS"]
|
||
CS -->|t4| CS
|
||
CONVST_B -->|tCONV| CS
|
||
CONVST_B -->|tRESET| RESET["RESET"]
|
||
```
|
||
</details>
|
||
|
||
Figure 1. CONVST Timing-Reading After a Conversion
|
||
|
||
|
||
|
||
<details>
|
||
<summary>flowchart</summary>
|
||
|
||
This diagram illustrates the timing relationships and signal flow between a system, including convolutional and busy states, reset, and synchronization intervals.
|
||
</details>
|
||
|
||
Figure 2. CONVST Timing-Reading During a Conversion
|
||
|
||
|
||
|
||
<details>
|
||
<summary>text_image</summary>
|
||
|
||
CS
|
||
RD
|
||
DATA:
|
||
DB[15:0]
|
||
FRSTDATA
|
||
t8
|
||
t10
|
||
t11
|
||
t13
|
||
t14
|
||
t15
|
||
t16
|
||
t17
|
||
t24
|
||
t26
|
||
t27
|
||
t29
|
||
t8
|
||
t10
|
||
t11
|
||
t14
|
||
t15
|
||
t16
|
||
t17
|
||
V1
|
||
V2
|
||
V3
|
||
V4
|
||
V7
|
||
V8
|
||
</details>
|
||
|
||
Figure 3. Parallel Mode, Separate CS and RD Pulses
|
||
|
||
|
||
<details>
|
||
<summary>text_image</summary>
|
||
|
||
CS AND RD
|
||
DATA:
|
||
DB[15:0]
|
||
V1 V2 V3 V4 V5 V6 V7 V8
|
||
t12
|
||
t13
|
||
t16
|
||
t17
|
||
FRSTDATA
|
||
</details>
|
||
|
||
Figure 4. CS and RD, Linked Parallel Mode
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
|
||
|
||
<details>
|
||
<summary>text_image</summary>
|
||
|
||
CS
|
||
SCLK
|
||
DOUTA,
|
||
DOUTB
|
||
FRSTDATA
|
||
t18
|
||
t19
|
||
t21
|
||
t20
|
||
t22
|
||
t23
|
||
t25
|
||
DB15
|
||
DB14
|
||
DB13
|
||
DB1
|
||
DB0
|
||
t28
|
||
t29
|
||
</details>
|
||
|
||
Figure 5. Serial Read Operation (Channel 1)
|
||
|
||
|
||
|
||
<details>
|
||
<summary>text_image</summary>
|
||
|
||
CS
|
||
RD
|
||
DATA:
|
||
DB[7:0]
|
||
FRSTDATA
|
||
t8
|
||
t10
|
||
t11
|
||
t9
|
||
t13
|
||
t14
|
||
t15
|
||
t16
|
||
t17
|
||
t24
|
||
t26
|
||
t27
|
||
t29
|
||
INVALID
|
||
HIGH BYTE V1
|
||
LOW BYTE V1
|
||
HIGH BYTE V8
|
||
LOW BYTE V8
|
||
</details>
|
||
|
||
Figure 6. BYTE Mode Read Operation
|
||
|
||
# 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
## Detailed Description
|
||
|
||
## Overview
|
||
|
||
The TPAFE5160 is a 16-bit, 8-channel simultaneous sampling, successive approximation (SAR) ADC. Each channel has a complete analog front end, as well as an ADC operating at 350 kSPS per channel. The analog front end features the input clamp, a programmable gain amplifier (PGA) with a high input impedance of 1 MΩ, a low pass filter, and an ADC input driver.
|
||
|
||
The device features an internal precision reference with a buffer to drive the ADC. A digital interface supports serial, parallel, and parallel byte communication, which can be used with various host controllers.
|
||
|
||
The TPAFE5160 can accept ±10-V or ±5-V true bipolar inputs with a single 5-V supply. Also, the high input impedance allows direct connection to transformers or other sensors without external driver circuits.
|
||
|
||
## Feature Description
|
||
|
||
## Analog Inputs
|
||
|
||
The TPAFE5160 has 8 analog input channels, and positive inputs AIN\_nP (n = 1 to 8) are the single-ended analog inputs. The negative inputs AIN\_nGND should be tied to GND.
|
||
|
||
The input voltage range can be configured to bipolar ±10 V or ±5 V by the RANGE pin.
|
||
|
||
The device allows a ±0.3-V range on the AIN\_nGND.
|
||
|
||
## Analog Input Impedance
|
||
|
||
Each analog input channel in the device presents a constant resistive impedance of 1 MΩ.
|
||
|
||
Matching the external source impedance on the AIN\_nP input pin with an equivalent resistance on the AIN\_nGND pin is recommended to cancel any additional offset error contributed by the external resistance.
|
||
|
||
## Input Clamp Protection Circuit
|
||
|
||
The input clamp protection circuit allows the analog input to swing up to ±30 V (typical). The input clamp circuit turns on beyond the clamp voltage.
|
||
|
||
For input voltages above the clamp threshold, make sure that the input current never exceeds the absolute maximum rating to prevent any damage to the device.
|
||
|
||
Don't keep the device in a state such that the clamp circuit is activated for extended periods of time, because this fault condition can degrade the performance and reliability of the device.
|
||
|
||
## Programmable Gain Amplifier (PGA)
|
||
|
||
The device has a programmable gain amplifier (PGA) at each individual input channel. The PGA converts the single-ended input signal into a fully-differential signal to drive internal ADC. The PGA also adjusts the common-mode voltage feeding into the ADC to ensure maximum usage of the ADC input dynamic range. The PGA gain is adjusted by configuring the RANGE pin of the ADC accordingly.
|
||
|
||
## Low Pass Filter
|
||
|
||
Each channel of the TPAFE5160 features a second-order antialiasing low pass filter (LPF) at the output of the PGA, to remove the noise of the front-end amplifiers and gain resistors of the PGA.
|
||
|
||
## ADC Driver
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
There is an integrated ADC input driver before each ADC channel. This integrated ADC driver eliminates the need of any external amplifier, helping inputs of the ADC to settle to better than 16-bit accuracy before any sampled analog voltage gets converted. And thus, the signal chain design for the user is simplified.
|
||
|
||
## Digital Filter
|
||
|
||
The TPAFE5160 has an optional digital averaging filter that can be used in slower throughput applications requiring lower noise and higher dynamic range. The oversampling ratio of the digital filter is determined by the configuration of the OS[2:0] pins.
|
||
|
||
In oversampling mode, the samples are averaged to reduce the noise of the signal chain as well as to improve the SNR of the ADC. The final output is also decimated to provide data for each channel.
|
||
|
||
<table><tr><td>OS [2:0]</td><td>OS RATIO</td><td>MAX THROUGHPUT PER CHANNEL (kSPS)</td></tr><tr><td>000</td><td>NO OS</td><td>350</td></tr><tr><td>001</td><td>2</td><td>175</td></tr><tr><td>010</td><td>4</td><td>87.5</td></tr><tr><td>011</td><td>8</td><td>43.75</td></tr><tr><td>100</td><td>16</td><td>21.875</td></tr><tr><td>101</td><td>32</td><td>10.94</td></tr><tr><td>110</td><td>64</td><td>5.47</td></tr><tr><td>111</td><td>NA</td><td>350</td></tr></table>
|
||
|
||
## Reference
|
||
|
||
The TPAFE5160 can operate with either an internal voltage reference or an external voltage reference. The internal or external reference selection is determined by an external REFSEL pin,
|
||
|
||
The REFIN/REFOUT pin outputs the internal band-gap voltage (in the internal reference mode) or functions as the input pin to the external reference voltage (in the external reference mode). The on-chip amplifier is enabled in both modes to drive the actual reference input of the internal ADC core. The REFCAPA and REFCAPB pins must be shorted together externally and a ceramic capacitor of a minimum 10 μF should be connected between this node and REFGND to ensure that the internal reference buffer is operating as a closed loop.
|
||
|
||
## ADC Transfer Function
|
||
|
||
The TPAFE5160 outputs 16-bit data in binary twos complement format for both bipolar input ranges. The format for the output codes is the same across all analog channels.
|
||
|
||
<table><tr><td>Input Range (V)</td><td>Full-Scale Range (V)</td><td>LSB (μV)</td></tr><tr><td>±10</td><td>20</td><td>305.18</td></tr><tr><td>±5</td><td>10</td><td>152.59</td></tr></table>
|
||
|
||
## Device Functional Modes
|
||
|
||
Device Interface: Pin Description
|
||
|
||
REFSEL (Input)
|
||
|
||
The REFSEL pin selects between the internal and external reference modes of the device.
|
||
|
||
If the REFSEL pin is set to logic high, then the internal reference is enabled and selected.
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
If the REFSEL pin is set to logic low, then the internal reference circuit is disabled and powered down. In this mode, an external reference voltage must be provided to the REFIN/REFOUT pin.
|
||
|
||
The internal reference buffer is always enabled under both conditions.
|
||
|
||
The reference mode after power-up depends on the state of the REFSEL input pin.
|
||
|
||
## RANGE (Input)
|
||
|
||
The RANGE pin selects the input range for all analog input channels.
|
||
|
||
If this pin is set to logic high, the device is configured to operate in the ±10-V input range.
|
||
|
||
If this pin is set to logic low, the device is configured to operate in the ±5-V input range.
|
||
|
||
The RANGE pin is also used to put the device in standby or shutdown mode depending on the state of the STBY input pin, as explained in the Power Down Modes.
|
||
|
||
## STBY (Input)
|
||
|
||
The STBY pin puts the device into one of the two power-down modes: standby and power down.
|
||
|
||
If this pin is set to logic high, the device is in normal operation mode.
|
||
|
||
If this pin is set to logic low, the device is in the standby or power down mode, depending on the state of the RANGE pin.
|
||
|
||
In the shutdown mode, all internal circuitry is powered down,
|
||
|
||
In the standby mode, the internal reference remains powered up to enable a relatively quicker recovery to normal operation mode.
|
||
|
||
## PAR/SER/BYTE SEL (Input)
|
||
|
||
The PAR/SER/BYTE SEL pin selects between the parallel, serial, and parallel byte interface modes for reading data from the device.
|
||
|
||
If this pin is set to logic high, then the serial or parallel byte interface mode is selected depending on the state of the DB15/BYTE SEL pin. If the DB15/BYTE SEL pin is high, the parallel byte interface is selected, and if the DB15/BYTE SEL is low, then the serial mode is selected.
|
||
|
||
## CONVSTA, CONVSTB (Input)
|
||
|
||
CONVSTA, and CONVSTB (Input) are conversion control input pins.
|
||
|
||
CONVSTA can be used to simultaneously sample and initiate the conversion process for the first half count of the input channels (channels 1-4), and CONVSTB can be used to simultaneously sample and initiate the conversion process for the latter half count of the input channels (channels 5-8).
|
||
|
||
On the rising edge of the CONVSTA, CONVSTB signals, the internal track-and-hold circuits for each analog input channel are placed into the hold mode and the sampled input signal is converted.
|
||
|
||
The CONVSTA, and CONVSTB signals can be pulled low when the internal conversion is over, as indicated by the BUSY signal. At this point, the front-end circuit for all analog input channels acquires the respective input signals and the internal ADC is not converting.
|
||
|
||
The output data can be read from the device irrespective of the status of the CONVSTA and CONVSTB pins.
|
||
|
||
## RESET (Input)
|
||
|
||
The RESET pin can be used to reset the device at any time in an asynchronous manner. When the RESET pin is set to logic high, the device is in the reset mode and remains in the state until the pin returns low.
|
||
|
||
The device should be reset after power-up or recovery from the shut down mode when all the supplies and references have settled to the required accuracy.
|
||
|
||
## RD/SCLK (Input)
|
||
|
||
RD/SCLK (Input) is a dual-function pin to be used in different interface modes.
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
<table><tr><td colspan="2">Device Operating Condition</td><td>Functionality of RD/SCLK(Input)</td></tr><tr><td>Parallel Interface</td><td>PAR/SER/BYTR SEL = 0DB15/BYTE = 0</td><td rowspan="2">The active-low digital input pin to read the output data from the device.In the parallel or parallel byte interface mode, the output bus is enabled when both the CS and RD inputs are tied to a logic-low input.</td></tr><tr><td>Parallel Byte Interface</td><td>PAR/SER/BYTR SEL = 1DB15/BYTE = 1</td></tr><tr><td>Serial Interface</td><td>PAR/SER/BYTR SEL = 1DB15/BYTE = 0</td><td>The external clock input for the serial data interface. In the serial mode, all synchronous accesses to the device are timed with respect to the rising edge of the SCLK signal.</td></tr></table>
|
||
|
||
## $\overline{CS}$ (Input)
|
||
|
||
The $\overline{CS}$ pin is an active-low, chip-select signal.
|
||
|
||
A rising edge on the $\overline{CS}$ signal outputs all the data lines in tri-state mode.
|
||
|
||
A falling edge of the $\overline{CS}$ signal marks the beginning of the output data transfer frame in any interface mode of operation for the device.
|
||
|
||
## OS [2:0]
|
||
|
||
The OS [2:0] pins are active-high digital input pins used to configure the oversampling ratio for the internal digital filter on the device.
|
||
|
||
When OS [2:0] = 111, a higher filter bandwidth of $\sim$ 30 kHz is selected.
|
||
|
||
## Device Modes of Operation
|
||
|
||
## Power Down Modes
|
||
|
||
The device supports two power-down modes: standby mode and shutdown mode. The device can enter either power-down mode by pulling the STBY pin to a logic level. Additionally, the selection between these two power-down modes is done by the state of the RANGE pin.
|
||
|
||
<table><tr><td>Power Down Mode</td><td> $\overline{STBY}$ </td><td>Range</td></tr><tr><td>Standby</td><td>0</td><td>1</td></tr><tr><td>Shutdown</td><td>0</td><td>0</td></tr></table>
|
||
|
||
## Standby Mode
|
||
|
||
In the standby mode, only the internal reference of the circuit is powered up, and the analog front-end, signal-conditioning circuit for each channel remains powered down.
|
||
|
||
## Shutdown Mode
|
||
|
||
In the shutdown mode, the entire internal circuitry is powered down.
|
||
|
||
## Conversion Control
|
||
|
||
The device offers precise control of simultaneously sampling all analog input channels.
|
||
|
||
## Simultaneous Sampling on All Input Channels
|
||
|
||
All the analog input channels are to be simultaneously sampled by connecting CONVSTA and CONVSTB signals together, and a single CONVST signal should be used to control the sampling of all analog input channels of the device.
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
## Simultaneous Sampling Two Sets of Input Channels
|
||
|
||
Two sets of analog input channels can be simultaneously sampled by separating CONVSTA and CONVSTB signals. And the device could not operate in oversampling mode in this state.
|
||
|
||
## Data read operation
|
||
|
||
The device updates the internal data registers with the conversion data for all analog channels at the end of every conversion phase (when BUSY goes low).
|
||
|
||
If the output data are read after BUSY goes low, then the device outputs the conversion results for the current sample.
|
||
|
||
If the output data are read when BUSY is high, then the device outputs conversion results for the previous sample.
|
||
|
||
There are three interface modes:
|
||
|
||
<table><tr><td>Interface mode</td><td> $\overline{PAR}/SER/BYTE SEL$ </td><td>DB15/BYTE SEL</td></tr><tr><td>Parallel Interface</td><td>0</td><td>0</td></tr><tr><td>Parallel Byte Interface</td><td>1</td><td>1</td></tr><tr><td>Serial Interface</td><td>1</td><td>0</td></tr></table>
|
||
|
||
## Parallel Data Read
|
||
|
||
The device supports a parallel interface mode for reading the output data of the device using the control inputs ( $\overline{CS}$ and $\overline{RD}$ ), the parallel output bus (DB [15:0]), and the BUSY indicator.
|
||
|
||
For applications that use only one device in the system and do not share the parallel output bus with any other devices, the CS and RD input signals can be tied together, or the CS signal can be permanently tied low. At the first falling edge of the CS and RD signal, the output data of channel 1 becomes available on the parallel bus to be read by the digital host. At this instant, the FRSTDATA output also goes high, indicating channel 1 data is ready to be read back. The output data for the remaining channels are clocked out on the parallel bus on subsequent falling edges of the CS and RD signal in a sequential manner.
|
||
|
||
For applications that use multiple devices in the system, the CS and RD input signals must be driven separately.
|
||
|
||
## Parallel Byte Data Read
|
||
|
||
The parallel byte interface mode is very similar to the parallel interface mode, except that the output data for each channel is read in two data transfers of 8-bit byte sizes.
|
||
|
||
In the parallel byte mode, the DB14/HBEN pin decides the order of the most significant byte (MSB byte) and the least significant byte (LSB byte). When the DB14/HBEN pin is tied high, the MSB byte of the conversion results is output first followed by the LSB byte. This order is reversed when DB14/HBEN is tied to logic low.
|
||
|
||
At the first falling edge of the $\overline{RD}$ signal, the first byte of the channel 1 conversion result becomes available on DB [7:0]. This byte is followed by the second byte of conversion data on the next falling edge of the RD signal.
|
||
|
||
## Serial Data Read
|
||
|
||
This interface mode uses a CS control input, a communication clock input (SCLK), BUSY and FRSTDATA output indicators, and serial data output lines DOUTA and DOUTB.
|
||
|
||
A total of 16 SCLK cycles are required to clock out 16 bits of conversion result for each channel and the same process can be repeated for the remaining channels in an ascending order.
|
||
|
||
The conversion results from the first set of channels appear first on DOUTA, followed by the second set of channels if only DOUTA is used for reading data. This order is reversed for DOUTB, in which the second set of channels appear first followed by the first set of channels. The use of both data output lines reduces the time needed for data retrieval and a higher throughput can therefore be achieved in this mode.
|
||
|
||
## Data Read During Conversion
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
The device allows data read when the ADC is converting and the BUSY output is high status. In this case, the ADC outputs conversion results for previous samples.
|
||
|
||
The data read back during conversion mode allows faster throughput to be achieved from the device.
|
||
|
||
## Data Read During Conversion
|
||
|
||
The device can be configured in the oversampling mode by the OS [2:0] pins. The input on the OS pins is latched on the falling edge of the BUSY signal to configure the oversampling rate for the next conversion.
|
||
|
||
In this mode, the CONVST A and CONVST B signals should be tied or driven together.
|
||
|
||
The BUSY signal duration varies with the OSR setting because the conversion time increases with the OSR setting.
|
||
|
||
Oversampling the input signal reduces noise during the conversion process, thus reducing the histogram code spread for a DC input signal to the ADC.
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
## Application and Implementation
|
||
|
||
Note
|
||
|
||
Information in the following application sections is not part of the 3PEAK's component specification and 3PEAK does not warrant its accuracy or completeness. 3PEAK's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
Tape and Reel Information
|
||
|
||
|
||
<details>
|
||
<summary>natural_image</summary>
|
||
|
||
Technical line drawing of a wheel with four spokes and a central hub, no text or symbols present
|
||
</details>
|
||
|
||
D1:Reel Diameter
|
||
|
||
|
||
|
||
<details>
|
||
<summary>natural_image</summary>
|
||
|
||
Pure diagram of a vertical structure with horizontal lines and a central horizontal bar, labeled W1 at the bottom (no text or symbols beyond label)
|
||
</details>
|
||
|
||
|
||
|
||
<details>
|
||
<summary>text_image</summary>
|
||
|
||
Direction of Feed
|
||
W0
|
||
P0
|
||
A0
|
||
B0
|
||
K0
|
||
</details>
|
||
|
||
<table><tr><td>Order Number</td><td>Package</td><td>D1 (mm)</td><td>W1 (mm)</td><td>A0 (mm)</td><td>B0 (mm)</td><td>K0 (mm)</td><td>P0 (mm)</td><td>W0 (mm)</td><td>Pin1 Quadrant</td></tr><tr><td>TPAFE5160SI08-QP7R</td><td>LQFP10×10-64</td><td>330</td><td>28.4</td><td>12.085</td><td>12.085</td><td>2.1</td><td>16</td><td>24</td><td>Q2</td></tr></table>
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
## Package Outline Dimensions
|
||
|
||
LQFP10x10-64
|
||
|
||
Package Outline Dimensions
|
||
QP5(LQFP10X10-64-A)
|
||
|
||
|
||
<details>
|
||
<summary>text_image</summary>
|
||
|
||
D
|
||
D1
|
||
64
|
||
1
|
||
PIN 1
|
||
E1
|
||
E
|
||
</details>
|
||
|
||
|
||
|
||
<details>
|
||
<summary>text_image</summary>
|
||
|
||
WITH PLATING
|
||
b
|
||
c
|
||
BASE
|
||
METAL
|
||
</details>
|
||
|
||
SECTION N-N
|
||
|
||
|
||
|
||
<details>
|
||
<summary>natural_image</summary>
|
||
|
||
Pure electrical circuit lines without any symbols
|
||
</details>
|
||
|
||
|
||
|
||
|
||
|
||
<details>
|
||
<summary>text_image</summary>
|
||
|
||
A
|
||
A2
|
||
SEATING
|
||
PLANE
|
||
A1
|
||
C
|
||
e
|
||
b
|
||
θ
|
||
L
|
||
N
|
||
</details>
|
||
|
||
DETAIL Y
|
||
|
||
## NOTES
|
||
|
||
1. Do not include mold flash or protrusion.
|
||
2. This drawing is subject to change without notice.
|
||
|
||
<table><tr><td rowspan="2">Symbol</td><td colspan="2">Dimensions In Millimeters</td><td colspan="2">Dimensions In Inches</td></tr><tr><td>MIN</td><td>MAX</td><td>MIN</td><td>MAX</td></tr><tr><td>A</td><td>1.400</td><td>1.600</td><td>0.055</td><td>0.063</td></tr><tr><td>A1</td><td>0.050</td><td>0.150</td><td>0.002</td><td>0.006</td></tr><tr><td>A2</td><td>1.350</td><td>1.450</td><td>0.053</td><td>0.057</td></tr><tr><td>b</td><td>0.170</td><td>0.270</td><td>0.007</td><td>0.011</td></tr><tr><td>c</td><td>0.090</td><td>0.200</td><td>0.004</td><td>0.008</td></tr><tr><td>D</td><td>11.800</td><td>12.200</td><td>0.465</td><td>0.480</td></tr><tr><td>D1</td><td>9.900</td><td>10.100</td><td>0.390</td><td>0.398</td></tr><tr><td>E</td><td>11.800</td><td>12.200</td><td>0.465</td><td>0.480</td></tr><tr><td>E1</td><td>9.900</td><td>10.100</td><td>0.390</td><td>0.398</td></tr><tr><td>e</td><td colspan="2">0.500 BSC</td><td colspan="2">0.020 BSC</td></tr><tr><td>L</td><td>0.450</td><td>0.750</td><td>0.018</td><td>0.030</td></tr><tr><td>θ</td><td>0</td><td>7°</td><td>0</td><td>7°</td></tr></table>
|
||
|
||
## 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
Order Information
|
||
|
||
<table><tr><td>Order Number</td><td>Operating Temperature Range</td><td>Package</td><td>Marking Information</td><td>MSL</td><td>Transport Media, Quantity</td><td>Eco Plan</td></tr><tr><td>TPAFE5160SI08-QP7R</td><td>-40 to 125°C</td><td>LQFP10×10-64</td><td>AFE5160</td><td>3</td><td>Tape and Reel, 1000</td><td>Green</td></tr></table>
|
||
|
||
Green: 3PEAK defines "Green" to mean RoHS compatible and free of halogen substances.
|
||
|
||
# 16-Bit, 8-Channel, Simultaneous Sampling ADC with Bipolar Inputs
|
||
|
||
## IMPORTANT NOTICE AND DISCLAIMER
|
||
|
||
Copyright© 3PEAK 2012-2024. All rights reserved.
|
||
|
||
Trademarks. Any of the 思瑞浦 or 3PEAK trade names, trademarks, graphic marks, and domain names contained in this document /material are the property of 3PEAK. You may NOT reproduce, modify, publish, transmit or distribute any Trademark without the prior written consent of 3PEAK.
|
||
|
||
Performance Information. Performance tests or performance range contained in this document/material are either results of design simulation or actual tests conducted under designated testing environment. Any variation in testing environment or simulation environment, including but not limited to testing method, testing process or testing temperature, may affect actual performance of the product.
|
||
|
||
Disclaimer. 3PEAK provides technical and reliability data (including data sheets), design resources (including reference designs), application or other design recommendations, networking tools, security information and other resources "As Is". 3PEAK makes no warranty as to the absence of defects, and makes no warranties of any kind, express or implied, including without limitation, implied warranties as to merchantability, fitness for a particular purpose or non-infringement of any third-party's intellectual property rights. Unless otherwise specified in writing, products supplied by 3PEAK are not designed to be used in any life-threatening scenarios, including critical medical applications, automotive safety-critical systems, aviation, aerospace, or any situations where failure could result in bodily harm, loss of life, or significant property damage. 3PEAK disclaims all liability for any such unauthorized use. |